./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:15:29,547 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:15:29,553 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:15:29,589 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:15:29,589 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:15:29,593 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:15:29,594 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:15:29,598 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:15:29,599 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:15:29,603 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:15:29,604 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:15:29,605 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:15:29,605 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:15:29,607 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:15:29,608 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:15:29,611 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:15:29,612 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:15:29,613 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:15:29,615 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:15:29,617 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:15:29,619 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:15:29,620 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:15:29,621 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:15:29,622 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:15:29,625 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:15:29,625 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:15:29,625 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:15:29,626 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:15:29,627 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:15:29,627 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:15:29,627 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:15:29,628 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:15:29,629 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:15:29,630 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:15:29,631 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:15:29,631 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:15:29,631 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:15:29,631 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:15:29,632 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:15:29,632 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:15:29,633 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:15:29,634 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:15:29,662 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:15:29,665 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:15:29,665 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:15:29,665 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:15:29,666 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:15:29,666 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:15:29,666 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:15:29,666 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:15:29,667 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:15:29,667 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:15:29,667 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:15:29,668 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:15:29,668 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:15:29,668 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:15:29,668 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:15:29,668 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:15:29,668 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:15:29,669 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:15:29,670 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:15:29,671 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:15:29,671 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:15:29,671 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:15:29,671 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:15:29,671 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:15:29,671 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:15:29,672 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:15:29,672 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:15:29,672 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2021-12-19 19:15:29,853 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:15:29,879 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:15:29,881 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:15:29,882 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:15:29,882 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:15:29,883 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-19 19:15:29,922 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bbebdfc05/229cc2809d91401cb130c7a2e2155287/FLAG71f360f1b [2021-12-19 19:15:30,294 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:15:30,297 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-19 19:15:30,308 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bbebdfc05/229cc2809d91401cb130c7a2e2155287/FLAG71f360f1b [2021-12-19 19:15:30,318 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bbebdfc05/229cc2809d91401cb130c7a2e2155287 [2021-12-19 19:15:30,320 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:15:30,323 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:15:30,324 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:30,324 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:15:30,326 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:15:30,326 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,327 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b1177b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30, skipping insertion in model container [2021-12-19 19:15:30,328 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,331 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:15:30,357 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:15:30,499 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-19 19:15:30,543 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:30,553 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:15:30,561 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-19 19:15:30,580 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:30,593 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:15:30,593 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30 WrapperNode [2021-12-19 19:15:30,593 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:30,594 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:30,594 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:15:30,594 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:15:30,598 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,610 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,635 INFO L137 Inliner]: procedures = 29, calls = 31, calls flagged for inlining = 26, calls inlined = 27, statements flattened = 303 [2021-12-19 19:15:30,635 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:30,636 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:15:30,636 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:15:30,636 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:15:30,641 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,641 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,650 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,650 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,657 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,663 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,664 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,668 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:15:30,670 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:15:30,670 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:15:30,670 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:15:30,671 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (1/1) ... [2021-12-19 19:15:30,675 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:15:30,681 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:15:30,704 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:15:30,722 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:15:30,730 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:15:30,735 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:15:30,736 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:15:30,736 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:15:30,803 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:15:30,804 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:15:30,966 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:15:30,971 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:15:30,971 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-19 19:15:30,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:30 BoogieIcfgContainer [2021-12-19 19:15:30,973 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:15:30,973 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:15:30,973 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:15:30,976 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:15:30,976 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:30,976 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:15:30" (1/3) ... [2021-12-19 19:15:30,977 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c1c247e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:30, skipping insertion in model container [2021-12-19 19:15:30,977 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:30,977 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:30" (2/3) ... [2021-12-19 19:15:30,978 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c1c247e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:30, skipping insertion in model container [2021-12-19 19:15:30,978 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:30,978 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:30" (3/3) ... [2021-12-19 19:15:30,979 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2021-12-19 19:15:31,004 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:15:31,005 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:15:31,005 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:15:31,005 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:15:31,005 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:15:31,005 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:15:31,005 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:15:31,005 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:15:31,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-19 19:15:31,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,036 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,036 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:15:31,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-19 19:15:31,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,051 INFO L791 eck$LassoCheckResult]: Stem: 99#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 64#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68#L222true assume !(1 == ~q_req_up~0); 10#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 31#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 37#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 105#L65true assume !(1 == ~p_dw_pc~0); 29#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 53#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34#L315true assume !(0 != activate_threads_~tmp~1#1); 65#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 97#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 71#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 90#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5#L323true assume !(0 != activate_threads_~tmp___0~1#1); 46#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98#L293true assume !(1 == ~q_read_ev~0); 3#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 35#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2021-12-19 19:15:31,052 INFO L793 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 101#L364true assume false; 60#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82#L222-3true assume !(1 == ~q_req_up~0); 32#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 38#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 52#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 18#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 72#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 83#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 57#L84-3true assume !(1 == ~c_dr_pc~0); 88#L84-5true is_do_read_c_triggered_~__retres1~1#1 := 0; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 58#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 103#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 6#L293-5true assume !(1 == ~q_write_ev~0); 51#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 55#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2021-12-19 19:15:31,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,055 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2021-12-19 19:15:31,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534583083] [2021-12-19 19:15:31,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,215 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534583083] [2021-12-19 19:15:31,216 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534583083] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,216 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,216 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:31,217 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888007917] [2021-12-19 19:15:31,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,220 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:31,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1951455462, now seen corresponding path program 1 times [2021-12-19 19:15:31,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315938162] [2021-12-19 19:15:31,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315938162] [2021-12-19 19:15:31,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315938162] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:31,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588917829] [2021-12-19 19:15:31,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,254 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,255 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:31,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:31,281 INFO L87 Difference]: Start difference. First operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:31,314 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2021-12-19 19:15:31,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:31,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2021-12-19 19:15:31,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-19 19:15:31,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2021-12-19 19:15:31,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2021-12-19 19:15:31,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2021-12-19 19:15:31,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2021-12-19 19:15:31,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:31,351 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-19 19:15:31,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2021-12-19 19:15:31,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2021-12-19 19:15:31,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2021-12-19 19:15:31,374 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-19 19:15:31,374 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-19 19:15:31,374 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:15:31,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2021-12-19 19:15:31,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-19 19:15:31,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,380 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,380 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,380 INFO L791 eck$LassoCheckResult]: Stem: 307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 249#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 245#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 281#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 300#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 298#L275 assume !(0 == ~q_read_ev~0); 299#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 284#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 283#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 241#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 242#L315 assume !(0 != activate_threads_~tmp~1#1); 251#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 252#L84 assume 1 == ~c_dr_pc~0; 291#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 262#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 263#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 224#L323 assume !(0 != activate_threads_~tmp___0~1#1); 225#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306#L293 assume !(1 == ~q_read_ev~0); 213#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 214#L298-1 assume { :end_inline_reset_delta_events } true; 247#L419-2 [2021-12-19 19:15:31,381 INFO L793 eck$LassoCheckResult]: Loop: 247#L419-2 assume !false; 248#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 236#L364 assume !false; 285#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 259#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 266#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 267#L344 assume !(0 != eval_~tmp___1~0#1); 230#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L222-3 assume !(1 == ~q_req_up~0); 292#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 280#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 232#L65-3 assume !(1 == ~p_dw_pc~0); 233#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 270#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 264#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 265#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 293#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 278#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 222#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 223#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 276#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 228#L293-5 assume !(1 == ~q_write_ev~0); 229#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 288#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 289#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 215#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 216#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 239#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 261#L436 assume !(0 != start_simulation_~tmp~4#1); 247#L419-2 [2021-12-19 19:15:31,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,382 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2021-12-19 19:15:31,382 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161892811] [2021-12-19 19:15:31,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,383 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161892811] [2021-12-19 19:15:31,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161892811] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-19 19:15:31,449 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654371534] [2021-12-19 19:15:31,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,450 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:31,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,452 INFO L85 PathProgramCache]: Analyzing trace with hash -1517218729, now seen corresponding path program 1 times [2021-12-19 19:15:31,455 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407504081] [2021-12-19 19:15:31,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,498 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407504081] [2021-12-19 19:15:31,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407504081] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,499 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:31,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821826991] [2021-12-19 19:15:31,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,500 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,501 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:31,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:31,501 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:31,573 INFO L93 Difference]: Finished difference Result 211 states and 299 transitions. [2021-12-19 19:15:31,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:31,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 299 transitions. [2021-12-19 19:15:31,579 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 177 [2021-12-19 19:15:31,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 299 transitions. [2021-12-19 19:15:31,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2021-12-19 19:15:31,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2021-12-19 19:15:31,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 299 transitions. [2021-12-19 19:15:31,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:31,586 INFO L681 BuchiCegarLoop]: Abstraction has 211 states and 299 transitions. [2021-12-19 19:15:31,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 299 transitions. [2021-12-19 19:15:31,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2021-12-19 19:15:31,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.4285714285714286) internal successors, (280), 195 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 280 transitions. [2021-12-19 19:15:31,598 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2021-12-19 19:15:31,598 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2021-12-19 19:15:31,599 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:15:31,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 280 transitions. [2021-12-19 19:15:31,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 164 [2021-12-19 19:15:31,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,601 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,601 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,601 INFO L791 eck$LassoCheckResult]: Stem: 624#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 564#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 565#L222 assume !(1 == ~q_req_up~0); 560#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 598#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 615#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 612#L275 assume !(0 == ~q_read_ev~0); 613#L275-2 assume !(0 == ~q_write_ev~0); 599#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 600#L65 assume !(1 == ~p_dw_pc~0); 606#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 607#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 556#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 557#L315 assume !(0 != activate_threads_~tmp~1#1); 566#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 567#L84 assume !(1 == ~c_dr_pc~0); 587#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 578#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 579#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 540#L323 assume !(0 != activate_threads_~tmp___0~1#1); 541#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 623#L293 assume !(1 == ~q_read_ev~0); 532#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 533#L298-1 assume { :end_inline_reset_delta_events } true; 619#L419-2 [2021-12-19 19:15:31,601 INFO L793 eck$LassoCheckResult]: Loop: 619#L419-2 assume !false; 695#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 692#L364 assume !false; 690#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 688#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 686#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 684#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 682#L344 assume !(0 != eval_~tmp___1~0#1); 679#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 676#L222-3 assume !(1 == ~q_req_up~0); 672#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 663#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 660#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 548#L65-3 assume !(1 == ~p_dw_pc~0); 549#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 586#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 580#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 581#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 724#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 723#L84-3 assume !(1 == ~c_dr_pc~0); 722#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 721#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 720#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 719#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 593#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 594#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 544#L293-5 assume !(1 == ~q_write_ev~0); 545#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 713#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 712#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 710#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 708#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 706#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 704#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 702#L436 assume !(0 != start_simulation_~tmp~4#1); 619#L419-2 [2021-12-19 19:15:31,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2021-12-19 19:15:31,602 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67294213] [2021-12-19 19:15:31,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,603 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,640 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67294213] [2021-12-19 19:15:31,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67294213] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-19 19:15:31,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135361359] [2021-12-19 19:15:31,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,642 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:31,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,642 INFO L85 PathProgramCache]: Analyzing trace with hash -340614410, now seen corresponding path program 1 times [2021-12-19 19:15:31,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880221858] [2021-12-19 19:15:31,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880221858] [2021-12-19 19:15:31,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880221858] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,670 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:31,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075038269] [2021-12-19 19:15:31,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:31,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:31,671 INFO L87 Difference]: Start difference. First operand 196 states and 280 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:31,740 INFO L93 Difference]: Finished difference Result 449 states and 621 transitions. [2021-12-19 19:15:31,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:31,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 621 transitions. [2021-12-19 19:15:31,745 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2021-12-19 19:15:31,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 621 transitions. [2021-12-19 19:15:31,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2021-12-19 19:15:31,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2021-12-19 19:15:31,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 621 transitions. [2021-12-19 19:15:31,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:31,749 INFO L681 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-19 19:15:31,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 621 transitions. [2021-12-19 19:15:31,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2021-12-19 19:15:31,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3830734966592428) internal successors, (621), 448 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 621 transitions. [2021-12-19 19:15:31,764 INFO L704 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-19 19:15:31,764 INFO L587 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-19 19:15:31,764 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:15:31,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 621 transitions. [2021-12-19 19:15:31,765 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2021-12-19 19:15:31,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,766 INFO L791 eck$LassoCheckResult]: Stem: 1299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1222#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1223#L222 assume !(1 == ~q_req_up~0); 1232#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1260#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1261#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1279#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1338#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1278#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1289#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1326#L65 assume !(1 == ~p_dw_pc~0); 1325#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1324#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1323#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1322#L315 assume !(0 != activate_threads_~tmp~1#1); 1321#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1320#L84 assume !(1 == ~c_dr_pc~0); 1319#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1318#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1317#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1316#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1315#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1314#L293 assume !(1 == ~q_read_ev~0); 1312#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1313#L298-1 assume { :end_inline_reset_delta_events } true; 1503#L419-2 [2021-12-19 19:15:31,767 INFO L793 eck$LassoCheckResult]: Loop: 1503#L419-2 assume !false; 1497#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1494#L364 assume !false; 1493#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1491#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1489#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1488#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1486#L344 assume !(0 != eval_~tmp___1~0#1); 1487#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1580#L222-3 assume !(1 == ~q_req_up~0); 1578#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1577#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1572#L275-5 assume !(0 == ~q_write_ev~0); 1570#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1568#L65-3 assume !(1 == ~p_dw_pc~0); 1566#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1564#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1562#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1560#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1558#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1556#L84-3 assume !(1 == ~c_dr_pc~0); 1554#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1552#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1550#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1548#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1546#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1544#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1538#L293-5 assume !(1 == ~q_write_ev~0); 1537#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1533#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1530#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1528#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1527#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1526#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1517#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1507#L436 assume !(0 != start_simulation_~tmp~4#1); 1503#L419-2 [2021-12-19 19:15:31,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2021-12-19 19:15:31,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753059546] [2021-12-19 19:15:31,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,783 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753059546] [2021-12-19 19:15:31,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753059546] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,784 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:31,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275670630] [2021-12-19 19:15:31,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,784 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:31,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,785 INFO L85 PathProgramCache]: Analyzing trace with hash -474627916, now seen corresponding path program 1 times [2021-12-19 19:15:31,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206441154] [2021-12-19 19:15:31,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,806 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1206441154] [2021-12-19 19:15:31,806 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1206441154] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,807 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:31,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019021132] [2021-12-19 19:15:31,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,807 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,807 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:31,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:31,808 INFO L87 Difference]: Start difference. First operand 449 states and 621 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:31,825 INFO L93 Difference]: Finished difference Result 701 states and 951 transitions. [2021-12-19 19:15:31,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:31,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 951 transitions. [2021-12-19 19:15:31,829 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 586 [2021-12-19 19:15:31,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 951 transitions. [2021-12-19 19:15:31,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2021-12-19 19:15:31,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2021-12-19 19:15:31,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 951 transitions. [2021-12-19 19:15:31,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:31,833 INFO L681 BuchiCegarLoop]: Abstraction has 701 states and 951 transitions. [2021-12-19 19:15:31,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 951 transitions. [2021-12-19 19:15:31,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2021-12-19 19:15:31,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3588235294117648) internal successors, (693), 509 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 693 transitions. [2021-12-19 19:15:31,849 INFO L704 BuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2021-12-19 19:15:31,849 INFO L587 BuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2021-12-19 19:15:31,849 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:15:31,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 693 transitions. [2021-12-19 19:15:31,851 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2021-12-19 19:15:31,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,852 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,852 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,852 INFO L791 eck$LassoCheckResult]: Stem: 2451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2380#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2381#L222 assume !(1 == ~q_req_up~0); 2376#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2377#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2418#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2436#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2433#L275 assume !(0 == ~q_read_ev~0); 2434#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2442#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2483#L65 assume !(1 == ~p_dw_pc~0); 2481#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2479#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2477#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2475#L315 assume !(0 != activate_threads_~tmp~1#1); 2473#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2471#L84 assume !(1 == ~c_dr_pc~0); 2469#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2467#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2465#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2463#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2461#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2459#L293 assume !(1 == ~q_read_ev~0); 2456#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2348#L298-1 assume { :end_inline_reset_delta_events } true; 2441#L419-2 [2021-12-19 19:15:31,852 INFO L793 eck$LassoCheckResult]: Loop: 2441#L419-2 assume !false; 2425#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2393#L364 assume !false; 2421#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2391#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2354#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2535#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2532#L344 assume !(0 != eval_~tmp___1~0#1); 2533#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2853#L222-3 assume !(1 == ~q_req_up~0); 2851#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2850#L275-3 assume !(0 == ~q_read_ev~0); 2443#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2444#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2840#L65-3 assume !(1 == ~p_dw_pc~0); 2839#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2838#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2837#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2836#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2835#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2834#L84-3 assume !(1 == ~c_dr_pc~0); 2833#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2832#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2831#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2830#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2829#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2828#L293-3 assume !(1 == ~q_read_ev~0); 2702#L293-5 assume !(1 == ~q_write_ev~0); 2358#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2422#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2423#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2345#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2346#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2370#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2371#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2549#L436 assume !(0 != start_simulation_~tmp~4#1); 2441#L419-2 [2021-12-19 19:15:31,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,853 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2021-12-19 19:15:31,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944185146] [2021-12-19 19:15:31,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944185146] [2021-12-19 19:15:31,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944185146] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-19 19:15:31,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258982210] [2021-12-19 19:15:31,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,871 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:31,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,871 INFO L85 PathProgramCache]: Analyzing trace with hash -593092810, now seen corresponding path program 1 times [2021-12-19 19:15:31,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281613578] [2021-12-19 19:15:31,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281613578] [2021-12-19 19:15:31,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281613578] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:31,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055391297] [2021-12-19 19:15:31,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,895 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,895 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:31,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:31,895 INFO L87 Difference]: Start difference. First operand 510 states and 693 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:31,933 INFO L93 Difference]: Finished difference Result 745 states and 1002 transitions. [2021-12-19 19:15:31,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-19 19:15:31,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 1002 transitions. [2021-12-19 19:15:31,936 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 622 [2021-12-19 19:15:31,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 1002 transitions. [2021-12-19 19:15:31,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2021-12-19 19:15:31,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2021-12-19 19:15:31,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 1002 transitions. [2021-12-19 19:15:31,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:31,940 INFO L681 BuchiCegarLoop]: Abstraction has 745 states and 1002 transitions. [2021-12-19 19:15:31,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 1002 transitions. [2021-12-19 19:15:31,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2021-12-19 19:15:31,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:31,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2021-12-19 19:15:31,946 INFO L704 BuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2021-12-19 19:15:31,946 INFO L587 BuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2021-12-19 19:15:31,946 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:15:31,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2021-12-19 19:15:31,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2021-12-19 19:15:31,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:31,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:31,948 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,948 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:31,949 INFO L791 eck$LassoCheckResult]: Stem: 3712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3645#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3646#L222 assume !(1 == ~q_req_up~0); 3641#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3642#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3771#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3705#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3696#L275 assume !(0 == ~q_read_ev~0); 3697#L275-2 assume !(0 == ~q_write_ev~0); 3683#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3684#L65 assume !(1 == ~p_dw_pc~0); 3690#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3691#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3639#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3640#L315 assume !(0 != activate_threads_~tmp~1#1); 3647#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3648#L84 assume !(1 == ~c_dr_pc~0); 3669#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3662#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3663#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3620#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3621#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3709#L293 assume !(1 == ~q_read_ev~0); 3612#L293-2 assume !(1 == ~q_write_ev~0); 3613#L298-1 assume { :end_inline_reset_delta_events } true; 3704#L419-2 [2021-12-19 19:15:31,949 INFO L793 eck$LassoCheckResult]: Loop: 3704#L419-2 assume !false; 3827#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3719#L364 assume !false; 3682#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3656#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3615#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3664#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3665#L344 assume !(0 != eval_~tmp___1~0#1); 3626#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3627#L222-3 assume !(1 == ~q_req_up~0); 3689#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3678#L275-3 assume !(0 == ~q_read_ev~0); 3679#L275-5 assume !(0 == ~q_write_ev~0); 3706#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3628#L65-3 assume !(1 == ~p_dw_pc~0); 3629#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3668#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3660#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3661#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4157#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4156#L84-3 assume !(1 == ~c_dr_pc~0); 4155#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4153#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4152#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4150#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4149#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4148#L293-3 assume !(1 == ~q_read_ev~0); 4102#L293-5 assume !(1 == ~q_write_ev~0); 3720#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3721#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4098#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4095#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3834#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3832#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3831#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3828#L436 assume !(0 != start_simulation_~tmp~4#1); 3704#L419-2 [2021-12-19 19:15:31,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,949 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2021-12-19 19:15:31,949 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638675997] [2021-12-19 19:15:31,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,950 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:31,954 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:31,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:31,969 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:31,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:31,969 INFO L85 PathProgramCache]: Analyzing trace with hash -727106316, now seen corresponding path program 1 times [2021-12-19 19:15:31,969 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:31,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007478567] [2021-12-19 19:15:31,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:31,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:31,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:31,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:31,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:31,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007478567] [2021-12-19 19:15:31,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007478567] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:31,989 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:31,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:31,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115955188] [2021-12-19 19:15:31,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:31,989 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:31,990 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:31,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:31,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:31,990 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:32,025 INFO L93 Difference]: Finished difference Result 763 states and 1023 transitions. [2021-12-19 19:15:32,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:15:32,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 763 states and 1023 transitions. [2021-12-19 19:15:32,029 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2021-12-19 19:15:32,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 763 states to 763 states and 1023 transitions. [2021-12-19 19:15:32,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 763 [2021-12-19 19:15:32,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 763 [2021-12-19 19:15:32,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 763 states and 1023 transitions. [2021-12-19 19:15:32,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:32,032 INFO L681 BuchiCegarLoop]: Abstraction has 763 states and 1023 transitions. [2021-12-19 19:15:32,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states and 1023 transitions. [2021-12-19 19:15:32,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 581. [2021-12-19 19:15:32,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3373493975903614) internal successors, (777), 580 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 777 transitions. [2021-12-19 19:15:32,039 INFO L704 BuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2021-12-19 19:15:32,039 INFO L587 BuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2021-12-19 19:15:32,039 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:15:32,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 777 transitions. [2021-12-19 19:15:32,041 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2021-12-19 19:15:32,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:32,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:32,041 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,041 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,042 INFO L791 eck$LassoCheckResult]: Stem: 5075#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4986#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4987#L222 assume !(1 == ~q_req_up~0); 4999#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5148#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5146#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5063#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5048#L275 assume !(0 == ~q_read_ev~0); 5049#L275-2 assume !(0 == ~q_write_ev~0); 5064#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5121#L65 assume !(1 == ~p_dw_pc~0); 5119#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5117#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5115#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5113#L315 assume !(0 != activate_threads_~tmp~1#1); 5111#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5109#L84 assume !(1 == ~c_dr_pc~0); 5107#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5105#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5103#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5101#L323 assume !(0 != activate_threads_~tmp___0~1#1); 5099#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5097#L293 assume !(1 == ~q_read_ev~0); 4952#L293-2 assume !(1 == ~q_write_ev~0); 4953#L298-1 assume { :end_inline_reset_delta_events } true; 5467#L419-2 [2021-12-19 19:15:32,042 INFO L793 eck$LassoCheckResult]: Loop: 5467#L419-2 assume !false; 5466#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5460#L364 assume !false; 5454#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5449#L255 assume !(0 == ~p_dw_st~0); 5439#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5427#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5422#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5421#L344 assume !(0 != eval_~tmp___1~0#1); 5420#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5037#L222-3 assume !(1 == ~q_req_up~0); 5038#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5027#L275-3 assume !(0 == ~q_read_ev~0); 5028#L275-5 assume !(0 == ~q_write_ev~0); 5067#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4971#L65-3 assume !(1 == ~p_dw_pc~0); 4972#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5518#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5517#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5516#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5515#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5514#L84-3 assume !(1 == ~c_dr_pc~0); 5513#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5512#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5511#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5510#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5492#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5487#L293-3 assume !(1 == ~q_read_ev~0); 5483#L293-5 assume !(1 == ~q_write_ev~0); 5482#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5480#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5478#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5476#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5475#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5473#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5471#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5470#L436 assume !(0 != start_simulation_~tmp~4#1); 5467#L419-2 [2021-12-19 19:15:32,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2021-12-19 19:15:32,042 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560876797] [2021-12-19 19:15:32,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,043 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,047 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,052 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,052 INFO L85 PathProgramCache]: Analyzing trace with hash -366252558, now seen corresponding path program 1 times [2021-12-19 19:15:32,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890590431] [2021-12-19 19:15:32,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:32,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:32,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:32,094 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890590431] [2021-12-19 19:15:32,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890590431] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:32,095 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:32,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:32,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017911609] [2021-12-19 19:15:32,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:32,095 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:32,095 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:32,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:32,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:32,096 INFO L87 Difference]: Start difference. First operand 581 states and 777 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:32,128 INFO L93 Difference]: Finished difference Result 1103 states and 1485 transitions. [2021-12-19 19:15:32,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:15:32,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1103 states and 1485 transitions. [2021-12-19 19:15:32,132 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 998 [2021-12-19 19:15:32,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1103 states to 1103 states and 1485 transitions. [2021-12-19 19:15:32,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1103 [2021-12-19 19:15:32,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1103 [2021-12-19 19:15:32,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1103 states and 1485 transitions. [2021-12-19 19:15:32,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:32,137 INFO L681 BuchiCegarLoop]: Abstraction has 1103 states and 1485 transitions. [2021-12-19 19:15:32,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1103 states and 1485 transitions. [2021-12-19 19:15:32,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1103 to 593. [2021-12-19 19:15:32,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 593 states, 593 states have (on average 1.3102866779089377) internal successors, (777), 592 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 593 states to 593 states and 777 transitions. [2021-12-19 19:15:32,144 INFO L704 BuchiCegarLoop]: Abstraction has 593 states and 777 transitions. [2021-12-19 19:15:32,144 INFO L587 BuchiCegarLoop]: Abstraction has 593 states and 777 transitions. [2021-12-19 19:15:32,145 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:15:32,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 593 states and 777 transitions. [2021-12-19 19:15:32,146 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-19 19:15:32,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:32,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:32,147 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,147 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,147 INFO L791 eck$LassoCheckResult]: Stem: 6766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6685#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6686#L222 assume !(1 == ~q_req_up~0); 6681#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6682#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6726#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6743#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6817#L275 assume !(0 == ~q_read_ev~0); 6756#L275-2 assume !(0 == ~q_write_ev~0); 6757#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6805#L65 assume !(1 == ~p_dw_pc~0); 6803#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6801#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6799#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6797#L315 assume !(0 != activate_threads_~tmp~1#1); 6795#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6793#L84 assume !(1 == ~c_dr_pc~0); 6791#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6789#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6787#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6785#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6783#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6781#L293 assume !(1 == ~q_read_ev~0); 6780#L293-2 assume !(1 == ~q_write_ev~0); 6753#L298-1 assume { :end_inline_reset_delta_events } true; 6754#L419-2 [2021-12-19 19:15:32,147 INFO L793 eck$LassoCheckResult]: Loop: 6754#L419-2 assume !false; 6904#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6898#L364 assume !false; 6896#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6894#L255 assume !(0 == ~p_dw_st~0); 6891#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6888#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6886#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6883#L344 assume !(0 != eval_~tmp___1~0#1); 6880#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6877#L222-3 assume !(1 == ~q_req_up~0); 6878#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6931#L275-3 assume !(0 == ~q_read_ev~0); 6932#L275-5 assume !(0 == ~q_write_ev~0); 6991#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6668#L65-3 assume !(1 == ~p_dw_pc~0); 6669#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6990#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6989#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6985#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6981#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6977#L84-3 assume !(1 == ~c_dr_pc~0); 6973#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6969#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6965#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6961#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6957#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L293-3 assume !(1 == ~q_read_ev~0); 6934#L293-5 assume !(1 == ~q_write_ev~0); 6942#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6937#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6929#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6926#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6924#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6921#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6918#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6915#L436 assume !(0 != start_simulation_~tmp~4#1); 6754#L419-2 [2021-12-19 19:15:32,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2021-12-19 19:15:32,148 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436205718] [2021-12-19 19:15:32,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,148 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,152 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,156 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1934570032, now seen corresponding path program 1 times [2021-12-19 19:15:32,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592287705] [2021-12-19 19:15:32,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:32,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:32,168 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:32,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592287705] [2021-12-19 19:15:32,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592287705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:32,168 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:32,168 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:32,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789704505] [2021-12-19 19:15:32,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:32,169 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:32,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:32,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:32,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:32,170 INFO L87 Difference]: Start difference. First operand 593 states and 777 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:32,183 INFO L93 Difference]: Finished difference Result 832 states and 1065 transitions. [2021-12-19 19:15:32,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:32,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 832 states and 1065 transitions. [2021-12-19 19:15:32,186 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-19 19:15:32,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 832 states to 832 states and 1065 transitions. [2021-12-19 19:15:32,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 832 [2021-12-19 19:15:32,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 832 [2021-12-19 19:15:32,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 832 states and 1065 transitions. [2021-12-19 19:15:32,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:32,190 INFO L681 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-19 19:15:32,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 832 states and 1065 transitions. [2021-12-19 19:15:32,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 832 to 832. [2021-12-19 19:15:32,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 832 states, 832 states have (on average 1.2800480769230769) internal successors, (1065), 831 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 832 states to 832 states and 1065 transitions. [2021-12-19 19:15:32,198 INFO L704 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-19 19:15:32,198 INFO L587 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-19 19:15:32,198 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:15:32,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 832 states and 1065 transitions. [2021-12-19 19:15:32,201 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-19 19:15:32,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:32,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:32,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,201 INFO L791 eck$LassoCheckResult]: Stem: 8200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8114#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8115#L222 assume !(1 == ~q_req_up~0); 8112#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8113#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 8155#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8329#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8327#L275 assume !(0 == ~q_read_ev~0); 8325#L275-2 assume !(0 == ~q_write_ev~0); 8280#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8323#L65 assume !(1 == ~p_dw_pc~0); 8321#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8319#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8317#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8315#L315 assume !(0 != activate_threads_~tmp~1#1); 8313#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8311#L84 assume !(1 == ~c_dr_pc~0); 8309#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8307#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8305#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8303#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8301#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8299#L293 assume !(1 == ~q_read_ev~0); 8298#L293-2 assume !(1 == ~q_write_ev~0); 8186#L298-1 assume { :end_inline_reset_delta_events } true; 8116#L419-2 [2021-12-19 19:15:32,202 INFO L793 eck$LassoCheckResult]: Loop: 8116#L419-2 assume !false; 8117#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8173#L364 assume !false; 8213#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8835#L255 assume !(0 == ~p_dw_st~0); 8237#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8833#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8911#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8901#L344 assume !(0 != eval_~tmp___1~0#1); 8899#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8897#L222-3 assume !(1 == ~q_req_up~0); 8183#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8153#L275-3 assume !(0 == ~q_read_ev~0); 8154#L275-5 assume !(0 == ~q_write_ev~0); 8193#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8216#L65-3 assume !(1 == ~p_dw_pc~0); 8877#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8191#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8192#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8870#L315-3 assume !(0 != activate_threads_~tmp~1#1); 8169#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8087#L84-3 assume !(1 == ~c_dr_pc~0); 8088#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8152#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8089#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8090#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8150#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8151#L293-3 assume !(1 == ~q_read_ev~0); 8188#L293-5 assume !(1 == ~q_write_ev~0); 8215#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8160#L255-1 assume !(0 == ~p_dw_st~0); 8161#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8162#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8163#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8842#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8841#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8840#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8166#L436 assume !(0 != start_simulation_~tmp~4#1); 8116#L419-2 [2021-12-19 19:15:32,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2021-12-19 19:15:32,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561493908] [2021-12-19 19:15:32,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:32,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:32,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:32,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561493908] [2021-12-19 19:15:32,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561493908] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:32,213 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:32,213 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:32,213 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781389499] [2021-12-19 19:15:32,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:32,213 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:32,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,213 INFO L85 PathProgramCache]: Analyzing trace with hash -282414912, now seen corresponding path program 1 times [2021-12-19 19:15:32,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108559713] [2021-12-19 19:15:32,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:32,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:32,257 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:32,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108559713] [2021-12-19 19:15:32,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108559713] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:32,257 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:32,258 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:32,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966025239] [2021-12-19 19:15:32,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:32,258 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:32,258 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:32,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:32,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:32,259 INFO L87 Difference]: Start difference. First operand 832 states and 1065 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:32,264 INFO L93 Difference]: Finished difference Result 754 states and 971 transitions. [2021-12-19 19:15:32,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:32,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 754 states and 971 transitions. [2021-12-19 19:15:32,268 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-19 19:15:32,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 754 states to 754 states and 971 transitions. [2021-12-19 19:15:32,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 754 [2021-12-19 19:15:32,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 754 [2021-12-19 19:15:32,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 754 states and 971 transitions. [2021-12-19 19:15:32,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:32,272 INFO L681 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-19 19:15:32,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states and 971 transitions. [2021-12-19 19:15:32,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 754. [2021-12-19 19:15:32,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 754 states, 754 states have (on average 1.2877984084880636) internal successors, (971), 753 states have internal predecessors, (971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 971 transitions. [2021-12-19 19:15:32,279 INFO L704 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-19 19:15:32,279 INFO L587 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-19 19:15:32,279 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:15:32,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 754 states and 971 transitions. [2021-12-19 19:15:32,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-19 19:15:32,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:32,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:32,282 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,282 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,282 INFO L791 eck$LassoCheckResult]: Stem: 9790#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9711#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9712#L222 assume !(1 == ~q_req_up~0); 9722#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9753#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9754#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9774#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9771#L275 assume !(0 == ~q_read_ev~0); 9772#L275-2 assume !(0 == ~q_write_ev~0); 9783#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9829#L65 assume !(1 == ~p_dw_pc~0); 9827#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9825#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9823#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9821#L315 assume !(0 != activate_threads_~tmp~1#1); 9819#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9817#L84 assume !(1 == ~c_dr_pc~0); 9815#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9813#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9811#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9809#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9807#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9805#L293 assume !(1 == ~q_read_ev~0); 9804#L293-2 assume !(1 == ~q_write_ev~0); 9781#L298-1 assume { :end_inline_reset_delta_events } true; 9782#L419-2 assume !false; 10323#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10317#L364 [2021-12-19 19:15:32,282 INFO L793 eck$LassoCheckResult]: Loop: 10317#L364 assume !false; 10320#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10318#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10302#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10300#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10292#L344 assume 0 != eval_~tmp___1~0#1; 9876#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9877#L353 assume !(0 != eval_~tmp~2#1); 10225#L349 assume !(0 == ~c_dr_st~0); 10317#L364 [2021-12-19 19:15:32,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,282 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2021-12-19 19:15:32,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970440958] [2021-12-19 19:15:32,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,290 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,305 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,306 INFO L85 PathProgramCache]: Analyzing trace with hash -479000201, now seen corresponding path program 1 times [2021-12-19 19:15:32,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315313625] [2021-12-19 19:15:32,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,308 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,315 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,316 INFO L85 PathProgramCache]: Analyzing trace with hash 519639655, now seen corresponding path program 1 times [2021-12-19 19:15:32,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985239567] [2021-12-19 19:15:32,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:32,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:32,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:32,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985239567] [2021-12-19 19:15:32,328 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985239567] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:32,328 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:32,328 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:32,328 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861053598] [2021-12-19 19:15:32,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:32,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:32,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:32,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:32,366 INFO L87 Difference]: Start difference. First operand 754 states and 971 transitions. cyclomatic complexity: 221 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:32,379 INFO L93 Difference]: Finished difference Result 844 states and 1081 transitions. [2021-12-19 19:15:32,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:32,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1081 transitions. [2021-12-19 19:15:32,383 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 735 [2021-12-19 19:15:32,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1081 transitions. [2021-12-19 19:15:32,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2021-12-19 19:15:32,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2021-12-19 19:15:32,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1081 transitions. [2021-12-19 19:15:32,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:32,387 INFO L681 BuchiCegarLoop]: Abstraction has 844 states and 1081 transitions. [2021-12-19 19:15:32,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1081 transitions. [2021-12-19 19:15:32,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 824. [2021-12-19 19:15:32,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 824 states, 824 states have (on average 1.2851941747572815) internal successors, (1059), 823 states have internal predecessors, (1059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:32,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 824 states to 824 states and 1059 transitions. [2021-12-19 19:15:32,394 INFO L704 BuchiCegarLoop]: Abstraction has 824 states and 1059 transitions. [2021-12-19 19:15:32,394 INFO L587 BuchiCegarLoop]: Abstraction has 824 states and 1059 transitions. [2021-12-19 19:15:32,394 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:15:32,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 824 states and 1059 transitions. [2021-12-19 19:15:32,396 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 715 [2021-12-19 19:15:32,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:32,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:32,397 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,397 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:32,397 INFO L791 eck$LassoCheckResult]: Stem: 11401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11315#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11316#L222 assume !(1 == ~q_req_up~0); 11331#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11472#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 11468#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11394#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11383#L275 assume !(0 == ~q_read_ev~0); 11384#L275-2 assume !(0 == ~q_write_ev~0); 11395#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11450#L65 assume !(1 == ~p_dw_pc~0); 11448#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 11446#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11444#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11442#L315 assume !(0 != activate_threads_~tmp~1#1); 11440#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11438#L84 assume !(1 == ~c_dr_pc~0); 11436#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11434#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11432#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11430#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11428#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11426#L293 assume !(1 == ~q_read_ev~0); 11425#L293-2 assume !(1 == ~q_write_ev~0); 11390#L298-1 assume { :end_inline_reset_delta_events } true; 11391#L419-2 assume !false; 11861#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 11850#L364 [2021-12-19 19:15:32,397 INFO L793 eck$LassoCheckResult]: Loop: 11850#L364 assume !false; 11851#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11846#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11847#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11841#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 11842#L344 assume 0 != eval_~tmp___1~0#1; 11762#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 11763#L353 assume !(0 != eval_~tmp~2#1); 11855#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 11853#L368 assume !(0 != eval_~tmp___0~2#1); 11850#L364 [2021-12-19 19:15:32,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,398 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2021-12-19 19:15:32,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188587107] [2021-12-19 19:15:32,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,401 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,406 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1964106000, now seen corresponding path program 1 times [2021-12-19 19:15:32,406 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280665712] [2021-12-19 19:15:32,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,407 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,408 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,410 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:32,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041536, now seen corresponding path program 1 times [2021-12-19 19:15:32,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:32,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809156808] [2021-12-19 19:15:32,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:32,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:32,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,414 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:32,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:32,420 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:32,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.12 07:15:32 BoogieIcfgContainer [2021-12-19 19:15:32,973 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-19 19:15:32,974 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-19 19:15:32,974 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-19 19:15:32,974 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-19 19:15:32,974 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:30" (3/4) ... [2021-12-19 19:15:32,976 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-19 19:15:32,998 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-19 19:15:32,998 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-19 19:15:32,998 INFO L158 Benchmark]: Toolchain (without parser) took 2675.52ms. Allocated memory was 104.9MB in the beginning and 157.3MB in the end (delta: 52.4MB). Free memory was 75.3MB in the beginning and 100.1MB in the end (delta: -24.8MB). Peak memory consumption was 27.0MB. Max. memory is 16.1GB. [2021-12-19 19:15:32,998 INFO L158 Benchmark]: CDTParser took 0.10ms. Allocated memory is still 104.9MB. Free memory is still 62.3MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-19 19:15:32,999 INFO L158 Benchmark]: CACSL2BoogieTranslator took 270.04ms. Allocated memory is still 104.9MB. Free memory was 75.3MB in the beginning and 79.0MB in the end (delta: -3.7MB). Peak memory consumption was 9.7MB. Max. memory is 16.1GB. [2021-12-19 19:15:32,999 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.41ms. Allocated memory is still 104.9MB. Free memory was 79.0MB in the beginning and 76.6MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-19 19:15:32,999 INFO L158 Benchmark]: Boogie Preprocessor took 33.13ms. Allocated memory is still 104.9MB. Free memory was 76.6MB in the beginning and 75.3MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-19 19:15:32,999 INFO L158 Benchmark]: RCFGBuilder took 303.15ms. Allocated memory is still 104.9MB. Free memory was 74.9MB in the beginning and 59.8MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2021-12-19 19:15:33,000 INFO L158 Benchmark]: BuchiAutomizer took 2000.06ms. Allocated memory was 104.9MB in the beginning and 157.3MB in the end (delta: 52.4MB). Free memory was 59.6MB in the beginning and 103.2MB in the end (delta: -43.6MB). Peak memory consumption was 43.0MB. Max. memory is 16.1GB. [2021-12-19 19:15:33,000 INFO L158 Benchmark]: Witness Printer took 24.08ms. Allocated memory is still 157.3MB. Free memory was 103.2MB in the beginning and 100.1MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:15:33,001 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10ms. Allocated memory is still 104.9MB. Free memory is still 62.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 270.04ms. Allocated memory is still 104.9MB. Free memory was 75.3MB in the beginning and 79.0MB in the end (delta: -3.7MB). Peak memory consumption was 9.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 41.41ms. Allocated memory is still 104.9MB. Free memory was 79.0MB in the beginning and 76.6MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 33.13ms. Allocated memory is still 104.9MB. Free memory was 76.6MB in the beginning and 75.3MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 303.15ms. Allocated memory is still 104.9MB. Free memory was 74.9MB in the beginning and 59.8MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 2000.06ms. Allocated memory was 104.9MB in the beginning and 157.3MB in the end (delta: 52.4MB). Free memory was 59.6MB in the beginning and 103.2MB in the end (delta: -43.6MB). Peak memory consumption was 43.0MB. Max. memory is 16.1GB. * Witness Printer took 24.08ms. Allocated memory is still 157.3MB. Free memory was 103.2MB in the beginning and 100.1MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 824 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.9s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.2s. Construction of modules took 0.1s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 10 MinimizatonAttempts, 1100 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 832 states and ocurred in iteration 8. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1879 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1879 mSDsluCounter, 3054 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1617 mSDsCounter, 69 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 229 IncrementalHoareTripleChecker+Invalid, 298 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 69 mSolverCounterUnsat, 1437 mSDtfsCounter, 229 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e48a88c=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1233779c=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3de6ec57=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42382af4=0, p_dw_pc=0, q_free=1, __retres1=1, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7aa5839=0, kernel_st=1, p_num_write=0, q_buf_0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@237621c5=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) [L280] COND FALSE !((int )q_write_ev == 0) [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; [L65] COND FALSE !((int )p_dw_pc == 1) [L75] __retres1 = 0 [L77] return (__retres1); [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; [L84] COND FALSE !((int )c_dr_pc == 1) [L94] __retres1 = 0 [L96] return (__retres1); [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) [L298] COND FALSE !((int )q_write_ev == 1) [L416] RET reset_delta_events() [L419] COND TRUE 1 [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-19 19:15:33,029 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)