./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:15:43,058 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:15:43,060 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:15:43,108 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:15:43,109 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:15:43,113 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:15:43,114 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:15:43,117 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:15:43,119 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:15:43,123 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:15:43,123 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:15:43,125 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:15:43,125 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:15:43,143 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:15:43,144 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:15:43,144 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:15:43,145 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:15:43,146 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:15:43,147 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:15:43,150 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:15:43,151 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:15:43,152 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:15:43,153 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:15:43,154 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:15:43,156 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:15:43,156 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:15:43,156 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:15:43,157 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:15:43,157 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:15:43,158 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:15:43,158 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:15:43,159 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:15:43,159 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:15:43,160 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:15:43,161 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:15:43,161 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:15:43,162 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:15:43,162 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:15:43,162 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:15:43,163 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:15:43,163 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:15:43,164 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:15:43,200 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:15:43,200 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:15:43,201 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:15:43,201 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:15:43,202 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:15:43,202 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:15:43,202 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:15:43,203 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:15:43,203 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:15:43,203 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:15:43,204 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:15:43,204 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:15:43,204 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:15:43,204 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:15:43,204 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:15:43,205 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:15:43,206 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:15:43,206 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:15:43,206 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:15:43,207 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:15:43,207 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:15:43,207 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:15:43,208 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:15:43,208 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:15:43,208 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:15:43,208 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:15:43,208 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:15:43,209 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:15:43,209 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2021-12-19 19:15:43,398 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:15:43,414 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:15:43,416 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:15:43,417 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:15:43,417 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:15:43,419 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-12-19 19:15:43,466 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ed655baca/b3d0bae5f2c04e899fea3b5e62fd1e2b/FLAG06478b493 [2021-12-19 19:15:43,894 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:15:43,896 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-12-19 19:15:43,903 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ed655baca/b3d0bae5f2c04e899fea3b5e62fd1e2b/FLAG06478b493 [2021-12-19 19:15:44,278 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ed655baca/b3d0bae5f2c04e899fea3b5e62fd1e2b [2021-12-19 19:15:44,280 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:15:44,281 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:15:44,283 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:44,283 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:15:44,286 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:15:44,286 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,288 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7bc6f5ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44, skipping insertion in model container [2021-12-19 19:15:44,288 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,294 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:15:44,319 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:15:44,450 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2021-12-19 19:15:44,500 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:44,508 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:15:44,517 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2021-12-19 19:15:44,542 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:44,555 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:15:44,556 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44 WrapperNode [2021-12-19 19:15:44,556 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:44,557 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:44,557 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:15:44,557 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:15:44,563 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,571 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,624 INFO L137 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 62, statements flattened = 813 [2021-12-19 19:15:44,633 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:44,634 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:15:44,634 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:15:44,634 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:15:44,641 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,641 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,655 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,663 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,686 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,704 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,706 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,711 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:15:44,731 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:15:44,731 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:15:44,732 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:15:44,733 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (1/1) ... [2021-12-19 19:15:44,738 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:15:44,746 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:15:44,757 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:15:44,759 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:15:44,782 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:15:44,783 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:15:44,783 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:15:44,783 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:15:44,845 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:15:44,846 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:15:45,428 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:15:45,437 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:15:45,437 INFO L301 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-19 19:15:45,439 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:45 BoogieIcfgContainer [2021-12-19 19:15:45,439 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:15:45,440 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:15:45,440 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:15:45,443 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:15:45,443 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:45,443 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:15:44" (1/3) ... [2021-12-19 19:15:45,444 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@17c1dc3f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:45, skipping insertion in model container [2021-12-19 19:15:45,445 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:45,445 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:44" (2/3) ... [2021-12-19 19:15:45,445 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@17c1dc3f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:45, skipping insertion in model container [2021-12-19 19:15:45,445 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:45,445 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:45" (3/3) ... [2021-12-19 19:15:45,446 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2021-12-19 19:15:45,501 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:15:45,501 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:15:45,501 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:15:45,502 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:15:45,502 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:15:45,502 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:15:45,502 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:15:45,502 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:15:45,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:45,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2021-12-19 19:15:45,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:45,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:45,577 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,577 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,577 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:15:45,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:45,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2021-12-19 19:15:45,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:45,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:45,592 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,592 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,599 INFO L791 eck$LassoCheckResult]: Stem: 314#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 215#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 221#L641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 308#L285true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 204#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 194#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 254#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 144#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L439-1true assume !(0 == ~T3_E~0); 169#L444-1true assume !(0 == ~E_M~0); 277#L449-1true assume !(0 == ~E_1~0); 59#L454-1true assume !(0 == ~E_2~0); 301#L459-1true assume !(0 == ~E_3~0); 38#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294#L208true assume 1 == ~m_pc~0; 299#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 324#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L220true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 48#L531true assume !(0 != activate_threads_~tmp~1#1); 133#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117#L227true assume !(1 == ~t1_pc~0); 47#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 195#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197#L239true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58#L539true assume !(0 != activate_threads_~tmp___0~0#1); 139#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77#L246true assume 1 == ~t2_pc~0; 130#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 149#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#L258true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 208#L547true assume !(0 != activate_threads_~tmp___1~0#1); 232#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83#L265true assume !(1 == ~t3_pc~0); 309#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 4#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L277true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320#L555true assume !(0 != activate_threads_~tmp___2~0#1); 64#L555-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199#L477true assume !(1 == ~M_E~0); 261#L477-2true assume !(1 == ~T1_E~0); 216#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 167#L487-1true assume !(1 == ~T3_E~0); 250#L492-1true assume !(1 == ~E_M~0); 41#L497-1true assume !(1 == ~E_1~0); 138#L502-1true assume !(1 == ~E_2~0); 29#L507-1true assume !(1 == ~E_3~0); 115#L512-1true assume { :end_inline_reset_delta_events } true; 191#L678-2true [2021-12-19 19:15:45,600 INFO L793 eck$LassoCheckResult]: Loop: 191#L678-2true assume !false; 282#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140#L404true assume false; 5#L419true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63#L285-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 263#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 326#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 189#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 71#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 95#L454-3true assume 0 == ~E_2~0;~E_2~0 := 1; 234#L459-3true assume !(0 == ~E_3~0); 60#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246#L208-15true assume 1 == ~m_pc~0; 279#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 243#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52#L220-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 153#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286#L227-15true assume !(1 == ~t1_pc~0); 271#L227-17true is_transmit1_triggered_~__retres1~1#1 := 0; 235#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19#L239-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170#L246-15true assume !(1 == ~t2_pc~0); 14#L246-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 288#L258-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 311#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L265-15true assume !(1 == ~t3_pc~0); 265#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 126#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90#L277-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 212#L555-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L477-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 260#L482-3true assume !(1 == ~T2_E~0); 96#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 51#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 285#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 137#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 182#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 54#L343-1true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 207#L697true assume !(0 == start_simulation_~tmp~3#1); 3#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 251#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 81#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 70#L343-2true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 323#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 196#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 275#L660true start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 82#L710true assume !(0 != start_simulation_~tmp___0~1#1); 191#L678-2true [2021-12-19 19:15:45,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:45,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2021-12-19 19:15:45,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:45,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242301415] [2021-12-19 19:15:45,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:45,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:45,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:45,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:45,759 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:45,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242301415] [2021-12-19 19:15:45,760 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242301415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:45,760 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:45,760 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:45,761 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209463583] [2021-12-19 19:15:45,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:45,765 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:45,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:45,766 INFO L85 PathProgramCache]: Analyzing trace with hash -203279494, now seen corresponding path program 1 times [2021-12-19 19:15:45,766 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:45,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189558726] [2021-12-19 19:15:45,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:45,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:45,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:45,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:45,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:45,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189558726] [2021-12-19 19:15:45,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189558726] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:45,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:45,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:45,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705169973] [2021-12-19 19:15:45,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:45,790 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:45,791 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:45,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:45,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:45,821 INFO L87 Difference]: Start difference. First operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:45,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:45,864 INFO L93 Difference]: Finished difference Result 323 states and 481 transitions. [2021-12-19 19:15:45,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:45,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 481 transitions. [2021-12-19 19:15:45,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:45,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 318 states and 476 transitions. [2021-12-19 19:15:45,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-19 19:15:45,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-19 19:15:45,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 476 transitions. [2021-12-19 19:15:45,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:45,904 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-19 19:15:45,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 476 transitions. [2021-12-19 19:15:45,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-19 19:15:45,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:45,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 476 transitions. [2021-12-19 19:15:45,963 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-19 19:15:45,963 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-19 19:15:45,963 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:15:45,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 476 transitions. [2021-12-19 19:15:45,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:45,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:45,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:45,975 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:45,981 INFO L791 eck$LassoCheckResult]: Stem: 973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 943#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 947#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 847#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 848#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 934#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 919#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 920#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 927#L429 assume !(0 == ~M_E~0); 756#L429-2 assume !(0 == ~T1_E~0); 757#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 878#L439-1 assume !(0 == ~T3_E~0); 900#L444-1 assume !(0 == ~E_M~0); 901#L449-1 assume !(0 == ~E_1~0); 762#L454-1 assume !(0 == ~E_2~0); 763#L459-1 assume !(0 == ~E_3~0); 723#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 724#L208 assume 1 == ~m_pc~0; 969#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 971#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 743#L531 assume !(0 != activate_threads_~tmp~1#1); 744#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 853#L227 assume !(1 == ~t1_pc~0); 741#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 742#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 928#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 760#L539 assume !(0 != activate_threads_~tmp___0~0#1); 761#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793#L246 assume 1 == ~t2_pc~0; 794#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 866#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 933#L547 assume !(0 != activate_threads_~tmp___1~0#1); 938#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 803#L265 assume !(1 == ~t3_pc~0); 685#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 658#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 659#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 883#L555 assume !(0 != activate_threads_~tmp___2~0#1); 775#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 776#L477 assume !(1 == ~M_E~0); 932#L477-2 assume !(1 == ~T1_E~0); 944#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 895#L487-1 assume !(1 == ~T3_E~0); 896#L492-1 assume !(1 == ~E_M~0); 731#L497-1 assume !(1 == ~E_1~0); 732#L502-1 assume !(1 == ~E_2~0); 710#L507-1 assume !(1 == ~E_3~0); 711#L512-1 assume { :end_inline_reset_delta_events } true; 800#L678-2 [2021-12-19 19:15:45,981 INFO L793 eck$LassoCheckResult]: Loop: 800#L678-2 assume !false; 925#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L404 assume !false; 852#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 833#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 695#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 727#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 780#L357 assume !(0 != eval_~tmp~0#1); 660#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 661#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 771#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 962#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 921#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 922#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 769#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 770#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 787#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 819#L459-3 assume !(0 == ~E_3~0); 764#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 765#L208-15 assume !(1 == ~m_pc~0); 906#L208-17 is_master_triggered_~__retres1~0#1 := 0; 907#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 751#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 752#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 788#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 789#L227-15 assume !(1 == ~t1_pc~0); 965#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 952#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 687#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 917#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L246-15 assume 1 == ~t2_pc~0; 666#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 667#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 958#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 966#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 753#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 754#L265-15 assume 1 == ~t3_pc~0; 828#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 830#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 811#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 806#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 807#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 908#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 909#L482-3 assume !(1 == ~T2_E~0); 818#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 747#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 748#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 872#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 873#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 842#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 714#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 675#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 676#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 755#L697 assume !(0 == start_simulation_~tmp~3#1); 656#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 657#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 798#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 783#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 784#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 929#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 930#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 799#L710 assume !(0 != start_simulation_~tmp___0~1#1); 800#L678-2 [2021-12-19 19:15:45,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:45,982 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2021-12-19 19:15:45,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:45,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229659151] [2021-12-19 19:15:45,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:45,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:45,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229659151] [2021-12-19 19:15:46,028 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229659151] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,028 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715925748] [2021-12-19 19:15:46,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,029 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:46,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,030 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 1 times [2021-12-19 19:15:46,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698888816] [2021-12-19 19:15:46,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,030 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698888816] [2021-12-19 19:15:46,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698888816] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445902623] [2021-12-19 19:15:46,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,102 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:46,102 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:46,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:46,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:46,103 INFO L87 Difference]: Start difference. First operand 318 states and 476 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:46,120 INFO L93 Difference]: Finished difference Result 318 states and 475 transitions. [2021-12-19 19:15:46,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:46,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 475 transitions. [2021-12-19 19:15:46,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:46,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 475 transitions. [2021-12-19 19:15:46,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-19 19:15:46,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-19 19:15:46,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 475 transitions. [2021-12-19 19:15:46,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:46,128 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-19 19:15:46,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 475 transitions. [2021-12-19 19:15:46,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-19 19:15:46,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 475 transitions. [2021-12-19 19:15:46,136 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-19 19:15:46,136 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-19 19:15:46,136 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:15:46,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 475 transitions. [2021-12-19 19:15:46,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:46,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:46,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:46,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,140 INFO L791 eck$LassoCheckResult]: Stem: 1616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1587#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1590#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1493#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 1494#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1577#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1562#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1563#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570#L429 assume !(0 == ~M_E~0); 1399#L429-2 assume !(0 == ~T1_E~0); 1400#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1521#L439-1 assume !(0 == ~T3_E~0); 1543#L444-1 assume !(0 == ~E_M~0); 1544#L449-1 assume !(0 == ~E_1~0); 1407#L454-1 assume !(0 == ~E_2~0); 1408#L459-1 assume !(0 == ~E_3~0); 1366#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1367#L208 assume 1 == ~m_pc~0; 1612#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1614#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1435#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1386#L531 assume !(0 != activate_threads_~tmp~1#1); 1387#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1497#L227 assume !(1 == ~t1_pc~0); 1384#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1385#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1571#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1403#L539 assume !(0 != activate_threads_~tmp___0~0#1); 1404#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1436#L246 assume 1 == ~t2_pc~0; 1437#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1509#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1524#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1576#L547 assume !(0 != activate_threads_~tmp___1~0#1); 1581#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1446#L265 assume !(1 == ~t3_pc~0); 1328#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1301#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1302#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1526#L555 assume !(0 != activate_threads_~tmp___2~0#1); 1415#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1416#L477 assume !(1 == ~M_E~0); 1575#L477-2 assume !(1 == ~T1_E~0); 1585#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1538#L487-1 assume !(1 == ~T3_E~0); 1539#L492-1 assume !(1 == ~E_M~0); 1371#L497-1 assume !(1 == ~E_1~0); 1372#L502-1 assume !(1 == ~E_2~0); 1353#L507-1 assume !(1 == ~E_3~0); 1354#L512-1 assume { :end_inline_reset_delta_events } true; 1443#L678-2 [2021-12-19 19:15:46,140 INFO L793 eck$LassoCheckResult]: Loop: 1443#L678-2 assume !false; 1566#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1332#L404 assume !false; 1495#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1471#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1338#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1370#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1422#L357 assume !(0 != eval_~tmp~0#1); 1303#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1304#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1414#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1564#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1565#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1412#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1413#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1428#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1461#L459-3 assume !(0 == ~E_3~0); 1405#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1406#L208-15 assume 1 == ~m_pc~0; 1600#L209-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1550#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1394#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1395#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1429#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1430#L227-15 assume !(1 == ~t1_pc~0); 1607#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1595#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1329#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1330#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1560#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1545#L246-15 assume 1 == ~t2_pc~0; 1313#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1314#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1601#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1610#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1396#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1397#L265-15 assume 1 == ~t3_pc~0; 1472#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1474#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1455#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1450#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1451#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1583#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1551#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1552#L482-3 assume !(1 == ~T2_E~0); 1462#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1392#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1393#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1515#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1516#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1485#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1357#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1320#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1321#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1398#L697 assume !(0 == start_simulation_~tmp~3#1); 1299#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1300#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1441#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1426#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 1427#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1572#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1573#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1442#L710 assume !(0 != start_simulation_~tmp___0~1#1); 1443#L678-2 [2021-12-19 19:15:46,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2021-12-19 19:15:46,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809175117] [2021-12-19 19:15:46,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809175117] [2021-12-19 19:15:46,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809175117] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811977800] [2021-12-19 19:15:46,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,191 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:46,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,192 INFO L85 PathProgramCache]: Analyzing trace with hash 378529221, now seen corresponding path program 1 times [2021-12-19 19:15:46,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2460843] [2021-12-19 19:15:46,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2460843] [2021-12-19 19:15:46,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2460843] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101763956] [2021-12-19 19:15:46,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,272 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:46,272 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:46,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:46,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:46,273 INFO L87 Difference]: Start difference. First operand 318 states and 475 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:46,286 INFO L93 Difference]: Finished difference Result 318 states and 474 transitions. [2021-12-19 19:15:46,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:46,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 474 transitions. [2021-12-19 19:15:46,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:46,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 474 transitions. [2021-12-19 19:15:46,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-19 19:15:46,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-19 19:15:46,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 474 transitions. [2021-12-19 19:15:46,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:46,292 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-19 19:15:46,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 474 transitions. [2021-12-19 19:15:46,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-19 19:15:46,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 474 transitions. [2021-12-19 19:15:46,298 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-19 19:15:46,299 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-19 19:15:46,299 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:15:46,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 474 transitions. [2021-12-19 19:15:46,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-19 19:15:46,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:46,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:46,302 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,302 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,302 INFO L791 eck$LassoCheckResult]: Stem: 2259#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2229#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2233#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2131#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2132#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2220#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2204#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2205#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2213#L429 assume !(0 == ~M_E~0); 2042#L429-2 assume !(0 == ~T1_E~0); 2043#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2163#L439-1 assume !(0 == ~T3_E~0); 2186#L444-1 assume !(0 == ~E_M~0); 2187#L449-1 assume !(0 == ~E_1~0); 2048#L454-1 assume !(0 == ~E_2~0); 2049#L459-1 assume !(0 == ~E_3~0); 2009#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2010#L208 assume 1 == ~m_pc~0; 2255#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2257#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2077#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2029#L531 assume !(0 != activate_threads_~tmp~1#1); 2030#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2139#L227 assume !(1 == ~t1_pc~0); 2027#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2028#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2214#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2046#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2047#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2078#L246 assume 1 == ~t2_pc~0; 2079#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2152#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2167#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2219#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2223#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2087#L265 assume !(1 == ~t3_pc~0); 1971#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1944#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1945#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2169#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2058#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2059#L477 assume !(1 == ~M_E~0); 2218#L477-2 assume !(1 == ~T1_E~0); 2230#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2181#L487-1 assume !(1 == ~T3_E~0); 2182#L492-1 assume !(1 == ~E_M~0); 2014#L497-1 assume !(1 == ~E_1~0); 2015#L502-1 assume !(1 == ~E_2~0); 1996#L507-1 assume !(1 == ~E_3~0); 1997#L512-1 assume { :end_inline_reset_delta_events } true; 2086#L678-2 [2021-12-19 19:15:46,302 INFO L793 eck$LassoCheckResult]: Loop: 2086#L678-2 assume !false; 2209#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1975#L404 assume !false; 2138#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2114#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1981#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2013#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2065#L357 assume !(0 != eval_~tmp~0#1); 1946#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1947#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2057#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2248#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2207#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2208#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2055#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2056#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2071#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2104#L459-3 assume !(0 == ~E_3~0); 2050#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2051#L208-15 assume !(1 == ~m_pc~0); 2192#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2193#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2037#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2038#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2072#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2073#L227-15 assume !(1 == ~t1_pc~0); 2250#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2238#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1972#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1973#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2203#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2188#L246-15 assume 1 == ~t2_pc~0; 1956#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1957#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2244#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2253#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2039#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2040#L265-15 assume 1 == ~t3_pc~0; 2115#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2117#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2098#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2093#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2094#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2226#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2194#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2195#L482-3 assume !(1 == ~T2_E~0); 2105#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2035#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2036#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2158#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2159#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2129#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2000#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1963#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1964#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2041#L697 assume !(0 == start_simulation_~tmp~3#1); 1942#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1943#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2084#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2069#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2070#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2215#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2216#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2085#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2086#L678-2 [2021-12-19 19:15:46,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,303 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2021-12-19 19:15:46,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216625823] [2021-12-19 19:15:46,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,337 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216625823] [2021-12-19 19:15:46,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216625823] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,338 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,338 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742782048] [2021-12-19 19:15:46,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,339 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:46,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,339 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 2 times [2021-12-19 19:15:46,339 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482445110] [2021-12-19 19:15:46,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,340 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,370 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,371 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482445110] [2021-12-19 19:15:46,371 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482445110] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,371 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,371 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185574103] [2021-12-19 19:15:46,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,372 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:46,372 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:46,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:46,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:46,373 INFO L87 Difference]: Start difference. First operand 318 states and 474 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:46,439 INFO L93 Difference]: Finished difference Result 551 states and 816 transitions. [2021-12-19 19:15:46,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:46,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 816 transitions. [2021-12-19 19:15:46,443 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-19 19:15:46,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 816 transitions. [2021-12-19 19:15:46,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-19 19:15:46,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-19 19:15:46,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 816 transitions. [2021-12-19 19:15:46,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:46,448 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-19 19:15:46,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 816 transitions. [2021-12-19 19:15:46,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-19 19:15:46,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 816 transitions. [2021-12-19 19:15:46,467 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-19 19:15:46,467 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-19 19:15:46,467 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:15:46,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 816 transitions. [2021-12-19 19:15:46,469 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-19 19:15:46,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:46,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:46,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,475 INFO L791 eck$LassoCheckResult]: Stem: 3168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3124#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3129#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3013#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3014#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3115#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3096#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3097#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3106#L429 assume !(0 == ~M_E~0); 2922#L429-2 assume !(0 == ~T1_E~0); 2923#L434-1 assume !(0 == ~T2_E~0); 3051#L439-1 assume !(0 == ~T3_E~0); 3075#L444-1 assume !(0 == ~E_M~0); 3076#L449-1 assume !(0 == ~E_1~0); 2928#L454-1 assume !(0 == ~E_2~0); 2929#L459-1 assume !(0 == ~E_3~0); 2888#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2889#L208 assume 1 == ~m_pc~0; 3162#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3164#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2958#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2909#L531 assume !(0 != activate_threads_~tmp~1#1); 2910#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3023#L227 assume !(1 == ~t1_pc~0); 2907#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2908#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3107#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2926#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2927#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2959#L246 assume 1 == ~t2_pc~0; 2960#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3038#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3055#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3114#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3118#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2968#L265 assume !(1 == ~t3_pc~0); 2850#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2823#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3057#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2938#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2939#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 3111#L477-2 assume !(1 == ~T1_E~0); 3230#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3126#L487-1 assume !(1 == ~T3_E~0); 3228#L492-1 assume !(1 == ~E_M~0); 3227#L497-1 assume !(1 == ~E_1~0); 3225#L502-1 assume !(1 == ~E_2~0); 3223#L507-1 assume !(1 == ~E_3~0); 3020#L512-1 assume { :end_inline_reset_delta_events } true; 2967#L678-2 [2021-12-19 19:15:46,476 INFO L793 eck$LassoCheckResult]: Loop: 2967#L678-2 assume !false; 3101#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2854#L404 assume !false; 3021#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3022#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2892#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2893#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3156#L357 assume !(0 != eval_~tmp~0#1); 2825#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2826#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2937#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3169#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3099#L434-3 assume !(0 == ~T2_E~0); 3100#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2935#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2936#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2952#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2985#L459-3 assume !(0 == ~E_3~0); 2930#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2931#L208-15 assume 1 == ~m_pc~0; 3142#L209-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3084#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2917#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2918#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2953#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2954#L227-15 assume !(1 == ~t1_pc~0); 3154#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3136#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2851#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2852#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3095#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3077#L246-15 assume 1 == ~t2_pc~0; 2835#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2836#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3160#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2919#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2920#L265-15 assume 1 == ~t3_pc~0; 2996#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2998#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2979#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2974#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2975#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3121#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3085#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3086#L482-3 assume !(1 == ~T2_E~0); 2986#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2915#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2916#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3044#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3045#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3011#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2879#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2842#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2843#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2921#L697 assume !(0 == start_simulation_~tmp~3#1); 2821#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2822#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3245#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3243#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 3241#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3239#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3237#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2966#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2967#L678-2 [2021-12-19 19:15:46,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,476 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2021-12-19 19:15:46,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705114401] [2021-12-19 19:15:46,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705114401] [2021-12-19 19:15:46,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705114401] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:46,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092949963] [2021-12-19 19:15:46,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,531 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:46,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1916869251, now seen corresponding path program 1 times [2021-12-19 19:15:46,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363610807] [2021-12-19 19:15:46,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363610807] [2021-12-19 19:15:46,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363610807] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,590 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,591 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:46,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132823236] [2021-12-19 19:15:46,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,592 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:46,592 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:46,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:46,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:46,593 INFO L87 Difference]: Start difference. First operand 551 states and 816 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:46,639 INFO L93 Difference]: Finished difference Result 1023 states and 1493 transitions. [2021-12-19 19:15:46,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:46,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1023 states and 1493 transitions. [2021-12-19 19:15:46,648 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 957 [2021-12-19 19:15:46,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1023 states to 1023 states and 1493 transitions. [2021-12-19 19:15:46,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1023 [2021-12-19 19:15:46,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1023 [2021-12-19 19:15:46,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1023 states and 1493 transitions. [2021-12-19 19:15:46,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:46,656 INFO L681 BuchiCegarLoop]: Abstraction has 1023 states and 1493 transitions. [2021-12-19 19:15:46,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1023 states and 1493 transitions. [2021-12-19 19:15:46,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1023 to 969. [2021-12-19 19:15:46,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4643962848297214) internal successors, (1419), 968 states have internal predecessors, (1419), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1419 transitions. [2021-12-19 19:15:46,674 INFO L704 BuchiCegarLoop]: Abstraction has 969 states and 1419 transitions. [2021-12-19 19:15:46,674 INFO L587 BuchiCegarLoop]: Abstraction has 969 states and 1419 transitions. [2021-12-19 19:15:46,674 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:15:46,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1419 transitions. [2021-12-19 19:15:46,678 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 903 [2021-12-19 19:15:46,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:46,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:46,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,680 INFO L791 eck$LassoCheckResult]: Stem: 4746#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4697#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4704#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4596#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4597#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4687#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4668#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4669#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4676#L429 assume !(0 == ~M_E~0); 4504#L429-2 assume !(0 == ~T1_E~0); 4505#L434-1 assume !(0 == ~T2_E~0); 4625#L439-1 assume !(0 == ~T3_E~0); 4648#L444-1 assume !(0 == ~E_M~0); 4649#L449-1 assume !(0 == ~E_1~0); 4510#L454-1 assume !(0 == ~E_2~0); 4511#L459-1 assume !(0 == ~E_3~0); 4471#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4472#L208 assume !(1 == ~m_pc~0); 4741#L208-2 is_master_triggered_~__retres1~0#1 := 0; 4742#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4541#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4491#L531 assume !(0 != activate_threads_~tmp~1#1); 4492#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4602#L227 assume !(1 == ~t1_pc~0); 4489#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4490#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4677#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4508#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4509#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4542#L246 assume 1 == ~t2_pc~0; 4543#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4613#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4629#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4683#L547 assume !(0 != activate_threads_~tmp___1~0#1); 4692#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4553#L265 assume !(1 == ~t3_pc~0); 4433#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4406#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4407#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4631#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4522#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4523#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 4681#L477-2 assume !(1 == ~T1_E~0); 5118#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4699#L487-1 assume !(1 == ~T3_E~0); 5112#L492-1 assume !(1 == ~E_M~0); 5110#L497-1 assume !(1 == ~E_1~0); 5108#L502-1 assume !(1 == ~E_2~0); 5106#L507-1 assume !(1 == ~E_3~0); 5103#L512-1 assume { :end_inline_reset_delta_events } true; 5102#L678-2 [2021-12-19 19:15:46,681 INFO L793 eck$LassoCheckResult]: Loop: 5102#L678-2 assume !false; 5101#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5098#L404 assume !false; 5097#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4798#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4796#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4781#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4782#L357 assume !(0 != eval_~tmp~0#1); 5083#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5082#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5081#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4750#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4670#L434-3 assume !(0 == ~T2_E~0); 4671#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4708#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5326#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5325#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5324#L459-3 assume !(0 == ~E_3~0); 5323#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5322#L208-15 assume !(1 == ~m_pc~0); 5321#L208-17 is_master_triggered_~__retres1~0#1 := 0; 5320#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5319#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5318#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5317#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5316#L227-15 assume 1 == ~t1_pc~0; 5314#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5313#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5312#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5179#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5178#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5176#L246-15 assume 1 == ~t2_pc~0; 5173#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5171#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5169#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5167#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5164#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5162#L265-15 assume !(1 == ~t3_pc~0); 5159#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5157#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5156#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5154#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5152#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5150#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4719#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5147#L482-3 assume !(1 == ~T2_E~0); 4722#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5143#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5141#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5139#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5137#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5135#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5129#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5126#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5124#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 5120#L697 assume !(0 == start_simulation_~tmp~3#1); 5119#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5115#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5113#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5111#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 5109#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5107#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5105#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5104#L710 assume !(0 != start_simulation_~tmp___0~1#1); 5102#L678-2 [2021-12-19 19:15:46,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,685 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2021-12-19 19:15:46,685 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834632473] [2021-12-19 19:15:46,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,686 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834632473] [2021-12-19 19:15:46,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834632473] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,739 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,739 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:46,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [805438687] [2021-12-19 19:15:46,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:46,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,744 INFO L85 PathProgramCache]: Analyzing trace with hash 327802308, now seen corresponding path program 1 times [2021-12-19 19:15:46,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131077466] [2021-12-19 19:15:46,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,746 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:46,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:46,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:46,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131077466] [2021-12-19 19:15:46,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131077466] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:46,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:46,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:46,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093241507] [2021-12-19 19:15:46,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:46,794 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:46,795 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:46,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:46,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:46,796 INFO L87 Difference]: Start difference. First operand 969 states and 1419 transitions. cyclomatic complexity: 454 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:46,903 INFO L93 Difference]: Finished difference Result 2427 states and 3501 transitions. [2021-12-19 19:15:46,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:46,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2427 states and 3501 transitions. [2021-12-19 19:15:46,918 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2323 [2021-12-19 19:15:46,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2427 states to 2427 states and 3501 transitions. [2021-12-19 19:15:46,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2427 [2021-12-19 19:15:46,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2427 [2021-12-19 19:15:46,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2427 states and 3501 transitions. [2021-12-19 19:15:46,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:46,935 INFO L681 BuchiCegarLoop]: Abstraction has 2427 states and 3501 transitions. [2021-12-19 19:15:46,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2427 states and 3501 transitions. [2021-12-19 19:15:46,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2427 to 2343. [2021-12-19 19:15:46,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.4498506188647033) internal successors, (3397), 2342 states have internal predecessors, (3397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:46,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3397 transitions. [2021-12-19 19:15:46,973 INFO L704 BuchiCegarLoop]: Abstraction has 2343 states and 3397 transitions. [2021-12-19 19:15:46,973 INFO L587 BuchiCegarLoop]: Abstraction has 2343 states and 3397 transitions. [2021-12-19 19:15:46,973 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:15:46,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3397 transitions. [2021-12-19 19:15:46,982 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2263 [2021-12-19 19:15:46,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:46,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:46,983 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,983 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:46,983 INFO L791 eck$LassoCheckResult]: Stem: 8191#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 8119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8120#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8125#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8007#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 8008#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8110#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8092#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8093#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8101#L429 assume !(0 == ~M_E~0); 7914#L429-2 assume !(0 == ~T1_E~0); 7915#L434-1 assume !(0 == ~T2_E~0); 8040#L439-1 assume !(0 == ~T3_E~0); 8072#L444-1 assume !(0 == ~E_M~0); 8073#L449-1 assume !(0 == ~E_1~0); 7920#L454-1 assume !(0 == ~E_2~0); 7921#L459-1 assume !(0 == ~E_3~0); 7880#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7881#L208 assume !(1 == ~m_pc~0); 8180#L208-2 is_master_triggered_~__retres1~0#1 := 0; 8181#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7953#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7900#L531 assume !(0 != activate_threads_~tmp~1#1); 7901#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8014#L227 assume !(1 == ~t1_pc~0); 7898#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7899#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8102#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7918#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7919#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7954#L246 assume !(1 == ~t2_pc~0); 7955#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8046#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8047#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8108#L547 assume !(0 != activate_threads_~tmp___1~0#1); 8113#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7962#L265 assume !(1 == ~t3_pc~0); 7843#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7814#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7815#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8050#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7930#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7931#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 8106#L477-2 assume !(1 == ~T1_E~0); 8121#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8067#L487-1 assume !(1 == ~T3_E~0); 8068#L492-1 assume !(1 == ~E_M~0); 9643#L497-1 assume !(1 == ~E_1~0); 9641#L502-1 assume !(1 == ~E_2~0); 9639#L507-1 assume !(1 == ~E_3~0); 9637#L512-1 assume { :end_inline_reset_delta_events } true; 9628#L678-2 [2021-12-19 19:15:46,983 INFO L793 eck$LassoCheckResult]: Loop: 9628#L678-2 assume !false; 9538#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9533#L404 assume !false; 9530#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9515#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9509#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9504#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9500#L357 assume !(0 != eval_~tmp~0#1); 7816#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7817#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7929#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8157#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8095#L434-3 assume !(0 == ~T2_E~0); 8096#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7927#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7928#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7946#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9971#L459-3 assume !(0 == ~E_3~0); 9970#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8142#L208-15 assume !(1 == ~m_pc~0); 8079#L208-17 is_master_triggered_~__retres1~0#1 := 0; 8080#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7908#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7909#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7947#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7948#L227-15 assume !(1 == ~t1_pc~0); 9977#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 10052#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10051#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10050#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10049#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L246-15 assume !(1 == ~t2_pc~0); 10047#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 10046#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10045#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10044#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10043#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10042#L265-15 assume !(1 == ~t3_pc~0); 10040#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 8023#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7972#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7967#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7968#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8117#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8081#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8082#L482-3 assume !(1 == ~T2_E~0); 9874#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9872#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9870#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9868#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9864#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9862#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9813#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9807#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9802#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 9796#L697 assume !(0 == start_simulation_~tmp~3#1); 9795#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9785#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9780#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9775#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 9772#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9769#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9766#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9638#L710 assume !(0 != start_simulation_~tmp___0~1#1); 9628#L678-2 [2021-12-19 19:15:46,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:46,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2021-12-19 19:15:46,984 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:46,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700186004] [2021-12-19 19:15:46,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:46,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:46,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,005 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700186004] [2021-12-19 19:15:47,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700186004] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,006 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,006 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:47,006 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049790241] [2021-12-19 19:15:47,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,006 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:47,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,007 INFO L85 PathProgramCache]: Analyzing trace with hash 2089283462, now seen corresponding path program 1 times [2021-12-19 19:15:47,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10643953] [2021-12-19 19:15:47,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,033 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10643953] [2021-12-19 19:15:47,034 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10643953] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,034 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,034 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:47,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215075072] [2021-12-19 19:15:47,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,034 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:47,035 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:47,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:47,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:47,035 INFO L87 Difference]: Start difference. First operand 2343 states and 3397 transitions. cyclomatic complexity: 1062 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:47,066 INFO L93 Difference]: Finished difference Result 3421 states and 4961 transitions. [2021-12-19 19:15:47,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:47,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3421 states and 4961 transitions. [2021-12-19 19:15:47,100 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3333 [2021-12-19 19:15:47,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3421 states to 3421 states and 4961 transitions. [2021-12-19 19:15:47,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3421 [2021-12-19 19:15:47,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3421 [2021-12-19 19:15:47,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3421 states and 4961 transitions. [2021-12-19 19:15:47,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:47,123 INFO L681 BuchiCegarLoop]: Abstraction has 3421 states and 4961 transitions. [2021-12-19 19:15:47,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3421 states and 4961 transitions. [2021-12-19 19:15:47,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3421 to 2383. [2021-12-19 19:15:47,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2383 states, 2383 states have (on average 1.454049517415023) internal successors, (3465), 2382 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2383 states to 2383 states and 3465 transitions. [2021-12-19 19:15:47,163 INFO L704 BuchiCegarLoop]: Abstraction has 2383 states and 3465 transitions. [2021-12-19 19:15:47,163 INFO L587 BuchiCegarLoop]: Abstraction has 2383 states and 3465 transitions. [2021-12-19 19:15:47,163 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:15:47,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2383 states and 3465 transitions. [2021-12-19 19:15:47,171 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2311 [2021-12-19 19:15:47,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:47,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:47,172 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,172 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,173 INFO L791 eck$LassoCheckResult]: Stem: 13929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 13880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13881#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13885#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13775#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 13776#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13870#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13854#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13855#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13863#L429 assume !(0 == ~M_E~0); 13687#L429-2 assume !(0 == ~T1_E~0); 13688#L434-1 assume !(0 == ~T2_E~0); 13809#L439-1 assume !(0 == ~T3_E~0); 13833#L444-1 assume !(0 == ~E_M~0); 13834#L449-1 assume !(0 == ~E_1~0); 13693#L454-1 assume !(0 == ~E_2~0); 13694#L459-1 assume !(0 == ~E_3~0); 13654#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13655#L208 assume !(1 == ~m_pc~0); 13923#L208-2 is_master_triggered_~__retres1~0#1 := 0; 13924#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13724#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13674#L531 assume !(0 != activate_threads_~tmp~1#1); 13675#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13785#L227 assume !(1 == ~t1_pc~0); 13672#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13673#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13864#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13691#L539 assume !(0 != activate_threads_~tmp___0~0#1); 13692#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13725#L246 assume !(1 == ~t2_pc~0); 13726#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13813#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13814#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13869#L547 assume !(0 != activate_threads_~tmp___1~0#1); 13874#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13733#L265 assume !(1 == ~t3_pc~0); 13616#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13587#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13588#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13816#L555 assume !(0 != activate_threads_~tmp___2~0#1); 13703#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13704#L477 assume !(1 == ~M_E~0); 13868#L477-2 assume !(1 == ~T1_E~0); 13882#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13828#L487-1 assume !(1 == ~T3_E~0); 13829#L492-1 assume !(1 == ~E_M~0); 13659#L497-1 assume !(1 == ~E_1~0); 13660#L502-1 assume !(1 == ~E_2~0); 13641#L507-1 assume !(1 == ~E_3~0); 13642#L512-1 assume { :end_inline_reset_delta_events } true; 13783#L678-2 [2021-12-19 19:15:47,173 INFO L793 eck$LassoCheckResult]: Loop: 13783#L678-2 assume !false; 15744#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15738#L404 assume !false; 15736#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15734#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15730#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15728#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15725#L357 assume !(0 != eval_~tmp~0#1); 15723#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15720#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15718#L429-3 assume !(0 == ~M_E~0); 15716#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15714#L434-3 assume !(0 == ~T2_E~0); 15712#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15710#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15709#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15707#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15705#L459-3 assume !(0 == ~E_3~0); 15703#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15701#L208-15 assume !(1 == ~m_pc~0); 15699#L208-17 is_master_triggered_~__retres1~0#1 := 0; 15696#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15694#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15692#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15690#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15688#L227-15 assume !(1 == ~t1_pc~0); 15687#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 15686#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15685#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15684#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15683#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15682#L246-15 assume !(1 == ~t2_pc~0); 15681#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15677#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15675#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15673#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15671#L265-15 assume !(1 == ~t3_pc~0); 15668#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 15666#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15664#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15662#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15659#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15657#L477-3 assume !(1 == ~M_E~0); 14962#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15654#L482-3 assume !(1 == ~T2_E~0); 15652#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15650#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15647#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15645#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15643#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15641#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15633#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15630#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15628#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 15041#L697 assume !(0 == start_simulation_~tmp~3#1); 15042#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15759#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15757#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15754#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 15751#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15750#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15747#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 15746#L710 assume !(0 != start_simulation_~tmp___0~1#1); 13783#L678-2 [2021-12-19 19:15:47,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,173 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2021-12-19 19:15:47,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015468001] [2021-12-19 19:15:47,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,199 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015468001] [2021-12-19 19:15:47,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015468001] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,199 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:47,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054549291] [2021-12-19 19:15:47,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,200 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:47,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,200 INFO L85 PathProgramCache]: Analyzing trace with hash -906963002, now seen corresponding path program 1 times [2021-12-19 19:15:47,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91388333] [2021-12-19 19:15:47,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,201 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,230 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91388333] [2021-12-19 19:15:47,230 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91388333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,230 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,230 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:47,231 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919769035] [2021-12-19 19:15:47,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,231 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:47,231 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:47,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:47,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:47,232 INFO L87 Difference]: Start difference. First operand 2383 states and 3465 transitions. cyclomatic complexity: 1086 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:47,303 INFO L93 Difference]: Finished difference Result 3415 states and 4919 transitions. [2021-12-19 19:15:47,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:47,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3415 states and 4919 transitions. [2021-12-19 19:15:47,321 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3333 [2021-12-19 19:15:47,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3415 states to 3415 states and 4919 transitions. [2021-12-19 19:15:47,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3415 [2021-12-19 19:15:47,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3415 [2021-12-19 19:15:47,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3415 states and 4919 transitions. [2021-12-19 19:15:47,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:47,342 INFO L681 BuchiCegarLoop]: Abstraction has 3415 states and 4919 transitions. [2021-12-19 19:15:47,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3415 states and 4919 transitions. [2021-12-19 19:15:47,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3415 to 2383. [2021-12-19 19:15:47,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2383 states, 2383 states have (on average 1.4435585396558959) internal successors, (3440), 2382 states have internal predecessors, (3440), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2383 states to 2383 states and 3440 transitions. [2021-12-19 19:15:47,382 INFO L704 BuchiCegarLoop]: Abstraction has 2383 states and 3440 transitions. [2021-12-19 19:15:47,382 INFO L587 BuchiCegarLoop]: Abstraction has 2383 states and 3440 transitions. [2021-12-19 19:15:47,382 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:15:47,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2383 states and 3440 transitions. [2021-12-19 19:15:47,388 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2311 [2021-12-19 19:15:47,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:47,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:47,389 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,389 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,389 INFO L791 eck$LassoCheckResult]: Stem: 19743#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 19696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 19697#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19701#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19594#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 19595#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19687#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19671#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19672#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19679#L429 assume !(0 == ~M_E~0); 19496#L429-2 assume !(0 == ~T1_E~0); 19497#L434-1 assume !(0 == ~T2_E~0); 19623#L439-1 assume !(0 == ~T3_E~0); 19647#L444-1 assume !(0 == ~E_M~0); 19648#L449-1 assume !(0 == ~E_1~0); 19504#L454-1 assume !(0 == ~E_2~0); 19505#L459-1 assume !(0 == ~E_3~0); 19463#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19464#L208 assume !(1 == ~m_pc~0); 19734#L208-2 is_master_triggered_~__retres1~0#1 := 0; 19735#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19535#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19483#L531 assume !(0 != activate_threads_~tmp~1#1); 19484#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19599#L227 assume !(1 == ~t1_pc~0); 19481#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19482#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19680#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19500#L539 assume !(0 != activate_threads_~tmp___0~0#1); 19501#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19536#L246 assume !(1 == ~t2_pc~0); 19537#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19626#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19627#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19685#L547 assume !(0 != activate_threads_~tmp___1~0#1); 19692#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19545#L265 assume !(1 == ~t3_pc~0); 19426#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19397#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19398#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19631#L555 assume !(0 != activate_threads_~tmp___2~0#1); 19518#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19519#L477 assume !(1 == ~M_E~0); 19684#L477-2 assume !(1 == ~T1_E~0); 19698#L482-1 assume !(1 == ~T2_E~0); 19645#L487-1 assume !(1 == ~T3_E~0); 19646#L492-1 assume !(1 == ~E_M~0); 19471#L497-1 assume !(1 == ~E_1~0); 19472#L502-1 assume !(1 == ~E_2~0); 19453#L507-1 assume !(1 == ~E_3~0); 19454#L512-1 assume { :end_inline_reset_delta_events } true; 19596#L678-2 [2021-12-19 19:15:47,389 INFO L793 eck$LassoCheckResult]: Loop: 19596#L678-2 assume !false; 21182#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21176#L404 assume !false; 21174#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21159#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21143#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21140#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21137#L357 assume !(0 != eval_~tmp~0#1); 21135#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21133#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21131#L429-3 assume !(0 == ~M_E~0); 21129#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21126#L434-3 assume !(0 == ~T2_E~0); 21124#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21122#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21120#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21118#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21110#L459-3 assume !(0 == ~E_3~0); 21103#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21098#L208-15 assume !(1 == ~m_pc~0); 21090#L208-17 is_master_triggered_~__retres1~0#1 := 0; 21084#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21080#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21074#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21068#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21064#L227-15 assume !(1 == ~t1_pc~0); 21063#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21062#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21061#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21060#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21059#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21058#L246-15 assume !(1 == ~t2_pc~0); 21057#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21056#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21054#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21052#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21050#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21048#L265-15 assume !(1 == ~t3_pc~0); 21045#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21043#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21041#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21038#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21036#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21034#L477-3 assume !(1 == ~M_E~0); 20776#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21031#L482-3 assume !(1 == ~T2_E~0); 21029#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21028#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21026#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21024#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21022#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21020#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21010#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21007#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21005#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20858#L697 assume !(0 == start_simulation_~tmp~3#1); 20859#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21199#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21196#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21194#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 21192#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21190#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21189#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21185#L710 assume !(0 != start_simulation_~tmp___0~1#1); 19596#L678-2 [2021-12-19 19:15:47,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2021-12-19 19:15:47,390 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322834675] [2021-12-19 19:15:47,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:47,397 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:47,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:47,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:47,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,422 INFO L85 PathProgramCache]: Analyzing trace with hash -906963002, now seen corresponding path program 2 times [2021-12-19 19:15:47,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850596929] [2021-12-19 19:15:47,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850596929] [2021-12-19 19:15:47,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850596929] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:47,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425185128] [2021-12-19 19:15:47,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:47,449 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:47,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:47,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:47,449 INFO L87 Difference]: Start difference. First operand 2383 states and 3440 transitions. cyclomatic complexity: 1061 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:47,531 INFO L93 Difference]: Finished difference Result 4132 states and 5855 transitions. [2021-12-19 19:15:47,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:15:47,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4132 states and 5855 transitions. [2021-12-19 19:15:47,568 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4040 [2021-12-19 19:15:47,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4132 states to 4132 states and 5855 transitions. [2021-12-19 19:15:47,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4132 [2021-12-19 19:15:47,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4132 [2021-12-19 19:15:47,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4132 states and 5855 transitions. [2021-12-19 19:15:47,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:47,593 INFO L681 BuchiCegarLoop]: Abstraction has 4132 states and 5855 transitions. [2021-12-19 19:15:47,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4132 states and 5855 transitions. [2021-12-19 19:15:47,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4132 to 2419. [2021-12-19 19:15:47,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2419 states, 2419 states have (on average 1.4369574204216617) internal successors, (3476), 2418 states have internal predecessors, (3476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2419 states to 2419 states and 3476 transitions. [2021-12-19 19:15:47,641 INFO L704 BuchiCegarLoop]: Abstraction has 2419 states and 3476 transitions. [2021-12-19 19:15:47,641 INFO L587 BuchiCegarLoop]: Abstraction has 2419 states and 3476 transitions. [2021-12-19 19:15:47,641 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:15:47,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2419 states and 3476 transitions. [2021-12-19 19:15:47,647 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2347 [2021-12-19 19:15:47,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:47,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:47,648 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,648 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:47,649 INFO L791 eck$LassoCheckResult]: Stem: 26310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26240#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26244#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26123#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 26124#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26230#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26209#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26210#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26217#L429 assume !(0 == ~M_E~0); 26029#L429-2 assume !(0 == ~T1_E~0); 26030#L434-1 assume !(0 == ~T2_E~0); 26156#L439-1 assume !(0 == ~T3_E~0); 26186#L444-1 assume !(0 == ~E_M~0); 26187#L449-1 assume !(0 == ~E_1~0); 26037#L454-1 assume !(0 == ~E_2~0); 26038#L459-1 assume !(0 == ~E_3~0); 25996#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25997#L208 assume !(1 == ~m_pc~0); 26300#L208-2 is_master_triggered_~__retres1~0#1 := 0; 26301#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26067#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26016#L531 assume !(0 != activate_threads_~tmp~1#1); 26017#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26129#L227 assume !(1 == ~t1_pc~0); 26014#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26015#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26218#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26033#L539 assume !(0 != activate_threads_~tmp___0~0#1); 26034#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26068#L246 assume !(1 == ~t2_pc~0); 26069#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26161#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26162#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26227#L547 assume !(0 != activate_threads_~tmp___1~0#1); 26233#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26078#L265 assume !(1 == ~t3_pc~0); 25957#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25928#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25929#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26167#L555 assume !(0 != activate_threads_~tmp___2~0#1); 26051#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26052#L477 assume !(1 == ~M_E~0); 26223#L477-2 assume !(1 == ~T1_E~0); 26241#L482-1 assume !(1 == ~T2_E~0); 26184#L487-1 assume !(1 == ~T3_E~0); 26185#L492-1 assume !(1 == ~E_M~0); 26002#L497-1 assume !(1 == ~E_1~0); 26003#L502-1 assume !(1 == ~E_2~0); 25984#L507-1 assume !(1 == ~E_3~0); 25985#L512-1 assume { :end_inline_reset_delta_events } true; 26075#L678-2 [2021-12-19 19:15:47,649 INFO L793 eck$LassoCheckResult]: Loop: 26075#L678-2 assume !false; 26215#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25961#L404 assume !false; 28047#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28044#L320 assume !(0 == ~m_st~0); 28045#L324 assume !(0 == ~t1_st~0); 28041#L328 assume !(0 == ~t2_st~0); 28042#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28043#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27535#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27536#L357 assume !(0 != eval_~tmp~0#1); 25930#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25931#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26044#L429-3 assume !(0 == ~M_E~0); 26278#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26211#L434-3 assume !(0 == ~T2_E~0); 26212#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26042#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26043#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26093#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26094#L459-3 assume !(0 == ~E_3~0); 26035#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26036#L208-15 assume !(1 == ~m_pc~0); 26193#L208-17 is_master_triggered_~__retres1~0#1 := 0; 26194#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28209#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26165#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26166#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26294#L227-15 assume !(1 == ~t1_pc~0); 26295#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 28208#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25958#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25959#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26206#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26207#L246-15 assume !(1 == ~t2_pc~0); 28206#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 26268#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26269#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28205#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28204#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26222#L265-15 assume 1 == ~t3_pc~0; 26104#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26106#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26136#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28200#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28199#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26271#L477-3 assume !(1 == ~M_E~0); 26272#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28281#L482-3 assume !(1 == ~T2_E~0); 28279#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28277#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28275#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28273#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26202#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26118#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26119#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28317#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28315#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 28312#L697 assume !(0 == start_simulation_~tmp~3#1); 28307#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26270#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26073#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26058#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 26059#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26219#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26220#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 26074#L710 assume !(0 != start_simulation_~tmp___0~1#1); 26075#L678-2 [2021-12-19 19:15:47,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2021-12-19 19:15:47,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349164255] [2021-12-19 19:15:47,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:47,656 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:47,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:47,673 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:47,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:47,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1858993461, now seen corresponding path program 1 times [2021-12-19 19:15:47,674 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:47,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2294553] [2021-12-19 19:15:47,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:47,674 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:47,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:47,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:47,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:47,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2294553] [2021-12-19 19:15:47,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2294553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:47,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:47,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:47,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052116597] [2021-12-19 19:15:47,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:47,741 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:47,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:47,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:47,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:47,742 INFO L87 Difference]: Start difference. First operand 2419 states and 3476 transitions. cyclomatic complexity: 1061 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:47,912 INFO L93 Difference]: Finished difference Result 4762 states and 6781 transitions. [2021-12-19 19:15:47,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:15:47,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4762 states and 6781 transitions. [2021-12-19 19:15:47,930 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4682 [2021-12-19 19:15:47,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4762 states to 4762 states and 6781 transitions. [2021-12-19 19:15:47,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4762 [2021-12-19 19:15:47,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4762 [2021-12-19 19:15:47,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4762 states and 6781 transitions. [2021-12-19 19:15:47,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:47,955 INFO L681 BuchiCegarLoop]: Abstraction has 4762 states and 6781 transitions. [2021-12-19 19:15:47,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4762 states and 6781 transitions. [2021-12-19 19:15:47,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4762 to 2500. [2021-12-19 19:15:47,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2500 states, 2500 states have (on average 1.414) internal successors, (3535), 2499 states have internal predecessors, (3535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:47,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2500 states to 2500 states and 3535 transitions. [2021-12-19 19:15:47,999 INFO L704 BuchiCegarLoop]: Abstraction has 2500 states and 3535 transitions. [2021-12-19 19:15:47,999 INFO L587 BuchiCegarLoop]: Abstraction has 2500 states and 3535 transitions. [2021-12-19 19:15:48,000 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:15:48,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2500 states and 3535 transitions. [2021-12-19 19:15:48,006 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2428 [2021-12-19 19:15:48,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:48,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:48,007 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,007 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,007 INFO L791 eck$LassoCheckResult]: Stem: 33504#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 33437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 33438#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33443#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33316#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 33317#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33426#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33406#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33407#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33415#L429 assume !(0 == ~M_E~0); 33222#L429-2 assume !(0 == ~T1_E~0); 33223#L434-1 assume !(0 == ~T2_E~0); 33353#L439-1 assume !(0 == ~T3_E~0); 33383#L444-1 assume !(0 == ~E_M~0); 33384#L449-1 assume !(0 == ~E_1~0); 33228#L454-1 assume !(0 == ~E_2~0); 33229#L459-1 assume !(0 == ~E_3~0); 33190#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33191#L208 assume !(1 == ~m_pc~0); 33493#L208-2 is_master_triggered_~__retres1~0#1 := 0; 33494#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33258#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33209#L531 assume !(0 != activate_threads_~tmp~1#1); 33210#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33326#L227 assume !(1 == ~t1_pc~0); 33207#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33208#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33416#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33226#L539 assume !(0 != activate_threads_~tmp___0~0#1); 33227#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33259#L246 assume !(1 == ~t2_pc~0); 33260#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33358#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33359#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33423#L547 assume !(0 != activate_threads_~tmp___1~0#1); 33429#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33267#L265 assume !(1 == ~t3_pc~0); 33151#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33122#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33123#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33361#L555 assume !(0 != activate_threads_~tmp___2~0#1); 33238#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33239#L477 assume !(1 == ~M_E~0); 33422#L477-2 assume !(1 == ~T1_E~0); 33439#L482-1 assume !(1 == ~T2_E~0); 33378#L487-1 assume !(1 == ~T3_E~0); 33379#L492-1 assume !(1 == ~E_M~0); 33195#L497-1 assume !(1 == ~E_1~0); 33196#L502-1 assume !(1 == ~E_2~0); 33176#L507-1 assume !(1 == ~E_3~0); 33177#L512-1 assume { :end_inline_reset_delta_events } true; 33324#L678-2 [2021-12-19 19:15:48,007 INFO L793 eck$LassoCheckResult]: Loop: 33324#L678-2 assume !false; 34527#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34523#L404 assume !false; 34522#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34520#L320 assume !(0 == ~m_st~0); 34521#L324 assume !(0 == ~t1_st~0); 34517#L328 assume !(0 == ~t2_st~0); 34518#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 34519#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34380#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34381#L357 assume !(0 != eval_~tmp~0#1); 34620#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34619#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34618#L429-3 assume !(0 == ~M_E~0); 34617#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34616#L434-3 assume !(0 == ~T2_E~0); 34615#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34614#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34613#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34612#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34611#L459-3 assume !(0 == ~E_3~0); 33230#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33231#L208-15 assume !(1 == ~m_pc~0); 33459#L208-17 is_master_triggered_~__retres1~0#1 := 0; 34501#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34499#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34497#L531-15 assume !(0 != activate_threads_~tmp~1#1); 34495#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34493#L227-15 assume !(1 == ~t1_pc~0); 34491#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 34489#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34487#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34485#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34483#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34481#L246-15 assume !(1 == ~t2_pc~0); 34479#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 34477#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34475#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34473#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34471#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34469#L265-15 assume !(1 == ~t3_pc~0); 34466#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 34463#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34461#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34459#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34456#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34453#L477-3 assume !(1 == ~M_E~0); 34450#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34447#L482-3 assume !(1 == ~T2_E~0); 34444#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34441#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34438#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34435#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34432#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34429#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34391#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34383#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34377#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 33610#L697 assume !(0 == start_simulation_~tmp~3#1); 33611#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34546#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34542#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34540#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 34538#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34536#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34534#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 34530#L710 assume !(0 != start_simulation_~tmp___0~1#1); 33324#L678-2 [2021-12-19 19:15:48,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,008 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2021-12-19 19:15:48,008 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554261618] [2021-12-19 19:15:48,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,009 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,014 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,025 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,026 INFO L85 PathProgramCache]: Analyzing trace with hash 1187102926, now seen corresponding path program 1 times [2021-12-19 19:15:48,026 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440132522] [2021-12-19 19:15:48,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:48,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:48,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:48,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440132522] [2021-12-19 19:15:48,045 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440132522] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:48,045 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:48,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:48,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027499522] [2021-12-19 19:15:48,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:48,046 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:48,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:48,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:48,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:48,046 INFO L87 Difference]: Start difference. First operand 2500 states and 3535 transitions. cyclomatic complexity: 1039 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:48,107 INFO L93 Difference]: Finished difference Result 3810 states and 5295 transitions. [2021-12-19 19:15:48,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:48,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3810 states and 5295 transitions. [2021-12-19 19:15:48,122 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3736 [2021-12-19 19:15:48,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3810 states to 3810 states and 5295 transitions. [2021-12-19 19:15:48,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3810 [2021-12-19 19:15:48,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3810 [2021-12-19 19:15:48,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3810 states and 5295 transitions. [2021-12-19 19:15:48,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:48,147 INFO L681 BuchiCegarLoop]: Abstraction has 3810 states and 5295 transitions. [2021-12-19 19:15:48,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3810 states and 5295 transitions. [2021-12-19 19:15:48,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3810 to 3678. [2021-12-19 19:15:48,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3678 states, 3678 states have (on average 1.3923327895595432) internal successors, (5121), 3677 states have internal predecessors, (5121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3678 states to 3678 states and 5121 transitions. [2021-12-19 19:15:48,199 INFO L704 BuchiCegarLoop]: Abstraction has 3678 states and 5121 transitions. [2021-12-19 19:15:48,199 INFO L587 BuchiCegarLoop]: Abstraction has 3678 states and 5121 transitions. [2021-12-19 19:15:48,200 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:15:48,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3678 states and 5121 transitions. [2021-12-19 19:15:48,209 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3604 [2021-12-19 19:15:48,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:48,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:48,210 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,210 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,210 INFO L791 eck$LassoCheckResult]: Stem: 39812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 39755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39756#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39760#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39632#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 39633#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39743#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39725#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39726#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39734#L429 assume !(0 == ~M_E~0); 39538#L429-2 assume !(0 == ~T1_E~0); 39539#L434-1 assume !(0 == ~T2_E~0); 39675#L439-1 assume !(0 == ~T3_E~0); 39705#L444-1 assume !(0 == ~E_M~0); 39706#L449-1 assume !(0 == ~E_1~0); 39544#L454-1 assume !(0 == ~E_2~0); 39545#L459-1 assume !(0 == ~E_3~0); 39505#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39506#L208 assume !(1 == ~m_pc~0); 39803#L208-2 is_master_triggered_~__retres1~0#1 := 0; 39804#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39575#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 39525#L531 assume !(0 != activate_threads_~tmp~1#1); 39526#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39642#L227 assume !(1 == ~t1_pc~0); 39523#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39524#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39735#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39542#L539 assume !(0 != activate_threads_~tmp___0~0#1); 39543#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39576#L246 assume !(1 == ~t2_pc~0); 39577#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39681#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39682#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39741#L547 assume !(0 != activate_threads_~tmp___1~0#1); 39747#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39585#L265 assume !(1 == ~t3_pc~0); 39468#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39438#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39439#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39686#L555 assume !(0 != activate_threads_~tmp___2~0#1); 39554#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39555#L477 assume !(1 == ~M_E~0); 39740#L477-2 assume !(1 == ~T1_E~0); 39757#L482-1 assume !(1 == ~T2_E~0); 39700#L487-1 assume !(1 == ~T3_E~0); 39701#L492-1 assume !(1 == ~E_M~0); 39510#L497-1 assume !(1 == ~E_1~0); 39511#L502-1 assume !(1 == ~E_2~0); 39493#L507-1 assume !(1 == ~E_3~0); 39494#L512-1 assume { :end_inline_reset_delta_events } true; 39640#L678-2 assume !false; 40685#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40681#L404 [2021-12-19 19:15:48,210 INFO L793 eck$LassoCheckResult]: Loop: 40681#L404 assume !false; 40651#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40652#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40891#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40889#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40888#L357 assume 0 != eval_~tmp~0#1; 40886#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40880#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 40807#L362 assume !(0 == ~t1_st~0); 40802#L376 assume !(0 == ~t2_st~0); 40684#L390 assume !(0 == ~t3_st~0); 40681#L404 [2021-12-19 19:15:48,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,211 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2021-12-19 19:15:48,211 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185751009] [2021-12-19 19:15:48,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,212 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,221 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,241 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,242 INFO L85 PathProgramCache]: Analyzing trace with hash 257277008, now seen corresponding path program 1 times [2021-12-19 19:15:48,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384593630] [2021-12-19 19:15:48,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,245 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,248 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1138955338, now seen corresponding path program 1 times [2021-12-19 19:15:48,249 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121805691] [2021-12-19 19:15:48,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,249 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:48,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:48,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:48,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121805691] [2021-12-19 19:15:48,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121805691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:48,270 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:48,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:48,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813478404] [2021-12-19 19:15:48,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:48,360 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:48,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:48,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:48,360 INFO L87 Difference]: Start difference. First operand 3678 states and 5121 transitions. cyclomatic complexity: 1449 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:48,407 INFO L93 Difference]: Finished difference Result 6615 states and 9099 transitions. [2021-12-19 19:15:48,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:48,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6615 states and 9099 transitions. [2021-12-19 19:15:48,469 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 6120 [2021-12-19 19:15:48,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6615 states to 6615 states and 9099 transitions. [2021-12-19 19:15:48,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6615 [2021-12-19 19:15:48,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6615 [2021-12-19 19:15:48,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6615 states and 9099 transitions. [2021-12-19 19:15:48,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:48,531 INFO L681 BuchiCegarLoop]: Abstraction has 6615 states and 9099 transitions. [2021-12-19 19:15:48,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6615 states and 9099 transitions. [2021-12-19 19:15:48,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6615 to 6370. [2021-12-19 19:15:48,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6370 states, 6370 states have (on average 1.3789638932496076) internal successors, (8784), 6369 states have internal predecessors, (8784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6370 states to 6370 states and 8784 transitions. [2021-12-19 19:15:48,670 INFO L704 BuchiCegarLoop]: Abstraction has 6370 states and 8784 transitions. [2021-12-19 19:15:48,670 INFO L587 BuchiCegarLoop]: Abstraction has 6370 states and 8784 transitions. [2021-12-19 19:15:48,670 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:15:48,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6370 states and 8784 transitions. [2021-12-19 19:15:48,703 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5875 [2021-12-19 19:15:48,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:48,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:48,704 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,704 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,705 INFO L791 eck$LassoCheckResult]: Stem: 50173#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 50083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50084#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50089#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49935#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 49936#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 50090#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50038#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50039#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50121#L429 assume !(0 == ~M_E~0); 50122#L429-2 assume !(0 == ~T1_E~0); 49981#L434-1 assume !(0 == ~T2_E~0); 49982#L439-1 assume !(0 == ~T3_E~0); 50013#L444-1 assume !(0 == ~E_M~0); 50014#L449-1 assume !(0 == ~E_1~0); 49845#L454-1 assume !(0 == ~E_2~0); 49846#L459-1 assume !(0 == ~E_3~0); 49804#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49805#L208 assume !(1 == ~m_pc~0); 50160#L208-2 is_master_triggered_~__retres1~0#1 := 0; 50161#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49876#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49877#L531 assume !(0 != activate_threads_~tmp~1#1); 49966#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49967#L227 assume !(1 == ~t1_pc~0); 49824#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49825#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50053#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50054#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49844#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49878#L246 assume !(1 == ~t2_pc~0); 49879#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49985#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49986#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50074#L547 assume !(0 != activate_threads_~tmp___1~0#1); 50075#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49888#L265 assume !(1 == ~t3_pc~0); 49889#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49739#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49740#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50175#L555 assume !(0 != activate_threads_~tmp___2~0#1); 50176#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50058#L477 assume !(1 == ~M_E~0); 50059#L477-2 assume !(1 == ~T1_E~0); 50085#L482-1 assume !(1 == ~T2_E~0); 50086#L487-1 assume !(1 == ~T3_E~0); 50119#L492-1 assume !(1 == ~E_M~0); 50120#L497-1 assume !(1 == ~E_1~0); 49971#L502-1 assume !(1 == ~E_2~0); 49972#L507-1 assume !(1 == ~E_3~0); 49942#L512-1 assume { :end_inline_reset_delta_events } true; 49943#L678-2 assume !false; 50494#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50490#L404 [2021-12-19 19:15:48,705 INFO L793 eck$LassoCheckResult]: Loop: 50490#L404 assume !false; 50474#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 50475#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 50452#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 50453#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50439#L357 assume 0 != eval_~tmp~0#1; 50440#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 50424#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 50425#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 50408#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 50409#L376 assume !(0 == ~t2_st~0); 50493#L390 assume !(0 == ~t3_st~0); 50490#L404 [2021-12-19 19:15:48,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,705 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2021-12-19 19:15:48,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485160569] [2021-12-19 19:15:48,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,706 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:48,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:48,721 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:48,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485160569] [2021-12-19 19:15:48,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485160569] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:48,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:48,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:48,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479566844] [2021-12-19 19:15:48,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:48,722 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:48,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,722 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 1 times [2021-12-19 19:15:48,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624380117] [2021-12-19 19:15:48,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,725 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,728 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,805 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:48,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:48,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:48,806 INFO L87 Difference]: Start difference. First operand 6370 states and 8784 transitions. cyclomatic complexity: 2425 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:48,823 INFO L93 Difference]: Finished difference Result 4842 states and 6698 transitions. [2021-12-19 19:15:48,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:48,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4842 states and 6698 transitions. [2021-12-19 19:15:48,840 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4770 [2021-12-19 19:15:48,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4842 states to 4842 states and 6698 transitions. [2021-12-19 19:15:48,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4842 [2021-12-19 19:15:48,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4842 [2021-12-19 19:15:48,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4842 states and 6698 transitions. [2021-12-19 19:15:48,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:48,863 INFO L681 BuchiCegarLoop]: Abstraction has 4842 states and 6698 transitions. [2021-12-19 19:15:48,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4842 states and 6698 transitions. [2021-12-19 19:15:48,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4842 to 4842. [2021-12-19 19:15:48,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4842 states, 4842 states have (on average 1.3833126807104503) internal successors, (6698), 4841 states have internal predecessors, (6698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:48,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4842 states to 4842 states and 6698 transitions. [2021-12-19 19:15:48,914 INFO L704 BuchiCegarLoop]: Abstraction has 4842 states and 6698 transitions. [2021-12-19 19:15:48,914 INFO L587 BuchiCegarLoop]: Abstraction has 4842 states and 6698 transitions. [2021-12-19 19:15:48,914 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:15:48,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4842 states and 6698 transitions. [2021-12-19 19:15:48,924 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4770 [2021-12-19 19:15:48,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:48,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:48,925 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,925 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:48,925 INFO L791 eck$LassoCheckResult]: Stem: 61330#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 61277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 61278#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61282#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61163#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 61164#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61265#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61245#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61246#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61254#L429 assume !(0 == ~M_E~0); 61060#L429-2 assume !(0 == ~T1_E~0); 61061#L434-1 assume !(0 == ~T2_E~0); 61194#L439-1 assume !(0 == ~T3_E~0); 61220#L444-1 assume !(0 == ~E_M~0); 61221#L449-1 assume !(0 == ~E_1~0); 61068#L454-1 assume !(0 == ~E_2~0); 61069#L459-1 assume !(0 == ~E_3~0); 61025#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61026#L208 assume !(1 == ~m_pc~0); 61322#L208-2 is_master_triggered_~__retres1~0#1 := 0; 61323#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61099#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 61047#L531 assume !(0 != activate_threads_~tmp~1#1); 61048#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61168#L227 assume !(1 == ~t1_pc~0); 61045#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61046#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61255#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61064#L539 assume !(0 != activate_threads_~tmp___0~0#1); 61065#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61100#L246 assume !(1 == ~t2_pc~0); 61101#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61198#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61199#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61263#L547 assume !(0 != activate_threads_~tmp___1~0#1); 61271#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61112#L265 assume !(1 == ~t3_pc~0); 60986#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60957#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60958#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61203#L555 assume !(0 != activate_threads_~tmp___2~0#1); 61082#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61083#L477 assume !(1 == ~M_E~0); 61261#L477-2 assume !(1 == ~T1_E~0); 61279#L482-1 assume !(1 == ~T2_E~0); 61218#L487-1 assume !(1 == ~T3_E~0); 61219#L492-1 assume !(1 == ~E_M~0); 61034#L497-1 assume !(1 == ~E_1~0); 61035#L502-1 assume !(1 == ~E_2~0); 61012#L507-1 assume !(1 == ~E_3~0); 61013#L512-1 assume { :end_inline_reset_delta_events } true; 61165#L678-2 assume !false; 62716#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62710#L404 [2021-12-19 19:15:48,926 INFO L793 eck$LassoCheckResult]: Loop: 62710#L404 assume !false; 62708#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 62705#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 62702#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 62700#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62698#L357 assume 0 != eval_~tmp~0#1; 62695#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 62693#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 62691#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 62689#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 62690#L376 assume !(0 == ~t2_st~0); 62715#L390 assume !(0 == ~t3_st~0); 62710#L404 [2021-12-19 19:15:48,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2021-12-19 19:15:48,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288601715] [2021-12-19 19:15:48,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,932 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,941 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,941 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 2 times [2021-12-19 19:15:48,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,942 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763938840] [2021-12-19 19:15:48,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,944 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:48,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:48,947 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:48,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:48,947 INFO L85 PathProgramCache]: Analyzing trace with hash 943838511, now seen corresponding path program 1 times [2021-12-19 19:15:48,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:48,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954084017] [2021-12-19 19:15:48,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:48,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:48,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:48,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:48,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:48,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954084017] [2021-12-19 19:15:48,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954084017] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:48,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:48,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:48,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482811725] [2021-12-19 19:15:48,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:49,048 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:49,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:49,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:49,049 INFO L87 Difference]: Start difference. First operand 4842 states and 6698 transitions. cyclomatic complexity: 1862 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:49,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:49,102 INFO L93 Difference]: Finished difference Result 8547 states and 11753 transitions. [2021-12-19 19:15:49,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:49,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8547 states and 11753 transitions. [2021-12-19 19:15:49,172 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8467 [2021-12-19 19:15:49,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8547 states to 8547 states and 11753 transitions. [2021-12-19 19:15:49,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8547 [2021-12-19 19:15:49,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8547 [2021-12-19 19:15:49,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8547 states and 11753 transitions. [2021-12-19 19:15:49,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:49,210 INFO L681 BuchiCegarLoop]: Abstraction has 8547 states and 11753 transitions. [2021-12-19 19:15:49,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8547 states and 11753 transitions. [2021-12-19 19:15:49,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8547 to 8393. [2021-12-19 19:15:49,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8393 states, 8393 states have (on average 1.3769808173477898) internal successors, (11557), 8392 states have internal predecessors, (11557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:49,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8393 states to 8393 states and 11557 transitions. [2021-12-19 19:15:49,307 INFO L704 BuchiCegarLoop]: Abstraction has 8393 states and 11557 transitions. [2021-12-19 19:15:49,307 INFO L587 BuchiCegarLoop]: Abstraction has 8393 states and 11557 transitions. [2021-12-19 19:15:49,307 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:15:49,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8393 states and 11557 transitions. [2021-12-19 19:15:49,324 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8313 [2021-12-19 19:15:49,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:49,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:49,324 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:49,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:49,325 INFO L791 eck$LassoCheckResult]: Stem: 74736#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 74674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 74675#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74680#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74550#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 74551#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74664#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74645#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74646#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74654#L429 assume !(0 == ~M_E~0); 74452#L429-2 assume !(0 == ~T1_E~0); 74453#L434-1 assume !(0 == ~T2_E~0); 74586#L439-1 assume !(0 == ~T3_E~0); 74619#L444-1 assume !(0 == ~E_M~0); 74620#L449-1 assume !(0 == ~E_1~0); 74458#L454-1 assume !(0 == ~E_2~0); 74459#L459-1 assume !(0 == ~E_3~0); 74417#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74418#L208 assume !(1 == ~m_pc~0); 74724#L208-2 is_master_triggered_~__retres1~0#1 := 0; 74725#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74491#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74439#L531 assume !(0 != activate_threads_~tmp~1#1); 74440#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74561#L227 assume !(1 == ~t1_pc~0); 74437#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74438#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74655#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 74456#L539 assume !(0 != activate_threads_~tmp___0~0#1); 74457#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74492#L246 assume !(1 == ~t2_pc~0); 74493#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74594#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74595#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 74662#L547 assume !(0 != activate_threads_~tmp___1~0#1); 74669#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74500#L265 assume !(1 == ~t3_pc~0); 74381#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74354#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74355#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 74598#L555 assume !(0 != activate_threads_~tmp___2~0#1); 74468#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74469#L477 assume !(1 == ~M_E~0); 74661#L477-2 assume !(1 == ~T1_E~0); 74676#L482-1 assume !(1 == ~T2_E~0); 74614#L487-1 assume !(1 == ~T3_E~0); 74615#L492-1 assume !(1 == ~E_M~0); 74422#L497-1 assume !(1 == ~E_1~0); 74423#L502-1 assume !(1 == ~E_2~0); 74405#L507-1 assume !(1 == ~E_3~0); 74406#L512-1 assume { :end_inline_reset_delta_events } true; 74558#L678-2 assume !false; 77307#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77302#L404 [2021-12-19 19:15:49,325 INFO L793 eck$LassoCheckResult]: Loop: 77302#L404 assume !false; 77299#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 77296#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 77294#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 77292#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77290#L357 assume 0 != eval_~tmp~0#1; 77285#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 77283#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 77281#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 77131#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 76811#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 76621#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 76623#L390 assume !(0 == ~t3_st~0); 77302#L404 [2021-12-19 19:15:49,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:49,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2021-12-19 19:15:49,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:49,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919649724] [2021-12-19 19:15:49,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:49,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:49,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:49,334 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:49,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:49,344 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:49,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:49,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1990224393, now seen corresponding path program 1 times [2021-12-19 19:15:49,345 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:49,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447419489] [2021-12-19 19:15:49,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:49,346 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:49,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:49,349 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:49,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:49,353 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:49,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:49,355 INFO L85 PathProgramCache]: Analyzing trace with hash -805906575, now seen corresponding path program 1 times [2021-12-19 19:15:49,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:49,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246311753] [2021-12-19 19:15:49,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:49,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:49,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:49,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:49,380 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:49,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246311753] [2021-12-19 19:15:49,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246311753] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:49,380 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:49,380 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:49,381 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019257284] [2021-12-19 19:15:49,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:49,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:49,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:49,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:49,510 INFO L87 Difference]: Start difference. First operand 8393 states and 11557 transitions. cyclomatic complexity: 3170 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:49,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:49,583 INFO L93 Difference]: Finished difference Result 14004 states and 19181 transitions. [2021-12-19 19:15:49,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:49,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14004 states and 19181 transitions. [2021-12-19 19:15:49,644 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 13898 [2021-12-19 19:15:49,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14004 states to 14004 states and 19181 transitions. [2021-12-19 19:15:49,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14004 [2021-12-19 19:15:49,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14004 [2021-12-19 19:15:49,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14004 states and 19181 transitions. [2021-12-19 19:15:49,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:49,712 INFO L681 BuchiCegarLoop]: Abstraction has 14004 states and 19181 transitions. [2021-12-19 19:15:49,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14004 states and 19181 transitions. [2021-12-19 19:15:49,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14004 to 13764. [2021-12-19 19:15:49,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13764 states, 13764 states have (on average 1.3761261261261262) internal successors, (18941), 13763 states have internal predecessors, (18941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:49,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13764 states to 13764 states and 18941 transitions. [2021-12-19 19:15:49,985 INFO L704 BuchiCegarLoop]: Abstraction has 13764 states and 18941 transitions. [2021-12-19 19:15:49,986 INFO L587 BuchiCegarLoop]: Abstraction has 13764 states and 18941 transitions. [2021-12-19 19:15:49,986 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:15:49,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13764 states and 18941 transitions. [2021-12-19 19:15:50,037 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 13658 [2021-12-19 19:15:50,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:50,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:50,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:50,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:50,038 INFO L791 eck$LassoCheckResult]: Stem: 97164#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 97090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 97091#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97096#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96957#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 96958#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97075#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97057#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97058#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97066#L429 assume !(0 == ~M_E~0); 96857#L429-2 assume !(0 == ~T1_E~0); 96858#L434-1 assume !(0 == ~T2_E~0); 96997#L439-1 assume !(0 == ~T3_E~0); 97031#L444-1 assume !(0 == ~E_M~0); 97032#L449-1 assume !(0 == ~E_1~0); 96863#L454-1 assume !(0 == ~E_2~0); 96864#L459-1 assume !(0 == ~E_3~0); 96823#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96824#L208 assume !(1 == ~m_pc~0); 97149#L208-2 is_master_triggered_~__retres1~0#1 := 0; 97150#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96894#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 96844#L531 assume !(0 != activate_threads_~tmp~1#1); 96845#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96967#L227 assume !(1 == ~t1_pc~0); 96842#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96843#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97067#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 96861#L539 assume !(0 != activate_threads_~tmp___0~0#1); 96862#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96895#L246 assume !(1 == ~t2_pc~0); 96896#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 97003#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97004#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 97073#L547 assume !(0 != activate_threads_~tmp___1~0#1); 97082#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96905#L265 assume !(1 == ~t3_pc~0); 96786#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96759#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96760#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 97007#L555 assume !(0 != activate_threads_~tmp___2~0#1); 96873#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96874#L477 assume !(1 == ~M_E~0); 97072#L477-2 assume !(1 == ~T1_E~0); 97092#L482-1 assume !(1 == ~T2_E~0); 97026#L487-1 assume !(1 == ~T3_E~0); 97027#L492-1 assume !(1 == ~E_M~0); 96828#L497-1 assume !(1 == ~E_1~0); 96829#L502-1 assume !(1 == ~E_2~0); 96810#L507-1 assume !(1 == ~E_3~0); 96811#L512-1 assume { :end_inline_reset_delta_events } true; 96965#L678-2 assume !false; 101599#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101584#L404 [2021-12-19 19:15:50,039 INFO L793 eck$LassoCheckResult]: Loop: 101584#L404 assume !false; 101598#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 101596#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 101595#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 101594#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 101593#L357 assume 0 != eval_~tmp~0#1; 101592#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 101590#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 101589#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 101588#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 101587#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 101586#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 101585#L390 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 101091#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 101584#L404 [2021-12-19 19:15:50,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:50,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2021-12-19 19:15:50,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:50,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456988801] [2021-12-19 19:15:50,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:50,040 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:50,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,046 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:50,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,055 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:50,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:50,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1567417278, now seen corresponding path program 1 times [2021-12-19 19:15:50,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:50,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948843478] [2021-12-19 19:15:50,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:50,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:50,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,060 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:50,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:50,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:50,063 INFO L85 PathProgramCache]: Analyzing trace with hash 786696712, now seen corresponding path program 1 times [2021-12-19 19:15:50,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:50,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355932589] [2021-12-19 19:15:50,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:50,063 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:50,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,070 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:15:50,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:15:50,082 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:15:51,085 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.12 07:15:51 BoogieIcfgContainer [2021-12-19 19:15:51,086 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-19 19:15:51,086 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-19 19:15:51,086 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-19 19:15:51,086 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-19 19:15:51,087 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:45" (3/4) ... [2021-12-19 19:15:51,089 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-19 19:15:51,123 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-19 19:15:51,123 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-19 19:15:51,124 INFO L158 Benchmark]: Toolchain (without parser) took 6842.58ms. Allocated memory was 102.8MB in the beginning and 396.4MB in the end (delta: 293.6MB). Free memory was 72.2MB in the beginning and 214.2MB in the end (delta: -142.1MB). Peak memory consumption was 152.0MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,124 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 79.7MB. Free memory is still 44.5MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-19 19:15:51,125 INFO L158 Benchmark]: CACSL2BoogieTranslator took 273.06ms. Allocated memory is still 102.8MB. Free memory was 71.9MB in the beginning and 76.0MB in the end (delta: -4.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,125 INFO L158 Benchmark]: Boogie Procedure Inliner took 76.53ms. Allocated memory is still 102.8MB. Free memory was 76.0MB in the beginning and 72.4MB in the end (delta: 3.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,125 INFO L158 Benchmark]: Boogie Preprocessor took 85.20ms. Allocated memory is still 102.8MB. Free memory was 72.4MB in the beginning and 69.7MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,125 INFO L158 Benchmark]: RCFGBuilder took 708.51ms. Allocated memory is still 102.8MB. Free memory was 69.2MB in the beginning and 39.3MB in the end (delta: 29.9MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,126 INFO L158 Benchmark]: BuchiAutomizer took 5645.85ms. Allocated memory was 102.8MB in the beginning and 396.4MB in the end (delta: 293.6MB). Free memory was 39.3MB in the beginning and 217.4MB in the end (delta: -178.1MB). Peak memory consumption was 196.8MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,126 INFO L158 Benchmark]: Witness Printer took 37.44ms. Allocated memory is still 396.4MB. Free memory was 217.4MB in the beginning and 214.2MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:15:51,127 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 79.7MB. Free memory is still 44.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 273.06ms. Allocated memory is still 102.8MB. Free memory was 71.9MB in the beginning and 76.0MB in the end (delta: -4.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 76.53ms. Allocated memory is still 102.8MB. Free memory was 76.0MB in the beginning and 72.4MB in the end (delta: 3.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 85.20ms. Allocated memory is still 102.8MB. Free memory was 72.4MB in the beginning and 69.7MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 708.51ms. Allocated memory is still 102.8MB. Free memory was 69.2MB in the beginning and 39.3MB in the end (delta: 29.9MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 5645.85ms. Allocated memory was 102.8MB in the beginning and 396.4MB in the end (delta: 293.6MB). Free memory was 39.3MB in the beginning and 217.4MB in the end (delta: -178.1MB). Peak memory consumption was 196.8MB. Max. memory is 16.1GB. * Witness Printer took 37.44ms. Allocated memory is still 396.4MB. Free memory was 217.4MB in the beginning and 214.2MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13764 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.5s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.3s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.9s AutomataMinimizationTime, 15 MinimizatonAttempts, 6954 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had 13764 states and ocurred in iteration 15. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9160 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9160 mSDsluCounter, 14339 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6968 mSDsCounter, 156 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 340 IncrementalHoareTripleChecker+Invalid, 496 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 156 mSolverCounterUnsat, 7371 mSDtfsCounter, 340 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@366cd98=0, token=0, NULL=1, tmp=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@336cbac5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@276b875=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41e33260=0, tmp_ndt_2=0, E_3=2, E_1=2, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@412529e7=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17e067fc=0, m_st=0, NULL=0, t3_pc=0, __retres1=0, tmp___0=0, tmp___2=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c889d16=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d336909=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d062bc=0, __retres1=0, M_E=2, __retres1=1, t2_i=1, \result=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cb4f87=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16d4edb0=0, t1_st=0, __retres1=0, local=0, t2_pc=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) [L434] COND FALSE !(T1_E == 0) [L439] COND FALSE !(T2_E == 0) [L444] COND FALSE !(T3_E == 0) [L449] COND FALSE !(E_M == 0) [L454] COND FALSE !(E_1 == 0) [L459] COND FALSE !(E_2 == 0) [L464] COND FALSE !(E_3 == 0) [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; [L208] COND FALSE !(m_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; [L227] COND FALSE !(t1_pc == 1) [L237] __retres1 = 0 [L239] return (__retres1); [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; [L246] COND FALSE !(t2_pc == 1) [L256] __retres1 = 0 [L258] return (__retres1); [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; [L265] COND FALSE !(t3_pc == 1) [L275] __retres1 = 0 [L277] return (__retres1); [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) [L482] COND FALSE !(T1_E == 1) [L487] COND FALSE !(T2_E == 1) [L492] COND FALSE !(T3_E == 1) [L497] COND FALSE !(E_M == 1) [L502] COND FALSE !(E_1 == 1) [L507] COND FALSE !(E_2 == 1) [L512] COND FALSE !(E_3 == 1) [L675] RET reset_delta_events() [L678] COND TRUE 1 [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-19 19:15:51,171 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)