./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:15:50,746 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:15:50,774 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:15:50,800 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:15:50,801 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:15:50,803 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:15:50,804 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:15:50,808 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:15:50,809 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:15:50,811 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:15:50,811 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:15:50,812 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:15:50,813 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:15:50,816 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:15:50,817 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:15:50,818 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:15:50,819 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:15:50,821 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:15:50,822 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:15:50,824 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:15:50,827 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:15:50,828 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:15:50,829 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:15:50,829 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:15:50,844 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:15:50,845 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:15:50,845 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:15:50,846 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:15:50,847 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:15:50,847 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:15:50,848 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:15:50,849 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:15:50,850 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:15:50,851 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:15:50,852 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:15:50,852 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:15:50,853 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:15:50,853 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:15:50,853 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:15:50,853 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:15:50,854 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:15:50,855 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:15:50,885 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:15:50,885 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:15:50,885 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:15:50,886 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:15:50,887 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:15:50,887 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:15:50,887 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:15:50,887 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:15:50,887 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:15:50,887 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:15:50,888 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:15:50,888 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:15:50,888 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:15:50,889 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:15:50,889 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:15:50,890 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:15:50,891 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:15:50,891 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:15:50,891 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:15:50,891 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:15:50,891 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:15:50,892 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:15:50,892 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:15:50,893 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2021-12-19 19:15:51,069 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:15:51,092 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:15:51,094 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:15:51,094 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:15:51,095 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:15:51,096 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2021-12-19 19:15:51,157 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86f29b209/196026e30a6f4d8f8d9450e250081ece/FLAGbe2f0ad99 [2021-12-19 19:15:51,498 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:15:51,506 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2021-12-19 19:15:51,514 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86f29b209/196026e30a6f4d8f8d9450e250081ece/FLAGbe2f0ad99 [2021-12-19 19:15:51,525 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86f29b209/196026e30a6f4d8f8d9450e250081ece [2021-12-19 19:15:51,527 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:15:51,529 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:15:51,539 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:51,539 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:15:51,541 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:15:51,542 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,542 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@706270d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51, skipping insertion in model container [2021-12-19 19:15:51,542 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,547 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:15:51,568 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:15:51,693 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2021-12-19 19:15:51,760 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:51,767 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:15:51,774 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2021-12-19 19:15:51,800 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:51,810 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:15:51,811 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51 WrapperNode [2021-12-19 19:15:51,811 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:51,812 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:51,812 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:15:51,812 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:15:51,817 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,823 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,884 INFO L137 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1662 [2021-12-19 19:15:51,884 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:51,885 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:15:51,885 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:15:51,885 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:15:51,891 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,891 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,907 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,908 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,925 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,949 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,964 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,968 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:15:51,969 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:15:51,969 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:15:51,969 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:15:51,970 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (1/1) ... [2021-12-19 19:15:51,974 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:15:51,993 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:15:52,019 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:15:52,021 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:15:52,057 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:15:52,057 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:15:52,061 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:15:52,061 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:15:52,123 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:15:52,124 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:15:52,889 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:15:52,904 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:15:52,904 INFO L301 CfgBuilder]: Removed 9 assume(true) statements. [2021-12-19 19:15:52,907 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:52 BoogieIcfgContainer [2021-12-19 19:15:52,907 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:15:52,908 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:15:52,908 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:15:52,910 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:15:52,911 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:52,911 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:15:51" (1/3) ... [2021-12-19 19:15:52,912 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a19a155 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:52, skipping insertion in model container [2021-12-19 19:15:52,912 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:52,912 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:51" (2/3) ... [2021-12-19 19:15:52,912 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a19a155 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:52, skipping insertion in model container [2021-12-19 19:15:52,913 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:52,913 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:52" (3/3) ... [2021-12-19 19:15:52,914 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2021-12-19 19:15:52,948 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:15:52,948 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:15:52,948 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:15:52,948 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:15:52,948 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:15:52,948 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:15:52,948 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:15:52,949 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:15:52,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2021-12-19 19:15:53,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:53,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:53,022 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,022 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,022 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:15:53,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2021-12-19 19:15:53,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:53,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:53,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,036 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,067 INFO L791 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 558#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 487#L1028true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 400#L480true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 514#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 125#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 261#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 47#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 143#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 33#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 113#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 532#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 217#L696true assume !(0 == ~M_E~0); 526#L696-2true assume !(0 == ~T1_E~0); 529#L701-1true assume !(0 == ~T2_E~0); 557#L706-1true assume !(0 == ~T3_E~0); 299#L711-1true assume !(0 == ~T4_E~0); 145#L716-1true assume !(0 == ~T5_E~0); 577#L721-1true assume !(0 == ~T6_E~0); 266#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 463#L731-1true assume !(0 == ~E_1~0); 242#L736-1true assume !(0 == ~E_2~0); 309#L741-1true assume !(0 == ~E_3~0); 618#L746-1true assume !(0 == ~E_4~0); 166#L751-1true assume !(0 == ~E_5~0); 227#L756-1true assume !(0 == ~E_6~0); 142#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L346true assume !(1 == ~m_pc~0); 174#L346-2true is_master_triggered_~__retres1~0#1 := 0; 413#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12#L358true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 546#L861true assume !(0 != activate_threads_~tmp~1#1); 461#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70#L365true assume 1 == ~t1_pc~0; 132#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 508#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 488#L377true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66#L869true assume !(0 != activate_threads_~tmp___0~0#1); 361#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 492#L384true assume !(1 == ~t2_pc~0); 356#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 620#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111#L396true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 231#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228#L403true assume 1 == ~t3_pc~0; 146#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 673#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137#L415true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 410#L885true assume !(0 != activate_threads_~tmp___2~0#1); 221#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 427#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 359#L434true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 438#L893true assume !(0 != activate_threads_~tmp___3~0#1); 286#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34#L441true assume !(1 == ~t5_pc~0); 453#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 608#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560#L453true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 691#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 417#L460true assume 1 == ~t6_pc~0; 5#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 549#L472true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414#L909true assume !(0 != activate_threads_~tmp___5~0#1); 542#L909-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274#L774true assume !(1 == ~M_E~0); 582#L774-2true assume !(1 == ~T1_E~0); 431#L779-1true assume !(1 == ~T2_E~0); 204#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 578#L789-1true assume !(1 == ~T4_E~0); 62#L794-1true assume !(1 == ~T5_E~0); 657#L799-1true assume !(1 == ~T6_E~0); 593#L804-1true assume !(1 == ~E_M~0); 650#L809-1true assume !(1 == ~E_1~0); 263#L814-1true assume !(1 == ~E_2~0); 13#L819-1true assume !(1 == ~E_3~0); 319#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 639#L829-1true assume !(1 == ~E_5~0); 420#L834-1true assume !(1 == ~E_6~0); 133#L839-1true assume { :end_inline_reset_delta_events } true; 127#L1065-2true [2021-12-19 19:15:53,068 INFO L793 eck$LassoCheckResult]: Loop: 127#L1065-2true assume !false; 336#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 475#L671true assume false; 597#L686true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326#L480-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 572#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 192#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 665#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 541#L711-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 527#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 315#L721-3true assume !(0 == ~T6_E~0); 178#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 303#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 501#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 304#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 140#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 223#L751-3true assume 0 == ~E_5~0;~E_5~0 := 1; 421#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 76#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L346-24true assume !(1 == ~m_pc~0); 136#L346-26true is_master_triggered_~__retres1~0#1 := 0; 305#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534#L358-8true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 489#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109#L365-24true assume !(1 == ~t1_pc~0); 687#L365-26true is_transmit1_triggered_~__retres1~1#1 := 0; 646#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216#L377-8true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 385#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 576#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84#L384-24true assume 1 == ~t2_pc~0; 694#L385-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 631#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 491#L396-8true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 295#L877-24true assume !(0 != activate_threads_~tmp___1~0#1); 97#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168#L403-24true assume !(1 == ~t3_pc~0); 587#L403-26true is_transmit3_triggered_~__retres1~3#1 := 0; 193#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 626#L415-8true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 566#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126#L422-24true assume !(1 == ~t4_pc~0); 289#L422-26true is_transmit4_triggered_~__retres1~4#1 := 0; 102#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 609#L434-8true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 531#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 436#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134#L441-24true assume !(1 == ~t5_pc~0); 288#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 280#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373#L453-8true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67#L901-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 367#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364#L460-24true assume !(1 == ~t6_pc~0); 432#L460-26true is_transmit6_triggered_~__retres1~6#1 := 0; 679#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 395#L472-8true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 452#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 357#L909-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 628#L774-3true assume 1 == ~M_E~0;~M_E~0 := 2; 294#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 177#L779-3true assume !(1 == ~T2_E~0); 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 678#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 14#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 71#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 278#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 510#L809-3true assume 1 == ~E_1~0;~E_1~0 := 2; 69#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 215#L819-3true assume !(1 == ~E_3~0); 151#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 139#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 342#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 61#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 440#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 267#L568-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32#L1084true assume !(0 == start_simulation_~tmp~3#1); 478#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 164#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 82#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 383#L568-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 167#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75#L1047true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 171#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 127#L1065-2true [2021-12-19 19:15:53,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,072 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2021-12-19 19:15:53,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095009825] [2021-12-19 19:15:53,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095009825] [2021-12-19 19:15:53,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095009825] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,203 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,204 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948279204] [2021-12-19 19:15:53,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,224 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:53,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,224 INFO L85 PathProgramCache]: Analyzing trace with hash -1299006910, now seen corresponding path program 1 times [2021-12-19 19:15:53,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355388427] [2021-12-19 19:15:53,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355388427] [2021-12-19 19:15:53,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355388427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,263 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:53,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364120030] [2021-12-19 19:15:53,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,264 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:53,264 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:53,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:53,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:53,308 INFO L87 Difference]: Start difference. First operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:53,397 INFO L93 Difference]: Finished difference Result 692 states and 1034 transitions. [2021-12-19 19:15:53,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:53,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 692 states and 1034 transitions. [2021-12-19 19:15:53,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 692 states to 686 states and 1028 transitions. [2021-12-19 19:15:53,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:53,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:53,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1028 transitions. [2021-12-19 19:15:53,429 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:53,429 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2021-12-19 19:15:53,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1028 transitions. [2021-12-19 19:15:53,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:53,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1028 transitions. [2021-12-19 19:15:53,467 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2021-12-19 19:15:53,467 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2021-12-19 19:15:53,467 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:15:53,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1028 transitions. [2021-12-19 19:15:53,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:53,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:53,474 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,477 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,478 INFO L791 eck$LassoCheckResult]: Stem: 2080#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2033#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1979#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1980#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1644#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1645#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1494#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1495#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1461#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1622#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1782#L696 assume !(0 == ~M_E~0); 1783#L696-2 assume !(0 == ~T1_E~0); 2048#L701-1 assume !(0 == ~T2_E~0); 2050#L706-1 assume !(0 == ~T3_E~0); 1893#L711-1 assume !(0 == ~T4_E~0); 1678#L716-1 assume !(0 == ~T5_E~0); 1679#L721-1 assume !(0 == ~T6_E~0); 1849#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1850#L731-1 assume !(0 == ~E_1~0); 1821#L736-1 assume !(0 == ~E_2~0); 1822#L741-1 assume !(0 == ~E_3~0); 1900#L746-1 assume !(0 == ~E_4~0); 1712#L751-1 assume !(0 == ~E_5~0); 1713#L756-1 assume !(0 == ~E_6~0); 1675#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1509#L346 assume !(1 == ~m_pc~0); 1510#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1723#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1419#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1420#L861 assume !(0 != activate_threads_~tmp~1#1); 2020#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541#L365 assume 1 == ~t1_pc~0; 1542#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1662#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2036#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1531#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1532#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1947#L384 assume !(1 == ~t2_pc~0); 1939#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1940#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1618#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1443#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1444#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1800#L403 assume 1 == ~t3_pc~0; 1680#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1681#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1671#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1672#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1793#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1794#L422 assume 1 == ~t4_pc~0; 1440#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1441#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1944#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1877#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1463#L441 assume !(1 == ~t5_pc~0); 1464#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2017#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2060#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2061#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1886#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1887#L460 assume 1 == ~t6_pc~0; 1403#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1404#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1471#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1988#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1989#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1859#L774 assume !(1 == ~M_E~0); 1860#L774-2 assume !(1 == ~T1_E~0); 2003#L779-1 assume !(1 == ~T2_E~0); 1764#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1765#L789-1 assume !(1 == ~T4_E~0); 1525#L794-1 assume !(1 == ~T5_E~0); 1526#L799-1 assume !(1 == ~T6_E~0); 2071#L804-1 assume !(1 == ~E_M~0); 2072#L809-1 assume !(1 == ~E_1~0); 1847#L814-1 assume !(1 == ~E_2~0); 1421#L819-1 assume !(1 == ~E_3~0); 1422#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1907#L829-1 assume !(1 == ~E_5~0); 1995#L834-1 assume !(1 == ~E_6~0); 1663#L839-1 assume { :end_inline_reset_delta_events } true; 1649#L1065-2 [2021-12-19 19:15:53,478 INFO L793 eck$LassoCheckResult]: Loop: 1649#L1065-2 assume !false; 1650#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1702#L671 assume !false; 2029#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1975#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1512#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1923#L582 assume !(0 != eval_~tmp~0#1); 2073#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1910#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1698#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1699#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1744#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1745#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2054#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2049#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1903#L721-3 assume !(0 == ~T6_E~0); 1727#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1728#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1897#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1898#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1673#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1674#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1795#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1551#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1552#L346-24 assume 1 == ~m_pc~0; 1585#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1666#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1899#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2037#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2001#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1613#L365-24 assume 1 == ~t1_pc~0; 1614#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1902#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1780#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1781#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1966#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L384-24 assume !(1 == ~t2_pc~0); 1568#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1587#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2038#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1888#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1592#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1593#L403-24 assume 1 == ~t3_pc~0; 1715#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1746#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1747#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1845#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1846#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1646#L422-24 assume 1 == ~t4_pc~0; 1648#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1599#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2051#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2009#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1659#L441-24 assume 1 == ~t5_pc~0; 1660#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1865#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1866#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1533#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1534#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1948#L460-24 assume !(1 == ~t6_pc~0); 1949#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2004#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1977#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1978#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1937#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1938#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1885#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1726#L779-3 assume !(1 == ~T2_E~0); 1438#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1439#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1417#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1418#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1540#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1864#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1539#L819-3 assume !(1 == ~E_3~0); 1688#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1669#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1670#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1523#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1524#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1521#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1609#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1456#L1084 assume !(0 == start_simulation_~tmp~3#1); 1458#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1708#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1424#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1563#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1714#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1556#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1549#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1550#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1649#L1065-2 [2021-12-19 19:15:53,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,479 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2021-12-19 19:15:53,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833979481] [2021-12-19 19:15:53,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833979481] [2021-12-19 19:15:53,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833979481] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,558 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609854631] [2021-12-19 19:15:53,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,559 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:53,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1167110331, now seen corresponding path program 1 times [2021-12-19 19:15:53,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004744194] [2021-12-19 19:15:53,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004744194] [2021-12-19 19:15:53,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004744194] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,642 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338545977] [2021-12-19 19:15:53,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:53,642 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:53,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:53,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:53,643 INFO L87 Difference]: Start difference. First operand 686 states and 1028 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:53,692 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2021-12-19 19:15:53,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:53,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1027 transitions. [2021-12-19 19:15:53,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1027 transitions. [2021-12-19 19:15:53,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:53,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:53,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1027 transitions. [2021-12-19 19:15:53,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:53,708 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2021-12-19 19:15:53,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1027 transitions. [2021-12-19 19:15:53,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:53,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1027 transitions. [2021-12-19 19:15:53,723 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2021-12-19 19:15:53,723 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2021-12-19 19:15:53,723 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:15:53,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1027 transitions. [2021-12-19 19:15:53,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:53,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:53,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,732 INFO L791 eck$LassoCheckResult]: Stem: 3459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3412#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3358#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3359#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3023#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3024#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2871#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2872#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2840#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2841#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3001#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3161#L696 assume !(0 == ~M_E~0); 3162#L696-2 assume !(0 == ~T1_E~0); 3427#L701-1 assume !(0 == ~T2_E~0); 3429#L706-1 assume !(0 == ~T3_E~0); 3272#L711-1 assume !(0 == ~T4_E~0); 3057#L716-1 assume !(0 == ~T5_E~0); 3058#L721-1 assume !(0 == ~T6_E~0); 3228#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3229#L731-1 assume !(0 == ~E_1~0); 3200#L736-1 assume !(0 == ~E_2~0); 3201#L741-1 assume !(0 == ~E_3~0); 3279#L746-1 assume !(0 == ~E_4~0); 3091#L751-1 assume !(0 == ~E_5~0); 3092#L756-1 assume !(0 == ~E_6~0); 3054#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2888#L346 assume !(1 == ~m_pc~0); 2889#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3102#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2796#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2797#L861 assume !(0 != activate_threads_~tmp~1#1); 3399#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2919#L365 assume 1 == ~t1_pc~0; 2920#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3038#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3413#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2910#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2911#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3326#L384 assume !(1 == ~t2_pc~0); 3316#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3317#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2997#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2822#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2823#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3178#L403 assume 1 == ~t3_pc~0; 3059#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3060#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3046#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3047#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3169#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3170#L422 assume 1 == ~t4_pc~0; 2817#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2818#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3322#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3323#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3256#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2842#L441 assume !(1 == ~t5_pc~0); 2843#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3396#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3439#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3440#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3264#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3265#L460 assume 1 == ~t6_pc~0; 2779#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2780#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2850#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3367#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3368#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3238#L774 assume !(1 == ~M_E~0); 3239#L774-2 assume !(1 == ~T1_E~0); 3382#L779-1 assume !(1 == ~T2_E~0); 3143#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3144#L789-1 assume !(1 == ~T4_E~0); 2904#L794-1 assume !(1 == ~T5_E~0); 2905#L799-1 assume !(1 == ~T6_E~0); 3450#L804-1 assume !(1 == ~E_M~0); 3451#L809-1 assume !(1 == ~E_1~0); 3226#L814-1 assume !(1 == ~E_2~0); 2798#L819-1 assume !(1 == ~E_3~0); 2799#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3286#L829-1 assume !(1 == ~E_5~0); 3374#L834-1 assume !(1 == ~E_6~0); 3039#L839-1 assume { :end_inline_reset_delta_events } true; 3028#L1065-2 [2021-12-19 19:15:53,733 INFO L793 eck$LassoCheckResult]: Loop: 3028#L1065-2 assume !false; 3029#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3081#L671 assume !false; 3408#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3354#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2881#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2891#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3301#L582 assume !(0 != eval_~tmp~0#1); 3452#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3289#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3077#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3078#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3123#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3124#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3433#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3428#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3281#L721-3 assume !(0 == ~T6_E~0); 3106#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3107#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3276#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3277#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3052#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3053#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3174#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2930#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2931#L346-24 assume 1 == ~m_pc~0; 2961#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3045#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3278#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3414#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3380#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2992#L365-24 assume 1 == ~t1_pc~0; 2993#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3282#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3159#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3160#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3346#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2946#L384-24 assume !(1 == ~t2_pc~0); 2947#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3417#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3267#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 2972#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2973#L403-24 assume 1 == ~t3_pc~0; 3094#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3125#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3126#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3224#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3225#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3025#L422-24 assume !(1 == ~t4_pc~0); 3026#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2979#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2980#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3430#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3388#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3040#L441-24 assume 1 == ~t5_pc~0; 3041#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3245#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3246#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2912#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2913#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3327#L460-24 assume !(1 == ~t6_pc~0); 3328#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 3383#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3356#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3357#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3318#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3319#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3266#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3105#L779-3 assume !(1 == ~T2_E~0); 2820#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2821#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2800#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2801#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2922#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3243#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2917#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2918#L819-3 assume !(1 == ~E_3~0); 3067#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3050#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3051#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2902#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2903#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2900#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2988#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2837#L1084 assume !(0 == start_simulation_~tmp~3#1); 2839#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3087#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2803#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2942#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3093#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2936#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2928#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2929#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3028#L1065-2 [2021-12-19 19:15:53,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,736 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2021-12-19 19:15:53,737 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146683165] [2021-12-19 19:15:53,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,738 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146683165] [2021-12-19 19:15:53,785 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146683165] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,789 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767060354] [2021-12-19 19:15:53,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,802 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:53,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,803 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 1 times [2021-12-19 19:15:53,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,803 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343468955] [2021-12-19 19:15:53,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343468955] [2021-12-19 19:15:53,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343468955] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,873 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501421381] [2021-12-19 19:15:53,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,874 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:53,874 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:53,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:53,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:53,875 INFO L87 Difference]: Start difference. First operand 686 states and 1027 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:53,887 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2021-12-19 19:15:53,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:53,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1026 transitions. [2021-12-19 19:15:53,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1026 transitions. [2021-12-19 19:15:53,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:53,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:53,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1026 transitions. [2021-12-19 19:15:53,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:53,897 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2021-12-19 19:15:53,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1026 transitions. [2021-12-19 19:15:53,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:53,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:53,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1026 transitions. [2021-12-19 19:15:53,906 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2021-12-19 19:15:53,906 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2021-12-19 19:15:53,906 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:15:53,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1026 transitions. [2021-12-19 19:15:53,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:53,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:53,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:53,915 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,915 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:53,916 INFO L791 eck$LassoCheckResult]: Stem: 4838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4816#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4791#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4737#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4738#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4402#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4403#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4250#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4251#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4219#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4220#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4380#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4540#L696 assume !(0 == ~M_E~0); 4541#L696-2 assume !(0 == ~T1_E~0); 4806#L701-1 assume !(0 == ~T2_E~0); 4808#L706-1 assume !(0 == ~T3_E~0); 4651#L711-1 assume !(0 == ~T4_E~0); 4436#L716-1 assume !(0 == ~T5_E~0); 4437#L721-1 assume !(0 == ~T6_E~0); 4607#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4608#L731-1 assume !(0 == ~E_1~0); 4579#L736-1 assume !(0 == ~E_2~0); 4580#L741-1 assume !(0 == ~E_3~0); 4658#L746-1 assume !(0 == ~E_4~0); 4470#L751-1 assume !(0 == ~E_5~0); 4471#L756-1 assume !(0 == ~E_6~0); 4433#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4267#L346 assume !(1 == ~m_pc~0); 4268#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4481#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4175#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4176#L861 assume !(0 != activate_threads_~tmp~1#1); 4778#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4298#L365 assume 1 == ~t1_pc~0; 4299#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4417#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4792#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4290#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4705#L384 assume !(1 == ~t2_pc~0); 4695#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4696#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4376#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4201#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4202#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4557#L403 assume 1 == ~t3_pc~0; 4438#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4439#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4425#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4426#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4548#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4549#L422 assume 1 == ~t4_pc~0; 4196#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4197#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4701#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4702#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4635#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4221#L441 assume !(1 == ~t5_pc~0); 4222#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4775#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4818#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4819#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4643#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4644#L460 assume 1 == ~t6_pc~0; 4158#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4159#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4229#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4746#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4747#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4617#L774 assume !(1 == ~M_E~0); 4618#L774-2 assume !(1 == ~T1_E~0); 4761#L779-1 assume !(1 == ~T2_E~0); 4522#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4523#L789-1 assume !(1 == ~T4_E~0); 4283#L794-1 assume !(1 == ~T5_E~0); 4284#L799-1 assume !(1 == ~T6_E~0); 4829#L804-1 assume !(1 == ~E_M~0); 4830#L809-1 assume !(1 == ~E_1~0); 4605#L814-1 assume !(1 == ~E_2~0); 4177#L819-1 assume !(1 == ~E_3~0); 4178#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4665#L829-1 assume !(1 == ~E_5~0); 4753#L834-1 assume !(1 == ~E_6~0); 4418#L839-1 assume { :end_inline_reset_delta_events } true; 4407#L1065-2 [2021-12-19 19:15:53,916 INFO L793 eck$LassoCheckResult]: Loop: 4407#L1065-2 assume !false; 4408#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4460#L671 assume !false; 4787#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4733#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4260#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4680#L582 assume !(0 != eval_~tmp~0#1); 4831#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4668#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4456#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4457#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4502#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4503#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4812#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4807#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4660#L721-3 assume !(0 == ~T6_E~0); 4485#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4486#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4655#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4656#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4431#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4432#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4553#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4309#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4310#L346-24 assume 1 == ~m_pc~0; 4340#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4424#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4657#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4793#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4759#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4371#L365-24 assume 1 == ~t1_pc~0; 4372#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4661#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4538#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4539#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4725#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4327#L384-24 assume !(1 == ~t2_pc~0); 4328#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4345#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4796#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4646#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 4351#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4352#L403-24 assume 1 == ~t3_pc~0; 4473#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4504#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4505#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4603#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4604#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4404#L422-24 assume !(1 == ~t4_pc~0); 4405#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 4358#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4359#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4809#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4767#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4419#L441-24 assume 1 == ~t5_pc~0; 4420#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4624#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4625#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4292#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4706#L460-24 assume !(1 == ~t6_pc~0); 4707#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4762#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4735#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4736#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4697#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4698#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4645#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4484#L779-3 assume !(1 == ~T2_E~0); 4199#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4200#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4179#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4180#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4301#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4622#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4296#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4297#L819-3 assume !(1 == ~E_3~0); 4446#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4429#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4430#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4281#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4282#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4279#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4367#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4216#L1084 assume !(0 == start_simulation_~tmp~3#1); 4218#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4466#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4182#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4321#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4472#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4315#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4307#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4407#L1065-2 [2021-12-19 19:15:53,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,918 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2021-12-19 19:15:53,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502136206] [2021-12-19 19:15:53,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:53,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:53,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:53,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502136206] [2021-12-19 19:15:53,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502136206] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:53,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:53,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:53,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727235946] [2021-12-19 19:15:53,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:53,982 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:53,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:53,985 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 2 times [2021-12-19 19:15:53,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:53,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342313373] [2021-12-19 19:15:53,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:53,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:53,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,031 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342313373] [2021-12-19 19:15:54,032 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342313373] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,035 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,035 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,046 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113084070] [2021-12-19 19:15:54,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,047 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,048 INFO L87 Difference]: Start difference. First operand 686 states and 1026 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,061 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2021-12-19 19:15:54,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1025 transitions. [2021-12-19 19:15:54,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1025 transitions. [2021-12-19 19:15:54,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:54,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:54,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1025 transitions. [2021-12-19 19:15:54,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,069 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2021-12-19 19:15:54,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1025 transitions. [2021-12-19 19:15:54,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:54,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1025 transitions. [2021-12-19 19:15:54,077 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2021-12-19 19:15:54,077 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2021-12-19 19:15:54,077 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:15:54,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1025 transitions. [2021-12-19 19:15:54,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,080 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,081 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,081 INFO L791 eck$LassoCheckResult]: Stem: 6217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6170#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6116#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6117#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5781#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5782#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5631#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5632#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5598#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5599#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5759#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5919#L696 assume !(0 == ~M_E~0); 5920#L696-2 assume !(0 == ~T1_E~0); 6185#L701-1 assume !(0 == ~T2_E~0); 6187#L706-1 assume !(0 == ~T3_E~0); 6030#L711-1 assume !(0 == ~T4_E~0); 5815#L716-1 assume !(0 == ~T5_E~0); 5816#L721-1 assume !(0 == ~T6_E~0); 5986#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5987#L731-1 assume !(0 == ~E_1~0); 5958#L736-1 assume !(0 == ~E_2~0); 5959#L741-1 assume !(0 == ~E_3~0); 6037#L746-1 assume !(0 == ~E_4~0); 5849#L751-1 assume !(0 == ~E_5~0); 5850#L756-1 assume !(0 == ~E_6~0); 5812#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5646#L346 assume !(1 == ~m_pc~0); 5647#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5860#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5556#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5557#L861 assume !(0 != activate_threads_~tmp~1#1); 6157#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5678#L365 assume 1 == ~t1_pc~0; 5679#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5799#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6174#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5668#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5669#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6084#L384 assume !(1 == ~t2_pc~0); 6076#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6077#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5755#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5582#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5583#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5937#L403 assume 1 == ~t3_pc~0; 5817#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5818#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5808#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5809#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5930#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5931#L422 assume 1 == ~t4_pc~0; 5577#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5578#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6080#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6014#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5600#L441 assume !(1 == ~t5_pc~0); 5601#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6154#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6197#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6198#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6023#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6024#L460 assume 1 == ~t6_pc~0; 5540#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5541#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5608#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6125#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6126#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5996#L774 assume !(1 == ~M_E~0); 5997#L774-2 assume !(1 == ~T1_E~0); 6140#L779-1 assume !(1 == ~T2_E~0); 5901#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5902#L789-1 assume !(1 == ~T4_E~0); 5662#L794-1 assume !(1 == ~T5_E~0); 5663#L799-1 assume !(1 == ~T6_E~0); 6208#L804-1 assume !(1 == ~E_M~0); 6209#L809-1 assume !(1 == ~E_1~0); 5984#L814-1 assume !(1 == ~E_2~0); 5558#L819-1 assume !(1 == ~E_3~0); 5559#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6044#L829-1 assume !(1 == ~E_5~0); 6132#L834-1 assume !(1 == ~E_6~0); 5800#L839-1 assume { :end_inline_reset_delta_events } true; 5789#L1065-2 [2021-12-19 19:15:54,081 INFO L793 eck$LassoCheckResult]: Loop: 5789#L1065-2 assume !false; 5790#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L671 assume !false; 6166#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6112#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5639#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5649#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6060#L582 assume !(0 != eval_~tmp~0#1); 6210#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6047#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5835#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5836#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5881#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5882#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6191#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6186#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6040#L721-3 assume !(0 == ~T6_E~0); 5864#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5865#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6034#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6035#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5810#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5811#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5932#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5688#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5689#L346-24 assume 1 == ~m_pc~0; 5722#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5801#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6036#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6171#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6138#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5750#L365-24 assume 1 == ~t1_pc~0; 5751#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6039#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5917#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5918#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6103#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5704#L384-24 assume !(1 == ~t2_pc~0); 5705#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5724#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6175#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6025#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 5729#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5730#L403-24 assume 1 == ~t3_pc~0; 5852#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5883#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5884#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5982#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5983#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5783#L422-24 assume !(1 == ~t4_pc~0); 5784#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5736#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5737#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6188#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6146#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5796#L441-24 assume 1 == ~t5_pc~0; 5797#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6002#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6003#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5670#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5671#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6085#L460-24 assume !(1 == ~t6_pc~0); 6086#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 6141#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6114#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6115#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6074#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6075#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6022#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5863#L779-3 assume !(1 == ~T2_E~0); 5575#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5576#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5554#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5555#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5677#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6001#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L819-3 assume !(1 == ~E_3~0); 5825#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5806#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5807#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5660#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5661#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5658#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5746#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5595#L1084 assume !(0 == start_simulation_~tmp~3#1); 5597#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5845#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5561#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5700#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5851#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5693#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5686#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5687#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5789#L1065-2 [2021-12-19 19:15:54,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2021-12-19 19:15:54,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627657985] [2021-12-19 19:15:54,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627657985] [2021-12-19 19:15:54,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627657985] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456190964] [2021-12-19 19:15:54,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,102 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,102 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 3 times [2021-12-19 19:15:54,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875025202] [2021-12-19 19:15:54,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875025202] [2021-12-19 19:15:54,126 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875025202] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,126 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,126 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,126 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124870087] [2021-12-19 19:15:54,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,126 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,127 INFO L87 Difference]: Start difference. First operand 686 states and 1025 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,146 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2021-12-19 19:15:54,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2021-12-19 19:15:54,150 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1024 transitions. [2021-12-19 19:15:54,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:54,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:54,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1024 transitions. [2021-12-19 19:15:54,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,153 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2021-12-19 19:15:54,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1024 transitions. [2021-12-19 19:15:54,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:54,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1024 transitions. [2021-12-19 19:15:54,160 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2021-12-19 19:15:54,161 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2021-12-19 19:15:54,161 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:15:54,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1024 transitions. [2021-12-19 19:15:54,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,164 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,164 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,164 INFO L791 eck$LassoCheckResult]: Stem: 7596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7549#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7495#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7496#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7160#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7161#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7008#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7009#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6977#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6978#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7138#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7298#L696 assume !(0 == ~M_E~0); 7299#L696-2 assume !(0 == ~T1_E~0); 7564#L701-1 assume !(0 == ~T2_E~0); 7566#L706-1 assume !(0 == ~T3_E~0); 7409#L711-1 assume !(0 == ~T4_E~0); 7194#L716-1 assume !(0 == ~T5_E~0); 7195#L721-1 assume !(0 == ~T6_E~0); 7365#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7366#L731-1 assume !(0 == ~E_1~0); 7337#L736-1 assume !(0 == ~E_2~0); 7338#L741-1 assume !(0 == ~E_3~0); 7416#L746-1 assume !(0 == ~E_4~0); 7228#L751-1 assume !(0 == ~E_5~0); 7229#L756-1 assume !(0 == ~E_6~0); 7191#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7025#L346 assume !(1 == ~m_pc~0); 7026#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7239#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6933#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6934#L861 assume !(0 != activate_threads_~tmp~1#1); 7536#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7056#L365 assume 1 == ~t1_pc~0; 7057#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7175#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7550#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7047#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7048#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7463#L384 assume !(1 == ~t2_pc~0); 7453#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7454#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7134#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6959#L877 assume !(0 != activate_threads_~tmp___1~0#1); 6960#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7315#L403 assume 1 == ~t3_pc~0; 7196#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7197#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7183#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7184#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7306#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7307#L422 assume 1 == ~t4_pc~0; 6954#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6955#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7459#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7460#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7393#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6979#L441 assume !(1 == ~t5_pc~0); 6980#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7533#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7576#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7577#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7401#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7402#L460 assume 1 == ~t6_pc~0; 6916#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6917#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6987#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7504#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7505#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7375#L774 assume !(1 == ~M_E~0); 7376#L774-2 assume !(1 == ~T1_E~0); 7519#L779-1 assume !(1 == ~T2_E~0); 7280#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7281#L789-1 assume !(1 == ~T4_E~0); 7041#L794-1 assume !(1 == ~T5_E~0); 7042#L799-1 assume !(1 == ~T6_E~0); 7587#L804-1 assume !(1 == ~E_M~0); 7588#L809-1 assume !(1 == ~E_1~0); 7363#L814-1 assume !(1 == ~E_2~0); 6935#L819-1 assume !(1 == ~E_3~0); 6936#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7423#L829-1 assume !(1 == ~E_5~0); 7511#L834-1 assume !(1 == ~E_6~0); 7176#L839-1 assume { :end_inline_reset_delta_events } true; 7165#L1065-2 [2021-12-19 19:15:54,164 INFO L793 eck$LassoCheckResult]: Loop: 7165#L1065-2 assume !false; 7166#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7218#L671 assume !false; 7545#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7491#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7018#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7028#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7438#L582 assume !(0 != eval_~tmp~0#1); 7589#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7426#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7214#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7215#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7260#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7261#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7570#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7565#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7418#L721-3 assume !(0 == ~T6_E~0); 7243#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7244#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7413#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7414#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7189#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7190#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7311#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7067#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7068#L346-24 assume 1 == ~m_pc~0; 7098#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7182#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7415#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7551#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7517#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7129#L365-24 assume 1 == ~t1_pc~0; 7130#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7419#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7296#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7297#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7483#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7083#L384-24 assume !(1 == ~t2_pc~0); 7084#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7103#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7554#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7404#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 7109#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7110#L403-24 assume !(1 == ~t3_pc~0); 7232#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7262#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7263#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7361#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7362#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7162#L422-24 assume !(1 == ~t4_pc~0); 7163#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 7116#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7117#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7567#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7525#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7177#L441-24 assume 1 == ~t5_pc~0; 7178#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7382#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7383#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7049#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7050#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7464#L460-24 assume !(1 == ~t6_pc~0); 7465#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7520#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7493#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7494#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7455#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7456#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7403#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7242#L779-3 assume !(1 == ~T2_E~0); 6957#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6958#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6937#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6938#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7059#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7380#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7054#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7055#L819-3 assume !(1 == ~E_3~0); 7204#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7187#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7188#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7039#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7040#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7037#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7125#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6974#L1084 assume !(0 == start_simulation_~tmp~3#1); 6976#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7224#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6940#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7079#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7230#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7073#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7065#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7066#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7165#L1065-2 [2021-12-19 19:15:54,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,165 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2021-12-19 19:15:54,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780530934] [2021-12-19 19:15:54,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,165 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780530934] [2021-12-19 19:15:54,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780530934] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,181 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,181 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,181 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927516242] [2021-12-19 19:15:54,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,181 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1807208579, now seen corresponding path program 1 times [2021-12-19 19:15:54,182 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886864693] [2021-12-19 19:15:54,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,182 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,203 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886864693] [2021-12-19 19:15:54,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886864693] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,203 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,204 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117370076] [2021-12-19 19:15:54,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,204 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,205 INFO L87 Difference]: Start difference. First operand 686 states and 1024 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,213 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2021-12-19 19:15:54,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1023 transitions. [2021-12-19 19:15:54,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1023 transitions. [2021-12-19 19:15:54,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2021-12-19 19:15:54,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2021-12-19 19:15:54,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1023 transitions. [2021-12-19 19:15:54,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,221 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2021-12-19 19:15:54,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1023 transitions. [2021-12-19 19:15:54,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2021-12-19 19:15:54,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1023 transitions. [2021-12-19 19:15:54,228 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2021-12-19 19:15:54,228 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2021-12-19 19:15:54,228 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:15:54,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1023 transitions. [2021-12-19 19:15:54,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2021-12-19 19:15:54,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,231 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,231 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,232 INFO L791 eck$LassoCheckResult]: Stem: 8975#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8928#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8874#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8875#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8539#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8540#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8387#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8388#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8356#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8357#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8517#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8677#L696 assume !(0 == ~M_E~0); 8678#L696-2 assume !(0 == ~T1_E~0); 8943#L701-1 assume !(0 == ~T2_E~0); 8945#L706-1 assume !(0 == ~T3_E~0); 8788#L711-1 assume !(0 == ~T4_E~0); 8573#L716-1 assume !(0 == ~T5_E~0); 8574#L721-1 assume !(0 == ~T6_E~0); 8744#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8745#L731-1 assume !(0 == ~E_1~0); 8716#L736-1 assume !(0 == ~E_2~0); 8717#L741-1 assume !(0 == ~E_3~0); 8795#L746-1 assume !(0 == ~E_4~0); 8607#L751-1 assume !(0 == ~E_5~0); 8608#L756-1 assume !(0 == ~E_6~0); 8570#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8404#L346 assume !(1 == ~m_pc~0); 8405#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8618#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8312#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8313#L861 assume !(0 != activate_threads_~tmp~1#1); 8915#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8436#L365 assume 1 == ~t1_pc~0; 8437#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8554#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8929#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8426#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8427#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8842#L384 assume !(1 == ~t2_pc~0); 8832#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8833#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8513#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8338#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8339#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8694#L403 assume 1 == ~t3_pc~0; 8575#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8576#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8564#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8565#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8685#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8686#L422 assume 1 == ~t4_pc~0; 8333#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8334#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8838#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8839#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8772#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8358#L441 assume !(1 == ~t5_pc~0); 8359#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8912#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8955#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8956#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8780#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8781#L460 assume 1 == ~t6_pc~0; 8295#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8296#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8366#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8883#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8884#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8754#L774 assume !(1 == ~M_E~0); 8755#L774-2 assume !(1 == ~T1_E~0); 8898#L779-1 assume !(1 == ~T2_E~0); 8659#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8660#L789-1 assume !(1 == ~T4_E~0); 8420#L794-1 assume !(1 == ~T5_E~0); 8421#L799-1 assume !(1 == ~T6_E~0); 8966#L804-1 assume !(1 == ~E_M~0); 8967#L809-1 assume !(1 == ~E_1~0); 8742#L814-1 assume !(1 == ~E_2~0); 8314#L819-1 assume !(1 == ~E_3~0); 8315#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8802#L829-1 assume !(1 == ~E_5~0); 8890#L834-1 assume !(1 == ~E_6~0); 8555#L839-1 assume { :end_inline_reset_delta_events } true; 8544#L1065-2 [2021-12-19 19:15:54,232 INFO L793 eck$LassoCheckResult]: Loop: 8544#L1065-2 assume !false; 8545#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8597#L671 assume !false; 8924#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8870#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8397#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8407#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8817#L582 assume !(0 != eval_~tmp~0#1); 8968#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8805#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8593#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8594#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8639#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8640#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8949#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8944#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8797#L721-3 assume !(0 == ~T6_E~0); 8622#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8623#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8792#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8793#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8568#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8569#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8690#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8446#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8447#L346-24 assume 1 == ~m_pc~0; 8477#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8561#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8794#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8930#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8896#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8510#L365-24 assume !(1 == ~t1_pc~0); 8512#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 8798#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8675#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8676#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8862#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8464#L384-24 assume !(1 == ~t2_pc~0); 8465#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8482#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8933#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8783#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 8488#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8489#L403-24 assume 1 == ~t3_pc~0; 8610#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8641#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8642#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8740#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8741#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8541#L422-24 assume !(1 == ~t4_pc~0); 8542#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 8495#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8496#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8946#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8904#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8556#L441-24 assume 1 == ~t5_pc~0; 8557#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8761#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8762#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8428#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8429#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8843#L460-24 assume !(1 == ~t6_pc~0); 8844#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8899#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8872#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8873#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8834#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8835#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8782#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8621#L779-3 assume !(1 == ~T2_E~0); 8336#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8337#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8316#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8317#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8435#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8759#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8430#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8431#L819-3 assume !(1 == ~E_3~0); 8581#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8562#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8563#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8418#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8419#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8416#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8503#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8351#L1084 assume !(0 == start_simulation_~tmp~3#1); 8353#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8603#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8319#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8458#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8609#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8448#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8444#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8445#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8544#L1065-2 [2021-12-19 19:15:54,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,233 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2021-12-19 19:15:54,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482017502] [2021-12-19 19:15:54,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,233 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482017502] [2021-12-19 19:15:54,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482017502] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526017593] [2021-12-19 19:15:54,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,255 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,256 INFO L85 PathProgramCache]: Analyzing trace with hash 870561277, now seen corresponding path program 1 times [2021-12-19 19:15:54,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032931882] [2021-12-19 19:15:54,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,256 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,275 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032931882] [2021-12-19 19:15:54,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032931882] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,276 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,276 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,276 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783418921] [2021-12-19 19:15:54,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,276 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,277 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:54,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:54,277 INFO L87 Difference]: Start difference. First operand 686 states and 1023 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,357 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2021-12-19 19:15:54,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:54,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1756 transitions. [2021-12-19 19:15:54,364 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2021-12-19 19:15:54,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1756 transitions. [2021-12-19 19:15:54,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2021-12-19 19:15:54,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2021-12-19 19:15:54,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1756 transitions. [2021-12-19 19:15:54,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,369 INFO L681 BuchiCegarLoop]: Abstraction has 1180 states and 1756 transitions. [2021-12-19 19:15:54,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1756 transitions. [2021-12-19 19:15:54,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1179. [2021-12-19 19:15:54,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1179 states to 1179 states and 1755 transitions. [2021-12-19 19:15:54,387 INFO L704 BuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2021-12-19 19:15:54,387 INFO L587 BuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2021-12-19 19:15:54,387 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:15:54,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1179 states and 1755 transitions. [2021-12-19 19:15:54,391 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2021-12-19 19:15:54,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,392 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,392 INFO L791 eck$LassoCheckResult]: Stem: 10911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10844#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10778#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10779#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10418#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10419#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10263#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10264#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10232#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10233#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10396#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10562#L696 assume !(0 == ~M_E~0); 10563#L696-2 assume !(0 == ~T1_E~0); 10862#L701-1 assume !(0 == ~T2_E~0); 10864#L706-1 assume !(0 == ~T3_E~0); 10677#L711-1 assume !(0 == ~T4_E~0); 10452#L716-1 assume !(0 == ~T5_E~0); 10453#L721-1 assume !(0 == ~T6_E~0); 10631#L726-1 assume !(0 == ~E_M~0); 10632#L731-1 assume !(0 == ~E_1~0); 10602#L736-1 assume !(0 == ~E_2~0); 10603#L741-1 assume !(0 == ~E_3~0); 10685#L746-1 assume !(0 == ~E_4~0); 10487#L751-1 assume !(0 == ~E_5~0); 10488#L756-1 assume !(0 == ~E_6~0); 10449#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10280#L346 assume !(1 == ~m_pc~0); 10281#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10500#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10188#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10189#L861 assume !(0 != activate_threads_~tmp~1#1); 10825#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10312#L365 assume 1 == ~t1_pc~0; 10313#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10433#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10845#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10303#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10304#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10740#L384 assume !(1 == ~t2_pc~0); 10729#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10730#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10392#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10214#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10215#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10580#L403 assume 1 == ~t3_pc~0; 10454#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10455#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10441#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10442#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10571#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10572#L422 assume 1 == ~t4_pc~0; 10209#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10210#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10736#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10737#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10661#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10234#L441 assume !(1 == ~t5_pc~0); 10235#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10822#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10875#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10876#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10669#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10670#L460 assume 1 == ~t6_pc~0; 10171#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10172#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10242#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10787#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10788#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10641#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10642#L774-2 assume !(1 == ~T1_E~0); 10989#L779-1 assume !(1 == ~T2_E~0); 10988#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10981#L789-1 assume !(1 == ~T4_E~0); 10297#L794-1 assume !(1 == ~T5_E~0); 10298#L799-1 assume !(1 == ~T6_E~0); 10945#L804-1 assume !(1 == ~E_M~0); 10893#L809-1 assume !(1 == ~E_1~0); 10942#L814-1 assume !(1 == ~E_2~0); 10940#L819-1 assume !(1 == ~E_3~0); 10939#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10938#L829-1 assume !(1 == ~E_5~0); 10794#L834-1 assume !(1 == ~E_6~0); 10795#L839-1 assume { :end_inline_reset_delta_events } true; 10931#L1065-2 [2021-12-19 19:15:54,393 INFO L793 eck$LassoCheckResult]: Loop: 10931#L1065-2 assume !false; 10710#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10477#L671 assume !false; 10877#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10878#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10283#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10284#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10913#L582 assume !(0 != eval_~tmp~0#1); 10915#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10696#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10697#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10916#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11074#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11073#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11072#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11071#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11070#L721-3 assume !(0 == ~T6_E~0); 11069#L726-3 assume !(0 == ~E_M~0); 11068#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11067#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11066#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11065#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11064#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11063#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11062#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11061#L346-24 assume 1 == ~m_pc~0; 11059#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11058#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11057#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11056#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11055#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11054#L365-24 assume !(1 == ~t1_pc~0); 11052#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11051#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11050#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11049#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11048#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11047#L384-24 assume 1 == ~t2_pc~0; 11045#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11044#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11043#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11042#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 11041#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11040#L403-24 assume 1 == ~t3_pc~0; 11038#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11037#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11036#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11035#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11034#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11033#L422-24 assume 1 == ~t4_pc~0; 11031#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11030#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11029#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11028#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11027#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11026#L441-24 assume 1 == ~t5_pc~0; 11024#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11023#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11022#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11021#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11020#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11019#L460-24 assume !(1 == ~t6_pc~0); 11017#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 11016#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11015#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11014#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11013#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11012#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10902#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11011#L779-3 assume !(1 == ~T2_E~0); 11010#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11009#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11008#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11007#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11006#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10647#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11005#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11004#L819-3 assume !(1 == ~E_3~0); 11003#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11002#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11001#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11000#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10998#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10992#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10991#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10990#L1084 assume !(0 == start_simulation_~tmp~3#1); 10817#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10483#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10195#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10762#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10763#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10329#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10321#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10322#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 10931#L1065-2 [2021-12-19 19:15:54,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2021-12-19 19:15:54,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145708566] [2021-12-19 19:15:54,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,394 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145708566] [2021-12-19 19:15:54,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145708566] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,413 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:54,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541763247] [2021-12-19 19:15:54,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,414 INFO L85 PathProgramCache]: Analyzing trace with hash 1530837245, now seen corresponding path program 1 times [2021-12-19 19:15:54,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187816837] [2021-12-19 19:15:54,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,439 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187816837] [2021-12-19 19:15:54,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187816837] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,442 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,442 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,443 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934679473] [2021-12-19 19:15:54,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,444 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,444 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,445 INFO L87 Difference]: Start difference. First operand 1179 states and 1755 transitions. cyclomatic complexity: 578 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,494 INFO L93 Difference]: Finished difference Result 2132 states and 3147 transitions. [2021-12-19 19:15:54,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2132 states and 3147 transitions. [2021-12-19 19:15:54,526 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2026 [2021-12-19 19:15:54,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2132 states to 2132 states and 3147 transitions. [2021-12-19 19:15:54,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2132 [2021-12-19 19:15:54,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2132 [2021-12-19 19:15:54,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2132 states and 3147 transitions. [2021-12-19 19:15:54,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,536 INFO L681 BuchiCegarLoop]: Abstraction has 2132 states and 3147 transitions. [2021-12-19 19:15:54,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2132 states and 3147 transitions. [2021-12-19 19:15:54,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2132 to 2128. [2021-12-19 19:15:54,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2128 states, 2128 states have (on average 1.4769736842105263) internal successors, (3143), 2127 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2128 states to 2128 states and 3143 transitions. [2021-12-19 19:15:54,562 INFO L704 BuchiCegarLoop]: Abstraction has 2128 states and 3143 transitions. [2021-12-19 19:15:54,562 INFO L587 BuchiCegarLoop]: Abstraction has 2128 states and 3143 transitions. [2021-12-19 19:15:54,562 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:15:54,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2128 states and 3143 transitions. [2021-12-19 19:15:54,568 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2022 [2021-12-19 19:15:54,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,569 INFO L791 eck$LassoCheckResult]: Stem: 14250#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 14198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14164#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14100#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14101#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 13731#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13732#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13582#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13583#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13549#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13550#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13710#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13875#L696 assume !(0 == ~M_E~0); 13876#L696-2 assume !(0 == ~T1_E~0); 14185#L701-1 assume !(0 == ~T2_E~0); 14187#L706-1 assume !(0 == ~T3_E~0); 13999#L711-1 assume !(0 == ~T4_E~0); 13765#L716-1 assume !(0 == ~T5_E~0); 13766#L721-1 assume !(0 == ~T6_E~0); 13949#L726-1 assume !(0 == ~E_M~0); 13950#L731-1 assume !(0 == ~E_1~0); 13914#L736-1 assume !(0 == ~E_2~0); 13915#L741-1 assume !(0 == ~E_3~0); 14009#L746-1 assume !(0 == ~E_4~0); 13801#L751-1 assume !(0 == ~E_5~0); 13802#L756-1 assume !(0 == ~E_6~0); 13762#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13598#L346 assume !(1 == ~m_pc~0); 13599#L346-2 is_master_triggered_~__retres1~0#1 := 0; 13812#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13507#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13508#L861 assume !(0 != activate_threads_~tmp~1#1); 14148#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13632#L365 assume !(1 == ~t1_pc~0); 13633#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14163#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14168#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13622#L869 assume !(0 != activate_threads_~tmp___0~0#1); 13623#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14064#L384 assume !(1 == ~t2_pc~0); 14056#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14057#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13707#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13531#L877 assume !(0 != activate_threads_~tmp___1~0#1); 13532#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13893#L403 assume 1 == ~t3_pc~0; 13767#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13768#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13758#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13759#L885 assume !(0 != activate_threads_~tmp___2~0#1); 13886#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13887#L422 assume 1 == ~t4_pc~0; 13528#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13529#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14062#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14063#L893 assume !(0 != activate_threads_~tmp___3~0#1); 13983#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13551#L441 assume !(1 == ~t5_pc~0); 13552#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14145#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14200#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14201#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13992#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13993#L460 assume 1 == ~t6_pc~0; 13492#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13493#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13559#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14110#L909 assume !(0 != activate_threads_~tmp___5~0#1); 14111#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13962#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 13963#L774-2 assume !(1 == ~T1_E~0); 14126#L779-1 assume !(1 == ~T2_E~0); 13854#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13855#L789-1 assume !(1 == ~T4_E~0); 13615#L794-1 assume !(1 == ~T5_E~0); 13616#L799-1 assume !(1 == ~T6_E~0); 14222#L804-1 assume !(1 == ~E_M~0); 14223#L809-1 assume !(1 == ~E_1~0); 13946#L814-1 assume !(1 == ~E_2~0); 13509#L819-1 assume !(1 == ~E_3~0); 13510#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14020#L829-1 assume !(1 == ~E_5~0); 14117#L834-1 assume !(1 == ~E_6~0); 14118#L839-1 assume { :end_inline_reset_delta_events } true; 13736#L1065-2 [2021-12-19 19:15:54,569 INFO L793 eck$LassoCheckResult]: Loop: 13736#L1065-2 assume !false; 13737#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14158#L671 assume !false; 14159#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14095#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13590#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14038#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14039#L582 assume !(0 != eval_~tmp~0#1); 14686#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14685#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14683#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14684#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13834#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13835#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15137#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15136#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15135#L721-3 assume !(0 == ~T6_E~0); 15134#L726-3 assume !(0 == ~E_M~0); 15133#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15132#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15131#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15130#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15129#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15128#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15127#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15126#L346-24 assume 1 == ~m_pc~0; 15124#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15123#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15122#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15121#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15120#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15119#L365-24 assume !(1 == ~t1_pc~0); 15118#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15116#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15114#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15112#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15110#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15108#L384-24 assume 1 == ~t2_pc~0; 15104#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15102#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15100#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15098#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 15096#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15094#L403-24 assume 1 == ~t3_pc~0; 15090#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15088#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15086#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15084#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15082#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15080#L422-24 assume 1 == ~t4_pc~0; 15076#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15074#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15072#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15070#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15068#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15066#L441-24 assume 1 == ~t5_pc~0; 15062#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15060#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15058#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15056#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15054#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15052#L460-24 assume !(1 == ~t6_pc~0); 15048#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 15046#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15044#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15042#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15040#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15039#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15036#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15034#L779-3 assume !(1 == ~T2_E~0); 15032#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15030#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15028#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15026#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15025#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15023#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15022#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15021#L819-3 assume !(1 == ~E_3~0); 15020#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15019#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15018#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15017#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15015#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15009#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15008#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15007#L1084 assume !(0 == start_simulation_~tmp~3#1); 14140#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14996#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14992#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14990#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14988#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14986#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14984#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14982#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 13736#L1065-2 [2021-12-19 19:15:54,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2021-12-19 19:15:54,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420765330] [2021-12-19 19:15:54,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420765330] [2021-12-19 19:15:54,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420765330] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,596 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171465472] [2021-12-19 19:15:54,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,596 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1530837245, now seen corresponding path program 2 times [2021-12-19 19:15:54,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844658949] [2021-12-19 19:15:54,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844658949] [2021-12-19 19:15:54,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844658949] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,619 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832122579] [2021-12-19 19:15:54,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:54,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:54,621 INFO L87 Difference]: Start difference. First operand 2128 states and 3143 transitions. cyclomatic complexity: 1019 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,735 INFO L93 Difference]: Finished difference Result 4867 states and 7117 transitions. [2021-12-19 19:15:54,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:54,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4867 states and 7117 transitions. [2021-12-19 19:15:54,757 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4746 [2021-12-19 19:15:54,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4867 states to 4867 states and 7117 transitions. [2021-12-19 19:15:54,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4867 [2021-12-19 19:15:54,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4867 [2021-12-19 19:15:54,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4867 states and 7117 transitions. [2021-12-19 19:15:54,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,785 INFO L681 BuchiCegarLoop]: Abstraction has 4867 states and 7117 transitions. [2021-12-19 19:15:54,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4867 states and 7117 transitions. [2021-12-19 19:15:54,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4867 to 3911. [2021-12-19 19:15:54,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3911 states, 3911 states have (on average 1.468678087445666) internal successors, (5744), 3910 states have internal predecessors, (5744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3911 states to 3911 states and 5744 transitions. [2021-12-19 19:15:54,840 INFO L704 BuchiCegarLoop]: Abstraction has 3911 states and 5744 transitions. [2021-12-19 19:15:54,840 INFO L587 BuchiCegarLoop]: Abstraction has 3911 states and 5744 transitions. [2021-12-19 19:15:54,840 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:15:54,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3911 states and 5744 transitions. [2021-12-19 19:15:54,848 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3804 [2021-12-19 19:15:54,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,849 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,850 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,850 INFO L791 eck$LassoCheckResult]: Stem: 21258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 21201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21152#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21087#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21088#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 20728#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20729#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20585#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20586#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20552#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20553#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20707#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20867#L696 assume !(0 == ~M_E~0); 20868#L696-2 assume !(0 == ~T1_E~0); 21178#L701-1 assume !(0 == ~T2_E~0); 21179#L706-1 assume !(0 == ~T3_E~0); 20993#L711-1 assume !(0 == ~T4_E~0); 20760#L716-1 assume !(0 == ~T5_E~0); 20761#L721-1 assume !(0 == ~T6_E~0); 20944#L726-1 assume !(0 == ~E_M~0); 20945#L731-1 assume !(0 == ~E_1~0); 20907#L736-1 assume !(0 == ~E_2~0); 20908#L741-1 assume !(0 == ~E_3~0); 20999#L746-1 assume !(0 == ~E_4~0); 20792#L751-1 assume !(0 == ~E_5~0); 20793#L756-1 assume !(0 == ~E_6~0); 20757#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20599#L346 assume !(1 == ~m_pc~0); 20600#L346-2 is_master_triggered_~__retres1~0#1 := 0; 20804#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20512#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20513#L861 assume !(0 != activate_threads_~tmp~1#1); 21136#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20631#L365 assume !(1 == ~t1_pc~0); 20632#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21151#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21156#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20621#L869 assume !(0 != activate_threads_~tmp___0~0#1); 20622#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21052#L384 assume !(1 == ~t2_pc~0); 21044#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21045#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20706#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20536#L877 assume !(0 != activate_threads_~tmp___1~0#1); 20537#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20883#L403 assume !(1 == ~t3_pc~0); 20884#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21082#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20753#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20754#L885 assume !(0 != activate_threads_~tmp___2~0#1); 20876#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20877#L422 assume 1 == ~t4_pc~0; 20531#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20532#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21050#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21051#L893 assume !(0 != activate_threads_~tmp___3~0#1); 20974#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20554#L441 assume !(1 == ~t5_pc~0); 20555#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21132#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21203#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21204#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20983#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20984#L460 assume 1 == ~t6_pc~0; 20497#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20498#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20564#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21095#L909 assume !(0 != activate_threads_~tmp___5~0#1); 21096#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20954#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 20955#L774-2 assume !(1 == ~T1_E~0); 21113#L779-1 assume !(1 == ~T2_E~0); 21114#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21219#L789-1 assume !(1 == ~T4_E~0); 20615#L794-1 assume !(1 == ~T5_E~0); 20616#L799-1 assume !(1 == ~T6_E~0); 21223#L804-1 assume !(1 == ~E_M~0); 21224#L809-1 assume !(1 == ~E_1~0); 20939#L814-1 assume !(1 == ~E_2~0); 20514#L819-1 assume !(1 == ~E_3~0); 20515#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21243#L829-1 assume !(1 == ~E_5~0); 21103#L834-1 assume !(1 == ~E_6~0); 21104#L839-1 assume { :end_inline_reset_delta_events } true; 23891#L1065-2 [2021-12-19 19:15:54,850 INFO L793 eck$LassoCheckResult]: Loop: 23891#L1065-2 assume !false; 23886#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23881#L671 assume !false; 23878#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23863#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23831#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23828#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23825#L582 assume !(0 != eval_~tmp~0#1); 21225#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21015#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20778#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20779#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20826#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20827#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21187#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21177#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21002#L721-3 assume !(0 == ~T6_E~0); 20807#L726-3 assume !(0 == ~E_M~0); 20808#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20996#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21162#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24289#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24288#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21105#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20639#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20640#L346-24 assume 1 == ~m_pc~0; 20670#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20748#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20998#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21153#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21111#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20701#L365-24 assume !(1 == ~t1_pc~0); 20702#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 21244#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20862#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20863#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21074#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20655#L384-24 assume !(1 == ~t2_pc~0); 20656#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 20675#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21157#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20985#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 20681#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20682#L403-24 assume !(1 == ~t3_pc~0); 20795#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 20828#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20829#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20933#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20934#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20730#L422-24 assume !(1 == ~t4_pc~0); 20731#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 20688#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20689#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21180#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21122#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20742#L441-24 assume 1 == ~t5_pc~0; 20743#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20961#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20962#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20623#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20624#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21054#L460-24 assume 1 == ~t6_pc~0; 21056#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21115#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21085#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21086#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21042#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21043#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20982#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20806#L779-3 assume !(1 == ~T2_E~0); 20529#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20530#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20510#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20511#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20630#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20960#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20628#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20629#L819-3 assume !(1 == ~E_3~0); 20767#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20751#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20752#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20613#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20614#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20611#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20697#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 24069#L1084 assume !(0 == start_simulation_~tmp~3#1); 21127#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 24050#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 24012#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 24005#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 23997#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23990#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23985#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 23894#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 23891#L1065-2 [2021-12-19 19:15:54,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,851 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2021-12-19 19:15:54,851 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,851 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118528144] [2021-12-19 19:15:54,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,851 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,903 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,903 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118528144] [2021-12-19 19:15:54,903 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [118528144] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,904 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,904 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,904 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205004866] [2021-12-19 19:15:54,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,905 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,906 INFO L85 PathProgramCache]: Analyzing trace with hash 373343423, now seen corresponding path program 1 times [2021-12-19 19:15:54,906 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138714693] [2021-12-19 19:15:54,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138714693] [2021-12-19 19:15:54,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138714693] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,928 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088819662] [2021-12-19 19:15:54,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,928 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:54,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:54,929 INFO L87 Difference]: Start difference. First operand 3911 states and 5744 transitions. cyclomatic complexity: 1837 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,059 INFO L93 Difference]: Finished difference Result 8988 states and 13093 transitions. [2021-12-19 19:15:55,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:55,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8988 states and 13093 transitions. [2021-12-19 19:15:55,098 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8850 [2021-12-19 19:15:55,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8988 states to 8988 states and 13093 transitions. [2021-12-19 19:15:55,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8988 [2021-12-19 19:15:55,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8988 [2021-12-19 19:15:55,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8988 states and 13093 transitions. [2021-12-19 19:15:55,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,144 INFO L681 BuchiCegarLoop]: Abstraction has 8988 states and 13093 transitions. [2021-12-19 19:15:55,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8988 states and 13093 transitions. [2021-12-19 19:15:55,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8988 to 7246. [2021-12-19 19:15:55,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7246 states, 7246 states have (on average 1.4624620480264974) internal successors, (10597), 7245 states have internal predecessors, (10597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7246 states to 7246 states and 10597 transitions. [2021-12-19 19:15:55,301 INFO L704 BuchiCegarLoop]: Abstraction has 7246 states and 10597 transitions. [2021-12-19 19:15:55,301 INFO L587 BuchiCegarLoop]: Abstraction has 7246 states and 10597 transitions. [2021-12-19 19:15:55,301 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:15:55,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7246 states and 10597 transitions. [2021-12-19 19:15:55,320 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7136 [2021-12-19 19:15:55,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,321 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,321 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,322 INFO L791 eck$LassoCheckResult]: Stem: 34177#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 34114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 34073#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34009#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34010#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 33633#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33634#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33487#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33488#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33456#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33457#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33612#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33777#L696 assume !(0 == ~M_E~0); 33778#L696-2 assume !(0 == ~T1_E~0); 34097#L701-1 assume !(0 == ~T2_E~0); 34099#L706-1 assume !(0 == ~T3_E~0); 33905#L711-1 assume !(0 == ~T4_E~0); 33666#L716-1 assume !(0 == ~T5_E~0); 33667#L721-1 assume !(0 == ~T6_E~0); 33858#L726-1 assume !(0 == ~E_M~0); 33859#L731-1 assume !(0 == ~E_1~0); 33818#L736-1 assume !(0 == ~E_2~0); 33819#L741-1 assume !(0 == ~E_3~0); 33913#L746-1 assume !(0 == ~E_4~0); 33702#L751-1 assume !(0 == ~E_5~0); 33703#L756-1 assume !(0 == ~E_6~0); 33663#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33503#L346 assume !(1 == ~m_pc~0); 33504#L346-2 is_master_triggered_~__retres1~0#1 := 0; 33713#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33418#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33419#L861 assume !(0 != activate_threads_~tmp~1#1); 34056#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33534#L365 assume !(1 == ~t1_pc~0); 33535#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34072#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34074#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33525#L869 assume !(0 != activate_threads_~tmp___0~0#1); 33526#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33969#L384 assume !(1 == ~t2_pc~0); 33960#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33961#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33609#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33439#L877 assume !(0 != activate_threads_~tmp___1~0#1); 33440#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33794#L403 assume !(1 == ~t3_pc~0); 33795#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34003#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33655#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33656#L885 assume !(0 != activate_threads_~tmp___2~0#1); 33785#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33786#L422 assume !(1 == ~t4_pc~0); 33927#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33928#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33965#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33966#L893 assume !(0 != activate_threads_~tmp___3~0#1); 33889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33458#L441 assume !(1 == ~t5_pc~0); 33459#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34053#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34116#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34117#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33897#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33898#L460 assume 1 == ~t6_pc~0; 33403#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33404#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33466#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34017#L909 assume !(0 != activate_threads_~tmp___5~0#1); 34018#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33869#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 33870#L774-2 assume !(1 == ~T1_E~0); 34139#L779-1 assume !(1 == ~T2_E~0); 33757#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33758#L789-1 assume !(1 == ~T4_E~0); 33519#L794-1 assume !(1 == ~T5_E~0); 33520#L799-1 assume !(1 == ~T6_E~0); 34147#L804-1 assume !(1 == ~E_M~0); 34148#L809-1 assume !(1 == ~E_1~0); 33853#L814-1 assume !(1 == ~E_2~0); 33854#L819-1 assume !(1 == ~E_3~0); 33923#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33924#L829-1 assume !(1 == ~E_5~0); 34025#L834-1 assume !(1 == ~E_6~0); 34026#L839-1 assume { :end_inline_reset_delta_events } true; 39708#L1065-2 [2021-12-19 19:15:55,322 INFO L793 eck$LassoCheckResult]: Loop: 39708#L1065-2 assume !false; 39704#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39699#L671 assume !false; 39698#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 39285#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 39277#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 39275#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 39273#L582 assume !(0 != eval_~tmp~0#1); 34149#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33929#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33685#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33686#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33737#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33738#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34104#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34098#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33916#L721-3 assume !(0 == ~T6_E~0); 33717#L726-3 assume !(0 == ~E_M~0); 33718#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33910#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33911#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33661#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33662#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33790#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33543#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33544#L346-24 assume 1 == ~m_pc~0; 33574#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33654#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33912#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34075#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34032#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33607#L365-24 assume !(1 == ~t1_pc~0); 33608#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 34167#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33775#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33776#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33994#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33559#L384-24 assume !(1 == ~t2_pc~0); 33560#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 33579#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34078#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33900#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 33582#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33583#L403-24 assume !(1 == ~t3_pc~0); 40099#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 40097#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40095#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40093#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40090#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40088#L422-24 assume !(1 == ~t4_pc~0); 36885#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 40085#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40083#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40081#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40078#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40076#L441-24 assume 1 == ~t5_pc~0; 40073#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40071#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40069#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40068#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40067#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40066#L460-24 assume 1 == ~t6_pc~0; 40064#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40061#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40059#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40057#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40055#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40053#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40050#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40049#L779-3 assume !(1 == ~T2_E~0); 40041#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40039#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40037#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40035#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40033#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40030#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40029#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40028#L819-3 assume !(1 == ~E_3~0); 40027#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40026#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40025#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40024#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 40022#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 40015#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 40013#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 40011#L1084 assume !(0 == start_simulation_~tmp~3#1); 40009#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 39885#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 39881#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 39878#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 39876#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39874#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39872#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 39710#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 39708#L1065-2 [2021-12-19 19:15:55,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2021-12-19 19:15:55,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068647486] [2021-12-19 19:15:55,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,323 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068647486] [2021-12-19 19:15:55,352 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068647486] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,352 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,352 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:55,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951170989] [2021-12-19 19:15:55,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,353 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,353 INFO L85 PathProgramCache]: Analyzing trace with hash 373343423, now seen corresponding path program 2 times [2021-12-19 19:15:55,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610928260] [2021-12-19 19:15:55,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610928260] [2021-12-19 19:15:55,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610928260] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721500615] [2021-12-19 19:15:55,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,378 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,378 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:55,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:55,379 INFO L87 Difference]: Start difference. First operand 7246 states and 10597 transitions. cyclomatic complexity: 3355 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,551 INFO L93 Difference]: Finished difference Result 17179 states and 25286 transitions. [2021-12-19 19:15:55,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:15:55,552 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17179 states and 25286 transitions. [2021-12-19 19:15:55,625 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16976 [2021-12-19 19:15:55,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17179 states to 17179 states and 25286 transitions. [2021-12-19 19:15:55,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17179 [2021-12-19 19:15:55,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17179 [2021-12-19 19:15:55,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17179 states and 25286 transitions. [2021-12-19 19:15:55,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,831 INFO L681 BuchiCegarLoop]: Abstraction has 17179 states and 25286 transitions. [2021-12-19 19:15:55,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17179 states and 25286 transitions. [2021-12-19 19:15:55,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17179 to 7561. [2021-12-19 19:15:55,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7561 states, 7561 states have (on average 1.4431953445311467) internal successors, (10912), 7560 states have internal predecessors, (10912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7561 states to 7561 states and 10912 transitions. [2021-12-19 19:15:55,981 INFO L704 BuchiCegarLoop]: Abstraction has 7561 states and 10912 transitions. [2021-12-19 19:15:55,981 INFO L587 BuchiCegarLoop]: Abstraction has 7561 states and 10912 transitions. [2021-12-19 19:15:55,981 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:15:55,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7561 states and 10912 transitions. [2021-12-19 19:15:56,002 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7448 [2021-12-19 19:15:56,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:56,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:56,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,004 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,004 INFO L791 eck$LassoCheckResult]: Stem: 58619#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 58560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 58512#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58443#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58444#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 58076#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58077#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57925#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57926#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57894#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57895#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58054#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58216#L696 assume !(0 == ~M_E~0); 58217#L696-2 assume !(0 == ~T1_E~0); 58537#L701-1 assume !(0 == ~T2_E~0); 58541#L706-1 assume !(0 == ~T3_E~0); 58344#L711-1 assume !(0 == ~T4_E~0); 58108#L716-1 assume !(0 == ~T5_E~0); 58109#L721-1 assume !(0 == ~T6_E~0); 58292#L726-1 assume !(0 == ~E_M~0); 58293#L731-1 assume !(0 == ~E_1~0); 58258#L736-1 assume !(0 == ~E_2~0); 58259#L741-1 assume !(0 == ~E_3~0); 58354#L746-1 assume !(0 == ~E_4~0); 58144#L751-1 assume !(0 == ~E_5~0); 58145#L756-1 assume !(0 == ~E_6~0); 58105#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57941#L346 assume !(1 == ~m_pc~0); 57942#L346-2 is_master_triggered_~__retres1~0#1 := 0; 58155#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57856#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57857#L861 assume !(0 != activate_threads_~tmp~1#1); 58495#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57973#L365 assume !(1 == ~t1_pc~0); 57974#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58511#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58513#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57964#L869 assume !(0 != activate_threads_~tmp___0~0#1); 57965#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58408#L384 assume !(1 == ~t2_pc~0); 58399#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58400#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58050#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57877#L877 assume !(0 != activate_threads_~tmp___1~0#1); 57878#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58234#L403 assume !(1 == ~t3_pc~0); 58235#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58438#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58097#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 58098#L885 assume !(0 != activate_threads_~tmp___2~0#1); 58225#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58226#L422 assume !(1 == ~t4_pc~0); 58368#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58369#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58404#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58405#L893 assume !(0 != activate_threads_~tmp___3~0#1); 58323#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57896#L441 assume !(1 == ~t5_pc~0); 57897#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58490#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58594#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58626#L901 assume !(0 != activate_threads_~tmp___4~0#1); 58336#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58337#L460 assume 1 == ~t6_pc~0; 57841#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57842#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57904#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58454#L909 assume !(0 != activate_threads_~tmp___5~0#1); 58455#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58303#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 58304#L774-2 assume !(1 == ~T1_E~0); 58473#L779-1 assume !(1 == ~T2_E~0); 58196#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58197#L789-1 assume !(1 == ~T4_E~0); 57957#L794-1 assume !(1 == ~T5_E~0); 57958#L799-1 assume !(1 == ~T6_E~0); 58586#L804-1 assume !(1 == ~E_M~0); 58587#L809-1 assume !(1 == ~E_1~0); 58288#L814-1 assume !(1 == ~E_2~0); 57858#L819-1 assume !(1 == ~E_3~0); 57859#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 58364#L829-1 assume !(1 == ~E_5~0); 58461#L834-1 assume !(1 == ~E_6~0); 58089#L839-1 assume { :end_inline_reset_delta_events } true; 58090#L1065-2 [2021-12-19 19:15:56,004 INFO L793 eck$LassoCheckResult]: Loop: 58090#L1065-2 assume !false; 63323#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63274#L671 assume !false; 63267#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 63182#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 63171#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 63164#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63157#L582 assume !(0 != eval_~tmp~0#1); 63158#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65219#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65218#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65217#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65215#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65205#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65204#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65203#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65172#L721-3 assume !(0 == ~T6_E~0); 65166#L726-3 assume !(0 == ~E_M~0); 65160#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65153#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65147#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65141#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65135#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65129#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57982#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57983#L346-24 assume 1 == ~m_pc~0; 58013#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 58096#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58352#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58514#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58470#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58047#L365-24 assume !(1 == ~t1_pc~0); 58048#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 58609#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58214#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58215#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58430#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57996#L384-24 assume !(1 == ~t2_pc~0); 57997#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 58018#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58517#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58339#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 58024#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58025#L403-24 assume !(1 == ~t3_pc~0); 64819#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 64816#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64814#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64725#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64722#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64720#L422-24 assume !(1 == ~t4_pc~0); 64636#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 64717#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64715#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64705#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64704#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64703#L441-24 assume 1 == ~t5_pc~0; 64701#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64699#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64697#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64695#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64693#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64691#L460-24 assume !(1 == ~t6_pc~0); 64688#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 64686#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64680#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64675#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64674#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64673#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62130#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63512#L779-3 assume !(1 == ~T2_E~0); 63511#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63510#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63509#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63508#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63507#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62112#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63504#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63498#L819-3 assume !(1 == ~E_3~0); 63497#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63496#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63495#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63494#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 63491#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 63484#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 63480#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 63454#L1084 assume !(0 == start_simulation_~tmp~3#1); 63436#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 63378#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 63372#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 63368#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 63365#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63362#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63343#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 63339#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 58090#L1065-2 [2021-12-19 19:15:56,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2021-12-19 19:15:56,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761710176] [2021-12-19 19:15:56,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,028 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761710176] [2021-12-19 19:15:56,029 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761710176] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,030 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,030 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,031 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163999355] [2021-12-19 19:15:56,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,031 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:56,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1203214336, now seen corresponding path program 1 times [2021-12-19 19:15:56,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233487068] [2021-12-19 19:15:56,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233487068] [2021-12-19 19:15:56,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233487068] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,051 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702911909] [2021-12-19 19:15:56,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,052 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:56,052 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:56,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:56,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:56,053 INFO L87 Difference]: Start difference. First operand 7561 states and 10912 transitions. cyclomatic complexity: 3355 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:56,247 INFO L93 Difference]: Finished difference Result 17748 states and 25401 transitions. [2021-12-19 19:15:56,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:56,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17748 states and 25401 transitions. [2021-12-19 19:15:56,316 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17572 [2021-12-19 19:15:56,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17748 states to 17748 states and 25401 transitions. [2021-12-19 19:15:56,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17748 [2021-12-19 19:15:56,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17748 [2021-12-19 19:15:56,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17748 states and 25401 transitions. [2021-12-19 19:15:56,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:56,395 INFO L681 BuchiCegarLoop]: Abstraction has 17748 states and 25401 transitions. [2021-12-19 19:15:56,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17748 states and 25401 transitions. [2021-12-19 19:15:56,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17748 to 14452. [2021-12-19 19:15:56,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14452 states, 14452 states have (on average 1.435441461389427) internal successors, (20745), 14451 states have internal predecessors, (20745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14452 states to 14452 states and 20745 transitions. [2021-12-19 19:15:56,708 INFO L704 BuchiCegarLoop]: Abstraction has 14452 states and 20745 transitions. [2021-12-19 19:15:56,708 INFO L587 BuchiCegarLoop]: Abstraction has 14452 states and 20745 transitions. [2021-12-19 19:15:56,709 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:15:56,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14452 states and 20745 transitions. [2021-12-19 19:15:56,750 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14332 [2021-12-19 19:15:56,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:56,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:56,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,752 INFO L791 eck$LassoCheckResult]: Stem: 83981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 83900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 83850#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83776#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83777#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 83387#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83388#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83242#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83243#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83210#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83211#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83366#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83530#L696 assume !(0 == ~M_E~0); 83531#L696-2 assume !(0 == ~T1_E~0); 83880#L701-1 assume !(0 == ~T2_E~0); 83881#L706-1 assume !(0 == ~T3_E~0); 83659#L711-1 assume !(0 == ~T4_E~0); 83420#L716-1 assume !(0 == ~T5_E~0); 83421#L721-1 assume !(0 == ~T6_E~0); 83602#L726-1 assume !(0 == ~E_M~0); 83603#L731-1 assume !(0 == ~E_1~0); 83568#L736-1 assume !(0 == ~E_2~0); 83569#L741-1 assume !(0 == ~E_3~0); 83666#L746-1 assume !(0 == ~E_4~0); 83453#L751-1 assume !(0 == ~E_5~0); 83454#L756-1 assume !(0 == ~E_6~0); 83417#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83256#L346 assume !(1 == ~m_pc~0); 83257#L346-2 is_master_triggered_~__retres1~0#1 := 0; 83466#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83174#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83175#L861 assume !(0 != activate_threads_~tmp~1#1); 83833#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83289#L365 assume !(1 == ~t1_pc~0); 83290#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83849#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83854#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83279#L869 assume !(0 != activate_threads_~tmp___0~0#1); 83280#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83730#L384 assume !(1 == ~t2_pc~0); 83722#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83723#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83365#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83195#L877 assume !(0 != activate_threads_~tmp___1~0#1); 83196#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83547#L403 assume !(1 == ~t3_pc~0); 83548#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83770#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83412#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83413#L885 assume !(0 != activate_threads_~tmp___2~0#1); 83539#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83540#L422 assume !(1 == ~t4_pc~0); 83682#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83683#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83728#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83729#L893 assume !(0 != activate_threads_~tmp___3~0#1); 83637#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83212#L441 assume !(1 == ~t5_pc~0); 83213#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 83830#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83902#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83903#L901 assume !(0 != activate_threads_~tmp___4~0#1); 83648#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83649#L460 assume !(1 == ~t6_pc~0); 83795#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83221#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83222#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83790#L909 assume !(0 != activate_threads_~tmp___5~0#1); 83791#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83614#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 83615#L774-2 assume !(1 == ~T1_E~0); 83927#L779-1 assume !(1 == ~T2_E~0); 83507#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83508#L789-1 assume !(1 == ~T4_E~0); 83272#L794-1 assume !(1 == ~T5_E~0); 83273#L799-1 assume !(1 == ~T6_E~0); 83934#L804-1 assume !(1 == ~E_M~0); 83935#L809-1 assume !(1 == ~E_1~0); 83597#L814-1 assume !(1 == ~E_2~0); 83598#L819-1 assume !(1 == ~E_3~0); 83675#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83676#L829-1 assume !(1 == ~E_5~0); 83799#L834-1 assume !(1 == ~E_6~0); 83800#L839-1 assume { :end_inline_reset_delta_events } true; 93597#L1065-2 [2021-12-19 19:15:56,752 INFO L793 eck$LassoCheckResult]: Loop: 93597#L1065-2 assume !false; 93593#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93589#L671 assume !false; 93588#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 93581#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 93575#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 93574#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 93211#L582 assume !(0 != eval_~tmp~0#1); 83939#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83940#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97209#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 97208#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 97206#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 97204#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97202#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97200#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97198#L721-3 assume !(0 == ~T6_E~0); 97195#L726-3 assume !(0 == ~E_M~0); 97193#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 97191#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97190#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 97129#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83541#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83542#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83298#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83299#L346-24 assume 1 == ~m_pc~0; 83329#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 83407#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83664#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83851#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83806#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83360#L365-24 assume !(1 == ~t1_pc~0); 83361#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 83967#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83526#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83527#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 83761#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83312#L384-24 assume !(1 == ~t2_pc~0); 83313#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 83334#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83855#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83650#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 83338#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83339#L403-24 assume !(1 == ~t3_pc~0); 83456#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 83489#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83490#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83592#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83593#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83910#L422-24 assume !(1 == ~t4_pc~0); 95005#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 95000#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94969#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94965#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94963#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94960#L441-24 assume 1 == ~t5_pc~0; 94955#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94949#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94942#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 94935#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 94929#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94921#L460-24 assume !(1 == ~t6_pc~0); 85019#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 94907#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94898#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94891#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94884#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94879#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94872#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94866#L779-3 assume !(1 == ~T2_E~0); 94861#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94855#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94847#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94841#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94836#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94826#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94820#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94814#L819-3 assume !(1 == ~E_3~0); 94806#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94803#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94800#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94797#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 94788#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 94778#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 94773#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 94767#L1084 assume !(0 == start_simulation_~tmp~3#1); 94762#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 94739#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 94733#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 94730#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 94727#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94723#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94718#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 93599#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 93597#L1065-2 [2021-12-19 19:15:56,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,753 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2021-12-19 19:15:56,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780746404] [2021-12-19 19:15:56,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,773 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780746404] [2021-12-19 19:15:56,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780746404] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,773 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,773 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:56,773 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99937119] [2021-12-19 19:15:56,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,774 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:56,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,774 INFO L85 PathProgramCache]: Analyzing trace with hash -1203214336, now seen corresponding path program 2 times [2021-12-19 19:15:56,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,774 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861050992] [2021-12-19 19:15:56,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,794 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861050992] [2021-12-19 19:15:56,794 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861050992] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,795 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,795 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,795 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127121803] [2021-12-19 19:15:56,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,795 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:56,795 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:56,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:56,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:56,796 INFO L87 Difference]: Start difference. First operand 14452 states and 20745 transitions. cyclomatic complexity: 6297 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:56,914 INFO L93 Difference]: Finished difference Result 21525 states and 30922 transitions. [2021-12-19 19:15:56,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:56,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21525 states and 30922 transitions. [2021-12-19 19:15:57,068 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21404 [2021-12-19 19:15:57,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21525 states to 21525 states and 30922 transitions. [2021-12-19 19:15:57,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21525 [2021-12-19 19:15:57,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21525 [2021-12-19 19:15:57,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21525 states and 30922 transitions. [2021-12-19 19:15:57,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:57,291 INFO L681 BuchiCegarLoop]: Abstraction has 21525 states and 30922 transitions. [2021-12-19 19:15:57,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21525 states and 30922 transitions. [2021-12-19 19:15:57,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21525 to 15082. [2021-12-19 19:15:57,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15082 states, 15082 states have (on average 1.4386023073862884) internal successors, (21697), 15081 states have internal predecessors, (21697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:57,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15082 states to 15082 states and 21697 transitions. [2021-12-19 19:15:57,447 INFO L704 BuchiCegarLoop]: Abstraction has 15082 states and 21697 transitions. [2021-12-19 19:15:57,447 INFO L587 BuchiCegarLoop]: Abstraction has 15082 states and 21697 transitions. [2021-12-19 19:15:57,447 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:15:57,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15082 states and 21697 transitions. [2021-12-19 19:15:57,471 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14976 [2021-12-19 19:15:57,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:57,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:57,473 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:57,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:57,474 INFO L791 eck$LassoCheckResult]: Stem: 119974#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 119908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 119856#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119772#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119773#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 119375#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119376#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119229#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119230#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119196#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119197#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 119354#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119527#L696 assume !(0 == ~M_E~0); 119528#L696-2 assume !(0 == ~T1_E~0); 119889#L701-1 assume !(0 == ~T2_E~0); 119890#L706-1 assume !(0 == ~T3_E~0); 119654#L711-1 assume !(0 == ~T4_E~0); 119408#L716-1 assume !(0 == ~T5_E~0); 119409#L721-1 assume !(0 == ~T6_E~0); 119600#L726-1 assume !(0 == ~E_M~0); 119601#L731-1 assume !(0 == ~E_1~0); 119565#L736-1 assume !(0 == ~E_2~0); 119566#L741-1 assume !(0 == ~E_3~0); 119660#L746-1 assume !(0 == ~E_4~0); 119444#L751-1 assume !(0 == ~E_5~0); 119445#L756-1 assume !(0 == ~E_6~0); 119405#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119243#L346 assume !(1 == ~m_pc~0); 119244#L346-2 is_master_triggered_~__retres1~0#1 := 0; 119458#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119159#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119160#L861 assume !(0 != activate_threads_~tmp~1#1); 119839#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119275#L365 assume !(1 == ~t1_pc~0); 119276#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119855#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119860#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119265#L869 assume !(0 != activate_threads_~tmp___0~0#1); 119266#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119726#L384 assume !(1 == ~t2_pc~0); 119719#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119720#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119353#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119181#L877 assume !(0 != activate_threads_~tmp___1~0#1); 119182#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119543#L403 assume !(1 == ~t3_pc~0); 119544#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119767#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119401#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119402#L885 assume !(0 != activate_threads_~tmp___2~0#1); 119536#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119537#L422 assume !(1 == ~t4_pc~0); 119677#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 119678#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119724#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119725#L893 assume !(0 != activate_threads_~tmp___3~0#1); 119631#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119198#L441 assume !(1 == ~t5_pc~0); 119199#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119833#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119910#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119911#L901 assume !(0 != activate_threads_~tmp___4~0#1); 119644#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119645#L460 assume !(1 == ~t6_pc~0); 119789#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 119207#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119208#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119784#L909 assume !(0 != activate_threads_~tmp___5~0#1); 119785#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119610#L774 assume !(1 == ~M_E~0); 119611#L774-2 assume !(1 == ~T1_E~0); 119809#L779-1 assume !(1 == ~T2_E~0); 119501#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119502#L789-1 assume !(1 == ~T4_E~0); 119259#L794-1 assume !(1 == ~T5_E~0); 119260#L799-1 assume !(1 == ~T6_E~0); 119936#L804-1 assume !(1 == ~E_M~0); 119937#L809-1 assume !(1 == ~E_1~0); 119595#L814-1 assume !(1 == ~E_2~0); 119161#L819-1 assume !(1 == ~E_3~0); 119162#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 119672#L829-1 assume !(1 == ~E_5~0); 119793#L834-1 assume !(1 == ~E_6~0); 119392#L839-1 assume { :end_inline_reset_delta_events } true; 119393#L1065-2 [2021-12-19 19:15:57,474 INFO L793 eck$LassoCheckResult]: Loop: 119393#L1065-2 assume !false; 130948#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130945#L671 assume !false; 130944#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 130939#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 130932#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 130930#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 130928#L582 assume !(0 != eval_~tmp~0#1); 130929#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 133830#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 133828#L696-3 assume !(0 == ~M_E~0); 133826#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 133824#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 133822#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 133820#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 133818#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 133816#L721-3 assume !(0 == ~T6_E~0); 133814#L726-3 assume !(0 == ~E_M~0); 133812#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 133810#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 133808#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 133806#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 133804#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 133801#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 133799#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133797#L346-24 assume 1 == ~m_pc~0; 133794#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 133792#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133790#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133788#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 133786#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133784#L365-24 assume !(1 == ~t1_pc~0); 133782#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 133780#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133778#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133777#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 133774#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133772#L384-24 assume !(1 == ~t2_pc~0); 133770#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 133767#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133766#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 133742#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 133741#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132613#L403-24 assume !(1 == ~t3_pc~0); 132611#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 132608#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132606#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132604#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132603#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127846#L422-24 assume !(1 == ~t4_pc~0); 127844#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 127842#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127840#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 127838#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127836#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127834#L441-24 assume 1 == ~t5_pc~0; 127831#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127828#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127825#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 127822#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 127820#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 127818#L460-24 assume !(1 == ~t6_pc~0); 127727#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 127815#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 127812#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 127810#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 127808#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127806#L774-3 assume !(1 == ~M_E~0); 125155#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 127803#L779-3 assume !(1 == ~T2_E~0); 127801#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 127799#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 127797#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 127795#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 127793#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 127789#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 127786#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 127784#L819-3 assume !(1 == ~E_3~0); 127782#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 127780#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 127778#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 127776#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 127774#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 127767#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 127765#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 119193#L1084 assume !(0 == start_simulation_~tmp~3#1); 119195#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 130969#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 130965#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 130963#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 130961#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130957#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130955#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 130953#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 119393#L1065-2 [2021-12-19 19:15:57,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:57,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2021-12-19 19:15:57,475 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:57,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161307535] [2021-12-19 19:15:57,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:57,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:57,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:57,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:57,497 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:57,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161307535] [2021-12-19 19:15:57,497 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161307535] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:57,497 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:57,497 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:57,497 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011825966] [2021-12-19 19:15:57,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:57,499 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:57,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:57,499 INFO L85 PathProgramCache]: Analyzing trace with hash -1159117248, now seen corresponding path program 1 times [2021-12-19 19:15:57,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:57,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248496222] [2021-12-19 19:15:57,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:57,500 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:57,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:57,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:57,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:57,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248496222] [2021-12-19 19:15:57,516 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248496222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:57,516 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:57,517 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:57,517 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072416806] [2021-12-19 19:15:57,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:57,517 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:57,517 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:57,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:57,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:57,518 INFO L87 Difference]: Start difference. First operand 15082 states and 21697 transitions. cyclomatic complexity: 6617 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:57,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:57,728 INFO L93 Difference]: Finished difference Result 24092 states and 34525 transitions. [2021-12-19 19:15:57,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:57,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24092 states and 34525 transitions. [2021-12-19 19:15:57,862 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23904 [2021-12-19 19:15:57,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24092 states to 24092 states and 34525 transitions. [2021-12-19 19:15:57,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24092 [2021-12-19 19:15:57,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24092 [2021-12-19 19:15:57,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24092 states and 34525 transitions. [2021-12-19 19:15:58,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:58,022 INFO L681 BuchiCegarLoop]: Abstraction has 24092 states and 34525 transitions. [2021-12-19 19:15:58,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24092 states and 34525 transitions. [2021-12-19 19:15:58,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24092 to 17225. [2021-12-19 19:15:58,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17225 states, 17225 states have (on average 1.4365166908563134) internal successors, (24744), 17224 states have internal predecessors, (24744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17225 states to 17225 states and 24744 transitions. [2021-12-19 19:15:58,322 INFO L704 BuchiCegarLoop]: Abstraction has 17225 states and 24744 transitions. [2021-12-19 19:15:58,322 INFO L587 BuchiCegarLoop]: Abstraction has 17225 states and 24744 transitions. [2021-12-19 19:15:58,322 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:15:58,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17225 states and 24744 transitions. [2021-12-19 19:15:58,356 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17056 [2021-12-19 19:15:58,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:58,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:58,358 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,358 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,359 INFO L791 eck$LassoCheckResult]: Stem: 159131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 159060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 159004#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 158934#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158935#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 158562#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158563#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158410#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158411#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158379#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158380#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 158540#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158702#L696 assume !(0 == ~M_E~0); 158703#L696-2 assume !(0 == ~T1_E~0); 159033#L701-1 assume !(0 == ~T2_E~0); 159036#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 158824#L711-1 assume !(0 == ~T4_E~0); 158825#L716-1 assume !(0 == ~T5_E~0); 159079#L721-1 assume !(0 == ~T6_E~0); 159080#L726-1 assume !(0 == ~E_M~0); 159179#L731-1 assume !(0 == ~E_1~0); 159178#L736-1 assume !(0 == ~E_2~0); 158833#L741-1 assume !(0 == ~E_3~0); 158834#L746-1 assume !(0 == ~E_4~0); 158628#L751-1 assume !(0 == ~E_5~0); 158629#L756-1 assume !(0 == ~E_6~0); 158720#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159176#L346 assume !(1 == ~m_pc~0); 159174#L346-2 is_master_triggered_~__retres1~0#1 := 0; 159173#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159172#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159051#L861 assume !(0 != activate_threads_~tmp~1#1); 158986#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158987#L365 assume !(1 == ~t1_pc~0); 159170#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159169#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159168#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159167#L869 assume !(0 != activate_threads_~tmp___0~0#1); 159166#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159165#L384 assume !(1 == ~t2_pc~0); 159163#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159111#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158535#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158536#L877 assume !(0 != activate_threads_~tmp___1~0#1); 159161#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159160#L403 assume !(1 == ~t3_pc~0); 159159#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159158#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158583#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158584#L885 assume !(0 != activate_threads_~tmp___2~0#1); 158711#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158712#L422 assume !(1 == ~t4_pc~0); 159022#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159154#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159153#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159152#L893 assume !(0 != activate_threads_~tmp___3~0#1); 158807#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158381#L441 assume !(1 == ~t5_pc~0); 158382#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158982#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159148#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159147#L901 assume !(0 != activate_threads_~tmp___4~0#1); 158816#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158817#L460 assume !(1 == ~t6_pc~0); 158950#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 159027#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 159052#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 158945#L909 assume !(0 != activate_threads_~tmp___5~0#1); 158946#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158788#L774 assume !(1 == ~M_E~0); 158789#L774-2 assume !(1 == ~T1_E~0); 159141#L779-1 assume !(1 == ~T2_E~0); 159140#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158683#L789-1 assume !(1 == ~T4_E~0); 158442#L794-1 assume !(1 == ~T5_E~0); 158443#L799-1 assume !(1 == ~T6_E~0); 159091#L804-1 assume !(1 == ~E_M~0); 159092#L809-1 assume !(1 == ~E_1~0); 158772#L814-1 assume !(1 == ~E_2~0); 158343#L819-1 assume !(1 == ~E_3~0); 158344#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 158841#L829-1 assume !(1 == ~E_5~0); 158954#L834-1 assume !(1 == ~E_6~0); 158575#L839-1 assume { :end_inline_reset_delta_events } true; 158576#L1065-2 [2021-12-19 19:15:58,359 INFO L793 eck$LassoCheckResult]: Loop: 158576#L1065-2 assume !false; 166731#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 166728#L671 assume !false; 166726#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 166720#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 166713#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 166711#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 166709#L582 assume !(0 != eval_~tmp~0#1); 159096#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159097#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 167449#L696-3 assume !(0 == ~M_E~0); 167263#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 167264#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 167146#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 167147#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 167140#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 167141#L721-3 assume !(0 == ~T6_E~0); 167134#L726-3 assume !(0 == ~E_M~0); 167135#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 167129#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 167130#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 167124#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 167125#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 167119#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 167120#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 167114#L346-24 assume 1 == ~m_pc~0; 167115#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 167109#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167110#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 166980#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 166981#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 166976#L365-24 assume !(1 == ~t1_pc~0); 166977#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 166971#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 166972#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 166965#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 166966#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166958#L384-24 assume !(1 == ~t2_pc~0); 166959#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 166574#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 166575#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 165973#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 165974#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165519#L403-24 assume !(1 == ~t3_pc~0); 165520#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 165506#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165507#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 165396#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 165397#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164093#L422-24 assume !(1 == ~t4_pc~0); 164094#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 164089#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164090#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164082#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 164083#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164075#L441-24 assume 1 == ~t5_pc~0; 164076#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164067#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164068#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163913#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163914#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163908#L460-24 assume !(1 == ~t6_pc~0); 163907#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 163906#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163905#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163904#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163903#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163902#L774-3 assume !(1 == ~M_E~0); 162919#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163901#L779-3 assume !(1 == ~T2_E~0); 163899#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163896#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163894#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163892#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 163890#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 163877#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 163865#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 163856#L819-3 assume !(1 == ~E_3~0); 163848#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163838#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163835#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 163823#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 163802#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 163786#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 163782#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 163598#L1084 assume !(0 == start_simulation_~tmp~3#1); 163599#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 166749#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 166745#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 166743#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 166741#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 166739#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 166737#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 166735#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 158576#L1065-2 [2021-12-19 19:15:58,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,360 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2021-12-19 19:15:58,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410694440] [2021-12-19 19:15:58,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,360 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410694440] [2021-12-19 19:15:58,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410694440] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,376 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664308079] [2021-12-19 19:15:58,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,376 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:58,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1159117248, now seen corresponding path program 2 times [2021-12-19 19:15:58,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774050860] [2021-12-19 19:15:58,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774050860] [2021-12-19 19:15:58,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774050860] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,394 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,395 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689372174] [2021-12-19 19:15:58,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,395 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:58,395 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:58,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:58,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:58,396 INFO L87 Difference]: Start difference. First operand 17225 states and 24744 transitions. cyclomatic complexity: 7521 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:58,469 INFO L93 Difference]: Finished difference Result 21938 states and 31343 transitions. [2021-12-19 19:15:58,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:58,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21938 states and 31343 transitions. [2021-12-19 19:15:58,532 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21824 [2021-12-19 19:15:58,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21938 states to 21938 states and 31343 transitions. [2021-12-19 19:15:58,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21938 [2021-12-19 19:15:58,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21938 [2021-12-19 19:15:58,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21938 states and 31343 transitions. [2021-12-19 19:15:58,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:58,695 INFO L681 BuchiCegarLoop]: Abstraction has 21938 states and 31343 transitions. [2021-12-19 19:15:58,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21938 states and 31343 transitions. [2021-12-19 19:15:58,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21938 to 15082. [2021-12-19 19:15:58,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15082 states, 15082 states have (on average 1.43210449542501) internal successors, (21599), 15081 states have internal predecessors, (21599), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15082 states to 15082 states and 21599 transitions. [2021-12-19 19:15:58,862 INFO L704 BuchiCegarLoop]: Abstraction has 15082 states and 21599 transitions. [2021-12-19 19:15:58,862 INFO L587 BuchiCegarLoop]: Abstraction has 15082 states and 21599 transitions. [2021-12-19 19:15:58,862 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:15:58,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15082 states and 21599 transitions. [2021-12-19 19:15:58,891 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14976 [2021-12-19 19:15:58,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:58,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:58,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,894 INFO L791 eck$LassoCheckResult]: Stem: 198300#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 198233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 198186#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 198116#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 198117#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 197733#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 197734#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197583#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197584#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197552#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 197553#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 197711#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 197883#L696 assume !(0 == ~M_E~0); 197884#L696-2 assume !(0 == ~T1_E~0); 198212#L701-1 assume !(0 == ~T2_E~0); 198214#L706-1 assume !(0 == ~T3_E~0); 198005#L711-1 assume !(0 == ~T4_E~0); 197767#L716-1 assume !(0 == ~T5_E~0); 197768#L721-1 assume !(0 == ~T6_E~0); 197955#L726-1 assume !(0 == ~E_M~0); 197956#L731-1 assume !(0 == ~E_1~0); 197924#L736-1 assume !(0 == ~E_2~0); 197925#L741-1 assume !(0 == ~E_3~0); 198015#L746-1 assume !(0 == ~E_4~0); 197802#L751-1 assume !(0 == ~E_5~0); 197803#L756-1 assume !(0 == ~E_6~0); 197764#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197598#L346 assume !(1 == ~m_pc~0); 197599#L346-2 is_master_triggered_~__retres1~0#1 := 0; 197814#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197516#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197517#L861 assume !(0 != activate_threads_~tmp~1#1); 198170#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197630#L365 assume !(1 == ~t1_pc~0); 197631#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 198185#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 198187#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 197620#L869 assume !(0 != activate_threads_~tmp___0~0#1); 197621#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198070#L384 assume !(1 == ~t2_pc~0); 198062#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 198063#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197707#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 197535#L877 assume !(0 != activate_threads_~tmp___1~0#1); 197536#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197901#L403 assume !(1 == ~t3_pc~0); 197902#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 198111#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197757#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 197758#L885 assume !(0 != activate_threads_~tmp___2~0#1); 197892#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197893#L422 assume !(1 == ~t4_pc~0); 198028#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 198029#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198066#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198067#L893 assume !(0 != activate_threads_~tmp___3~0#1); 197988#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 197554#L441 assume !(1 == ~t5_pc~0); 197555#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 198165#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198235#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198236#L901 assume !(0 != activate_threads_~tmp___4~0#1); 197998#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 197999#L460 assume !(1 == ~t6_pc~0); 198135#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 197561#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197562#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198130#L909 assume !(0 != activate_threads_~tmp___5~0#1); 198131#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197966#L774 assume !(1 == ~M_E~0); 197967#L774-2 assume !(1 == ~T1_E~0); 198146#L779-1 assume !(1 == ~T2_E~0); 197862#L784-1 assume !(1 == ~T3_E~0); 197863#L789-1 assume !(1 == ~T4_E~0); 197614#L794-1 assume !(1 == ~T5_E~0); 197615#L799-1 assume !(1 == ~T6_E~0); 198263#L804-1 assume !(1 == ~E_M~0); 198264#L809-1 assume !(1 == ~E_1~0); 197950#L814-1 assume !(1 == ~E_2~0); 197518#L819-1 assume !(1 == ~E_3~0); 197519#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 198022#L829-1 assume !(1 == ~E_5~0); 198138#L834-1 assume !(1 == ~E_6~0); 197749#L839-1 assume { :end_inline_reset_delta_events } true; 197750#L1065-2 [2021-12-19 19:15:58,894 INFO L793 eck$LassoCheckResult]: Loop: 197750#L1065-2 assume !false; 208558#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208554#L671 assume !false; 208552#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 208548#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 208541#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 208539#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 208537#L582 assume !(0 != eval_~tmp~0#1); 208538#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 209590#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 209586#L696-3 assume !(0 == ~M_E~0); 209582#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 209578#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 209574#L706-3 assume !(0 == ~T3_E~0); 209570#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 209566#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 209562#L721-3 assume !(0 == ~T6_E~0); 209558#L726-3 assume !(0 == ~E_M~0); 209554#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 209550#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 209546#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 209542#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 209538#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 209534#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 209530#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209526#L346-24 assume !(1 == ~m_pc~0); 209522#L346-26 is_master_triggered_~__retres1~0#1 := 0; 209514#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 209510#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 209506#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 209502#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209496#L365-24 assume !(1 == ~t1_pc~0); 209493#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 209491#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209489#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 209487#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 209485#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209483#L384-24 assume !(1 == ~t2_pc~0); 209481#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 209477#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209475#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 209473#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 209471#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209192#L403-24 assume !(1 == ~t3_pc~0); 209186#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 209184#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209182#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209180#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 209171#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 209166#L422-24 assume !(1 == ~t4_pc~0); 208976#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 209155#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209147#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 209140#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 209134#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 209129#L441-24 assume 1 == ~t5_pc~0; 209123#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 209115#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 209108#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 209101#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 209093#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 209086#L460-24 assume !(1 == ~t6_pc~0); 206383#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 209074#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209068#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 209062#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 209056#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 209051#L774-3 assume !(1 == ~M_E~0); 205377#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 209040#L779-3 assume !(1 == ~T2_E~0); 209034#L784-3 assume !(1 == ~T3_E~0); 209029#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 209024#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 209018#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 209011#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 209006#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 209002#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 208996#L819-3 assume !(1 == ~E_3~0); 208989#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 208984#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 208977#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 208972#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 208924#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 208915#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 208804#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 197547#L1084 assume !(0 == start_simulation_~tmp~3#1); 197549#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 208585#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 208579#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 208578#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 208576#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 208574#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 208572#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 208570#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 197750#L1065-2 [2021-12-19 19:15:58,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,895 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2021-12-19 19:15:58,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203425368] [2021-12-19 19:15:58,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,916 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203425368] [2021-12-19 19:15:58,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [203425368] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,917 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78016388] [2021-12-19 19:15:58,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:58,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1213339967, now seen corresponding path program 1 times [2021-12-19 19:15:58,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065110935] [2021-12-19 19:15:58,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,918 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065110935] [2021-12-19 19:15:58,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065110935] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131438578] [2021-12-19 19:15:58,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,936 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:58,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:58,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:58,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:58,937 INFO L87 Difference]: Start difference. First operand 15082 states and 21599 transitions. cyclomatic complexity: 6519 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:59,129 INFO L93 Difference]: Finished difference Result 23828 states and 33875 transitions. [2021-12-19 19:15:59,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:59,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23828 states and 33875 transitions. [2021-12-19 19:15:59,201 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23640 [2021-12-19 19:15:59,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23828 states to 23828 states and 33875 transitions. [2021-12-19 19:15:59,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23828 [2021-12-19 19:15:59,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23828 [2021-12-19 19:15:59,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23828 states and 33875 transitions. [2021-12-19 19:15:59,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:59,277 INFO L681 BuchiCegarLoop]: Abstraction has 23828 states and 33875 transitions. [2021-12-19 19:15:59,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23828 states and 33875 transitions. [2021-12-19 19:15:59,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23828 to 17209. [2021-12-19 19:15:59,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17209 states, 17209 states have (on average 1.4251844964843976) internal successors, (24526), 17208 states have internal predecessors, (24526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17209 states to 17209 states and 24526 transitions. [2021-12-19 19:15:59,446 INFO L704 BuchiCegarLoop]: Abstraction has 17209 states and 24526 transitions. [2021-12-19 19:15:59,446 INFO L587 BuchiCegarLoop]: Abstraction has 17209 states and 24526 transitions. [2021-12-19 19:15:59,446 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:15:59,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17209 states and 24526 transitions. [2021-12-19 19:15:59,490 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17040 [2021-12-19 19:15:59,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:59,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:59,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,493 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,493 INFO L791 eck$LassoCheckResult]: Stem: 237245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 237173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 237107#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 237031#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 237032#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 236649#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 236650#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 236503#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 236504#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 236471#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 236472#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 236628#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 236794#L696 assume !(0 == ~M_E~0); 236795#L696-2 assume !(0 == ~T1_E~0); 237138#L701-1 assume !(0 == ~T2_E~0); 237139#L706-1 assume !(0 == ~T3_E~0); 236918#L711-1 assume !(0 == ~T4_E~0); 236682#L716-1 assume !(0 == ~T5_E~0); 236683#L721-1 assume !(0 == ~T6_E~0); 236867#L726-1 assume !(0 == ~E_M~0); 236868#L731-1 assume !(0 == ~E_1~0); 236834#L736-1 assume !(0 == ~E_2~0); 236835#L741-1 assume !(0 == ~E_3~0); 236926#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 236715#L751-1 assume !(0 == ~E_5~0); 236716#L756-1 assume !(0 == ~E_6~0); 236812#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237295#L346 assume !(1 == ~m_pc~0); 236729#L346-2 is_master_triggered_~__retres1~0#1 := 0; 236730#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237294#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 237159#L861 assume !(0 != activate_threads_~tmp~1#1); 237091#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237092#L365 assume !(1 == ~t1_pc~0); 237292#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 237291#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237290#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 237289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 236981#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 236982#L384 assume !(1 == ~t2_pc~0); 237113#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 237217#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 236626#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 236627#L877 assume !(0 != activate_threads_~tmp___1~0#1); 237286#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237285#L403 assume !(1 == ~t3_pc~0); 237284#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 237248#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237249#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 237283#L885 assume !(0 != activate_threads_~tmp___2~0#1); 237282#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237281#L422 assume !(1 == ~t4_pc~0); 236937#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 236938#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 236979#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 236980#L893 assume !(0 != activate_threads_~tmp___3~0#1); 237074#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237277#L441 assume !(1 == ~t5_pc~0); 237086#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 237087#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237176#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 237177#L901 assume !(0 != activate_threads_~tmp___4~0#1); 237259#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 237270#L460 assume !(1 == ~t6_pc~0); 237269#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 236482#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 236483#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 237268#L909 assume !(0 != activate_threads_~tmp___5~0#1); 237151#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 237152#L774 assume !(1 == ~M_E~0); 237197#L774-2 assume !(1 == ~T1_E~0); 237063#L779-1 assume !(1 == ~T2_E~0); 236771#L784-1 assume !(1 == ~T3_E~0); 236772#L789-1 assume !(1 == ~T4_E~0); 237265#L794-1 assume !(1 == ~T5_E~0); 237264#L799-1 assume !(1 == ~T6_E~0); 237204#L804-1 assume !(1 == ~E_M~0); 237205#L809-1 assume !(1 == ~E_1~0); 237263#L814-1 assume !(1 == ~E_2~0); 236437#L819-1 assume !(1 == ~E_3~0); 236438#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 236934#L829-1 assume !(1 == ~E_5~0); 237053#L834-1 assume !(1 == ~E_6~0); 236665#L839-1 assume { :end_inline_reset_delta_events } true; 236666#L1065-2 [2021-12-19 19:15:59,493 INFO L793 eck$LassoCheckResult]: Loop: 236666#L1065-2 assume !false; 249183#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 249180#L671 assume !false; 249179#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 248927#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 248921#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 248920#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 248917#L582 assume !(0 != eval_~tmp~0#1); 248918#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 253188#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 253186#L696-3 assume !(0 == ~M_E~0); 253184#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 253182#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 253180#L706-3 assume !(0 == ~T3_E~0); 253178#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 253176#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 253174#L721-3 assume !(0 == ~T6_E~0); 253172#L726-3 assume !(0 == ~E_M~0); 253170#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 253167#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 253165#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 236676#L746-3 assume !(0 == ~E_4~0); 236678#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 253600#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 253599#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253598#L346-24 assume !(1 == ~m_pc~0); 253597#L346-26 is_master_triggered_~__retres1~0#1 := 0; 253595#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253594#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253592#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 253590#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253588#L365-24 assume !(1 == ~t1_pc~0); 253585#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 253583#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253581#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253579#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 253577#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253575#L384-24 assume 1 == ~t2_pc~0; 253571#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 253569#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253568#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253533#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 253529#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253523#L403-24 assume !(1 == ~t3_pc~0); 252800#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 253515#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253511#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253508#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 253506#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 253501#L422-24 assume !(1 == ~t4_pc~0); 253010#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 253493#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253492#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 253491#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 253489#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253488#L441-24 assume 1 == ~t5_pc~0; 253487#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 253485#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253483#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 253480#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 236993#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 236994#L460-24 assume !(1 == ~t6_pc~0); 249994#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 249992#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 249991#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 249990#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 249988#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 249986#L774-3 assume !(1 == ~M_E~0); 242653#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 249983#L779-3 assume !(1 == ~T2_E~0); 249981#L784-3 assume !(1 == ~T3_E~0); 249979#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 249977#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 249975#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 249973#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 249971#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 249969#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 249967#L819-3 assume !(1 == ~E_3~0); 247972#L824-3 assume !(1 == ~E_4~0); 247970#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 247969#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 247968#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 247962#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 247950#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 247947#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 242729#L1084 assume !(0 == start_simulation_~tmp~3#1); 242730#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 249204#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 249200#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 249198#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 249196#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 249192#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 249190#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 249188#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 236666#L1065-2 [2021-12-19 19:15:59,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2021-12-19 19:15:59,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610522832] [2021-12-19 19:15:59,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,494 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610522832] [2021-12-19 19:15:59,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610522832] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,512 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113602752] [2021-12-19 19:15:59,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:59,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,514 INFO L85 PathProgramCache]: Analyzing trace with hash -90750912, now seen corresponding path program 1 times [2021-12-19 19:15:59,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702595755] [2021-12-19 19:15:59,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,532 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,532 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702595755] [2021-12-19 19:15:59,532 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702595755] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,532 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,533 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923690520] [2021-12-19 19:15:59,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,533 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:59,533 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:59,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:59,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:59,534 INFO L87 Difference]: Start difference. First operand 17209 states and 24526 transitions. cyclomatic complexity: 7319 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:59,712 INFO L93 Difference]: Finished difference Result 21526 states and 30505 transitions. [2021-12-19 19:15:59,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:59,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21526 states and 30505 transitions. [2021-12-19 19:15:59,778 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21404 [2021-12-19 19:15:59,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21526 states to 21526 states and 30505 transitions. [2021-12-19 19:15:59,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21526 [2021-12-19 19:15:59,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21526 [2021-12-19 19:15:59,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21526 states and 30505 transitions. [2021-12-19 19:15:59,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:59,848 INFO L681 BuchiCegarLoop]: Abstraction has 21526 states and 30505 transitions. [2021-12-19 19:15:59,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21526 states and 30505 transitions. [2021-12-19 19:15:59,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21526 to 15082. [2021-12-19 19:15:59,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15082 states, 15082 states have (on average 1.418711046280334) internal successors, (21397), 15081 states have internal predecessors, (21397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15082 states to 15082 states and 21397 transitions. [2021-12-19 19:15:59,998 INFO L704 BuchiCegarLoop]: Abstraction has 15082 states and 21397 transitions. [2021-12-19 19:15:59,998 INFO L587 BuchiCegarLoop]: Abstraction has 15082 states and 21397 transitions. [2021-12-19 19:15:59,998 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:15:59,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15082 states and 21397 transitions. [2021-12-19 19:16:00,031 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14976 [2021-12-19 19:16:00,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:00,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:00,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,033 INFO L791 eck$LassoCheckResult]: Stem: 276001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 275926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 275867#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 275783#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 275784#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 275396#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 275397#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 275249#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 275250#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 275217#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 275218#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 275375#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 275538#L696 assume !(0 == ~M_E~0); 275539#L696-2 assume !(0 == ~T1_E~0); 275897#L701-1 assume !(0 == ~T2_E~0); 275898#L706-1 assume !(0 == ~T3_E~0); 275669#L711-1 assume !(0 == ~T4_E~0); 275428#L716-1 assume !(0 == ~T5_E~0); 275429#L721-1 assume !(0 == ~T6_E~0); 275616#L726-1 assume !(0 == ~E_M~0); 275617#L731-1 assume !(0 == ~E_1~0); 275578#L736-1 assume !(0 == ~E_2~0); 275579#L741-1 assume !(0 == ~E_3~0); 275675#L746-1 assume !(0 == ~E_4~0); 275461#L751-1 assume !(0 == ~E_5~0); 275462#L756-1 assume !(0 == ~E_6~0); 275425#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275263#L346 assume !(1 == ~m_pc~0); 275264#L346-2 is_master_triggered_~__retres1~0#1 := 0; 275474#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275181#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 275182#L861 assume !(0 != activate_threads_~tmp~1#1); 275849#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275296#L365 assume !(1 == ~t1_pc~0); 275297#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 275866#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 275871#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 275286#L869 assume !(0 != activate_threads_~tmp___0~0#1); 275287#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 275734#L384 assume !(1 == ~t2_pc~0); 275726#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 275727#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 275374#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 275202#L877 assume !(0 != activate_threads_~tmp___1~0#1); 275203#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275556#L403 assume !(1 == ~t3_pc~0); 275557#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 275777#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275421#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 275422#L885 assume !(0 != activate_threads_~tmp___2~0#1); 275548#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275549#L422 assume !(1 == ~t4_pc~0); 275687#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 275688#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275732#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 275733#L893 assume !(0 != activate_threads_~tmp___3~0#1); 275649#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 275219#L441 assume !(1 == ~t5_pc~0); 275220#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 275842#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275928#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 275929#L901 assume !(0 != activate_threads_~tmp___4~0#1); 275659#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 275660#L460 assume !(1 == ~t6_pc~0); 275803#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 275228#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 275229#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275798#L909 assume !(0 != activate_threads_~tmp___5~0#1); 275799#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275627#L774 assume !(1 == ~M_E~0); 275628#L774-2 assume !(1 == ~T1_E~0); 275817#L779-1 assume !(1 == ~T2_E~0); 275515#L784-1 assume !(1 == ~T3_E~0); 275516#L789-1 assume !(1 == ~T4_E~0); 275279#L794-1 assume !(1 == ~T5_E~0); 275280#L799-1 assume !(1 == ~T6_E~0); 275955#L804-1 assume !(1 == ~E_M~0); 275956#L809-1 assume !(1 == ~E_1~0); 275611#L814-1 assume !(1 == ~E_2~0); 275183#L819-1 assume !(1 == ~E_3~0); 275184#L824-1 assume !(1 == ~E_4~0); 275684#L829-1 assume !(1 == ~E_5~0); 275807#L834-1 assume !(1 == ~E_6~0); 275412#L839-1 assume { :end_inline_reset_delta_events } true; 275413#L1065-2 [2021-12-19 19:16:00,033 INFO L793 eck$LassoCheckResult]: Loop: 275413#L1065-2 assume !false; 284020#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 284009#L671 assume !false; 284004#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 283991#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 283980#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 283974#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 283966#L582 assume !(0 != eval_~tmp~0#1); 283967#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 290150#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290148#L696-3 assume !(0 == ~M_E~0); 290143#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 290141#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 290139#L706-3 assume !(0 == ~T3_E~0); 290137#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 290134#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 290133#L721-3 assume !(0 == ~T6_E~0); 290132#L726-3 assume !(0 == ~E_M~0); 290131#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 275880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 275673#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 275423#L746-3 assume !(0 == ~E_4~0); 275424#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 275550#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 275305#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275306#L346-24 assume 1 == ~m_pc~0; 275335#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 275414#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275674#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 275868#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 275813#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275814#L365-24 assume !(1 == ~t1_pc~0); 290096#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 290094#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290092#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 290090#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290088#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290086#L384-24 assume !(1 == ~t2_pc~0); 275340#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 275341#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 275872#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 275873#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 290077#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275464#L403-24 assume !(1 == ~t3_pc~0); 275465#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 275497#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275498#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 275977#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 289725#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 289565#L422-24 assume !(1 == ~t4_pc~0); 289564#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 289563#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 289562#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 289561#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 289560#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 289559#L441-24 assume !(1 == ~t5_pc~0); 289556#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 289553#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 289551#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 289549#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 289548#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 288682#L460-24 assume !(1 == ~t6_pc~0); 288680#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 288678#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 288676#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 288674#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 288672#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288670#L774-3 assume !(1 == ~M_E~0); 281258#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 288667#L779-3 assume !(1 == ~T2_E~0); 288665#L784-3 assume !(1 == ~T3_E~0); 288663#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 288661#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 288658#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 288656#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 288654#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 288652#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 288573#L819-3 assume !(1 == ~E_3~0); 288564#L824-3 assume !(1 == ~E_4~0); 288557#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 288240#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 287492#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 287490#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 287484#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282425#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 281392#L1084 assume !(0 == start_simulation_~tmp~3#1); 281393#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 284205#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 284193#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 284191#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 284189#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 284187#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 284185#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 284183#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 275413#L1065-2 [2021-12-19 19:16:00,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,034 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2021-12-19 19:16:00,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504418539] [2021-12-19 19:16:00,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:00,040 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:00,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:00,074 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:00,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1505920963, now seen corresponding path program 1 times [2021-12-19 19:16:00,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938342586] [2021-12-19 19:16:00,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938342586] [2021-12-19 19:16:00,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938342586] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,094 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090443299] [2021-12-19 19:16:00,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,094 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:00,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:00,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:00,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:00,095 INFO L87 Difference]: Start difference. First operand 15082 states and 21397 transitions. cyclomatic complexity: 6317 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:00,146 INFO L93 Difference]: Finished difference Result 17225 states and 24394 transitions. [2021-12-19 19:16:00,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:00,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17225 states and 24394 transitions. [2021-12-19 19:16:00,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17056 [2021-12-19 19:16:00,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17225 states to 17225 states and 24394 transitions. [2021-12-19 19:16:00,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17225 [2021-12-19 19:16:00,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17225 [2021-12-19 19:16:00,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17225 states and 24394 transitions. [2021-12-19 19:16:00,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:00,269 INFO L681 BuchiCegarLoop]: Abstraction has 17225 states and 24394 transitions. [2021-12-19 19:16:00,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17225 states and 24394 transitions. [2021-12-19 19:16:00,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17225 to 17225. [2021-12-19 19:16:00,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17225 states, 17225 states have (on average 1.4161973875181422) internal successors, (24394), 17224 states have internal predecessors, (24394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17225 states to 17225 states and 24394 transitions. [2021-12-19 19:16:00,547 INFO L704 BuchiCegarLoop]: Abstraction has 17225 states and 24394 transitions. [2021-12-19 19:16:00,548 INFO L587 BuchiCegarLoop]: Abstraction has 17225 states and 24394 transitions. [2021-12-19 19:16:00,548 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:16:00,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17225 states and 24394 transitions. [2021-12-19 19:16:00,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17056 [2021-12-19 19:16:00,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:00,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:00,592 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,592 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,593 INFO L791 eck$LassoCheckResult]: Stem: 308308#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 308222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 308173#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 308094#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 308095#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 307712#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307713#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307562#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307563#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307530#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 307531#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 307690#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307855#L696 assume !(0 == ~M_E~0); 307856#L696-2 assume !(0 == ~T1_E~0); 308197#L701-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 308198#L706-1 assume !(0 == ~T3_E~0); 308221#L711-1 assume !(0 == ~T4_E~0); 307744#L716-1 assume !(0 == ~T5_E~0); 307745#L721-1 assume !(0 == ~T6_E~0); 307927#L726-1 assume !(0 == ~E_M~0); 307928#L731-1 assume !(0 == ~E_1~0); 307894#L736-1 assume !(0 == ~E_2~0); 307895#L741-1 assume !(0 == ~E_3~0); 308276#L746-1 assume !(0 == ~E_4~0); 308277#L751-1 assume !(0 == ~E_5~0); 308359#L756-1 assume !(0 == ~E_6~0); 307741#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307576#L346 assume !(1 == ~m_pc~0); 307577#L346-2 is_master_triggered_~__retres1~0#1 := 0; 307790#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308105#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308211#L861 assume !(0 != activate_threads_~tmp~1#1); 308151#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308152#L365 assume !(1 == ~t1_pc~0); 308353#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 308352#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 308351#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308350#L869 assume !(0 != activate_threads_~tmp___0~0#1); 308349#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 308348#L384 assume !(1 == ~t2_pc~0); 308346#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 308278#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307689#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307515#L877 assume !(0 != activate_threads_~tmp___1~0#1); 307516#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307872#L403 assume !(1 == ~t3_pc~0); 307873#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 308088#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 308309#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 308339#L885 assume !(0 != activate_threads_~tmp___2~0#1); 308338#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 308337#L422 assume !(1 == ~t4_pc~0); 308002#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 308003#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308047#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 308048#L893 assume !(0 != activate_threads_~tmp___3~0#1); 308137#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 308333#L441 assume !(1 == ~t5_pc~0); 308205#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 308331#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308329#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 308326#L901 assume !(0 != activate_threads_~tmp___4~0#1); 308325#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 308324#L460 assume !(1 == ~t6_pc~0); 308323#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 307541#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307542#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 308106#L909 assume !(0 != activate_threads_~tmp___5~0#1); 308107#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307939#L774 assume !(1 == ~M_E~0); 307940#L774-2 assume !(1 == ~T1_E~0); 308128#L779-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 307832#L784-1 assume !(1 == ~T3_E~0); 307833#L789-1 assume !(1 == ~T4_E~0); 307592#L794-1 assume !(1 == ~T5_E~0); 307593#L799-1 assume !(1 == ~T6_E~0); 308254#L804-1 assume !(1 == ~E_M~0); 308255#L809-1 assume !(1 == ~E_1~0); 307923#L814-1 assume !(1 == ~E_2~0); 307495#L819-1 assume !(1 == ~E_3~0); 307496#L824-1 assume !(1 == ~E_4~0); 307995#L829-1 assume !(1 == ~E_5~0); 308115#L834-1 assume !(1 == ~E_6~0); 307728#L839-1 assume { :end_inline_reset_delta_events } true; 307729#L1065-2 [2021-12-19 19:16:00,593 INFO L793 eck$LassoCheckResult]: Loop: 307729#L1065-2 assume !false; 312138#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 311121#L671 assume !false; 312135#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 312130#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 312124#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312122#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 312120#L582 assume !(0 != eval_~tmp~0#1); 312121#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317602#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 317600#L696-3 assume !(0 == ~M_E~0); 317598#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 317596#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 317597#L706-3 assume !(0 == ~T3_E~0); 321187#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 321185#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 321183#L721-3 assume !(0 == ~T6_E~0); 321180#L726-3 assume !(0 == ~E_M~0); 321178#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 321176#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 321174#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 321172#L746-3 assume !(0 == ~E_4~0); 321170#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 321169#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 321166#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 321164#L346-24 assume 1 == ~m_pc~0; 321161#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 321159#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 321157#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 321155#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 321154#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 321153#L365-24 assume !(1 == ~t1_pc~0); 321152#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 321151#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321149#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 321148#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 321147#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 321146#L384-24 assume 1 == ~t2_pc~0; 321143#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 321142#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 321141#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 321140#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 321139#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 318846#L403-24 assume !(1 == ~t3_pc~0); 318844#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 318842#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318840#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318839#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 315173#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312720#L422-24 assume !(1 == ~t4_pc~0); 312718#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 312716#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 312714#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 312712#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 312710#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312708#L441-24 assume !(1 == ~t5_pc~0); 312704#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 312702#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 312700#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 312697#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 312694#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 312692#L460-24 assume !(1 == ~t6_pc~0); 312438#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 312689#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 312626#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 312617#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 312608#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312603#L774-3 assume !(1 == ~M_E~0); 312592#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 312584#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 312576#L784-3 assume !(1 == ~T3_E~0); 312569#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 312560#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 312555#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 312549#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 312545#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 312540#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 312535#L819-3 assume !(1 == ~E_3~0); 312530#L824-3 assume !(1 == ~E_4~0); 312524#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 312519#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 312515#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 312181#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 312174#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312171#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 312168#L1084 assume !(0 == start_simulation_~tmp~3#1); 312165#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 312157#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 312154#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312153#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 312152#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 312151#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 312143#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 312141#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 307729#L1065-2 [2021-12-19 19:16:00,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,594 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2021-12-19 19:16:00,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938515029] [2021-12-19 19:16:00,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938515029] [2021-12-19 19:16:00,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938515029] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,610 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059628342] [2021-12-19 19:16:00,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,611 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:00,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,611 INFO L85 PathProgramCache]: Analyzing trace with hash 1125105024, now seen corresponding path program 1 times [2021-12-19 19:16:00,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169850648] [2021-12-19 19:16:00,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,629 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169850648] [2021-12-19 19:16:00,629 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169850648] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,629 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,630 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447103192] [2021-12-19 19:16:00,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,630 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:00,630 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:00,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:00,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:00,631 INFO L87 Difference]: Start difference. First operand 17225 states and 24394 transitions. cyclomatic complexity: 7171 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:00,709 INFO L93 Difference]: Finished difference Result 21950 states and 31033 transitions. [2021-12-19 19:16:00,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:00,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21950 states and 31033 transitions. [2021-12-19 19:16:00,785 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21824 [2021-12-19 19:16:00,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21950 states to 21950 states and 31033 transitions. [2021-12-19 19:16:00,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21950 [2021-12-19 19:16:00,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21950 [2021-12-19 19:16:00,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21950 states and 31033 transitions. [2021-12-19 19:16:00,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:00,871 INFO L681 BuchiCegarLoop]: Abstraction has 21950 states and 31033 transitions. [2021-12-19 19:16:00,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21950 states and 31033 transitions. [2021-12-19 19:16:00,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21950 to 15082. [2021-12-19 19:16:01,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15082 states, 15082 states have (on average 1.4165230075586792) internal successors, (21364), 15081 states have internal predecessors, (21364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15082 states to 15082 states and 21364 transitions. [2021-12-19 19:16:01,025 INFO L704 BuchiCegarLoop]: Abstraction has 15082 states and 21364 transitions. [2021-12-19 19:16:01,025 INFO L587 BuchiCegarLoop]: Abstraction has 15082 states and 21364 transitions. [2021-12-19 19:16:01,025 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:16:01,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15082 states and 21364 transitions. [2021-12-19 19:16:01,060 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14976 [2021-12-19 19:16:01,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:01,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:01,156 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,157 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,157 INFO L791 eck$LassoCheckResult]: Stem: 347432#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 347369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 347328#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 347260#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 347261#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 346893#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 346894#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 346747#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 346748#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 346714#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 346715#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 346871#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 347036#L696 assume !(0 == ~M_E~0); 347037#L696-2 assume !(0 == ~T1_E~0); 347347#L701-1 assume !(0 == ~T2_E~0); 347348#L706-1 assume !(0 == ~T3_E~0); 347154#L711-1 assume !(0 == ~T4_E~0); 346925#L716-1 assume !(0 == ~T5_E~0); 346926#L721-1 assume !(0 == ~T6_E~0); 347104#L726-1 assume !(0 == ~E_M~0); 347105#L731-1 assume !(0 == ~E_1~0); 347075#L736-1 assume !(0 == ~E_2~0); 347076#L741-1 assume !(0 == ~E_3~0); 347161#L746-1 assume !(0 == ~E_4~0); 346960#L751-1 assume !(0 == ~E_5~0); 346961#L756-1 assume !(0 == ~E_6~0); 346922#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346761#L346 assume !(1 == ~m_pc~0); 346762#L346-2 is_master_triggered_~__retres1~0#1 := 0; 346972#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 346678#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 346679#L861 assume !(0 != activate_threads_~tmp~1#1); 347311#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346794#L365 assume !(1 == ~t1_pc~0); 346795#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 347327#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 347332#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 346784#L869 assume !(0 != activate_threads_~tmp___0~0#1); 346785#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 347219#L384 assume !(1 == ~t2_pc~0); 347211#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 347212#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 346870#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 346699#L877 assume !(0 != activate_threads_~tmp___1~0#1); 346700#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 347054#L403 assume !(1 == ~t3_pc~0); 347055#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 347255#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346918#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 346919#L885 assume !(0 != activate_threads_~tmp___2~0#1); 347046#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 347047#L422 assume !(1 == ~t4_pc~0); 347175#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 347176#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 347217#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 347218#L893 assume !(0 != activate_threads_~tmp___3~0#1); 347133#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 346716#L441 assume !(1 == ~t5_pc~0); 346717#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 347305#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 347371#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347372#L901 assume !(0 != activate_threads_~tmp___4~0#1); 347143#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 347144#L460 assume !(1 == ~t6_pc~0); 347277#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 346725#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 346726#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 347272#L909 assume !(0 != activate_threads_~tmp___5~0#1); 347273#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 347114#L774 assume !(1 == ~M_E~0); 347115#L774-2 assume !(1 == ~T1_E~0); 347289#L779-1 assume !(1 == ~T2_E~0); 347014#L784-1 assume !(1 == ~T3_E~0); 347015#L789-1 assume !(1 == ~T4_E~0); 346777#L794-1 assume !(1 == ~T5_E~0); 346778#L799-1 assume !(1 == ~T6_E~0); 347396#L804-1 assume !(1 == ~E_M~0); 347397#L809-1 assume !(1 == ~E_1~0); 347100#L814-1 assume !(1 == ~E_2~0); 346680#L819-1 assume !(1 == ~E_3~0); 346681#L824-1 assume !(1 == ~E_4~0); 347171#L829-1 assume !(1 == ~E_5~0); 347280#L834-1 assume !(1 == ~E_6~0); 346909#L839-1 assume { :end_inline_reset_delta_events } true; 346910#L1065-2 [2021-12-19 19:16:01,157 INFO L793 eck$LassoCheckResult]: Loop: 346910#L1065-2 assume !false; 360325#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 360318#L671 assume !false; 360317#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 360104#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 360098#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 360096#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 360094#L582 assume !(0 != eval_~tmp~0#1); 347398#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 347177#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 346944#L696-3 assume !(0 == ~M_E~0); 346945#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 346994#L701-3 assume !(0 == ~T2_E~0); 346995#L706-3 assume !(0 == ~T3_E~0); 347357#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 347346#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 347164#L721-3 assume !(0 == ~T6_E~0); 346975#L726-3 assume !(0 == ~E_M~0); 346976#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 347158#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 347159#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 346920#L746-3 assume !(0 == ~E_4~0); 346921#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 347048#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 346803#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346804#L346-24 assume 1 == ~m_pc~0; 346833#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 346911#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 347160#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 347329#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 347286#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346864#L365-24 assume !(1 == ~t1_pc~0); 346865#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 347420#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 347031#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 347032#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 347247#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346818#L384-24 assume 1 == ~t2_pc~0; 346820#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 346838#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 347333#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 347145#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 346841#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 346842#L403-24 assume !(1 == ~t3_pc~0); 346963#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 346996#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346997#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 347098#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 347099#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 346895#L422-24 assume !(1 == ~t4_pc~0); 346896#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 361489#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 361488#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 361487#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 361485#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 361484#L441-24 assume !(1 == ~t5_pc~0); 361483#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 361481#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 361479#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 361477#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 361369#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 361368#L460-24 assume !(1 == ~t6_pc~0); 355163#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 361367#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 361366#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 361365#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 361364#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361363#L774-3 assume !(1 == ~M_E~0); 351725#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 361360#L779-3 assume !(1 == ~T2_E~0); 361358#L784-3 assume !(1 == ~T3_E~0); 361356#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 361355#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 361248#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 361247#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 361246#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 361245#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 361244#L819-3 assume !(1 == ~E_3~0); 361243#L824-3 assume !(1 == ~E_4~0); 361242#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 361241#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 361240#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 361238#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 361232#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 361231#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 351806#L1084 assume !(0 == start_simulation_~tmp~3#1); 351807#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 360344#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 360340#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 360339#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 360337#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 360335#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 360333#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 360331#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 346910#L1065-2 [2021-12-19 19:16:01,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,158 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2021-12-19 19:16:01,158 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002057204] [2021-12-19 19:16:01,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:01,164 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:01,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:01,182 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:01,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1462555712, now seen corresponding path program 1 times [2021-12-19 19:16:01,182 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91234687] [2021-12-19 19:16:01,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91234687] [2021-12-19 19:16:01,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91234687] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,202 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:01,202 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043443150] [2021-12-19 19:16:01,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,203 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:01,203 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:01,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:01,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:01,204 INFO L87 Difference]: Start difference. First operand 15082 states and 21364 transitions. cyclomatic complexity: 6284 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:01,308 INFO L93 Difference]: Finished difference Result 26561 states and 37406 transitions. [2021-12-19 19:16:01,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:01,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26561 states and 37406 transitions. [2021-12-19 19:16:01,417 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26376 [2021-12-19 19:16:01,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26561 states to 26561 states and 37406 transitions. [2021-12-19 19:16:01,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26561 [2021-12-19 19:16:01,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26561 [2021-12-19 19:16:01,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26561 states and 37406 transitions. [2021-12-19 19:16:01,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:01,532 INFO L681 BuchiCegarLoop]: Abstraction has 26561 states and 37406 transitions. [2021-12-19 19:16:01,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26561 states and 37406 transitions. [2021-12-19 19:16:01,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26561 to 26529. [2021-12-19 19:16:01,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26529 states, 26529 states have (on average 1.4087979192581703) internal successors, (37374), 26528 states have internal predecessors, (37374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26529 states to 26529 states and 37374 transitions. [2021-12-19 19:16:01,829 INFO L704 BuchiCegarLoop]: Abstraction has 26529 states and 37374 transitions. [2021-12-19 19:16:01,829 INFO L587 BuchiCegarLoop]: Abstraction has 26529 states and 37374 transitions. [2021-12-19 19:16:01,829 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:16:01,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26529 states and 37374 transitions. [2021-12-19 19:16:01,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26344 [2021-12-19 19:16:01,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:01,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:01,916 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,916 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,916 INFO L791 eck$LassoCheckResult]: Stem: 389148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 389076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 389019#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 388938#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 388939#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 388543#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 388544#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 388394#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 388395#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 388363#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 388364#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 388522#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 388693#L696 assume !(0 == ~M_E~0); 388694#L696-2 assume !(0 == ~T1_E~0); 389046#L701-1 assume !(0 == ~T2_E~0); 389048#L706-1 assume !(0 == ~T3_E~0); 388823#L711-1 assume !(0 == ~T4_E~0); 388577#L716-1 assume !(0 == ~T5_E~0); 388578#L721-1 assume !(0 == ~T6_E~0); 388771#L726-1 assume !(0 == ~E_M~0); 388772#L731-1 assume !(0 == ~E_1~0); 388735#L736-1 assume !(0 == ~E_2~0); 388736#L741-1 assume 0 == ~E_3~0;~E_3~0 := 1; 388835#L746-1 assume !(0 == ~E_4~0); 388612#L751-1 assume !(0 == ~E_5~0); 388613#L756-1 assume !(0 == ~E_6~0); 388711#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 389203#L346 assume !(1 == ~m_pc~0); 388624#L346-2 is_master_triggered_~__retres1~0#1 := 0; 388625#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 389202#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 389065#L861 assume !(0 != activate_threads_~tmp~1#1); 388999#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 389000#L365 assume !(1 == ~t1_pc~0); 389200#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 389199#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 389198#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 389197#L869 assume !(0 != activate_threads_~tmp___0~0#1); 388894#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 388895#L384 assume !(1 == ~t2_pc~0); 389026#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 389126#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 388518#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 388519#L877 assume !(0 != activate_threads_~tmp___1~0#1); 389194#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 389193#L403 assume !(1 == ~t3_pc~0); 389192#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 389191#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 388564#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 388565#L885 assume !(0 != activate_threads_~tmp___2~0#1); 388702#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 388703#L422 assume !(1 == ~t4_pc~0); 389038#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 389187#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 389186#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 389185#L893 assume !(0 != activate_threads_~tmp___3~0#1); 388802#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 388365#L441 assume !(1 == ~t5_pc~0); 388366#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 388994#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 389119#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 389180#L901 assume !(0 != activate_threads_~tmp___4~0#1); 388813#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 388814#L460 assume !(1 == ~t6_pc~0); 388958#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 389042#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 389067#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 388953#L909 assume !(0 != activate_threads_~tmp___5~0#1); 388954#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 388783#L774 assume !(1 == ~M_E~0); 388784#L774-2 assume !(1 == ~T1_E~0); 389176#L779-1 assume !(1 == ~T2_E~0); 389175#L784-1 assume !(1 == ~T3_E~0); 389097#L789-1 assume !(1 == ~T4_E~0); 388425#L794-1 assume !(1 == ~T5_E~0); 388426#L799-1 assume !(1 == ~T6_E~0); 389170#L804-1 assume !(1 == ~E_M~0); 389169#L809-1 assume !(1 == ~E_1~0); 389168#L814-1 assume !(1 == ~E_2~0); 388327#L819-1 assume 1 == ~E_3~0;~E_3~0 := 2; 388328#L824-1 assume !(1 == ~E_4~0); 388843#L829-1 assume !(1 == ~E_5~0); 388961#L834-1 assume !(1 == ~E_6~0); 388556#L839-1 assume { :end_inline_reset_delta_events } true; 388557#L1065-2 [2021-12-19 19:16:01,916 INFO L793 eck$LassoCheckResult]: Loop: 388557#L1065-2 assume !false; 401916#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 401913#L671 assume !false; 401912#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401855#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401848#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401846#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 401833#L582 assume !(0 != eval_~tmp~0#1); 401834#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 411697#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 411695#L696-3 assume !(0 == ~M_E~0); 411693#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 411691#L701-3 assume !(0 == ~T2_E~0); 411689#L706-3 assume !(0 == ~T3_E~0); 411685#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 411683#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 411681#L721-3 assume !(0 == ~T6_E~0); 411679#L726-3 assume !(0 == ~E_M~0); 411677#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 411675#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 411671#L741-3 assume !(0 == ~E_3~0); 411669#L746-3 assume !(0 == ~E_4~0); 411665#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 411662#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 411659#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 411658#L346-24 assume 1 == ~m_pc~0; 411656#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 411655#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 411653#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 411651#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 411649#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 411647#L365-24 assume !(1 == ~t1_pc~0); 411644#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 411645#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 411639#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 411637#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 411636#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 411633#L384-24 assume !(1 == ~t2_pc~0); 411630#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 411627#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 411625#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 411621#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 411620#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 402196#L403-24 assume !(1 == ~t3_pc~0); 402191#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 402186#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 402181#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 402176#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 402171#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402167#L422-24 assume !(1 == ~t4_pc~0); 401872#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 402161#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 402156#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 402151#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 402146#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 402142#L441-24 assume 1 == ~t5_pc~0; 402134#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 402125#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 402116#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402107#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 402101#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 402095#L460-24 assume !(1 == ~t6_pc~0); 396624#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 402087#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 402081#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 402076#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 402071#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 402066#L774-3 assume !(1 == ~M_E~0); 402061#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 402057#L779-3 assume !(1 == ~T2_E~0); 402052#L784-3 assume !(1 == ~T3_E~0); 402048#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 402043#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 402039#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 402035#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 402031#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 402027#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 402023#L819-3 assume !(1 == ~E_3~0); 402020#L824-3 assume !(1 == ~E_4~0); 402017#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 402014#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 402010#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401979#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401968#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401963#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 401959#L1084 assume !(0 == start_simulation_~tmp~3#1); 401955#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401949#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401944#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401941#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 401938#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 401934#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 401928#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 401924#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 388557#L1065-2 [2021-12-19 19:16:01,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,917 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2021-12-19 19:16:01,917 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159843508] [2021-12-19 19:16:01,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,918 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,937 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,937 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159843508] [2021-12-19 19:16:01,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159843508] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:01,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026054762] [2021-12-19 19:16:01,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,938 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:01,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1465868348, now seen corresponding path program 1 times [2021-12-19 19:16:01,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128221593] [2021-12-19 19:16:01,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128221593] [2021-12-19 19:16:01,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128221593] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:01,968 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556378318] [2021-12-19 19:16:01,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,968 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:01,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:01,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:01,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:01,969 INFO L87 Difference]: Start difference. First operand 26529 states and 37374 transitions. cyclomatic complexity: 10847 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:02,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:02,206 INFO L93 Difference]: Finished difference Result 38018 states and 53485 transitions. [2021-12-19 19:16:02,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:02,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38018 states and 53485 transitions. [2021-12-19 19:16:02,349 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36620 [2021-12-19 19:16:02,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38018 states to 38018 states and 53485 transitions. [2021-12-19 19:16:02,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38018 [2021-12-19 19:16:02,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38018 [2021-12-19 19:16:02,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38018 states and 53485 transitions. [2021-12-19 19:16:02,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:02,456 INFO L681 BuchiCegarLoop]: Abstraction has 38018 states and 53485 transitions. [2021-12-19 19:16:02,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38018 states and 53485 transitions. [2021-12-19 19:16:02,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38018 to 26466. [2021-12-19 19:16:02,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26466 states, 26466 states have (on average 1.407655104662586) internal successors, (37255), 26465 states have internal predecessors, (37255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:02,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26466 states to 26466 states and 37255 transitions. [2021-12-19 19:16:02,692 INFO L704 BuchiCegarLoop]: Abstraction has 26466 states and 37255 transitions. [2021-12-19 19:16:02,692 INFO L587 BuchiCegarLoop]: Abstraction has 26466 states and 37255 transitions. [2021-12-19 19:16:02,692 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:16:02,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26466 states and 37255 transitions. [2021-12-19 19:16:02,745 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26344 [2021-12-19 19:16:02,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:02,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:02,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:02,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:02,750 INFO L791 eck$LassoCheckResult]: Stem: 453668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 453598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 453550#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453477#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 453478#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 453105#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 453106#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 452954#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452955#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 452923#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 452924#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 453082#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 453250#L696 assume !(0 == ~M_E~0); 453251#L696-2 assume !(0 == ~T1_E~0); 453574#L701-1 assume !(0 == ~T2_E~0); 453576#L706-1 assume !(0 == ~T3_E~0); 453369#L711-1 assume !(0 == ~T4_E~0); 453139#L716-1 assume !(0 == ~T5_E~0); 453140#L721-1 assume !(0 == ~T6_E~0); 453321#L726-1 assume !(0 == ~E_M~0); 453322#L731-1 assume !(0 == ~E_1~0); 453290#L736-1 assume !(0 == ~E_2~0); 453291#L741-1 assume !(0 == ~E_3~0); 453378#L746-1 assume !(0 == ~E_4~0); 453173#L751-1 assume !(0 == ~E_5~0); 453174#L756-1 assume !(0 == ~E_6~0); 453136#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 452970#L346 assume !(1 == ~m_pc~0); 452971#L346-2 is_master_triggered_~__retres1~0#1 := 0; 453185#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 452885#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 452886#L861 assume !(0 != activate_threads_~tmp~1#1); 453532#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 453002#L365 assume !(1 == ~t1_pc~0); 453003#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 453549#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453551#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 452993#L869 assume !(0 != activate_threads_~tmp___0~0#1); 452994#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453432#L384 assume !(1 == ~t2_pc~0); 453423#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 453424#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453078#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452906#L877 assume !(0 != activate_threads_~tmp___1~0#1); 452907#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 453268#L403 assume !(1 == ~t3_pc~0); 453269#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 453471#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 453126#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 453127#L885 assume !(0 != activate_threads_~tmp___2~0#1); 453259#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 453260#L422 assume !(1 == ~t4_pc~0); 453389#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 453390#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453428#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453429#L893 assume !(0 != activate_threads_~tmp___3~0#1); 453352#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 452925#L441 assume !(1 == ~t5_pc~0); 452926#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 453528#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453601#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 453602#L901 assume !(0 != activate_threads_~tmp___4~0#1); 453361#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 453362#L460 assume !(1 == ~t6_pc~0); 453496#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 452932#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 452933#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 453491#L909 assume !(0 != activate_threads_~tmp___5~0#1); 453492#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 453333#L774 assume !(1 == ~M_E~0); 453334#L774-2 assume !(1 == ~T1_E~0); 453509#L779-1 assume !(1 == ~T2_E~0); 453231#L784-1 assume !(1 == ~T3_E~0); 453232#L789-1 assume !(1 == ~T4_E~0); 452986#L794-1 assume !(1 == ~T5_E~0); 452987#L799-1 assume !(1 == ~T6_E~0); 453626#L804-1 assume !(1 == ~E_M~0); 453627#L809-1 assume !(1 == ~E_1~0); 453317#L814-1 assume !(1 == ~E_2~0); 452887#L819-1 assume !(1 == ~E_3~0); 452888#L824-1 assume !(1 == ~E_4~0); 453386#L829-1 assume !(1 == ~E_5~0); 453499#L834-1 assume !(1 == ~E_6~0); 453118#L839-1 assume { :end_inline_reset_delta_events } true; 453119#L1065-2 [2021-12-19 19:16:02,750 INFO L793 eck$LassoCheckResult]: Loop: 453119#L1065-2 assume !false; 472691#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 472688#L671 assume !false; 472687#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 470940#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 470933#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 470931#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 470928#L582 assume !(0 != eval_~tmp~0#1); 470929#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 478330#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 478324#L696-3 assume !(0 == ~M_E~0); 478322#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 478320#L701-3 assume !(0 == ~T2_E~0); 478318#L706-3 assume !(0 == ~T3_E~0); 478315#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 478313#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 478311#L721-3 assume !(0 == ~T6_E~0); 478309#L726-3 assume !(0 == ~E_M~0); 478307#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 478305#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 478302#L741-3 assume !(0 == ~E_3~0); 478300#L746-3 assume !(0 == ~E_4~0); 478298#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 478296#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 478294#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 478292#L346-24 assume !(1 == ~m_pc~0); 478173#L346-26 is_master_triggered_~__retres1~0#1 := 0; 478170#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 478167#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 478165#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 478163#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 478161#L365-24 assume !(1 == ~t1_pc~0); 478159#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 478157#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 478154#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478153#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 478147#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 478141#L384-24 assume 1 == ~t2_pc~0; 478135#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 478131#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478127#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 478126#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 478125#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475598#L403-24 assume !(1 == ~t3_pc~0); 475479#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 475472#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475463#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475455#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 475448#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470257#L422-24 assume !(1 == ~t4_pc~0); 470255#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 470253#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470251#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470249#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 470248#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 470246#L441-24 assume 1 == ~t5_pc~0; 470244#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 470245#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 470479#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470234#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 470232#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470217#L460-24 assume !(1 == ~t6_pc~0); 464993#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 470206#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 470201#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 470194#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470187#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 470180#L774-3 assume !(1 == ~M_E~0); 463285#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 470170#L779-3 assume !(1 == ~T2_E~0); 470165#L784-3 assume !(1 == ~T3_E~0); 470157#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 470149#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 470140#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 470131#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 470123#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 470114#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 470105#L819-3 assume !(1 == ~E_3~0); 470098#L824-3 assume !(1 == ~E_4~0); 470091#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 470086#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 470081#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 453858#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 453835#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 453828#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 453792#L1084 assume !(0 == start_simulation_~tmp~3#1); 453793#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 472712#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 472708#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 472706#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 472704#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 472700#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 472698#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 472696#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 453119#L1065-2 [2021-12-19 19:16:02,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:02,751 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2021-12-19 19:16:02,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:02,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792729087] [2021-12-19 19:16:02,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:02,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:02,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:02,758 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:02,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:02,778 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:02,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:02,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1931737412, now seen corresponding path program 1 times [2021-12-19 19:16:02,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:02,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51606183] [2021-12-19 19:16:02,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:02,779 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:02,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:02,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:02,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:02,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51606183] [2021-12-19 19:16:02,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51606183] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:02,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:02,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:02,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496923644] [2021-12-19 19:16:02,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:02,801 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:02,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:02,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:02,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:02,802 INFO L87 Difference]: Start difference. First operand 26466 states and 37255 transitions. cyclomatic complexity: 10791 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:02,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:02,957 INFO L93 Difference]: Finished difference Result 47610 states and 66419 transitions. [2021-12-19 19:16:02,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:16:02,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47610 states and 66419 transitions. [2021-12-19 19:16:03,133 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47456 [2021-12-19 19:16:03,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47610 states to 47610 states and 66419 transitions. [2021-12-19 19:16:03,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47610 [2021-12-19 19:16:03,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47610 [2021-12-19 19:16:03,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47610 states and 66419 transitions. [2021-12-19 19:16:03,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:03,308 INFO L681 BuchiCegarLoop]: Abstraction has 47610 states and 66419 transitions. [2021-12-19 19:16:03,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47610 states and 66419 transitions. [2021-12-19 19:16:03,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47610 to 26658. [2021-12-19 19:16:03,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26658 states, 26658 states have (on average 1.4047190336859479) internal successors, (37447), 26657 states have internal predecessors, (37447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:03,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26658 states to 26658 states and 37447 transitions. [2021-12-19 19:16:03,639 INFO L704 BuchiCegarLoop]: Abstraction has 26658 states and 37447 transitions. [2021-12-19 19:16:03,639 INFO L587 BuchiCegarLoop]: Abstraction has 26658 states and 37447 transitions. [2021-12-19 19:16:03,639 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:16:03,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26658 states and 37447 transitions. [2021-12-19 19:16:03,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26536 [2021-12-19 19:16:03,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:03,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:03,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,717 INFO L791 eck$LassoCheckResult]: Stem: 527759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 527693#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 527649#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 527575#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 527576#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 527195#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 527196#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 527046#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 527047#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 527015#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 527016#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 527174#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527341#L696 assume !(0 == ~M_E~0); 527342#L696-2 assume !(0 == ~T1_E~0); 527672#L701-1 assume !(0 == ~T2_E~0); 527673#L706-1 assume !(0 == ~T3_E~0); 527460#L711-1 assume !(0 == ~T4_E~0); 527229#L716-1 assume !(0 == ~T5_E~0); 527230#L721-1 assume !(0 == ~T6_E~0); 527409#L726-1 assume !(0 == ~E_M~0); 527410#L731-1 assume !(0 == ~E_1~0); 527378#L736-1 assume !(0 == ~E_2~0); 527379#L741-1 assume !(0 == ~E_3~0); 527469#L746-1 assume !(0 == ~E_4~0); 527263#L751-1 assume !(0 == ~E_5~0); 527264#L756-1 assume !(0 == ~E_6~0); 527226#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 527061#L346 assume !(1 == ~m_pc~0); 527062#L346-2 is_master_triggered_~__retres1~0#1 := 0; 527274#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 526978#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 526979#L861 assume !(0 != activate_threads_~tmp~1#1); 527631#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527094#L365 assume !(1 == ~t1_pc~0); 527095#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 527648#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527651#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 527084#L869 assume !(0 != activate_threads_~tmp___0~0#1); 527085#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 527529#L384 assume !(1 == ~t2_pc~0); 527521#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 527522#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 527173#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 527000#L877 assume !(0 != activate_threads_~tmp___1~0#1); 527001#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 527356#L403 assume !(1 == ~t3_pc~0); 527357#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 527569#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527216#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 527217#L885 assume !(0 != activate_threads_~tmp___2~0#1); 527350#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527351#L422 assume !(1 == ~t4_pc~0); 527481#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 527482#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527527#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527528#L893 assume !(0 != activate_threads_~tmp___3~0#1); 527440#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527017#L441 assume !(1 == ~t5_pc~0); 527018#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 527627#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527695#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527696#L901 assume !(0 != activate_threads_~tmp___4~0#1); 527450#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 527451#L460 assume !(1 == ~t6_pc~0); 527593#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 527026#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527027#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 527588#L909 assume !(0 != activate_threads_~tmp___5~0#1); 527589#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527421#L774 assume !(1 == ~M_E~0); 527422#L774-2 assume !(1 == ~T1_E~0); 527605#L779-1 assume !(1 == ~T2_E~0); 527319#L784-1 assume !(1 == ~T3_E~0); 527320#L789-1 assume !(1 == ~T4_E~0); 527078#L794-1 assume !(1 == ~T5_E~0); 527079#L799-1 assume !(1 == ~T6_E~0); 527722#L804-1 assume !(1 == ~E_M~0); 527723#L809-1 assume !(1 == ~E_1~0); 527406#L814-1 assume !(1 == ~E_2~0); 526980#L819-1 assume !(1 == ~E_3~0); 526981#L824-1 assume !(1 == ~E_4~0); 527476#L829-1 assume !(1 == ~E_5~0); 527596#L834-1 assume !(1 == ~E_6~0); 527211#L839-1 assume { :end_inline_reset_delta_events } true; 527212#L1065-2 [2021-12-19 19:16:03,718 INFO L793 eck$LassoCheckResult]: Loop: 527212#L1065-2 assume !false; 551957#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 545064#L671 assume !false; 551627#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 551624#L530 assume !(0 == ~m_st~0); 551625#L534 assume !(0 == ~t1_st~0); 551620#L538 assume !(0 == ~t2_st~0); 551621#L542 assume !(0 == ~t3_st~0); 551623#L546 assume !(0 == ~t4_st~0); 551618#L550 assume !(0 == ~t5_st~0); 551619#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 551622#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 532775#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 532776#L582 assume !(0 != eval_~tmp~0#1); 551599#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551597#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 551595#L696-3 assume !(0 == ~M_E~0); 551593#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 551591#L701-3 assume !(0 == ~T2_E~0); 551589#L706-3 assume !(0 == ~T3_E~0); 551587#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 551585#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 551583#L721-3 assume !(0 == ~T6_E~0); 551581#L726-3 assume !(0 == ~E_M~0); 551579#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551577#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 551575#L741-3 assume !(0 == ~E_3~0); 551573#L746-3 assume !(0 == ~E_4~0); 551571#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 551569#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 551567#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 551565#L346-24 assume 1 == ~m_pc~0; 551562#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 551559#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 551557#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 551555#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 551553#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 551551#L365-24 assume !(1 == ~t1_pc~0); 551549#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 551547#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 551545#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 551543#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 551541#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 551539#L384-24 assume 1 == ~t2_pc~0; 551536#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 551533#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 551531#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 551529#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 551527#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 551525#L403-24 assume !(1 == ~t3_pc~0); 549740#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 551521#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 551519#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 551517#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 551515#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 551513#L422-24 assume !(1 == ~t4_pc~0); 527875#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 551511#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 551509#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 551507#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 551505#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 551503#L441-24 assume 1 == ~t5_pc~0; 551500#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 551496#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 551492#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 551488#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 551485#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 551483#L460-24 assume !(1 == ~t6_pc~0); 538462#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 551481#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 551479#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 551477#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 551475#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 551473#L774-3 assume !(1 == ~M_E~0); 551472#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 551457#L779-3 assume !(1 == ~T2_E~0); 551458#L784-3 assume !(1 == ~T3_E~0); 551419#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 551420#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 551413#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 551414#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 550364#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 550365#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 550289#L819-3 assume !(1 == ~E_3~0); 550290#L824-3 assume !(1 == ~E_4~0); 550284#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 550285#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 550278#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 550279#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 549889#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 549890#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 548943#L1084 assume !(0 == start_simulation_~tmp~3#1); 548945#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 552150#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 552146#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 552135#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 552132#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 552125#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 552008#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 551997#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 527212#L1065-2 [2021-12-19 19:16:03,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,718 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2021-12-19 19:16:03,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842594691] [2021-12-19 19:16:03,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:03,726 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:03,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:03,748 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:03,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1042489974, now seen corresponding path program 1 times [2021-12-19 19:16:03,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627726164] [2021-12-19 19:16:03,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:03,774 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:03,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627726164] [2021-12-19 19:16:03,775 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627726164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:03,775 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:03,775 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:03,775 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134412232] [2021-12-19 19:16:03,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:03,776 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:03,776 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:03,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:03,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:03,776 INFO L87 Difference]: Start difference. First operand 26658 states and 37447 transitions. cyclomatic complexity: 10791 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:04,015 INFO L93 Difference]: Finished difference Result 52169 states and 72627 transitions. [2021-12-19 19:16:04,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-19 19:16:04,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52169 states and 72627 transitions. [2021-12-19 19:16:04,216 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51968 [2021-12-19 19:16:04,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52169 states to 52169 states and 72627 transitions. [2021-12-19 19:16:04,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52169 [2021-12-19 19:16:04,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52169 [2021-12-19 19:16:04,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52169 states and 72627 transitions. [2021-12-19 19:16:04,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,401 INFO L681 BuchiCegarLoop]: Abstraction has 52169 states and 72627 transitions. [2021-12-19 19:16:04,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52169 states and 72627 transitions. [2021-12-19 19:16:04,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52169 to 27765. [2021-12-19 19:16:04,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27765 states, 27765 states have (on average 1.3885827480641095) internal successors, (38554), 27764 states have internal predecessors, (38554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27765 states to 27765 states and 38554 transitions. [2021-12-19 19:16:04,724 INFO L704 BuchiCegarLoop]: Abstraction has 27765 states and 38554 transitions. [2021-12-19 19:16:04,724 INFO L587 BuchiCegarLoop]: Abstraction has 27765 states and 38554 transitions. [2021-12-19 19:16:04,724 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:16:04,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27765 states and 38554 transitions. [2021-12-19 19:16:04,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27640 [2021-12-19 19:16:04,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,794 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,794 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,795 INFO L791 eck$LassoCheckResult]: Stem: 606643#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 606567#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 606514#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 606440#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 606441#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 606041#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606042#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 605887#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 605888#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 605856#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 605857#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 606019#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606192#L696 assume !(0 == ~M_E~0); 606193#L696-2 assume !(0 == ~T1_E~0); 606542#L701-1 assume !(0 == ~T2_E~0); 606545#L706-1 assume !(0 == ~T3_E~0); 606319#L711-1 assume !(0 == ~T4_E~0); 606075#L716-1 assume !(0 == ~T5_E~0); 606076#L721-1 assume !(0 == ~T6_E~0); 606263#L726-1 assume !(0 == ~E_M~0); 606264#L731-1 assume !(0 == ~E_1~0); 606234#L736-1 assume !(0 == ~E_2~0); 606235#L741-1 assume !(0 == ~E_3~0); 606327#L746-1 assume !(0 == ~E_4~0); 606109#L751-1 assume !(0 == ~E_5~0); 606110#L756-1 assume !(0 == ~E_6~0); 606072#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 605902#L346 assume !(1 == ~m_pc~0); 605903#L346-2 is_master_triggered_~__retres1~0#1 := 0; 606121#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 605818#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 605819#L861 assume !(0 != activate_threads_~tmp~1#1); 606497#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 605933#L365 assume !(1 == ~t1_pc~0); 605934#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606513#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606515#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 605924#L869 assume !(0 != activate_threads_~tmp___0~0#1); 605925#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 606386#L384 assume !(1 == ~t2_pc~0); 606377#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606378#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 606014#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 606015#L877 assume !(0 != activate_threads_~tmp___1~0#1); 605840#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 606210#L403 assume !(1 == ~t3_pc~0); 606211#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 606433#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 606062#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 606063#L885 assume !(0 != activate_threads_~tmp___2~0#1); 606201#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 606202#L422 assume !(1 == ~t4_pc~0); 606339#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 606340#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 606382#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 606383#L893 assume !(0 != activate_threads_~tmp___3~0#1); 606300#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 605858#L441 assume !(1 == ~t5_pc~0); 605859#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 606492#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 606569#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 606570#L901 assume !(0 != activate_threads_~tmp___4~0#1); 606310#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606311#L460 assume !(1 == ~t6_pc~0); 606459#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 605865#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 605866#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606454#L909 assume !(0 != activate_threads_~tmp___5~0#1); 606455#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 606279#L774 assume !(1 == ~M_E~0); 606280#L774-2 assume !(1 == ~T1_E~0); 606470#L779-1 assume !(1 == ~T2_E~0); 606168#L784-1 assume !(1 == ~T3_E~0); 606169#L789-1 assume !(1 == ~T4_E~0); 605918#L794-1 assume !(1 == ~T5_E~0); 605919#L799-1 assume !(1 == ~T6_E~0); 606597#L804-1 assume !(1 == ~E_M~0); 606598#L809-1 assume !(1 == ~E_1~0); 606260#L814-1 assume !(1 == ~E_2~0); 605820#L819-1 assume !(1 == ~E_3~0); 605821#L824-1 assume !(1 == ~E_4~0); 606335#L829-1 assume !(1 == ~E_5~0); 606462#L834-1 assume !(1 == ~E_6~0); 606054#L839-1 assume { :end_inline_reset_delta_events } true; 606055#L1065-2 [2021-12-19 19:16:04,795 INFO L793 eck$LassoCheckResult]: Loop: 606055#L1065-2 assume !false; 630628#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 628841#L671 assume !false; 630625#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 630623#L530 assume !(0 == ~m_st~0); 630621#L534 assume !(0 == ~t1_st~0); 630619#L538 assume !(0 == ~t2_st~0); 630616#L542 assume !(0 == ~t3_st~0); 630614#L546 assume !(0 == ~t4_st~0); 630612#L550 assume !(0 == ~t5_st~0); 630609#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 630607#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 630605#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 630603#L582 assume !(0 != eval_~tmp~0#1); 630601#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 630599#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 630597#L696-3 assume !(0 == ~M_E~0); 630595#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 630593#L701-3 assume !(0 == ~T2_E~0); 630591#L706-3 assume !(0 == ~T3_E~0); 630589#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 630587#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 630585#L721-3 assume !(0 == ~T6_E~0); 630583#L726-3 assume !(0 == ~E_M~0); 630581#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 630579#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 630577#L741-3 assume !(0 == ~E_3~0); 630575#L746-3 assume !(0 == ~E_4~0); 630573#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 630570#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 630568#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630566#L346-24 assume 1 == ~m_pc~0; 630561#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 630559#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630556#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 630554#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630553#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630549#L365-24 assume !(1 == ~t1_pc~0); 630543#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 630541#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630531#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 630526#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 630520#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630519#L384-24 assume !(1 == ~t2_pc~0); 630517#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 630515#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630513#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630511#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 630474#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630468#L403-24 assume !(1 == ~t3_pc~0); 630454#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 630447#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630441#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630426#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 630147#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 626231#L422-24 assume !(1 == ~t4_pc~0); 626227#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 626224#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 626221#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 626218#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 626214#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 626211#L441-24 assume 1 == ~t5_pc~0; 626205#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 626195#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 626191#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 626187#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 626175#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 622885#L460-24 assume !(1 == ~t6_pc~0); 622883#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 622881#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 622879#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 622877#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 622875#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 622873#L774-3 assume !(1 == ~M_E~0); 621630#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 622871#L779-3 assume !(1 == ~T2_E~0); 622869#L784-3 assume !(1 == ~T3_E~0); 622867#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 622865#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 622863#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 622861#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 622859#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 622857#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 622854#L819-3 assume !(1 == ~E_3~0); 622853#L824-3 assume !(1 == ~E_4~0); 622852#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 622851#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 622848#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 622808#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 622797#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 622791#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 605853#L1084 assume !(0 == start_simulation_~tmp~3#1); 605855#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 630686#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 630683#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 630635#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 630634#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 630633#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630632#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 630631#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 606055#L1065-2 [2021-12-19 19:16:04,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,796 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2021-12-19 19:16:04,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914698862] [2021-12-19 19:16:04,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:04,801 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:04,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:04,815 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:04,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,815 INFO L85 PathProgramCache]: Analyzing trace with hash -802222645, now seen corresponding path program 1 times [2021-12-19 19:16:04,815 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858229459] [2021-12-19 19:16:04,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,816 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858229459] [2021-12-19 19:16:04,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858229459] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:04,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426340861] [2021-12-19 19:16:04,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,855 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:04,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:04,856 INFO L87 Difference]: Start difference. First operand 27765 states and 38554 transitions. cyclomatic complexity: 10791 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,097 INFO L93 Difference]: Finished difference Result 54301 states and 74829 transitions. [2021-12-19 19:16:05,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:05,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54301 states and 74829 transitions. [2021-12-19 19:16:05,314 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 54176 [2021-12-19 19:16:05,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54301 states to 54301 states and 74829 transitions. [2021-12-19 19:16:05,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54301 [2021-12-19 19:16:05,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54301 [2021-12-19 19:16:05,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54301 states and 74829 transitions. [2021-12-19 19:16:05,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,526 INFO L681 BuchiCegarLoop]: Abstraction has 54301 states and 74829 transitions. [2021-12-19 19:16:05,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54301 states and 74829 transitions. [2021-12-19 19:16:05,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54301 to 28365. [2021-12-19 19:16:05,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28365 states, 28365 states have (on average 1.374405076679006) internal successors, (38985), 28364 states have internal predecessors, (38985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28365 states to 28365 states and 38985 transitions. [2021-12-19 19:16:05,872 INFO L704 BuchiCegarLoop]: Abstraction has 28365 states and 38985 transitions. [2021-12-19 19:16:05,872 INFO L587 BuchiCegarLoop]: Abstraction has 28365 states and 38985 transitions. [2021-12-19 19:16:05,872 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:16:05,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28365 states and 38985 transitions. [2021-12-19 19:16:05,951 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28240 [2021-12-19 19:16:05,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,954 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,955 INFO L791 eck$LassoCheckResult]: Stem: 688726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 688650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 688600#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 688517#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 688518#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 688118#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 688119#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 687967#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 687968#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 687935#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 687936#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 688097#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 688269#L696 assume !(0 == ~M_E~0); 688270#L696-2 assume !(0 == ~T1_E~0); 688628#L701-1 assume !(0 == ~T2_E~0); 688629#L706-1 assume !(0 == ~T3_E~0); 688394#L711-1 assume !(0 == ~T4_E~0); 688153#L716-1 assume !(0 == ~T5_E~0); 688154#L721-1 assume !(0 == ~T6_E~0); 688340#L726-1 assume !(0 == ~E_M~0); 688341#L731-1 assume !(0 == ~E_1~0); 688306#L736-1 assume !(0 == ~E_2~0); 688307#L741-1 assume !(0 == ~E_3~0); 688400#L746-1 assume !(0 == ~E_4~0); 688187#L751-1 assume !(0 == ~E_5~0); 688188#L756-1 assume !(0 == ~E_6~0); 688150#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 687982#L346 assume !(1 == ~m_pc~0); 687983#L346-2 is_master_triggered_~__retres1~0#1 := 0; 688201#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 687899#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 687900#L861 assume !(0 != activate_threads_~tmp~1#1); 688580#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 688015#L365 assume !(1 == ~t1_pc~0); 688016#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 688599#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 688604#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 688005#L869 assume !(0 != activate_threads_~tmp___0~0#1); 688006#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 688468#L384 assume !(1 == ~t2_pc~0); 688461#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 688462#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 688740#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 688739#L877 assume !(0 != activate_threads_~tmp___1~0#1); 687921#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 688285#L403 assume !(1 == ~t3_pc~0); 688286#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 688511#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688144#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 688145#L885 assume !(0 != activate_threads_~tmp___2~0#1); 688278#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688279#L422 assume !(1 == ~t4_pc~0); 688415#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 688416#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 688466#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 688467#L893 assume !(0 != activate_threads_~tmp___3~0#1); 688374#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 687937#L441 assume !(1 == ~t5_pc~0); 687938#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 688575#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 688653#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 688654#L901 assume !(0 != activate_threads_~tmp___4~0#1); 688385#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 688386#L460 assume !(1 == ~t6_pc~0); 688535#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 687946#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 687947#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 688530#L909 assume !(0 != activate_threads_~tmp___5~0#1); 688531#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 688352#L774 assume !(1 == ~M_E~0); 688353#L774-2 assume !(1 == ~T1_E~0); 688547#L779-1 assume !(1 == ~T2_E~0); 688245#L784-1 assume !(1 == ~T3_E~0); 688246#L789-1 assume !(1 == ~T4_E~0); 687999#L794-1 assume !(1 == ~T5_E~0); 688000#L799-1 assume !(1 == ~T6_E~0); 688686#L804-1 assume !(1 == ~E_M~0); 688687#L809-1 assume !(1 == ~E_1~0); 688336#L814-1 assume !(1 == ~E_2~0); 687901#L819-1 assume !(1 == ~E_3~0); 687902#L824-1 assume !(1 == ~E_4~0); 688408#L829-1 assume !(1 == ~E_5~0); 688538#L834-1 assume !(1 == ~E_6~0); 688135#L839-1 assume { :end_inline_reset_delta_events } true; 688136#L1065-2 [2021-12-19 19:16:05,955 INFO L793 eck$LassoCheckResult]: Loop: 688136#L1065-2 assume !false; 700170#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 700166#L671 assume !false; 700163#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 700160#L530 assume !(0 == ~m_st~0); 700157#L534 assume !(0 == ~t1_st~0); 700154#L538 assume !(0 == ~t2_st~0); 700150#L542 assume !(0 == ~t3_st~0); 700148#L546 assume !(0 == ~t4_st~0); 700146#L550 assume !(0 == ~t5_st~0); 700144#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 700139#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 700137#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 700135#L582 assume !(0 != eval_~tmp~0#1); 700133#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 700131#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 700129#L696-3 assume !(0 == ~M_E~0); 700127#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 700125#L701-3 assume !(0 == ~T2_E~0); 700123#L706-3 assume !(0 == ~T3_E~0); 700122#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 700121#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 700119#L721-3 assume !(0 == ~T6_E~0); 700117#L726-3 assume !(0 == ~E_M~0); 700116#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 700115#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 700110#L741-3 assume !(0 == ~E_3~0); 700107#L746-3 assume !(0 == ~E_4~0); 700102#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 700084#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 700081#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 700079#L346-24 assume 1 == ~m_pc~0; 700074#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 700072#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 700070#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 700068#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 700066#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 700064#L365-24 assume !(1 == ~t1_pc~0); 700062#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 700060#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 700058#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 700056#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 700054#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 700052#L384-24 assume 1 == ~t2_pc~0; 700048#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 700046#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 700044#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 700042#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 700039#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 700037#L403-24 assume !(1 == ~t3_pc~0); 699430#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 700034#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 700032#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 700030#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 700028#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 700021#L422-24 assume !(1 == ~t4_pc~0); 697460#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 700010#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 700005#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 700004#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 700003#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 700002#L441-24 assume 1 == ~t5_pc~0; 699931#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 699922#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 699914#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 699907#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 699901#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 699895#L460-24 assume !(1 == ~t6_pc~0); 699761#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 699885#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 699879#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 699874#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 699868#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 699861#L774-3 assume !(1 == ~M_E~0); 697903#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 699848#L779-3 assume !(1 == ~T2_E~0); 699842#L784-3 assume !(1 == ~T3_E~0); 699833#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 699827#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 699820#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 699813#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 699804#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 699799#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699793#L819-3 assume !(1 == ~E_3~0); 699787#L824-3 assume !(1 == ~E_4~0); 699784#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 699780#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 699773#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 699718#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 699708#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 699704#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 688765#L1084 assume !(0 == start_simulation_~tmp~3#1); 688766#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 700210#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 700205#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 700202#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 700197#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 700192#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 700185#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 700180#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 688136#L1065-2 [2021-12-19 19:16:05,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,956 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2021-12-19 19:16:05,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531199238] [2021-12-19 19:16:05,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:05,963 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:05,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:05,977 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:05,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,977 INFO L85 PathProgramCache]: Analyzing trace with hash -925690870, now seen corresponding path program 1 times [2021-12-19 19:16:05,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739938225] [2021-12-19 19:16:05,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,009 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,009 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739938225] [2021-12-19 19:16:06,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739938225] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:06,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127715364] [2021-12-19 19:16:06,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,010 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:06,010 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:06,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:06,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:06,011 INFO L87 Difference]: Start difference. First operand 28365 states and 38985 transitions. cyclomatic complexity: 10622 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:06,231 INFO L93 Difference]: Finished difference Result 43533 states and 60160 transitions. [2021-12-19 19:16:06,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:06,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43533 states and 60160 transitions. [2021-12-19 19:16:06,398 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 43376 [2021-12-19 19:16:06,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43533 states to 43533 states and 60160 transitions. [2021-12-19 19:16:06,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43533 [2021-12-19 19:16:06,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43533 [2021-12-19 19:16:06,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43533 states and 60160 transitions. [2021-12-19 19:16:06,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:06,554 INFO L681 BuchiCegarLoop]: Abstraction has 43533 states and 60160 transitions. [2021-12-19 19:16:06,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43533 states and 60160 transitions. [2021-12-19 19:16:06,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43533 to 28413. [2021-12-19 19:16:06,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28413 states, 28413 states have (on average 1.3644458522507303) internal successors, (38768), 28412 states have internal predecessors, (38768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28413 states to 28413 states and 38768 transitions. [2021-12-19 19:16:06,881 INFO L704 BuchiCegarLoop]: Abstraction has 28413 states and 38768 transitions. [2021-12-19 19:16:06,881 INFO L587 BuchiCegarLoop]: Abstraction has 28413 states and 38768 transitions. [2021-12-19 19:16:06,881 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:16:06,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28413 states and 38768 transitions. [2021-12-19 19:16:06,952 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28288 [2021-12-19 19:16:06,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:06,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:06,954 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,954 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,955 INFO L791 eck$LassoCheckResult]: Stem: 760631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 760552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 760496#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 760412#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 760413#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 760028#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 760029#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 759880#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 759881#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 759848#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 759849#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 760007#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 760174#L696 assume !(0 == ~M_E~0); 760175#L696-2 assume !(0 == ~T1_E~0); 760529#L701-1 assume !(0 == ~T2_E~0); 760530#L706-1 assume !(0 == ~T3_E~0); 760296#L711-1 assume !(0 == ~T4_E~0); 760060#L716-1 assume !(0 == ~T5_E~0); 760061#L721-1 assume !(0 == ~T6_E~0); 760245#L726-1 assume !(0 == ~E_M~0); 760246#L731-1 assume !(0 == ~E_1~0); 760211#L736-1 assume !(0 == ~E_2~0); 760212#L741-1 assume !(0 == ~E_3~0); 760302#L746-1 assume !(0 == ~E_4~0); 760095#L751-1 assume !(0 == ~E_5~0); 760096#L756-1 assume !(0 == ~E_6~0); 760057#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759895#L346 assume !(1 == ~m_pc~0); 759896#L346-2 is_master_triggered_~__retres1~0#1 := 0; 760107#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 759812#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 759813#L861 assume !(0 != activate_threads_~tmp~1#1); 760475#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 759928#L365 assume !(1 == ~t1_pc~0); 759929#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 760495#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 760500#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 759918#L869 assume !(0 != activate_threads_~tmp___0~0#1); 759919#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 760367#L384 assume !(1 == ~t2_pc~0); 760359#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 760360#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 760643#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 760642#L877 assume !(0 != activate_threads_~tmp___1~0#1); 759834#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 760190#L403 assume !(1 == ~t3_pc~0); 760191#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 760405#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 760053#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 760054#L885 assume !(0 != activate_threads_~tmp___2~0#1); 760183#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 760184#L422 assume !(1 == ~t4_pc~0); 760316#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 760317#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 760365#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 760366#L893 assume !(0 != activate_threads_~tmp___3~0#1); 760276#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 759850#L441 assume !(1 == ~t5_pc~0); 759851#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 760470#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 760554#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 760555#L901 assume !(0 != activate_threads_~tmp___4~0#1); 760286#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 760287#L460 assume !(1 == ~t6_pc~0); 760429#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 759859#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 759860#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 760424#L909 assume !(0 != activate_threads_~tmp___5~0#1); 760425#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 760256#L774 assume !(1 == ~M_E~0); 760257#L774-2 assume !(1 == ~T1_E~0); 760443#L779-1 assume !(1 == ~T2_E~0); 760151#L784-1 assume !(1 == ~T3_E~0); 760152#L789-1 assume !(1 == ~T4_E~0); 759911#L794-1 assume !(1 == ~T5_E~0); 759912#L799-1 assume !(1 == ~T6_E~0); 760585#L804-1 assume !(1 == ~E_M~0); 760586#L809-1 assume !(1 == ~E_1~0); 760241#L814-1 assume !(1 == ~E_2~0); 759814#L819-1 assume !(1 == ~E_3~0); 759815#L824-1 assume !(1 == ~E_4~0); 760312#L829-1 assume !(1 == ~E_5~0); 760432#L834-1 assume !(1 == ~E_6~0); 760044#L839-1 assume { :end_inline_reset_delta_events } true; 760045#L1065-2 [2021-12-19 19:16:06,955 INFO L793 eck$LassoCheckResult]: Loop: 760045#L1065-2 assume !false; 768327#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 767043#L671 assume !false; 768005#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768003#L530 assume !(0 == ~m_st~0); 768004#L534 assume !(0 == ~t1_st~0); 767999#L538 assume !(0 == ~t2_st~0); 768000#L542 assume !(0 == ~t3_st~0); 768002#L546 assume !(0 == ~t4_st~0); 767997#L550 assume !(0 == ~t5_st~0); 767998#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 768001#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 786793#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 786791#L582 assume !(0 != eval_~tmp~0#1); 786789#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 786786#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 786784#L696-3 assume !(0 == ~M_E~0); 786782#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 786735#L701-3 assume !(0 == ~T2_E~0); 786516#L706-3 assume !(0 == ~T3_E~0); 786515#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 786514#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 786513#L721-3 assume !(0 == ~T6_E~0); 786512#L726-3 assume !(0 == ~E_M~0); 786511#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 786510#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 786508#L741-3 assume !(0 == ~E_3~0); 786506#L746-3 assume !(0 == ~E_4~0); 786505#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 786504#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 786503#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 786502#L346-24 assume 1 == ~m_pc~0; 786500#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 786499#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 786498#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 786497#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 786496#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 786495#L365-24 assume !(1 == ~t1_pc~0); 786494#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 786493#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 786492#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 786491#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 786490#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 786489#L384-24 assume !(1 == ~t2_pc~0); 786488#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 786509#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 786507#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 786483#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 786482#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 768590#L403-24 assume !(1 == ~t3_pc~0); 768588#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 768586#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 768550#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 768546#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 768545#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 768544#L422-24 assume !(1 == ~t4_pc~0); 766517#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 768542#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 768541#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 768540#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 768535#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 768534#L441-24 assume !(1 == ~t5_pc~0); 768528#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 768526#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 768524#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768522#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 768512#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 768505#L460-24 assume !(1 == ~t6_pc~0); 767707#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 768493#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 768487#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 768481#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 768476#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 768471#L774-3 assume !(1 == ~M_E~0); 768465#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 768460#L779-3 assume !(1 == ~T2_E~0); 768454#L784-3 assume !(1 == ~T3_E~0); 768449#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 768444#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 768441#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 768440#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 768439#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 768438#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 768437#L819-3 assume !(1 == ~E_3~0); 768436#L824-3 assume !(1 == ~E_4~0); 768435#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 768434#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 768433#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 760851#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 760846#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768403#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 768392#L1084 assume !(0 == start_simulation_~tmp~3#1); 768389#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768381#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 768377#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768375#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 768374#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 768343#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 768338#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 768335#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 760045#L1065-2 [2021-12-19 19:16:06,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,956 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2021-12-19 19:16:06,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089474085] [2021-12-19 19:16:06,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:06,961 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:06,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:06,975 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:06,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1899422162, now seen corresponding path program 1 times [2021-12-19 19:16:06,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329027680] [2021-12-19 19:16:06,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,976 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:07,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:07,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:07,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329027680] [2021-12-19 19:16:07,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329027680] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:07,007 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:07,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:07,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964198680] [2021-12-19 19:16:07,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:07,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:07,008 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:07,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:07,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:07,008 INFO L87 Difference]: Start difference. First operand 28413 states and 38768 transitions. cyclomatic complexity: 10357 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:07,171 INFO L93 Difference]: Finished difference Result 35597 states and 48255 transitions. [2021-12-19 19:16:07,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:07,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35597 states and 48255 transitions. [2021-12-19 19:16:07,292 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 35456 [2021-12-19 19:16:07,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35597 states to 35597 states and 48255 transitions. [2021-12-19 19:16:07,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35597 [2021-12-19 19:16:07,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35597 [2021-12-19 19:16:07,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35597 states and 48255 transitions. [2021-12-19 19:16:07,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:07,552 INFO L681 BuchiCegarLoop]: Abstraction has 35597 states and 48255 transitions. [2021-12-19 19:16:07,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35597 states and 48255 transitions. [2021-12-19 19:16:07,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35597 to 28461. [2021-12-19 19:16:07,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28461 states, 28461 states have (on average 1.3511471838656408) internal successors, (38455), 28460 states have internal predecessors, (38455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28461 states to 28461 states and 38455 transitions. [2021-12-19 19:16:07,769 INFO L704 BuchiCegarLoop]: Abstraction has 28461 states and 38455 transitions. [2021-12-19 19:16:07,769 INFO L587 BuchiCegarLoop]: Abstraction has 28461 states and 38455 transitions. [2021-12-19 19:16:07,769 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:16:07,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28461 states and 38455 transitions. [2021-12-19 19:16:07,831 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28336 [2021-12-19 19:16:07,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:07,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:07,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,834 INFO L791 eck$LassoCheckResult]: Stem: 824738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 824636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 824573#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 824474#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 824475#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 824053#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 824054#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 823903#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 823904#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 823872#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 823873#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 824032#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 824205#L696 assume !(0 == ~M_E~0); 824206#L696-2 assume !(0 == ~T1_E~0); 824609#L701-1 assume !(0 == ~T2_E~0); 824612#L706-1 assume !(0 == ~T3_E~0); 824346#L711-1 assume !(0 == ~T4_E~0); 824088#L716-1 assume !(0 == ~T5_E~0); 824089#L721-1 assume !(0 == ~T6_E~0); 824289#L726-1 assume !(0 == ~E_M~0); 824290#L731-1 assume !(0 == ~E_1~0); 824252#L736-1 assume !(0 == ~E_2~0); 824253#L741-1 assume !(0 == ~E_3~0); 824361#L746-1 assume !(0 == ~E_4~0); 824124#L751-1 assume !(0 == ~E_5~0); 824125#L756-1 assume !(0 == ~E_6~0); 824085#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 823920#L346 assume !(1 == ~m_pc~0); 823921#L346-2 is_master_triggered_~__retres1~0#1 := 0; 824136#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 823833#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 823834#L861 assume !(0 != activate_threads_~tmp~1#1); 824546#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 823952#L365 assume !(1 == ~t1_pc~0); 823953#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 824572#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 824574#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 823943#L869 assume !(0 != activate_threads_~tmp___0~0#1); 823944#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 824427#L384 assume !(1 == ~t2_pc~0); 824417#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 824418#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 824754#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 824753#L877 assume !(0 != activate_threads_~tmp___1~0#1); 823856#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 824226#L403 assume !(1 == ~t3_pc~0); 824227#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 824469#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 824075#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 824076#L885 assume !(0 != activate_threads_~tmp___2~0#1); 824215#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 824216#L422 assume !(1 == ~t4_pc~0); 824375#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 824376#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 824423#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 824424#L893 assume !(0 != activate_threads_~tmp___3~0#1); 824325#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 823874#L441 assume !(1 == ~t5_pc~0); 823875#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 824538#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 824639#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 824640#L901 assume !(0 != activate_threads_~tmp___4~0#1); 824337#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 824338#L460 assume !(1 == ~t6_pc~0); 824494#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 823881#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823882#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 824489#L909 assume !(0 != activate_threads_~tmp___5~0#1); 824490#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 824304#L774 assume !(1 == ~M_E~0); 824305#L774-2 assume !(1 == ~T1_E~0); 824511#L779-1 assume !(1 == ~T2_E~0); 824182#L784-1 assume !(1 == ~T3_E~0); 824183#L789-1 assume !(1 == ~T4_E~0); 823937#L794-1 assume !(1 == ~T5_E~0); 823938#L799-1 assume !(1 == ~T6_E~0); 824666#L804-1 assume !(1 == ~E_M~0); 824667#L809-1 assume !(1 == ~E_1~0); 824285#L814-1 assume !(1 == ~E_2~0); 823835#L819-1 assume !(1 == ~E_3~0); 823836#L824-1 assume !(1 == ~E_4~0); 824371#L829-1 assume !(1 == ~E_5~0); 824496#L834-1 assume !(1 == ~E_6~0); 824066#L839-1 assume { :end_inline_reset_delta_events } true; 824067#L1065-2 [2021-12-19 19:16:07,834 INFO L793 eck$LassoCheckResult]: Loop: 824067#L1065-2 assume !false; 828779#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 828776#L671 assume !false; 828775#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 828773#L530 assume !(0 == ~m_st~0); 828774#L534 assume !(0 == ~t1_st~0); 828769#L538 assume !(0 == ~t2_st~0); 828770#L542 assume !(0 == ~t3_st~0); 828772#L546 assume !(0 == ~t4_st~0); 828767#L550 assume !(0 == ~t5_st~0); 828768#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 828771#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 828762#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 828763#L582 assume !(0 != eval_~tmp~0#1); 846911#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 846910#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 846909#L696-3 assume !(0 == ~M_E~0); 846908#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 846907#L701-3 assume !(0 == ~T2_E~0); 846906#L706-3 assume !(0 == ~T3_E~0); 846905#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 846904#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 846903#L721-3 assume !(0 == ~T6_E~0); 846902#L726-3 assume !(0 == ~E_M~0); 846901#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 846900#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 846899#L741-3 assume !(0 == ~E_3~0); 846898#L746-3 assume !(0 == ~E_4~0); 846897#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 846896#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 846895#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 846893#L346-24 assume 1 == ~m_pc~0; 846890#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 846887#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 846885#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 824575#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 824576#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 846881#L365-24 assume !(1 == ~t1_pc~0); 846879#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 846876#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 846873#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 846870#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 846867#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823975#L384-24 assume !(1 == ~t2_pc~0); 823976#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 823997#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 848999#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 848997#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 824001#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 824002#L403-24 assume !(1 == ~t3_pc~0); 824127#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 824161#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 824162#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 824280#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 824281#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 824055#L422-24 assume !(1 == ~t4_pc~0); 824056#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 839406#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 839404#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 839402#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 839400#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839398#L441-24 assume !(1 == ~t5_pc~0); 839396#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 839393#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 839390#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 839386#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 839383#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 828920#L460-24 assume !(1 == ~t6_pc~0); 828918#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 828916#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 828915#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 828913#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 828911#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828909#L774-3 assume !(1 == ~M_E~0); 828905#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 828903#L779-3 assume !(1 == ~T2_E~0); 828901#L784-3 assume !(1 == ~T3_E~0); 828897#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 828895#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 828893#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 828891#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 828889#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 828887#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 828878#L819-3 assume !(1 == ~E_3~0); 828876#L824-3 assume !(1 == ~E_4~0); 828874#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 828872#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 828868#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 828842#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 828835#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 828832#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 828829#L1084 assume !(0 == start_simulation_~tmp~3#1); 828824#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 828817#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 828812#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 828807#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 828804#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 828801#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 828794#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 828789#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 824067#L1065-2 [2021-12-19 19:16:07,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,834 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2021-12-19 19:16:07,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562006331] [2021-12-19 19:16:07,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,835 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:07,840 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:07,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:07,852 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:07,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,852 INFO L85 PathProgramCache]: Analyzing trace with hash -1971898412, now seen corresponding path program 1 times [2021-12-19 19:16:07,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429817106] [2021-12-19 19:16:07,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:07,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:07,880 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:07,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429817106] [2021-12-19 19:16:07,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429817106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:07,881 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:07,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:07,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116079821] [2021-12-19 19:16:07,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:07,881 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:07,881 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:07,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:07,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:07,882 INFO L87 Difference]: Start difference. First operand 28461 states and 38455 transitions. cyclomatic complexity: 9996 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:08,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:08,083 INFO L93 Difference]: Finished difference Result 47347 states and 64282 transitions. [2021-12-19 19:16:08,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:08,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47347 states and 64282 transitions. [2021-12-19 19:16:08,256 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47190 [2021-12-19 19:16:08,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47347 states to 47347 states and 64282 transitions. [2021-12-19 19:16:08,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47347 [2021-12-19 19:16:08,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47347 [2021-12-19 19:16:08,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47347 states and 64282 transitions. [2021-12-19 19:16:08,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:08,402 INFO L681 BuchiCegarLoop]: Abstraction has 47347 states and 64282 transitions. [2021-12-19 19:16:08,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47347 states and 64282 transitions. [2021-12-19 19:16:08,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47347 to 29073. [2021-12-19 19:16:08,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29073 states, 29073 states have (on average 1.3378048361022254) internal successors, (38894), 29072 states have internal predecessors, (38894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:08,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29073 states to 29073 states and 38894 transitions. [2021-12-19 19:16:08,688 INFO L704 BuchiCegarLoop]: Abstraction has 29073 states and 38894 transitions. [2021-12-19 19:16:08,688 INFO L587 BuchiCegarLoop]: Abstraction has 29073 states and 38894 transitions. [2021-12-19 19:16:08,688 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:16:08,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29073 states and 38894 transitions. [2021-12-19 19:16:08,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28948 [2021-12-19 19:16:08,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:08,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:08,753 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:08,753 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:08,753 INFO L791 eck$LassoCheckResult]: Stem: 900468#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 900395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 900344#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 900264#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 900265#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 899878#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 899879#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 899726#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 899727#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 899695#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 899696#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 899856#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 900023#L696 assume !(0 == ~M_E~0); 900024#L696-2 assume !(0 == ~T1_E~0); 900371#L701-1 assume !(0 == ~T2_E~0); 900373#L706-1 assume !(0 == ~T3_E~0); 900150#L711-1 assume !(0 == ~T4_E~0); 899910#L716-1 assume !(0 == ~T5_E~0); 899911#L721-1 assume !(0 == ~T6_E~0); 900096#L726-1 assume !(0 == ~E_M~0); 900097#L731-1 assume !(0 == ~E_1~0); 900065#L736-1 assume !(0 == ~E_2~0); 900066#L741-1 assume !(0 == ~E_3~0); 900160#L746-1 assume !(0 == ~E_4~0); 899945#L751-1 assume !(0 == ~E_5~0); 899946#L756-1 assume !(0 == ~E_6~0); 899907#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 899742#L346 assume !(1 == ~m_pc~0); 899743#L346-2 is_master_triggered_~__retres1~0#1 := 0; 899957#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 899656#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 899657#L861 assume !(0 != activate_threads_~tmp~1#1); 900323#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 899775#L365 assume !(1 == ~t1_pc~0); 899776#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 900343#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 900345#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 899766#L869 assume !(0 != activate_threads_~tmp___0~0#1); 899767#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 900220#L384 assume !(1 == ~t2_pc~0); 900210#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 900211#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 900482#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 900481#L877 assume !(0 != activate_threads_~tmp___1~0#1); 899679#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 900041#L403 assume !(1 == ~t3_pc~0); 900042#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 900258#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 899899#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 899900#L885 assume !(0 != activate_threads_~tmp___2~0#1); 900032#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 900033#L422 assume !(1 == ~t4_pc~0); 900172#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 900173#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 900216#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 900217#L893 assume !(0 != activate_threads_~tmp___3~0#1); 900132#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 899697#L441 assume !(1 == ~t5_pc~0); 899698#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 900317#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 900397#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 900398#L901 assume !(0 != activate_threads_~tmp___4~0#1); 900142#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 900143#L460 assume !(1 == ~t6_pc~0); 900281#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 899704#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 899705#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 900276#L909 assume !(0 != activate_threads_~tmp___5~0#1); 900277#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 900112#L774 assume !(1 == ~M_E~0); 900113#L774-2 assume !(1 == ~T1_E~0); 900296#L779-1 assume !(1 == ~T2_E~0); 900001#L784-1 assume !(1 == ~T3_E~0); 900002#L789-1 assume !(1 == ~T4_E~0); 899758#L794-1 assume !(1 == ~T5_E~0); 899759#L799-1 assume !(1 == ~T6_E~0); 900424#L804-1 assume !(1 == ~E_M~0); 900425#L809-1 assume !(1 == ~E_1~0); 900092#L814-1 assume !(1 == ~E_2~0); 899658#L819-1 assume !(1 == ~E_3~0); 899659#L824-1 assume !(1 == ~E_4~0); 900168#L829-1 assume !(1 == ~E_5~0); 900284#L834-1 assume !(1 == ~E_6~0); 899891#L839-1 assume { :end_inline_reset_delta_events } true; 899892#L1065-2 [2021-12-19 19:16:08,753 INFO L793 eck$LassoCheckResult]: Loop: 899892#L1065-2 assume !false; 906334#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 906330#L671 assume !false; 906328#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 906323#L530 assume !(0 == ~m_st~0); 906324#L534 assume !(0 == ~t1_st~0); 906319#L538 assume !(0 == ~t2_st~0); 906320#L542 assume !(0 == ~t3_st~0); 906322#L546 assume !(0 == ~t4_st~0); 906317#L550 assume !(0 == ~t5_st~0); 906318#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 906321#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 906249#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 906250#L582 assume !(0 != eval_~tmp~0#1); 913012#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922654#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 922653#L696-3 assume !(0 == ~M_E~0); 922652#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 922651#L701-3 assume !(0 == ~T2_E~0); 922650#L706-3 assume !(0 == ~T3_E~0); 922649#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922648#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 922647#L721-3 assume !(0 == ~T6_E~0); 922646#L726-3 assume !(0 == ~E_M~0); 922645#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 922644#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 922643#L741-3 assume !(0 == ~E_3~0); 922642#L746-3 assume !(0 == ~E_4~0); 922641#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 922640#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 922639#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922638#L346-24 assume 1 == ~m_pc~0; 922636#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 922635#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 922634#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 922633#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 922632#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922631#L365-24 assume !(1 == ~t1_pc~0); 922630#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 922629#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 922628#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 922627#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 922626#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922625#L384-24 assume 1 == ~t2_pc~0; 922624#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 922622#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 922620#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 922618#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 922616#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 922615#L403-24 assume !(1 == ~t3_pc~0); 913493#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 922614#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 922613#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 922612#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 922611#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 922610#L422-24 assume !(1 == ~t4_pc~0); 912491#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 922609#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 922608#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 922607#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 922606#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 922605#L441-24 assume !(1 == ~t5_pc~0); 922604#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 922602#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 922600#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 922598#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 922596#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 902577#L460-24 assume !(1 == ~t6_pc~0); 902575#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 902573#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 902571#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 902569#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 902567#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 902565#L774-3 assume !(1 == ~M_E~0); 902408#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 902563#L779-3 assume !(1 == ~T2_E~0); 902561#L784-3 assume !(1 == ~T3_E~0); 902559#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 902557#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 902555#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 902553#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 902551#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 902549#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 902547#L819-3 assume !(1 == ~E_3~0); 902546#L824-3 assume !(1 == ~E_4~0); 902545#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 902544#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 902543#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 902541#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 902535#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 902534#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 902532#L1084 assume !(0 == start_simulation_~tmp~3#1); 902533#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 906356#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 906350#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 906348#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 906346#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 906341#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 906340#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 906339#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 899892#L1065-2 [2021-12-19 19:16:08,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:08,754 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2021-12-19 19:16:08,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:08,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232905655] [2021-12-19 19:16:08,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:08,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:08,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:08,763 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:08,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:08,776 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:08,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:08,777 INFO L85 PathProgramCache]: Analyzing trace with hash -1269863021, now seen corresponding path program 1 times [2021-12-19 19:16:08,777 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:08,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055171381] [2021-12-19 19:16:08,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:08,777 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:08,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:08,782 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:08,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:08,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:08,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:08,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1973474725, now seen corresponding path program 1 times [2021-12-19 19:16:08,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:08,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668340058] [2021-12-19 19:16:08,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:08,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:08,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:08,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:08,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:08,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668340058] [2021-12-19 19:16:08,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668340058] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:08,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:08,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:08,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563299094] [2021-12-19 19:16:08,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:10,133 INFO L210 LassoAnalysis]: Preferences: [2021-12-19 19:16:10,134 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-19 19:16:10,134 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-19 19:16:10,134 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-19 19:16:10,134 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-12-19 19:16:10,134 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,134 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-19 19:16:10,134 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-19 19:16:10,134 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-1.c_Iteration28_Loop [2021-12-19 19:16:10,135 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-19 19:16:10,135 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-19 19:16:10,148 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,154 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,155 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,156 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,157 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,160 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,161 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,163 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,165 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,166 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,169 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,171 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,172 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,173 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,175 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,176 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,178 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,179 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,180 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,185 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,186 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,188 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,189 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,192 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,199 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,202 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,205 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,208 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,210 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,213 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,215 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,216 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,217 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,219 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,222 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,223 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,225 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,231 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,237 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,243 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,245 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,246 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,251 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,253 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,256 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,261 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,264 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,268 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,270 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,271 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,275 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,279 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,281 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,290 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,291 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,293 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,294 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:10,733 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-19 19:16:10,737 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-12-19 19:16:10,738 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,738 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,740 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,746 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,746 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:10,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-19 19:16:10,767 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:10,768 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___3~0#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___3~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:10,785 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:10,785 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,785 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,786 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,790 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-19 19:16:10,791 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,791 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:10,812 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:10,812 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:10,827 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:10,827 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,828 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,839 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,848 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-19 19:16:10,849 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,849 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:10,858 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:10,858 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:10,886 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:10,887 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,887 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,888 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,889 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-19 19:16:10,890 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,891 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:10,911 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:10,912 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:10,930 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:10,930 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,930 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,939 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,941 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-19 19:16:10,943 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,943 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:10,956 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:10,957 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-1} Honda state: {~E_4~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:10,975 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:10,975 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:10,976 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:10,976 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:10,977 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-19 19:16:10,979 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:10,979 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,010 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,010 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,025 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,025 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,025 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,026 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,027 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-19 19:16:11,029 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,029 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,049 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,050 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,065 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,066 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,066 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,067 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,068 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-12-19 19:16:11,069 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,069 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,090 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,090 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,105 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,106 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,106 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,107 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,107 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-12-19 19:16:11,109 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,109 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,115 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,115 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_5~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_5~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,130 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2021-12-19 19:16:11,130 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,130 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,131 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,132 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-12-19 19:16:11,134 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,134 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,155 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,156 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0, ULTIMATE.start_stop_simulation_#res#1=0, ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0, ULTIMATE.start_stop_simulation_#res#1=0, ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,175 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,175 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,176 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,176 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,177 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-12-19 19:16:11,180 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,180 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,194 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,195 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,209 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,209 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,210 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,210 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,211 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-12-19 19:16:11,212 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,212 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,222 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,222 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,236 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2021-12-19 19:16:11,237 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,237 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,238 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,238 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-12-19 19:16:11,239 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,239 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,246 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,246 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,260 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2021-12-19 19:16:11,261 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,261 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,262 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,267 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-12-19 19:16:11,268 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,268 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,279 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,279 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,294 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,295 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,295 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,296 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,297 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-12-19 19:16:11,298 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,298 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,309 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,309 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=4} Honda state: {~t1_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,325 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2021-12-19 19:16:11,325 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,325 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,326 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,327 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2021-12-19 19:16:11,328 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,328 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,349 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,349 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=-1} Honda state: {~t5_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,364 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,364 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,364 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,365 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,366 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-12-19 19:16:11,369 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,369 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,389 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,390 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,407 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,407 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,407 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,411 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,412 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2021-12-19 19:16:11,412 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,413 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,428 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,428 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,447 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2021-12-19 19:16:11,447 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,448 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,448 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,452 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2021-12-19 19:16:11,460 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,460 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,471 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,471 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=1, ULTIMATE.start_activate_threads_~tmp___1~0#1=1} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=1, ULTIMATE.start_activate_threads_~tmp___1~0#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,488 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,488 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,488 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,489 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,490 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2021-12-19 19:16:11,491 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,491 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,512 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,512 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret18#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret18#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,528 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,529 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,529 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,530 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,530 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2021-12-19 19:16:11,532 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,532 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,553 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,553 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,568 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,568 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,568 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,569 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,570 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-12-19 19:16:11,571 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,571 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,592 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,592 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,609 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,609 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,609 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,610 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,610 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-12-19 19:16:11,612 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,612 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,618 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,618 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,635 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,635 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,635 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,636 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,637 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2021-12-19 19:16:11,638 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,638 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,661 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,661 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___5~0#1=0, ULTIMATE.start_is_transmit6_triggered_#res#1=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___5~0#1=0, ULTIMATE.start_is_transmit6_triggered_#res#1=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,678 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,678 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,678 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,688 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,688 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2021-12-19 19:16:11,690 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,690 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,710 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:11,710 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___4~0#1=0, ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___4~0#1=0, ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:11,726 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,727 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,727 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,743 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,744 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2021-12-19 19:16:11,746 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:11,746 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,791 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,791 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,791 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:11,792 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:11,807 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-12-19 19:16:11,807 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:11,808 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2021-12-19 19:16:11,829 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-12-19 19:16:11,845 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:11,845 INFO L210 LassoAnalysis]: Preferences: [2021-12-19 19:16:11,845 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-19 19:16:11,845 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-19 19:16:11,845 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-19 19:16:11,846 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-19 19:16:11,846 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:11,846 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-19 19:16:11,846 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-19 19:16:11,846 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-1.c_Iteration28_Loop [2021-12-19 19:16:11,846 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-19 19:16:11,846 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-19 19:16:11,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,855 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,858 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,859 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,864 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,865 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,867 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,868 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,870 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,874 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,875 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,877 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,879 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,881 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,882 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,884 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,889 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,896 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,897 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,902 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,905 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,912 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,916 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,918 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,922 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,927 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,929 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,930 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,933 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,936 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,941 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,943 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,944 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,946 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,952 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,956 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,959 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,961 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,967 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,972 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,980 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,982 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,983 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,985 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,986 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,989 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,991 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:11,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,013 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,018 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:12,449 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-19 19:16:12,452 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-19 19:16:12,453 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,453 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,471 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,478 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,478 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2021-12-19 19:16:12,484 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,484 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,484 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,484 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,484 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,486 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,486 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,489 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,504 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2021-12-19 19:16:12,504 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,504 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,505 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,505 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2021-12-19 19:16:12,507 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,512 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,512 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,512 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,512 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:12,512 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,513 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:12,513 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,514 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,528 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2021-12-19 19:16:12,529 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,529 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,530 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,530 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2021-12-19 19:16:12,532 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,537 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,537 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,537 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,537 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,537 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,538 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,538 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,557 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,573 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,574 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,574 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,575 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,577 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2021-12-19 19:16:12,578 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,583 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,583 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,583 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,583 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,584 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,584 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,584 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,585 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,601 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,601 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,601 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,602 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,602 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2021-12-19 19:16:12,604 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,608 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,608 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,609 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,609 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:12,609 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,609 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:12,609 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,610 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,626 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,627 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,627 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,628 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,628 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2021-12-19 19:16:12,629 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,634 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,634 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,634 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,634 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,634 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,635 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,635 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,651 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,667 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,667 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,667 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,669 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,669 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2021-12-19 19:16:12,671 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,676 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,676 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,676 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,676 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,677 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,677 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,691 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,705 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2021-12-19 19:16:12,706 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,706 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,706 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,707 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2021-12-19 19:16:12,708 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,713 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,714 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,714 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,714 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,714 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,714 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,714 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,715 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,729 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2021-12-19 19:16:12,730 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,730 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,731 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,734 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2021-12-19 19:16:12,735 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,740 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,740 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,741 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,741 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,741 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,741 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,741 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,742 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,757 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,757 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,757 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,758 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,758 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2021-12-19 19:16:12,760 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,765 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,765 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,765 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,765 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,765 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,765 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,765 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,787 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,814 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,815 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,815 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,815 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,816 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2021-12-19 19:16:12,818 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,823 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,823 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,823 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,823 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,823 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,825 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,825 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,826 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,841 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2021-12-19 19:16:12,841 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,841 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,842 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,845 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2021-12-19 19:16:12,845 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,852 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,852 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,852 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,852 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:12,852 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,852 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:12,853 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,854 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,868 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,868 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,869 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,869 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,870 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2021-12-19 19:16:12,872 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,877 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,877 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,877 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,877 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,877 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,878 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,878 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,879 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,894 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2021-12-19 19:16:12,894 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,894 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,895 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,895 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2021-12-19 19:16:12,897 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,902 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,902 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,902 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,902 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,902 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,903 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,903 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,904 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,918 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,919 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,919 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,920 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,920 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2021-12-19 19:16:12,922 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,927 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,927 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,927 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,927 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:12,927 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,928 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:12,928 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,929 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,945 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2021-12-19 19:16:12,946 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,946 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,947 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,948 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2021-12-19 19:16:12,949 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,955 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,955 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,955 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,955 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:12,955 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,956 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:12,956 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,960 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:12,974 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:12,975 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:12,975 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:12,976 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:12,976 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2021-12-19 19:16:12,978 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:12,985 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:12,985 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:12,985 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:12,985 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:12,985 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:12,986 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:12,986 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:12,987 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,005 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2021-12-19 19:16:13,006 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,006 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,007 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,007 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2021-12-19 19:16:13,009 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,015 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,015 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,015 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,015 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,015 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,016 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,016 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,017 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,032 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2021-12-19 19:16:13,032 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,032 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,033 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,034 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2021-12-19 19:16:13,036 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,041 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,042 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,042 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,042 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,042 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,043 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,043 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,048 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,063 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:13,063 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,063 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,064 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,066 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2021-12-19 19:16:13,067 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,072 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,072 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,072 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,072 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,072 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,073 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,073 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,077 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,092 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:13,092 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,092 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,093 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,094 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2021-12-19 19:16:13,095 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,100 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,100 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,101 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,101 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,101 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,101 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,101 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,102 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,117 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2021-12-19 19:16:13,117 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,117 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,118 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,120 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2021-12-19 19:16:13,122 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,127 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,127 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,127 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,127 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,127 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,127 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,127 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,128 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,143 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:13,143 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,143 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,144 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,145 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2021-12-19 19:16:13,146 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,151 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,151 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,152 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,152 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,152 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,152 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,152 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,153 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,168 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:13,168 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,168 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,170 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,170 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2021-12-19 19:16:13,172 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,176 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,177 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,177 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,177 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,177 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,177 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,177 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,178 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,192 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2021-12-19 19:16:13,193 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,193 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,193 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,196 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2021-12-19 19:16:13,197 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,202 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,203 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,203 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,203 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,203 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,203 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,203 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,204 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:13,219 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2021-12-19 19:16:13,219 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,219 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,220 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,220 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2021-12-19 19:16:13,222 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:13,226 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:13,227 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:13,227 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:13,227 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:13,227 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:13,227 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:13,227 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:13,229 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-19 19:16:13,233 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-12-19 19:16:13,233 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-12-19 19:16:13,234 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:13,234 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:13,256 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:13,257 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2021-12-19 19:16:13,258 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-19 19:16:13,258 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-12-19 19:16:13,258 INFO L513 LassoAnalysis]: Proved termination. [2021-12-19 19:16:13,258 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2021-12-19 19:16:13,287 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:13,289 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-12-19 19:16:13,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:13,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:13,353 INFO L263 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-19 19:16:13,354 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-19 19:16:13,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:13,521 INFO L263 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-19 19:16:13,522 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-19 19:16:13,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:13,806 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2021-12-19 19:16:13,806 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 29073 states and 38894 transitions. cyclomatic complexity: 9823 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:14,108 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 29073 states and 38894 transitions. cyclomatic complexity: 9823. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 58407 states and 78485 transitions. Complement of second has 4 states. [2021-12-19 19:16:14,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-12-19 19:16:14,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:14,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 979 transitions. [2021-12-19 19:16:14,114 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 979 transitions. Stem has 84 letters. Loop has 100 letters. [2021-12-19 19:16:14,118 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:14,118 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 979 transitions. Stem has 184 letters. Loop has 100 letters. [2021-12-19 19:16:14,118 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:14,118 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 979 transitions. Stem has 84 letters. Loop has 200 letters. [2021-12-19 19:16:14,119 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:14,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58407 states and 78485 transitions. [2021-12-19 19:16:14,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28948 [2021-12-19 19:16:14,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58407 states to 58407 states and 78485 transitions. [2021-12-19 19:16:14,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29074 [2021-12-19 19:16:14,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29251 [2021-12-19 19:16:14,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58407 states and 78485 transitions. [2021-12-19 19:16:14,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:14,516 INFO L681 BuchiCegarLoop]: Abstraction has 58407 states and 78485 transitions. [2021-12-19 19:16:14,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58407 states and 78485 transitions. [2021-12-19 19:16:14,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58407 to 58230. [2021-12-19 19:16:14,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58230 states, 58230 states have (on average 1.3428816761119697) internal successors, (78196), 58229 states have internal predecessors, (78196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:15,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58230 states to 58230 states and 78196 transitions. [2021-12-19 19:16:15,068 INFO L704 BuchiCegarLoop]: Abstraction has 58230 states and 78196 transitions. [2021-12-19 19:16:15,068 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:15,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:15,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:15,069 INFO L87 Difference]: Start difference. First operand 58230 states and 78196 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:15,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:15,488 INFO L93 Difference]: Finished difference Result 109134 states and 144108 transitions. [2021-12-19 19:16:15,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:15,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109134 states and 144108 transitions. [2021-12-19 19:16:15,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 54312 [2021-12-19 19:16:16,671 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:16,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109134 states to 109134 states and 144108 transitions. [2021-12-19 19:16:16,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54470 [2021-12-19 19:16:16,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54470 [2021-12-19 19:16:16,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109134 states and 144108 transitions. [2021-12-19 19:16:16,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:16,806 INFO L681 BuchiCegarLoop]: Abstraction has 109134 states and 144108 transitions. [2021-12-19 19:16:16,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109134 states and 144108 transitions. [2021-12-19 19:16:17,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109134 to 102638. [2021-12-19 19:16:18,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102638 states, 102638 states have (on average 1.3276564235468344) internal successors, (136268), 102637 states have internal predecessors, (136268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:18,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102638 states to 102638 states and 136268 transitions. [2021-12-19 19:16:18,163 INFO L704 BuchiCegarLoop]: Abstraction has 102638 states and 136268 transitions. [2021-12-19 19:16:18,191 INFO L587 BuchiCegarLoop]: Abstraction has 102638 states and 136268 transitions. [2021-12-19 19:16:18,191 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:16:18,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102638 states and 136268 transitions. [2021-12-19 19:16:18,445 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51064 [2021-12-19 19:16:18,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:18,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:18,455 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:18,455 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:18,455 INFO L791 eck$LassoCheckResult]: Stem: 1156768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1156584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1156477#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1156295#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1156296#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1155514#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1155515#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1155220#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1155221#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1155162#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1155163#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1155472#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1155810#L696 assume !(0 == ~M_E~0); 1155811#L696-2 assume !(0 == ~T1_E~0); 1156542#L701-1 assume !(0 == ~T2_E~0); 1156543#L706-1 assume !(0 == ~T3_E~0); 1156050#L711-1 assume !(0 == ~T4_E~0); 1155573#L716-1 assume !(0 == ~T5_E~0); 1155574#L721-1 assume !(0 == ~T6_E~0); 1155945#L726-1 assume !(0 == ~E_M~0); 1155946#L731-1 assume !(0 == ~E_1~0); 1155883#L736-1 assume !(0 == ~E_2~0); 1155884#L741-1 assume !(0 == ~E_3~0); 1156062#L746-1 assume !(0 == ~E_4~0); 1155642#L751-1 assume !(0 == ~E_5~0); 1155643#L756-1 assume !(0 == ~E_6~0); 1155568#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1155248#L346 assume !(1 == ~m_pc~0); 1155249#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1155667#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1155095#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1155096#L861 assume !(0 != activate_threads_~tmp~1#1); 1156435#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1155308#L365 assume !(1 == ~t1_pc~0); 1155309#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1156476#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1156487#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1155289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1155290#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1156195#L384 assume !(1 == ~t2_pc~0); 1156184#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1156185#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1155467#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1155468#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1155135#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1155841#L403 assume !(1 == ~t3_pc~0); 1155842#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1156287#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1155562#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1155563#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1155828#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1155829#L422 assume !(1 == ~t4_pc~0); 1156097#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1156098#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1156193#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1156194#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1156007#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1155164#L441 assume !(1 == ~t5_pc~0); 1155165#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1156423#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1156804#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1156797#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1156029#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1156030#L460 assume !(1 == ~t6_pc~0); 1156335#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1155179#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1155180#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1156326#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1156327#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1155968#L774 assume !(1 == ~M_E~0); 1155969#L774-2 assume !(1 == ~T1_E~0); 1156370#L779-1 assume !(1 == ~T2_E~0); 1155762#L784-1 assume !(1 == ~T3_E~0); 1155763#L789-1 assume !(1 == ~T4_E~0); 1155279#L794-1 assume !(1 == ~T5_E~0); 1155280#L799-1 assume !(1 == ~T6_E~0); 1156656#L804-1 assume !(1 == ~E_M~0); 1156657#L809-1 assume !(1 == ~E_1~0); 1155939#L814-1 assume !(1 == ~E_2~0); 1155097#L819-1 assume !(1 == ~E_3~0); 1155098#L824-1 assume !(1 == ~E_4~0); 1156084#L829-1 assume !(1 == ~E_5~0); 1156342#L834-1 assume !(1 == ~E_6~0); 1155545#L839-1 assume { :end_inline_reset_delta_events } true; 1155546#L1065-2 assume !false; 1187322#L1066 [2021-12-19 19:16:18,463 INFO L793 eck$LassoCheckResult]: Loop: 1187322#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1241874#L671 assume !false; 1241873#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1241871#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1238406#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1241868#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1241866#L582 assume 0 != eval_~tmp~0#1; 1241865#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1238390#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1241862#L74 assume 0 == ~m_pc~0; 1257686#L110 assume !false; 1257685#L86 ~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1257684#L346-3 assume !(1 == ~m_pc~0); 1257683#L346-5 is_master_triggered_~__retres1~0#1 := 0; 1257681#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1257680#L358-1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1257679#L861-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1257678#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1156086#L365-3 assume !(1 == ~t1_pc~0); 1155118#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1155119#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1155329#L377-1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1156519#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 1257274#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1257271#L384-3 assume !(1 == ~t2_pc~0); 1257267#L384-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1257262#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1257257#L396-1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1257251#L877-3 assume !(0 != activate_threads_~tmp___1~0#1); 1257245#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1257242#L403-3 assume !(1 == ~t3_pc~0); 1241381#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1257108#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1257087#L415-1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1257086#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 1257085#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1257083#L422-3 assume !(1 == ~t4_pc~0); 1256382#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1257081#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1257080#L434-1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1257079#L893-3 assume !(0 != activate_threads_~tmp___3~0#1); 1257078#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1257077#L441-3 assume !(1 == ~t5_pc~0); 1257075#L441-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1257073#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1257071#L453-1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1257070#L901-3 assume !(0 != activate_threads_~tmp___4~0#1); 1155870#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1155871#L460-3 assume !(1 == ~t6_pc~0); 1238409#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1238407#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1238404#L472-1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1238396#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 1238394#L909-5 assume { :end_inline_activate_threads } true; 1238392#L926 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1238388#L119 assume { :end_inline_master } true; 1238387#L587 assume !(0 == ~t1_st~0); 1238386#L601 assume !(0 == ~t2_st~0); 1238602#L615 assume !(0 == ~t3_st~0); 1236915#L629 assume !(0 == ~t4_st~0); 1238597#L643 assume !(0 == ~t5_st~0); 1238411#L657 assume !(0 == ~t6_st~0); 1238410#L671 assume !false; 1238408#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1238405#L530 assume !(0 == ~m_st~0); 1238403#L534 assume !(0 == ~t1_st~0); 1238399#L538 assume !(0 == ~t2_st~0); 1238400#L542 assume !(0 == ~t3_st~0); 1238402#L546 assume !(0 == ~t4_st~0); 1238397#L550 assume !(0 == ~t5_st~0); 1238398#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1238401#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1253997#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1253995#L582 assume !(0 != eval_~tmp~0#1); 1253996#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1255790#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1255787#L696-3 assume !(0 == ~M_E~0); 1253990#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1253989#L701-3 assume !(0 == ~T2_E~0); 1253988#L706-3 assume !(0 == ~T3_E~0); 1253986#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1253985#L716-3 assume !(0 == ~T5_E~0); 1253858#L721-3 assume !(0 == ~T6_E~0); 1253857#L726-3 assume !(0 == ~E_M~0); 1253855#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1253853#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1253851#L741-3 assume !(0 == ~E_3~0); 1253849#L746-3 assume !(0 == ~E_4~0); 1253845#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1253843#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1253841#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1253839#L346-24 assume 1 == ~m_pc~0; 1253835#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1253834#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1253833#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1253831#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1253779#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1253777#L365-24 assume !(1 == ~t1_pc~0); 1253775#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1253773#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1253771#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1253769#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1253767#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1253765#L384-24 assume !(1 == ~t2_pc~0); 1253763#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1253830#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1253829#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1253755#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1253706#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1253147#L403-24 assume !(1 == ~t3_pc~0); 1253146#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1253145#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1253144#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1253143#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1253142#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1253141#L422-24 assume !(1 == ~t4_pc~0); 1228051#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1253140#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1253139#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1253138#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1253137#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1253136#L441-24 assume 1 == ~t5_pc~0; 1253134#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1253135#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1253159#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1253129#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1253128#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1253127#L460-24 assume !(1 == ~t6_pc~0); 1251308#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1253126#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1253125#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1253124#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 1253123#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1253122#L774-3 assume !(1 == ~M_E~0); 1221535#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1245336#L779-3 assume !(1 == ~T2_E~0); 1245334#L784-3 assume !(1 == ~T3_E~0); 1245332#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1245329#L794-3 assume !(1 == ~T5_E~0); 1245322#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1245320#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1245318#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1245317#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1243432#L819-3 assume !(1 == ~E_3~0); 1243428#L824-3 assume !(1 == ~E_4~0); 1243424#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1243420#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1243421#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1241906#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1241904#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1241903#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1241901#L1084 assume !(0 == start_simulation_~tmp~3#1); 1241898#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1241896#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1238449#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1241893#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1241891#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1241887#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1241885#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1241883#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1241881#L1065-2 assume !false; 1187322#L1066 [2021-12-19 19:16:18,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:18,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 1 times [2021-12-19 19:16:18,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:18,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803882754] [2021-12-19 19:16:18,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:18,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:18,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:18,474 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:18,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:18,746 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:18,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:18,755 INFO L85 PathProgramCache]: Analyzing trace with hash 825496861, now seen corresponding path program 1 times [2021-12-19 19:16:18,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:18,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761512159] [2021-12-19 19:16:18,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:18,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:18,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:18,821 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:18,822 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:18,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761512159] [2021-12-19 19:16:18,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761512159] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:18,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:18,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:18,822 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868520831] [2021-12-19 19:16:18,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:18,823 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:18,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:18,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:18,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:18,823 INFO L87 Difference]: Start difference. First operand 102638 states and 136268 transitions. cyclomatic complexity: 33634 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:19,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:19,880 INFO L93 Difference]: Finished difference Result 244179 states and 321877 transitions. [2021-12-19 19:16:19,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:19,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244179 states and 321877 transitions. [2021-12-19 19:16:20,849 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 121476 [2021-12-19 19:16:21,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244179 states to 244179 states and 321877 transitions. [2021-12-19 19:16:21,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121887 [2021-12-19 19:16:21,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121887 [2021-12-19 19:16:21,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 244179 states and 321877 transitions. [2021-12-19 19:16:21,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:21,576 INFO L681 BuchiCegarLoop]: Abstraction has 244179 states and 321877 transitions. [2021-12-19 19:16:21,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244179 states and 321877 transitions. [2021-12-19 19:16:22,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244179 to 106289. [2021-12-19 19:16:22,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106289 states, 106289 states have (on average 1.316401509093133) internal successors, (139919), 106288 states have internal predecessors, (139919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:23,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106289 states to 106289 states and 139919 transitions. [2021-12-19 19:16:23,099 INFO L704 BuchiCegarLoop]: Abstraction has 106289 states and 139919 transitions. [2021-12-19 19:16:23,099 INFO L587 BuchiCegarLoop]: Abstraction has 106289 states and 139919 transitions. [2021-12-19 19:16:23,099 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-19 19:16:23,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106289 states and 139919 transitions. [2021-12-19 19:16:23,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52888 [2021-12-19 19:16:23,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:23,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:23,677 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:23,677 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:23,677 INFO L791 eck$LassoCheckResult]: Stem: 1503556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1503388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1503271#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1503109#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1503110#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1502344#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1502345#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1502046#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1502047#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1501991#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1501992#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1502302#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1502627#L696 assume !(0 == ~M_E~0); 1502628#L696-2 assume !(0 == ~T1_E~0); 1503334#L701-1 assume !(0 == ~T2_E~0); 1503339#L706-1 assume !(0 == ~T3_E~0); 1502865#L711-1 assume !(0 == ~T4_E~0); 1502403#L716-1 assume !(0 == ~T5_E~0); 1502404#L721-1 assume !(0 == ~T6_E~0); 1502767#L726-1 assume !(0 == ~E_M~0); 1502768#L731-1 assume !(0 == ~E_1~0); 1502704#L736-1 assume !(0 == ~E_2~0); 1502705#L741-1 assume !(0 == ~E_3~0); 1502883#L746-1 assume !(0 == ~E_4~0); 1502471#L751-1 assume !(0 == ~E_5~0); 1502472#L756-1 assume !(0 == ~E_6~0); 1502398#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1502077#L346 assume !(1 == ~m_pc~0); 1502078#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1502493#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1503136#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1503367#L861 assume !(0 != activate_threads_~tmp~1#1); 1503231#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1502134#L365 assume !(1 == ~t1_pc~0); 1502135#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1503270#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1503272#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1502118#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1502119#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1503008#L384 assume !(1 == ~t2_pc~0); 1502992#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1502993#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1503597#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1503596#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1501960#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1502658#L403 assume !(1 == ~t3_pc~0); 1502659#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1503097#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1502383#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1502384#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1502642#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1502643#L422 assume !(1 == ~t4_pc~0); 1502913#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1502914#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1503002#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1503003#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1502828#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1501993#L441 assume !(1 == ~t5_pc~0); 1501994#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1503220#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1503391#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1503392#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1502847#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1502848#L460 assume !(1 == ~t6_pc~0); 1503145#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1502004#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1502005#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1503137#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1503138#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1502789#L774 assume !(1 == ~M_E~0); 1502790#L774-2 assume !(1 == ~T1_E~0); 1503172#L779-1 assume !(1 == ~T2_E~0); 1502586#L784-1 assume !(1 == ~T3_E~0); 1502587#L789-1 assume !(1 == ~T4_E~0); 1502107#L794-1 assume !(1 == ~T5_E~0); 1502108#L799-1 assume !(1 == ~T6_E~0); 1503457#L804-1 assume !(1 == ~E_M~0); 1503458#L809-1 assume !(1 == ~E_1~0); 1502762#L814-1 assume !(1 == ~E_2~0); 1501922#L819-1 assume !(1 == ~E_3~0); 1501923#L824-1 assume !(1 == ~E_4~0); 1502904#L829-1 assume !(1 == ~E_5~0); 1503152#L834-1 assume !(1 == ~E_6~0); 1502368#L839-1 assume { :end_inline_reset_delta_events } true; 1502369#L1065-2 assume !false; 1590223#L1066 [2021-12-19 19:16:23,678 INFO L793 eck$LassoCheckResult]: Loop: 1590223#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1590195#L671 assume !false; 1590143#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1554264#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1554261#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1554258#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1554255#L582 assume 0 != eval_~tmp~0#1; 1554252#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1530845#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1554248#L74 assume 0 == ~m_pc~0; 1560521#L110 assume !false; 1560515#L86 ~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1560514#L346-3 assume !(1 == ~m_pc~0); 1560513#L346-5 is_master_triggered_~__retres1~0#1 := 0; 1560511#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1560509#L358-1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1560507#L861-3 assume !(0 != activate_threads_~tmp~1#1); 1560497#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1560492#L365-3 assume !(1 == ~t1_pc~0); 1560478#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1560472#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1560465#L377-1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1560457#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 1560449#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1560442#L384-3 assume 1 == ~t2_pc~0; 1560435#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1560427#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1560419#L396-1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1560409#L877-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1560400#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1560393#L403-3 assume !(1 == ~t3_pc~0); 1549872#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1560378#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1560371#L415-1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1560364#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 1560278#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1530907#L422-3 assume !(1 == ~t4_pc~0); 1530906#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1530905#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1530903#L434-1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1530901#L893-3 assume !(0 != activate_threads_~tmp___3~0#1); 1530899#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1530896#L441-3 assume 1 == ~t5_pc~0; 1530894#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1530895#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1531060#L453-1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1530885#L901-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1530883#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1530881#L460-3 assume !(1 == ~t6_pc~0); 1524653#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1530876#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1530874#L472-1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1530872#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 1530869#L909-5 assume { :end_inline_activate_threads } true; 1530867#L926 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1530843#L119 assume { :end_inline_master } true; 1530840#L587 assume !(0 == ~t1_st~0); 1530836#L601 assume !(0 == ~t2_st~0); 1575815#L615 assume !(0 == ~t3_st~0); 1575814#L629 assume !(0 == ~t4_st~0); 1579108#L643 assume !(0 == ~t5_st~0); 1578900#L657 assume !(0 == ~t6_st~0); 1578899#L671 assume !false; 1578898#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1578897#L530 assume !(0 == ~m_st~0); 1578896#L534 assume !(0 == ~t1_st~0); 1578892#L538 assume !(0 == ~t2_st~0); 1578893#L542 assume !(0 == ~t3_st~0); 1578895#L546 assume !(0 == ~t4_st~0); 1578890#L550 assume !(0 == ~t5_st~0); 1578891#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1578894#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1604422#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1604421#L582 assume !(0 != eval_~tmp~0#1); 1604420#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604419#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1604417#L696-3 assume !(0 == ~M_E~0); 1604415#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604413#L701-3 assume !(0 == ~T2_E~0); 1604411#L706-3 assume !(0 == ~T3_E~0); 1604409#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1604407#L716-3 assume !(0 == ~T5_E~0); 1604403#L721-3 assume !(0 == ~T6_E~0); 1604401#L726-3 assume !(0 == ~E_M~0); 1604398#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1604396#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1604394#L741-3 assume !(0 == ~E_3~0); 1604392#L746-3 assume !(0 == ~E_4~0); 1604390#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1604388#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1586700#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1586701#L346-24 assume !(1 == ~m_pc~0); 1586696#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1586692#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1586693#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1586689#L861-24 assume !(0 != activate_threads_~tmp~1#1); 1586688#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1586687#L365-24 assume !(1 == ~t1_pc~0); 1586686#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1586685#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1586684#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1586683#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1586682#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1586680#L384-24 assume 1 == ~t2_pc~0; 1586681#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1594909#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1594907#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1586669#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1586668#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1586664#L403-24 assume !(1 == ~t3_pc~0); 1583684#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1586661#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1586662#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1586657#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1586658#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1579229#L422-24 assume !(1 == ~t4_pc~0); 1579230#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1579217#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1579218#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1579205#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1579206#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1579190#L441-24 assume !(1 == ~t5_pc~0); 1579192#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1579168#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1579169#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1579147#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1579146#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1579010#L460-24 assume !(1 == ~t6_pc~0); 1579007#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1579004#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1579000#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1578996#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 1578992#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1578988#L774-3 assume !(1 == ~M_E~0); 1544329#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1578984#L779-3 assume !(1 == ~T2_E~0); 1578980#L784-3 assume !(1 == ~T3_E~0); 1578976#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1578971#L794-3 assume !(1 == ~T5_E~0); 1578965#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1578961#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1578957#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1578953#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1578949#L819-3 assume !(1 == ~E_3~0); 1578945#L824-3 assume !(1 == ~E_4~0); 1578941#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1578939#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1578937#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1578934#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1578935#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1596548#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1596546#L1084 assume !(0 == start_simulation_~tmp~3#1); 1596547#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1605114#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1578918#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1605108#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1605104#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1605101#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1605097#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1605092#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1590234#L1065-2 assume !false; 1590223#L1066 [2021-12-19 19:16:23,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:23,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 2 times [2021-12-19 19:16:23,678 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:23,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147385117] [2021-12-19 19:16:23,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:23,679 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:23,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:23,696 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:23,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:23,722 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:23,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:23,723 INFO L85 PathProgramCache]: Analyzing trace with hash 803781302, now seen corresponding path program 1 times [2021-12-19 19:16:23,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:23,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369603315] [2021-12-19 19:16:23,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:23,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:23,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:23,758 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:23,758 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:23,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369603315] [2021-12-19 19:16:23,758 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369603315] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:23,758 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:23,758 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:23,758 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738858833] [2021-12-19 19:16:23,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:23,759 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:23,759 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:23,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:23,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:23,759 INFO L87 Difference]: Start difference. First operand 106289 states and 139919 transitions. cyclomatic complexity: 33634 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:24,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:24,260 INFO L93 Difference]: Finished difference Result 198209 states and 259295 transitions. [2021-12-19 19:16:24,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:24,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198209 states and 259295 transitions. [2021-12-19 19:16:25,295 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 98672 [2021-12-19 19:16:26,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198209 states to 198209 states and 259295 transitions. [2021-12-19 19:16:26,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98897 [2021-12-19 19:16:26,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98897 [2021-12-19 19:16:26,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198209 states and 259295 transitions. [2021-12-19 19:16:26,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:26,228 INFO L681 BuchiCegarLoop]: Abstraction has 198209 states and 259295 transitions. [2021-12-19 19:16:26,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198209 states and 259295 transitions. [2021-12-19 19:16:27,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198209 to 190913. [2021-12-19 19:16:28,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190913 states, 190913 states have (on average 1.3159449592222636) internal successors, (251231), 190912 states have internal predecessors, (251231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:28,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190913 states to 190913 states and 251231 transitions. [2021-12-19 19:16:28,392 INFO L704 BuchiCegarLoop]: Abstraction has 190913 states and 251231 transitions. [2021-12-19 19:16:28,393 INFO L587 BuchiCegarLoop]: Abstraction has 190913 states and 251231 transitions. [2021-12-19 19:16:28,393 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-19 19:16:28,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190913 states and 251231 transitions. [2021-12-19 19:16:28,857 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 95024 [2021-12-19 19:16:28,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:28,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:28,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,896 INFO L791 eck$LassoCheckResult]: Stem: 1808150#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1807960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1807840#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1807665#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1807666#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1806853#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1806854#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1806551#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1806552#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1806496#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1806497#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1806809#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1807155#L696 assume !(0 == ~M_E~0); 1807156#L696-2 assume !(0 == ~T1_E~0); 1807909#L701-1 assume !(0 == ~T2_E~0); 1807914#L706-1 assume !(0 == ~T3_E~0); 1807403#L711-1 assume !(0 == ~T4_E~0); 1806916#L716-1 assume !(0 == ~T5_E~0); 1806917#L721-1 assume !(0 == ~T6_E~0); 1807304#L726-1 assume !(0 == ~E_M~0); 1807305#L731-1 assume !(0 == ~E_1~0); 1807235#L736-1 assume !(0 == ~E_2~0); 1807236#L741-1 assume !(0 == ~E_3~0); 1807425#L746-1 assume !(0 == ~E_4~0); 1806985#L751-1 assume !(0 == ~E_5~0); 1806986#L756-1 assume !(0 == ~E_6~0); 1806911#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1806579#L346 assume !(1 == ~m_pc~0); 1806580#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1807008#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1807695#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1807948#L861 assume !(0 != activate_threads_~tmp~1#1); 1807792#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1806640#L365 assume !(1 == ~t1_pc~0); 1806641#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1807836#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1807841#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1806624#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1806625#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1807561#L384 assume !(1 == ~t2_pc~0); 1807545#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1807546#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1806803#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1806804#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1806465#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1807188#L403 assume !(1 == ~t3_pc~0); 1807189#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1807656#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1806894#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1806895#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1807171#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1807172#L422 assume !(1 == ~t4_pc~0); 1807459#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1807460#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1807555#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1807556#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1807368#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1806498#L441 assume !(1 == ~t5_pc~0); 1806499#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1807782#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1808194#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1808185#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1807386#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1807387#L460 assume !(1 == ~t6_pc~0); 1807705#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1806509#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1806510#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1807696#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1807697#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1807328#L774 assume !(1 == ~M_E~0); 1807329#L774-2 assume !(1 == ~T1_E~0); 1807735#L779-1 assume !(1 == ~T2_E~0); 1807109#L784-1 assume !(1 == ~T3_E~0); 1807110#L789-1 assume !(1 == ~T4_E~0); 1806610#L794-1 assume !(1 == ~T5_E~0); 1806611#L799-1 assume !(1 == ~T6_E~0); 1808027#L804-1 assume !(1 == ~E_M~0); 1808028#L809-1 assume !(1 == ~E_1~0); 1807298#L814-1 assume !(1 == ~E_2~0); 1806427#L819-1 assume !(1 == ~E_3~0); 1806428#L824-1 assume !(1 == ~E_4~0); 1807447#L829-1 assume !(1 == ~E_5~0); 1807712#L834-1 assume !(1 == ~E_6~0); 1806878#L839-1 assume { :end_inline_reset_delta_events } true; 1806879#L1065-2 assume !false; 1872669#L1066 [2021-12-19 19:16:28,897 INFO L793 eck$LassoCheckResult]: Loop: 1872669#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1954116#L671 assume !false; 1954114#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1954107#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1954102#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1954099#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1954096#L582 assume 0 != eval_~tmp~0#1; 1953906#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1953904#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1953905#L74 assume 0 == ~m_pc~0; 1996422#L110 assume !false; 1807855#L86 ~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1807209#L346-3 assume !(1 == ~m_pc~0); 1807211#L346-5 is_master_triggered_~__retres1~0#1 := 0; 1807524#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1807799#L358-1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1806511#L861-3 assume !(0 != activate_threads_~tmp~1#1); 1806512#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1807091#L365-3 assume !(1 == ~t1_pc~0); 1807449#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1996461#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1996458#L377-1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1996456#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 1996454#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1996452#L384-3 assume !(1 == ~t2_pc~0); 1996450#L384-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1996672#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1996670#L396-1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1996145#L877-3 assume !(0 != activate_threads_~tmp___1~0#1); 1807276#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1806874#L403-3 assume !(1 == ~t3_pc~0); 1806875#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1807526#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1807902#L415-1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1807903#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 1806835#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1806836#L422-3 assume !(1 == ~t4_pc~0); 1954977#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1954975#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1954973#L434-1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1954971#L893-3 assume !(0 != activate_threads_~tmp___3~0#1); 1954970#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1954965#L441-3 assume !(1 == ~t5_pc~0); 1954961#L441-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1954959#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1954956#L453-1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1954953#L901-3 assume !(0 != activate_threads_~tmp___4~0#1); 1954951#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1954949#L460-3 assume !(1 == ~t6_pc~0); 1954948#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1954947#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1954946#L472-1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1954945#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 1954944#L909-5 assume { :end_inline_activate_threads } true; 1954943#L926 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1954939#L119 assume { :end_inline_master } true; 1954937#L587 assume !(0 == ~t1_st~0); 1954933#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1944644#L618 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 1954931#L166 assume 0 == ~t2_pc~0; 1985448#L177-1 assume !false; 1944647#L178 ~t2_pc~0 := 1;~t2_st~0 := 2; 1944645#L191 assume { :end_inline_transmit2 } true; 1944641#L615 assume !(0 == ~t3_st~0); 1944639#L629 assume !(0 == ~t4_st~0); 1955168#L643 assume !(0 == ~t5_st~0); 1954966#L657 assume !(0 == ~t6_st~0); 1954962#L671 assume !false; 1954960#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1954957#L530 assume !(0 == ~m_st~0); 1954954#L534 assume !(0 == ~t1_st~0); 1954955#L538 assume !(0 == ~t2_st~0); 1807878#L542 assume !(0 == ~t3_st~0); 1806563#L546 assume !(0 == ~t4_st~0); 1806565#L550 assume !(0 == ~t5_st~0); 1807503#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1807504#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1988012#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1988013#L582 assume !(0 != eval_~tmp~0#1); 1991292#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1991285#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1991280#L696-3 assume !(0 == ~M_E~0); 1991274#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1991196#L701-3 assume !(0 == ~T2_E~0); 1991194#L706-3 assume !(0 == ~T3_E~0); 1991191#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1991189#L716-3 assume !(0 == ~T5_E~0); 1991184#L721-3 assume !(0 == ~T6_E~0); 1991182#L726-3 assume !(0 == ~E_M~0); 1991179#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1991115#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1991109#L741-3 assume !(0 == ~E_3~0); 1959169#L746-3 assume !(0 == ~E_4~0); 1959165#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1959163#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1959161#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1959157#L346-24 assume 1 == ~m_pc~0; 1959153#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1959154#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1987767#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1987766#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1987764#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1987761#L365-24 assume !(1 == ~t1_pc~0); 1987759#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1987757#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1987756#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1987755#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1987754#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1987753#L384-24 assume !(1 == ~t2_pc~0); 1987750#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1987749#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1987748#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1987742#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1987744#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1992278#L403-24 assume !(1 == ~t3_pc~0); 1929796#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1992276#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1992274#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1992273#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1986900#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1956218#L422-24 assume !(1 == ~t4_pc~0); 1956216#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1956214#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1956212#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1956210#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1956208#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1956206#L441-24 assume 1 == ~t5_pc~0; 1956204#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1956205#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1956231#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1956193#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1956191#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1956188#L460-24 assume !(1 == ~t6_pc~0); 1956186#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1956184#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1956182#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1956180#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 1956178#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1956176#L774-3 assume !(1 == ~M_E~0); 1945034#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1956173#L779-3 assume !(1 == ~T2_E~0); 1956172#L784-3 assume !(1 == ~T3_E~0); 1956170#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1956168#L794-3 assume !(1 == ~T5_E~0); 1956166#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1956164#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1956162#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1956160#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1955560#L819-3 assume !(1 == ~E_3~0); 1955558#L824-3 assume !(1 == ~E_4~0); 1955556#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1955554#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1955553#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1955547#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1955542#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1955540#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1955538#L1084 assume !(0 == start_simulation_~tmp~3#1); 1955531#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1954148#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1954144#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1954140#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1954138#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1954136#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1954134#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1954131#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1954129#L1065-2 assume !false; 1872669#L1066 [2021-12-19 19:16:28,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,897 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 3 times [2021-12-19 19:16:28,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487854227] [2021-12-19 19:16:28,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,898 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,919 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:28,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:28,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1970817879, now seen corresponding path program 1 times [2021-12-19 19:16:28,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059693368] [2021-12-19 19:16:28,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:28,966 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:28,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:28,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059693368] [2021-12-19 19:16:28,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059693368] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:28,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:28,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:28,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754080968] [2021-12-19 19:16:28,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:28,983 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:28,983 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:28,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:28,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:28,984 INFO L87 Difference]: Start difference. First operand 190913 states and 251231 transitions. cyclomatic complexity: 60322 Second operand has 3 states, 3 states have (on average 55.333333333333336) internal successors, (166), 3 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:29,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:29,829 INFO L93 Difference]: Finished difference Result 187457 states and 244445 transitions. [2021-12-19 19:16:29,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:29,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187457 states and 244445 transitions. [2021-12-19 19:16:30,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 93296 [2021-12-19 19:16:31,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187457 states to 187457 states and 244445 transitions. [2021-12-19 19:16:31,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93521 [2021-12-19 19:16:31,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93521 [2021-12-19 19:16:31,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 187457 states and 244445 transitions. [2021-12-19 19:16:31,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:31,198 INFO L681 BuchiCegarLoop]: Abstraction has 187457 states and 244445 transitions. [2021-12-19 19:16:31,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187457 states and 244445 transitions. [2021-12-19 19:16:33,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187457 to 187457. [2021-12-19 19:16:33,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 187457 states, 187457 states have (on average 1.3040057186448093) internal successors, (244445), 187456 states have internal predecessors, (244445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:33,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187457 states to 187457 states and 244445 transitions. [2021-12-19 19:16:33,488 INFO L704 BuchiCegarLoop]: Abstraction has 187457 states and 244445 transitions. [2021-12-19 19:16:33,488 INFO L587 BuchiCegarLoop]: Abstraction has 187457 states and 244445 transitions. [2021-12-19 19:16:33,488 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-19 19:16:33,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 187457 states and 244445 transitions. [2021-12-19 19:16:33,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 93296 [2021-12-19 19:16:33,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:33,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:33,957 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:33,957 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:33,957 INFO L791 eck$LassoCheckResult]: Stem: 2186455#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2186277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2186168#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2186002#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2186003#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2185231#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2185232#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2184933#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2184934#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2184874#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2184875#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2185189#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2185528#L696 assume !(0 == ~M_E~0); 2185529#L696-2 assume !(0 == ~T1_E~0); 2186234#L701-1 assume !(0 == ~T2_E~0); 2186235#L706-1 assume !(0 == ~T3_E~0); 2185764#L711-1 assume !(0 == ~T4_E~0); 2185293#L716-1 assume !(0 == ~T5_E~0); 2185294#L721-1 assume !(0 == ~T6_E~0); 2185663#L726-1 assume !(0 == ~E_M~0); 2185664#L731-1 assume !(0 == ~E_1~0); 2185603#L736-1 assume !(0 == ~E_2~0); 2185604#L741-1 assume !(0 == ~E_3~0); 2185782#L746-1 assume !(0 == ~E_4~0); 2185360#L751-1 assume !(0 == ~E_5~0); 2185361#L756-1 assume !(0 == ~E_6~0); 2185288#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2184959#L346 assume !(1 == ~m_pc~0); 2184960#L346-2 is_master_triggered_~__retres1~0#1 := 0; 2185385#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2186031#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2186263#L861 assume !(0 != activate_threads_~tmp~1#1); 2186126#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2185021#L365 assume !(1 == ~t1_pc~0); 2185022#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2186167#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2186176#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2185002#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2185003#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2185903#L384 assume !(1 == ~t2_pc~0); 2185893#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2185894#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2185185#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2185186#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2184847#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2185560#L403 assume !(1 == ~t3_pc~0); 2185561#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2185987#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2185279#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2185280#L885 assume !(0 != activate_threads_~tmp___2~0#1); 2185546#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2185547#L422 assume !(1 == ~t4_pc~0); 2185810#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2185811#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2185901#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2185902#L893 assume !(0 != activate_threads_~tmp___3~0#1); 2185724#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2184876#L441 assume !(1 == ~t5_pc~0); 2184877#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2186118#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2186483#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2186477#L901 assume !(0 != activate_threads_~tmp___4~0#1); 2185744#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2185745#L460 assume !(1 == ~t6_pc~0); 2186040#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2184891#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2184892#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2186032#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2186033#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2185684#L774 assume !(1 == ~M_E~0); 2185685#L774-2 assume !(1 == ~T1_E~0); 2186072#L779-1 assume !(1 == ~T2_E~0); 2185476#L784-1 assume !(1 == ~T3_E~0); 2185477#L789-1 assume !(1 == ~T4_E~0); 2184990#L794-1 assume !(1 == ~T5_E~0); 2184991#L799-1 assume !(1 == ~T6_E~0); 2186348#L804-1 assume !(1 == ~E_M~0); 2186349#L809-1 assume !(1 == ~E_1~0); 2185657#L814-1 assume !(1 == ~E_2~0); 2184809#L819-1 assume !(1 == ~E_3~0); 2184810#L824-1 assume !(1 == ~E_4~0); 2185798#L829-1 assume !(1 == ~E_5~0); 2186048#L834-1 assume !(1 == ~E_6~0); 2185261#L839-1 assume { :end_inline_reset_delta_events } true; 2185262#L1065-2 assume !false; 2227716#L1066 [2021-12-19 19:16:33,958 INFO L793 eck$LassoCheckResult]: Loop: 2227716#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2300939#L671 assume !false; 2300937#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2299092#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2299093#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2312118#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2312116#L582 assume 0 != eval_~tmp~0#1; 2299082#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2299080#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 2299081#L74 assume 0 == ~m_pc~0; 2320622#L110 assume !false; 2320620#L86 ~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2320618#L346-3 assume !(1 == ~m_pc~0); 2320614#L346-5 is_master_triggered_~__retres1~0#1 := 0; 2320612#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2320610#L358-1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2320607#L861-3 assume !(0 != activate_threads_~tmp~1#1); 2320604#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2320602#L365-3 assume !(1 == ~t1_pc~0); 2320600#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 2320598#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2320596#L377-1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2320595#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 2320593#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2320590#L384-3 assume !(1 == ~t2_pc~0); 2320589#L384-5 is_transmit2_triggered_~__retres1~2#1 := 0; 2320730#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2320729#L396-1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2320580#L877-3 assume !(0 != activate_threads_~tmp___1~0#1); 2307924#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2320575#L403-3 assume !(1 == ~t3_pc~0); 2320203#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 2320572#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2320570#L415-1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2320568#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 2320566#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2320564#L422-3 assume !(1 == ~t4_pc~0); 2291702#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 2320561#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2320560#L434-1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2320559#L893-3 assume !(0 != activate_threads_~tmp___3~0#1); 2320558#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2320557#L441-3 assume 1 == ~t5_pc~0; 2320555#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2320556#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2320554#L453-1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2320549#L901-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2320547#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2312111#L460-3 assume !(1 == ~t6_pc~0); 2312110#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 2312109#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2312108#L472-1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2312107#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 2312106#L909-5 assume { :end_inline_activate_threads } true; 2312104#L926 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 2311679#L119 assume { :end_inline_master } true; 2311676#L587 assume !(0 == ~t1_st~0); 2300989#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2300986#L618 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 2300987#L166 assume 0 == ~t2_pc~0; 2307869#L177-1 assume !false; 2307865#L178 ~t2_pc~0 := 1;~t2_st~0 := 2; 2307861#L191 assume { :end_inline_transmit2 } true; 2307859#L615 assume !(0 == ~t3_st~0); 2307858#L629 assume !(0 == ~t4_st~0); 2308287#L643 assume !(0 == ~t5_st~0); 2308275#L657 assume !(0 == ~t6_st~0); 2308274#L671 assume !false; 2308273#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2308272#L530 assume !(0 == ~m_st~0); 2308271#L534 assume !(0 == ~t1_st~0); 2308270#L538 assume !(0 == ~t2_st~0); 2308269#L542 assume !(0 == ~t3_st~0); 2308268#L546 assume !(0 == ~t4_st~0); 2308267#L550 assume !(0 == ~t5_st~0); 2308264#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 2308260#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2308258#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2308255#L582 assume !(0 != eval_~tmp~0#1); 2308253#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2308251#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2308249#L696-3 assume !(0 == ~M_E~0); 2308247#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2308245#L701-3 assume !(0 == ~T2_E~0); 2308243#L706-3 assume !(0 == ~T3_E~0); 2308241#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2308239#L716-3 assume !(0 == ~T5_E~0); 2308235#L721-3 assume !(0 == ~T6_E~0); 2308233#L726-3 assume !(0 == ~E_M~0); 2308231#L731-3 assume !(0 == ~E_1~0); 2308229#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2308228#L741-3 assume !(0 == ~E_3~0); 2308226#L746-3 assume !(0 == ~E_4~0); 2308224#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2308223#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2308222#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2308221#L346-24 assume 1 == ~m_pc~0; 2308218#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2308219#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2320727#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2320726#L861-24 assume !(0 != activate_threads_~tmp~1#1); 2308165#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2308164#L365-24 assume !(1 == ~t1_pc~0); 2308163#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 2308161#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2308159#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2308157#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 2308155#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2308153#L384-24 assume 1 == ~t2_pc~0; 2308151#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2308152#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2320442#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2320440#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2308141#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2320439#L403-24 assume !(1 == ~t3_pc~0); 2311008#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 2320437#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2320436#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2320435#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 2320433#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2320432#L422-24 assume !(1 == ~t4_pc~0); 2306041#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2320430#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2320427#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2320426#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 2320425#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2320424#L441-24 assume 1 == ~t5_pc~0; 2320422#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2320423#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2321532#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2320415#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2320414#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2305006#L460-24 assume !(1 == ~t6_pc~0); 2305003#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2304999#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2304994#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2304989#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 2304983#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2304977#L774-3 assume !(1 == ~M_E~0); 2304971#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2304967#L779-3 assume !(1 == ~T2_E~0); 2304963#L784-3 assume !(1 == ~T3_E~0); 2304959#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2304955#L794-3 assume !(1 == ~T5_E~0); 2304951#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2304945#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2304940#L809-3 assume !(1 == ~E_1~0); 2304934#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2304928#L819-3 assume !(1 == ~E_3~0); 2304924#L824-3 assume !(1 == ~E_4~0); 2304920#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2304918#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2304914#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2304909#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2304910#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2311626#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2311623#L1084 assume !(0 == start_simulation_~tmp~3#1); 2311619#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2300967#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2300965#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2300961#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2300959#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2300957#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2300956#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2300950#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 2300948#L1065-2 assume !false; 2227716#L1066 [2021-12-19 19:16:33,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:33,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 4 times [2021-12-19 19:16:33,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:33,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794370660] [2021-12-19 19:16:33,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:33,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:33,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:33,963 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:33,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:33,977 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:33,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:33,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1077384089, now seen corresponding path program 1 times [2021-12-19 19:16:33,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:33,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830737984] [2021-12-19 19:16:33,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:33,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:33,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:33,992 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:33,992 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:33,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830737984] [2021-12-19 19:16:33,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830737984] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:33,992 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:33,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:33,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109759150] [2021-12-19 19:16:33,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:33,993 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:33,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:33,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:33,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:33,994 INFO L87 Difference]: Start difference. First operand 187457 states and 244445 transitions. cyclomatic complexity: 56992 Second operand has 3 states, 3 states have (on average 55.333333333333336) internal successors, (166), 3 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:35,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:35,096 INFO L93 Difference]: Finished difference Result 328417 states and 429373 transitions. [2021-12-19 19:16:35,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:35,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 328417 states and 429373 transitions. [2021-12-19 19:16:36,748 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 163424 [2021-12-19 19:16:37,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 328417 states to 328417 states and 429373 transitions. [2021-12-19 19:16:37,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163777 [2021-12-19 19:16:37,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163777 [2021-12-19 19:16:37,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328417 states and 429373 transitions. [2021-12-19 19:16:37,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:37,952 INFO L681 BuchiCegarLoop]: Abstraction has 328417 states and 429373 transitions. [2021-12-19 19:16:38,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328417 states and 429373 transitions. [2021-12-19 19:16:40,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328417 to 322273. [2021-12-19 19:16:40,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322273 states, 322273 states have (on average 1.3108792855746525) internal successors, (422461), 322272 states have internal predecessors, (422461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:41,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322273 states to 322273 states and 422461 transitions. [2021-12-19 19:16:41,336 INFO L704 BuchiCegarLoop]: Abstraction has 322273 states and 422461 transitions. [2021-12-19 19:16:41,336 INFO L587 BuchiCegarLoop]: Abstraction has 322273 states and 422461 transitions. [2021-12-19 19:16:41,336 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-19 19:16:41,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322273 states and 422461 transitions. [2021-12-19 19:16:42,630 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 160352 [2021-12-19 19:16:42,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:42,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:42,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:42,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:42,665 INFO L791 eck$LassoCheckResult]: Stem: 2702448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2702246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2702110#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2701917#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2701918#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2701103#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2701104#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2700809#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2700810#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2700753#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2700754#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2701063#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2701412#L696 assume !(0 == ~M_E~0); 2701413#L696-2 assume !(0 == ~T1_E~0); 2702195#L701-1 assume !(0 == ~T2_E~0); 2702196#L706-1 assume !(0 == ~T3_E~0); 2701668#L711-1 assume !(0 == ~T4_E~0); 2701164#L716-1 assume !(0 == ~T5_E~0); 2701165#L721-1 assume !(0 == ~T6_E~0); 2701554#L726-1 assume !(0 == ~E_M~0); 2701555#L731-1 assume !(0 == ~E_1~0); 2701488#L736-1 assume !(0 == ~E_2~0); 2701489#L741-1 assume !(0 == ~E_3~0); 2701682#L746-1 assume !(0 == ~E_4~0); 2701235#L751-1 assume !(0 == ~E_5~0); 2701236#L756-1 assume !(0 == ~E_6~0); 2701159#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2700835#L346 assume !(1 == ~m_pc~0); 2700836#L346-2 is_master_triggered_~__retres1~0#1 := 0; 2701260#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2701949#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2702226#L861 assume !(0 != activate_threads_~tmp~1#1); 2702059#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2700895#L365 assume !(1 == ~t1_pc~0); 2700896#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2702107#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702118#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2700876#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2700877#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2701821#L384 assume !(1 == ~t2_pc~0); 2701810#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2701811#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2701060#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2701061#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2700726#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2701441#L403 assume !(1 == ~t3_pc~0); 2701442#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2701908#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2701151#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2701152#L885 assume !(0 != activate_threads_~tmp___2~0#1); 2701430#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2701431#L422 assume !(1 == ~t4_pc~0); 2701720#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2701721#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2701819#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2701820#L893 assume !(0 != activate_threads_~tmp___3~0#1); 2701622#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2700755#L441 assume !(1 == ~t5_pc~0); 2700756#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2702049#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2702488#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2702480#L901 assume !(0 != activate_threads_~tmp___4~0#1); 2701646#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2701647#L460 assume !(1 == ~t6_pc~0); 2701958#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2700770#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2700771#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2701950#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2701951#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2701580#L774 assume !(1 == ~M_E~0); 2701581#L774-2 assume !(1 == ~T1_E~0); 2701985#L779-1 assume !(1 == ~T2_E~0); 2701363#L784-1 assume !(1 == ~T3_E~0); 2701364#L789-1 assume !(1 == ~T4_E~0); 2700864#L794-1 assume !(1 == ~T5_E~0); 2700865#L799-1 assume !(1 == ~T6_E~0); 2702319#L804-1 assume !(1 == ~E_M~0); 2702320#L809-1 assume !(1 == ~E_1~0); 2701547#L814-1 assume !(1 == ~E_2~0); 2700689#L819-1 assume !(1 == ~E_3~0); 2700690#L824-1 assume !(1 == ~E_4~0); 2701703#L829-1 assume !(1 == ~E_5~0); 2701965#L834-1 assume !(1 == ~E_6~0); 2701134#L839-1 assume { :end_inline_reset_delta_events } true; 2701135#L1065-2 assume !false; 2744005#L1066 [2021-12-19 19:16:42,665 INFO L793 eck$LassoCheckResult]: Loop: 2744005#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2998270#L671 assume !false; 2998269#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2912443#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2912438#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2912436#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2912399#L582 assume 0 != eval_~tmp~0#1; 2897327#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2897325#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 2702333#L74 assume 0 == ~m_pc~0; 2701297#L110 assume !false; 2702128#L86 ~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2702129#L346-3 assume 1 == ~m_pc~0; 2702457#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2702068#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2702069#L358-1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2702286#L861-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2700767#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2701707#L365-3 assume !(1 == ~t1_pc~0); 2701708#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 3022320#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3022319#L377-1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3022318#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 3022317#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2700990#L384-3 assume !(1 == ~t2_pc~0); 2700991#L384-5 is_transmit2_triggered_~__retres1~2#1 := 0; 2701166#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3022178#L396-1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3022179#L877-3 assume !(0 != activate_threads_~tmp___1~0#1); 2701529#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2701124#L403-3 assume !(1 == ~t3_pc~0); 2701125#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 2701785#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2702297#L415-1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3019635#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 3019630#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3019629#L422-3 assume !(1 == ~t4_pc~0); 2963372#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 3019626#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3019625#L434-1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3019624#L893-3 assume !(0 != activate_threads_~tmp___3~0#1); 3019623#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3019621#L441-3 assume !(1 == ~t5_pc~0); 3019618#L441-5 is_transmit5_triggered_~__retres1~5#1 := 0; 3019614#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3019612#L453-1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3019609#L901-3 assume !(0 != activate_threads_~tmp___4~0#1); 3019605#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2938892#L460-3 assume !(1 == ~t6_pc~0); 2938890#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 2938888#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2938887#L472-1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2938885#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 2938883#L909-5 assume { :end_inline_activate_threads } true; 2938881#L926 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 2938834#L119 assume { :end_inline_master } true; 2938832#L587 assume !(0 == ~t1_st~0); 2938829#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2938818#L618 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 2938826#L166 assume 0 == ~t2_pc~0; 2938822#L177-1 assume !false; 2938820#L178 ~t2_pc~0 := 1;~t2_st~0 := 2; 2938819#L191 assume { :end_inline_transmit2 } true; 2938814#L615 assume !(0 == ~t3_st~0); 2938811#L629 assume !(0 == ~t4_st~0); 2938807#L643 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 2922779#L660 assume 0 != eval_~tmp_ndt_6~0#1;~t5_st~0 := 1;assume { :begin_inline_transmit5 } true; 2922785#L274 assume 0 == ~t5_pc~0; 2922784#L285-1 assume !false; 2922782#L286 ~t5_pc~0 := 1;~t5_st~0 := 2; 2922780#L299 assume { :end_inline_transmit5 } true; 2922776#L657 assume !(0 == ~t6_st~0); 2922774#L671 assume !false; 2945441#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2945438#L530 assume !(0 == ~m_st~0); 2945436#L534 assume !(0 == ~t1_st~0); 2945434#L538 assume !(0 == ~t2_st~0); 2945432#L542 assume !(0 == ~t3_st~0); 2945430#L546 assume !(0 == ~t4_st~0); 2945428#L550 assume !(0 == ~t5_st~0); 2945425#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 2945421#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2945419#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2945417#L582 assume !(0 != eval_~tmp~0#1); 2945415#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2945414#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2945413#L696-3 assume !(0 == ~M_E~0); 2945412#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2945411#L701-3 assume !(0 == ~T2_E~0); 2945410#L706-3 assume !(0 == ~T3_E~0); 2945409#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2945407#L716-3 assume !(0 == ~T5_E~0); 2945405#L721-3 assume !(0 == ~T6_E~0); 2945403#L726-3 assume !(0 == ~E_M~0); 2945401#L731-3 assume !(0 == ~E_1~0); 2945399#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2945397#L741-3 assume !(0 == ~E_3~0); 2945395#L746-3 assume !(0 == ~E_4~0); 2945393#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2945391#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2945389#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2945387#L346-24 assume !(1 == ~m_pc~0); 2945385#L346-26 is_master_triggered_~__retres1~0#1 := 0; 2945381#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2945379#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2945375#L861-24 assume !(0 != activate_threads_~tmp~1#1); 2945373#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2945371#L365-24 assume !(1 == ~t1_pc~0); 2945369#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 2945367#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2945365#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2945364#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 2945362#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2945360#L384-24 assume !(1 == ~t2_pc~0); 2945356#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2945354#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2945352#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2945350#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2945351#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3007548#L403-24 assume !(1 == ~t3_pc~0); 2894981#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3007547#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3007546#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3007545#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 3007544#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3007543#L422-24 assume !(1 == ~t4_pc~0); 2903617#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 3007542#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3007541#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3007540#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 3007538#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3007536#L441-24 assume 1 == ~t5_pc~0; 3007533#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3007531#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3007529#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3007527#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3007525#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2917050#L460-24 assume !(1 == ~t6_pc~0); 2917048#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2917046#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2917044#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2917042#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 2917040#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2917038#L774-3 assume !(1 == ~M_E~0); 2917034#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2917032#L779-3 assume !(1 == ~T2_E~0); 2917030#L784-3 assume !(1 == ~T3_E~0); 2917029#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2917027#L794-3 assume !(1 == ~T5_E~0); 2916971#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2916969#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2916967#L809-3 assume !(1 == ~E_1~0); 2916965#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2916958#L819-3 assume !(1 == ~E_3~0); 2916956#L824-3 assume !(1 == ~E_4~0); 2916954#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2916952#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2916950#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2916947#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2916948#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2998659#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2998653#L1084 assume !(0 == start_simulation_~tmp~3#1); 2998645#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2998640#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2916931#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2998633#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2998281#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2998280#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2998279#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2998276#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 2998275#L1065-2 assume !false; 2744005#L1066 [2021-12-19 19:16:42,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:42,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 5 times [2021-12-19 19:16:42,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:42,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879894119] [2021-12-19 19:16:42,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:42,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:42,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:42,671 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:42,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:42,682 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:42,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:42,682 INFO L85 PathProgramCache]: Analyzing trace with hash -194968085, now seen corresponding path program 1 times [2021-12-19 19:16:42,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:42,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608956991] [2021-12-19 19:16:42,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:42,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:42,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:42,694 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:42,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:42,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608956991] [2021-12-19 19:16:42,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608956991] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:42,694 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:42,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:42,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613186586] [2021-12-19 19:16:42,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:42,695 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:42,695 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:42,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:42,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:42,696 INFO L87 Difference]: Start difference. First operand 322273 states and 422461 transitions. cyclomatic complexity: 100192 Second operand has 3 states, 3 states have (on average 57.0) internal successors, (171), 3 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:44,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:44,155 INFO L93 Difference]: Finished difference Result 399711 states and 517272 transitions. [2021-12-19 19:16:44,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:44,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399711 states and 517272 transitions.