./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:15:52,565 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:15:52,567 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:15:52,602 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:15:52,602 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:15:52,604 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:15:52,605 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:15:52,606 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:15:52,609 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:15:52,610 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:15:52,611 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:15:52,613 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:15:52,613 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:15:52,617 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:15:52,618 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:15:52,619 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:15:52,623 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:15:52,624 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:15:52,625 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:15:52,626 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:15:52,630 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:15:52,630 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:15:52,631 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:15:52,632 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:15:52,634 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:15:52,636 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:15:52,636 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:15:52,636 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:15:52,637 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:15:52,638 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:15:52,639 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:15:52,639 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:15:52,640 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:15:52,641 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:15:52,641 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:15:52,642 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:15:52,643 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:15:52,643 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:15:52,643 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:15:52,643 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:15:52,644 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:15:52,645 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:15:52,663 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:15:52,663 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:15:52,663 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:15:52,664 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:15:52,665 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:15:52,665 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:15:52,665 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:15:52,665 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:15:52,666 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:15:52,666 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:15:52,666 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:15:52,667 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:15:52,667 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:15:52,668 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:15:52,669 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:15:52,669 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:15:52,669 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:15:52,669 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:15:52,669 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:15:52,669 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:15:52,670 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:15:52,670 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:15:52,670 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2021-12-19 19:15:52,816 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:15:52,829 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:15:52,830 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:15:52,831 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:15:52,832 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:15:52,832 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2021-12-19 19:15:52,884 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cccc73b/89a624ee87f04556a9bfe8e2b8683431/FLAGe142ddf7f [2021-12-19 19:15:53,292 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:15:53,292 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2021-12-19 19:15:53,308 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cccc73b/89a624ee87f04556a9bfe8e2b8683431/FLAGe142ddf7f [2021-12-19 19:15:53,316 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cccc73b/89a624ee87f04556a9bfe8e2b8683431 [2021-12-19 19:15:53,318 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:15:53,320 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:15:53,321 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:53,321 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:15:53,323 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:15:53,324 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,324 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f5dd47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53, skipping insertion in model container [2021-12-19 19:15:53,335 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,339 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:15:53,387 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:15:53,502 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2021-12-19 19:15:53,546 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:53,558 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:15:53,567 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2021-12-19 19:15:53,610 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:15:53,621 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:15:53,621 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53 WrapperNode [2021-12-19 19:15:53,622 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:15:53,622 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:53,622 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:15:53,623 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:15:53,635 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,642 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,684 INFO L137 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 113, statements flattened = 1650 [2021-12-19 19:15:53,685 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:15:53,685 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:15:53,686 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:15:53,686 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:15:53,691 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,691 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,695 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,695 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,706 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,716 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,718 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,723 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:15:53,724 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:15:53,724 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:15:53,724 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:15:53,725 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (1/1) ... [2021-12-19 19:15:53,729 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:15:53,750 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:15:53,758 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:15:53,780 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:15:53,790 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:15:53,790 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:15:53,790 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:15:53,790 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:15:53,845 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:15:53,846 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:15:54,435 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:15:54,443 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:15:54,443 INFO L301 CfgBuilder]: Removed 9 assume(true) statements. [2021-12-19 19:15:54,445 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:54 BoogieIcfgContainer [2021-12-19 19:15:54,445 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:15:54,470 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:15:54,470 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:15:54,472 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:15:54,473 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:54,473 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:15:53" (1/3) ... [2021-12-19 19:15:54,474 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@70d49c7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:54, skipping insertion in model container [2021-12-19 19:15:54,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:54,474 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:15:53" (2/3) ... [2021-12-19 19:15:54,474 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@70d49c7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:15:54, skipping insertion in model container [2021-12-19 19:15:54,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:15:54,474 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:15:54" (3/3) ... [2021-12-19 19:15:54,475 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2021-12-19 19:15:54,499 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:15:54,499 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:15:54,499 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:15:54,499 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:15:54,500 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:15:54,500 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:15:54,500 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:15:54,500 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:15:54,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2021-12-19 19:15:54,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,558 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,558 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,559 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:15:54,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2021-12-19 19:15:54,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,571 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,572 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,577 INFO L791 eck$LassoCheckResult]: Stem: 671#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 565#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 533#L1016true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 495#L468true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 552#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 310#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 615#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 252#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 121#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 453#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 81#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 522#L684true assume !(0 == ~M_E~0); 437#L684-2true assume !(0 == ~T1_E~0); 279#L689-1true assume !(0 == ~T2_E~0); 663#L694-1true assume !(0 == ~T3_E~0); 278#L699-1true assume !(0 == ~T4_E~0); 431#L704-1true assume !(0 == ~T5_E~0); 240#L709-1true assume !(0 == ~T6_E~0); 199#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 399#L719-1true assume !(0 == ~E_1~0); 580#L724-1true assume !(0 == ~E_2~0); 66#L729-1true assume !(0 == ~E_3~0); 560#L734-1true assume !(0 == ~E_4~0); 487#L739-1true assume !(0 == ~E_5~0); 172#L744-1true assume !(0 == ~E_6~0); 401#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L334true assume !(1 == ~m_pc~0); 234#L334-2true is_master_triggered_~__retres1~0#1 := 0; 498#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63#L346true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156#L849true assume !(0 != activate_threads_~tmp~1#1); 363#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119#L353true assume 1 == ~t1_pc~0; 588#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 313#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71#L365true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 288#L857true assume !(0 != activate_threads_~tmp___0~0#1); 94#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 558#L372true assume !(1 == ~t2_pc~0); 162#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 230#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512#L384true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 473#L865true assume !(0 != activate_threads_~tmp___1~0#1); 41#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 449#L391true assume 1 == ~t3_pc~0; 572#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232#L403true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 392#L873true assume !(0 != activate_threads_~tmp___2~0#1); 159#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 469#L410true assume 1 == ~t4_pc~0; 587#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 368#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 540#L422true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475#L881true assume !(0 != activate_threads_~tmp___3~0#1); 164#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272#L429true assume !(1 == ~t5_pc~0); 68#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 650#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33#L441true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 336#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 359#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152#L448true assume 1 == ~t6_pc~0; 90#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 331#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 416#L460true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527#L897true assume !(0 != activate_threads_~tmp___5~0#1); 637#L897-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 630#L762true assume !(1 == ~M_E~0); 186#L762-2true assume !(1 == ~T1_E~0); 585#L767-1true assume !(1 == ~T2_E~0); 537#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 360#L777-1true assume !(1 == ~T4_E~0); 263#L782-1true assume !(1 == ~T5_E~0); 85#L787-1true assume !(1 == ~T6_E~0); 83#L792-1true assume !(1 == ~E_M~0); 105#L797-1true assume !(1 == ~E_1~0); 418#L802-1true assume !(1 == ~E_2~0); 237#L807-1true assume !(1 == ~E_3~0); 482#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 606#L817-1true assume !(1 == ~E_5~0); 280#L822-1true assume !(1 == ~E_6~0); 496#L827-1true assume { :end_inline_reset_delta_events } true; 157#L1053-2true [2021-12-19 19:15:54,578 INFO L793 eck$LassoCheckResult]: Loop: 157#L1053-2true assume !false; 472#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 549#L659true assume !true; 351#L674true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 314#L468-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 254#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 424#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 3#L689-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 184#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 29#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 345#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 478#L709-3true assume !(0 == ~T6_E~0); 323#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 179#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 26#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 304#L729-3true assume 0 == ~E_3~0;~E_3~0 := 1; 370#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 349#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 528#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 479#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32#L334-24true assume !(1 == ~m_pc~0); 104#L334-26true is_master_triggered_~__retres1~0#1 := 0; 318#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 656#L346-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 613#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L353-24true assume 1 == ~t1_pc~0; 380#L354-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 546#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 647#L365-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 574#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73#L372-24true assume !(1 == ~t2_pc~0); 555#L372-26true is_transmit2_triggered_~__retres1~2#1 := 0; 222#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95#L384-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 521#L865-24true assume !(0 != activate_threads_~tmp___1~0#1); 652#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201#L391-24true assume !(1 == ~t3_pc~0); 623#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 402#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484#L403-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 265#L873-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 246#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135#L410-24true assume 1 == ~t4_pc~0; 106#L411-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 374#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 400#L422-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132#L429-24true assume !(1 == ~t5_pc~0); 581#L429-26true is_transmit5_triggered_~__retres1~5#1 := 0; 373#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158#L441-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 108#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 215#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80#L448-24true assume 1 == ~t6_pc~0; 110#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 383#L460-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 503#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274#L897-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 494#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 243#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 567#L767-3true assume !(1 == ~T2_E~0); 660#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 69#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 636#L787-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 384#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 200#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 439#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 654#L807-3true assume !(1 == ~E_3~0); 300#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 490#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 394#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 376#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 213#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 377#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 238#L556-1true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 608#L1072true assume !(0 == start_simulation_~tmp~3#1); 144#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 486#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 36#L556-2true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 37#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 590#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 386#L1035true start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 397#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 157#L1053-2true [2021-12-19 19:15:54,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,582 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2021-12-19 19:15:54,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89947029] [2021-12-19 19:15:54,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89947029] [2021-12-19 19:15:54,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89947029] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,696 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406346484] [2021-12-19 19:15:54,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,700 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1046244752, now seen corresponding path program 1 times [2021-12-19 19:15:54,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966069182] [2021-12-19 19:15:54,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,722 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966069182] [2021-12-19 19:15:54,722 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966069182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,722 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,722 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:54,722 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667589119] [2021-12-19 19:15:54,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,723 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,724 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,745 INFO L87 Difference]: Start difference. First operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,787 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2021-12-19 19:15:54,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2021-12-19 19:15:54,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:54,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 681 states and 1019 transitions. [2021-12-19 19:15:54,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:54,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:54,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1019 transitions. [2021-12-19 19:15:54,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:54,809 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1019 transitions. [2021-12-19 19:15:54,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1019 transitions. [2021-12-19 19:15:54,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:54,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4963289280469898) internal successors, (1019), 680 states have internal predecessors, (1019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1019 transitions. [2021-12-19 19:15:54,846 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1019 transitions. [2021-12-19 19:15:54,846 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1019 transitions. [2021-12-19 19:15:54,846 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:15:54,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1019 transitions. [2021-12-19 19:15:54,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:54,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:54,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:54,860 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,860 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:54,861 INFO L791 eck$LassoCheckResult]: Stem: 2061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2033#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2016#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1566#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1567#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1882#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1883#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1811#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1615#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1616#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1547#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1548#L684 assume !(0 == ~M_E~0); 1984#L684-2 assume !(0 == ~T1_E~0); 1841#L689-1 assume !(0 == ~T2_E~0); 1842#L694-1 assume !(0 == ~T3_E~0); 1839#L699-1 assume !(0 == ~T4_E~0); 1840#L704-1 assume !(0 == ~T5_E~0); 1797#L709-1 assume !(0 == ~T6_E~0); 1742#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1743#L719-1 assume !(0 == ~E_1~0); 1961#L724-1 assume !(0 == ~E_2~0); 1519#L729-1 assume !(0 == ~E_3~0); 1520#L734-1 assume !(0 == ~E_4~0); 2013#L739-1 assume !(0 == ~E_5~0); 1702#L744-1 assume !(0 == ~E_6~0); 1703#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1480#L334 assume !(1 == ~m_pc~0); 1481#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1788#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1513#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1514#L849 assume !(0 != activate_threads_~tmp~1#1); 1676#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1610#L353 assume 1 == ~t1_pc~0; 1611#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1886#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1529#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1530#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1568#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569#L372 assume !(1 == ~t2_pc~0); 1663#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1662#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1782#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2004#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1467#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1468#L391 assume 1 == ~t3_pc~0; 1995#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1389#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1596#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1787#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1680#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1681#L410 assume 1 == ~t4_pc~0; 2003#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1903#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1935#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2005#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1690#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1691#L429 assume !(1 == ~t5_pc~0); 1523#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1524#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1454#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1455#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1909#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1671#L448 assume 1 == ~t6_pc~0; 1559#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1560#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1906#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1971#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2030#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2058#L762 assume !(1 == ~M_E~0); 1722#L762-2 assume !(1 == ~T1_E~0); 1723#L767-1 assume !(1 == ~T2_E~0); 2035#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1929#L777-1 assume !(1 == ~T4_E~0); 1824#L782-1 assume !(1 == ~T5_E~0); 1551#L787-1 assume !(1 == ~T6_E~0); 1549#L792-1 assume !(1 == ~E_M~0); 1550#L797-1 assume !(1 == ~E_1~0); 1587#L802-1 assume !(1 == ~E_2~0); 1793#L807-1 assume !(1 == ~E_3~0); 1794#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2009#L817-1 assume !(1 == ~E_5~0); 1845#L822-1 assume !(1 == ~E_6~0); 1846#L827-1 assume { :end_inline_reset_delta_events } true; 1678#L1053-2 [2021-12-19 19:15:54,861 INFO L793 eck$LassoCheckResult]: Loop: 1678#L1053-2 assume !false; 1679#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1391#L659 assume !false; 1641#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1642#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1644#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2062#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1953#L570 assume !(0 != eval_~tmp~0#1); 1921#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1887#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1816#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1817#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1382#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1383#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1442#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1443#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1914#L709-3 assume !(0 == ~T6_E~0); 1899#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1714#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1435#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1436#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1874#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1919#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1920#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2007#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1449#L334-24 assume 1 == ~m_pc~0; 1450#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1585#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1892#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1423#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1424#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1916#L353-24 assume 1 == ~t1_pc~0; 1917#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1946#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2036#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2046#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1471#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1472#L372-24 assume 1 == ~t2_pc~0; 1428#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1429#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1570#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1571#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 2024#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1747#L391-24 assume 1 == ~t3_pc~0; 1748#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1962#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1963#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1825#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1803#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1640#L410-24 assume 1 == ~t4_pc~0; 1586#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1516#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1937#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1686#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1545#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1546#L429-24 assume 1 == ~t5_pc~0; 1635#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1677#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1590#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1591#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1540#L448-24 assume !(1 == ~t6_pc~0); 1541#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1534#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1535#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1945#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1835#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1836#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1801#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1802#L767-3 assume !(1 == ~T2_E~0); 2042#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2032#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1525#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1526#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1947#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1744#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1745#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1986#L807-3 assume !(1 == ~E_3~0); 1868#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1869#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1956#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1941#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1765#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1426#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1791#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1792#L1072 assume !(0 == start_simulation_~tmp~3#1); 1654#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1655#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1536#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1456#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1457#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1458#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1949#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1950#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1678#L1053-2 [2021-12-19 19:15:54,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,862 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2021-12-19 19:15:54,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322253838] [2021-12-19 19:15:54,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322253838] [2021-12-19 19:15:54,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322253838] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102412862] [2021-12-19 19:15:54,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,895 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:54,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:54,896 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 1 times [2021-12-19 19:15:54,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:54,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375976275] [2021-12-19 19:15:54,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:54,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:54,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:54,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:54,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:54,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375976275] [2021-12-19 19:15:54,948 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375976275] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:54,948 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:54,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:54,948 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174073654] [2021-12-19 19:15:54,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:54,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:54,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:54,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:54,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:54,950 INFO L87 Difference]: Start difference. First operand 681 states and 1019 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:54,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:54,982 INFO L93 Difference]: Finished difference Result 681 states and 1018 transitions. [2021-12-19 19:15:54,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:54,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1018 transitions. [2021-12-19 19:15:54,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:54,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1018 transitions. [2021-12-19 19:15:54,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:54,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:54,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1018 transitions. [2021-12-19 19:15:55,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,001 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1018 transitions. [2021-12-19 19:15:55,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1018 transitions. [2021-12-19 19:15:55,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:55,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4948604992657857) internal successors, (1018), 680 states have internal predecessors, (1018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1018 transitions. [2021-12-19 19:15:55,017 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1018 transitions. [2021-12-19 19:15:55,017 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1018 transitions. [2021-12-19 19:15:55,017 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:15:55,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1018 transitions. [2021-12-19 19:15:55,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,021 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,021 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,021 INFO L791 eck$LassoCheckResult]: Stem: 3430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3402#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3385#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2933#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2934#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3251#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3252#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3180#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2985#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2914#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2915#L684 assume !(0 == ~M_E~0); 3353#L684-2 assume !(0 == ~T1_E~0); 3210#L689-1 assume !(0 == ~T2_E~0); 3211#L694-1 assume !(0 == ~T3_E~0); 3208#L699-1 assume !(0 == ~T4_E~0); 3209#L704-1 assume !(0 == ~T5_E~0); 3166#L709-1 assume !(0 == ~T6_E~0); 3111#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3112#L719-1 assume !(0 == ~E_1~0); 3330#L724-1 assume !(0 == ~E_2~0); 2888#L729-1 assume !(0 == ~E_3~0); 2889#L734-1 assume !(0 == ~E_4~0); 3382#L739-1 assume !(0 == ~E_5~0); 3071#L744-1 assume !(0 == ~E_6~0); 3072#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2849#L334 assume !(1 == ~m_pc~0); 2850#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3157#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2882#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2883#L849 assume !(0 != activate_threads_~tmp~1#1); 3045#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2979#L353 assume 1 == ~t1_pc~0; 2980#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3255#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2898#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2899#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2937#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2938#L372 assume !(1 == ~t2_pc~0); 3032#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3031#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3151#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3373#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2836#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2837#L391 assume 1 == ~t3_pc~0; 3363#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2756#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2965#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3155#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3049#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410 assume 1 == ~t4_pc~0; 3371#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3271#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3304#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3374#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3056#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3057#L429 assume !(1 == ~t5_pc~0); 2892#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2893#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2821#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2822#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3278#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3040#L448 assume 1 == ~t6_pc~0; 2928#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2929#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3275#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3340#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3399#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3427#L762 assume !(1 == ~M_E~0); 3091#L762-2 assume !(1 == ~T1_E~0); 3092#L767-1 assume !(1 == ~T2_E~0); 3404#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3298#L777-1 assume !(1 == ~T4_E~0); 3193#L782-1 assume !(1 == ~T5_E~0); 2920#L787-1 assume !(1 == ~T6_E~0); 2918#L792-1 assume !(1 == ~E_M~0); 2919#L797-1 assume !(1 == ~E_1~0); 2955#L802-1 assume !(1 == ~E_2~0); 3160#L807-1 assume !(1 == ~E_3~0); 3161#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3378#L817-1 assume !(1 == ~E_5~0); 3212#L822-1 assume !(1 == ~E_6~0); 3213#L827-1 assume { :end_inline_reset_delta_events } true; 3046#L1053-2 [2021-12-19 19:15:55,022 INFO L793 eck$LassoCheckResult]: Loop: 3046#L1053-2 assume !false; 3047#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2760#L659 assume !false; 3010#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3011#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3013#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3431#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3322#L570 assume !(0 != eval_~tmp~0#1); 3290#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3256#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3183#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3184#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2751#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2752#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2811#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2812#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3283#L709-3 assume !(0 == ~T6_E~0); 3266#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3080#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2804#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2805#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3243#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3288#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3289#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3376#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2818#L334-24 assume 1 == ~m_pc~0; 2819#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2954#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3261#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2790#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2791#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3285#L353-24 assume 1 == ~t1_pc~0; 3286#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3313#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3405#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3415#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2840#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2841#L372-24 assume 1 == ~t2_pc~0; 2797#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2798#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2939#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2940#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 3394#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3116#L391-24 assume 1 == ~t3_pc~0; 3117#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3331#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3195#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3174#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3009#L410-24 assume !(1 == ~t4_pc~0); 2884#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2885#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3306#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3055#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2916#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2917#L429-24 assume 1 == ~t5_pc~0; 3004#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3200#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3048#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2959#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2960#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2911#L448-24 assume !(1 == ~t6_pc~0); 2912#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2903#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2904#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3315#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3204#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3205#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3170#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3171#L767-3 assume !(1 == ~T2_E~0); 3411#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3401#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2894#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2895#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3316#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3113#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3114#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3355#L807-3 assume !(1 == ~E_3~0); 3237#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3238#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3325#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3310#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3134#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2795#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3162#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3163#L1072 assume !(0 == start_simulation_~tmp~3#1); 3023#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3024#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2905#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2827#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2828#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2829#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3318#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3319#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3046#L1053-2 [2021-12-19 19:15:55,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,023 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2021-12-19 19:15:55,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248423968] [2021-12-19 19:15:55,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,023 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248423968] [2021-12-19 19:15:55,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248423968] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,049 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000393865] [2021-12-19 19:15:55,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,049 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,050 INFO L85 PathProgramCache]: Analyzing trace with hash 590565595, now seen corresponding path program 1 times [2021-12-19 19:15:55,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693374696] [2021-12-19 19:15:55,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,050 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,084 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693374696] [2021-12-19 19:15:55,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693374696] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,085 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,085 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206884574] [2021-12-19 19:15:55,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,086 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,086 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:55,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:55,086 INFO L87 Difference]: Start difference. First operand 681 states and 1018 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,095 INFO L93 Difference]: Finished difference Result 681 states and 1017 transitions. [2021-12-19 19:15:55,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:55,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1017 transitions. [2021-12-19 19:15:55,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1017 transitions. [2021-12-19 19:15:55,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:55,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:55,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1017 transitions. [2021-12-19 19:15:55,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,115 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1017 transitions. [2021-12-19 19:15:55,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1017 transitions. [2021-12-19 19:15:55,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:55,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4933920704845816) internal successors, (1017), 680 states have internal predecessors, (1017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1017 transitions. [2021-12-19 19:15:55,123 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1017 transitions. [2021-12-19 19:15:55,124 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1017 transitions. [2021-12-19 19:15:55,124 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:15:55,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1017 transitions. [2021-12-19 19:15:55,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,128 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,129 INFO L791 eck$LassoCheckResult]: Stem: 4799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4771#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4754#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4302#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4303#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4620#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4621#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4549#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4353#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4354#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4283#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4284#L684 assume !(0 == ~M_E~0); 4722#L684-2 assume !(0 == ~T1_E~0); 4579#L689-1 assume !(0 == ~T2_E~0); 4580#L694-1 assume !(0 == ~T3_E~0); 4577#L699-1 assume !(0 == ~T4_E~0); 4578#L704-1 assume !(0 == ~T5_E~0); 4535#L709-1 assume !(0 == ~T6_E~0); 4480#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4481#L719-1 assume !(0 == ~E_1~0); 4699#L724-1 assume !(0 == ~E_2~0); 4257#L729-1 assume !(0 == ~E_3~0); 4258#L734-1 assume !(0 == ~E_4~0); 4751#L739-1 assume !(0 == ~E_5~0); 4440#L744-1 assume !(0 == ~E_6~0); 4441#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4218#L334 assume !(1 == ~m_pc~0); 4219#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4526#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4251#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4252#L849 assume !(0 != activate_threads_~tmp~1#1); 4414#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4348#L353 assume 1 == ~t1_pc~0; 4349#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4624#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4267#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4268#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4306#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4307#L372 assume !(1 == ~t2_pc~0); 4401#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4400#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4520#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4205#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4206#L391 assume 1 == ~t3_pc~0; 4732#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4125#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4334#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4524#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4418#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4419#L410 assume 1 == ~t4_pc~0; 4741#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4640#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4673#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4743#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4425#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4426#L429 assume !(1 == ~t5_pc~0); 4261#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4262#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4190#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4191#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4647#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4409#L448 assume 1 == ~t6_pc~0; 4297#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4298#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4644#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4709#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4768#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4796#L762 assume !(1 == ~M_E~0); 4460#L762-2 assume !(1 == ~T1_E~0); 4461#L767-1 assume !(1 == ~T2_E~0); 4773#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4667#L777-1 assume !(1 == ~T4_E~0); 4562#L782-1 assume !(1 == ~T5_E~0); 4289#L787-1 assume !(1 == ~T6_E~0); 4287#L792-1 assume !(1 == ~E_M~0); 4288#L797-1 assume !(1 == ~E_1~0); 4324#L802-1 assume !(1 == ~E_2~0); 4529#L807-1 assume !(1 == ~E_3~0); 4530#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4747#L817-1 assume !(1 == ~E_5~0); 4583#L822-1 assume !(1 == ~E_6~0); 4584#L827-1 assume { :end_inline_reset_delta_events } true; 4415#L1053-2 [2021-12-19 19:15:55,129 INFO L793 eck$LassoCheckResult]: Loop: 4415#L1053-2 assume !false; 4416#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4129#L659 assume !false; 4379#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4380#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4382#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4800#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4691#L570 assume !(0 != eval_~tmp~0#1); 4659#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4625#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4553#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4554#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4120#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4121#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4180#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4181#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4652#L709-3 assume !(0 == ~T6_E~0); 4635#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4449#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4173#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4174#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4612#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4657#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4658#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4745#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4187#L334-24 assume 1 == ~m_pc~0; 4188#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4323#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4630#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4159#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4160#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4654#L353-24 assume !(1 == ~t1_pc~0); 4656#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4682#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4774#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4784#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4209#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4210#L372-24 assume 1 == ~t2_pc~0; 4166#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4167#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4308#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4309#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 4763#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L391-24 assume 1 == ~t3_pc~0; 4486#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4700#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4701#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4564#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4543#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4378#L410-24 assume 1 == ~t4_pc~0; 4325#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4254#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4675#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4424#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4285#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4286#L429-24 assume 1 == ~t5_pc~0; 4373#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4569#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4417#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4328#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4329#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4280#L448-24 assume !(1 == ~t6_pc~0); 4281#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4272#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4273#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4684#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4573#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4574#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4539#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4540#L767-3 assume !(1 == ~T2_E~0); 4780#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4770#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4263#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4264#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4685#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4482#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4483#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4724#L807-3 assume !(1 == ~E_3~0); 4606#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4607#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4694#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4679#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4503#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4164#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4531#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4532#L1072 assume !(0 == start_simulation_~tmp~3#1); 4392#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4393#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4274#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4196#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4197#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4198#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4687#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4688#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L1053-2 [2021-12-19 19:15:55,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,130 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2021-12-19 19:15:55,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632680981] [2021-12-19 19:15:55,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,157 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632680981] [2021-12-19 19:15:55,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1632680981] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,158 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576503314] [2021-12-19 19:15:55,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,159 INFO L85 PathProgramCache]: Analyzing trace with hash 2040971931, now seen corresponding path program 1 times [2021-12-19 19:15:55,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109957927] [2021-12-19 19:15:55,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,185 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109957927] [2021-12-19 19:15:55,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109957927] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,186 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267325842] [2021-12-19 19:15:55,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,186 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,187 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:55,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:55,187 INFO L87 Difference]: Start difference. First operand 681 states and 1017 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,196 INFO L93 Difference]: Finished difference Result 681 states and 1016 transitions. [2021-12-19 19:15:55,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:55,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1016 transitions. [2021-12-19 19:15:55,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1016 transitions. [2021-12-19 19:15:55,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:55,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:55,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1016 transitions. [2021-12-19 19:15:55,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,203 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1016 transitions. [2021-12-19 19:15:55,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1016 transitions. [2021-12-19 19:15:55,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:55,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4919236417033774) internal successors, (1016), 680 states have internal predecessors, (1016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1016 transitions. [2021-12-19 19:15:55,223 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1016 transitions. [2021-12-19 19:15:55,223 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1016 transitions. [2021-12-19 19:15:55,223 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:15:55,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1016 transitions. [2021-12-19 19:15:55,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,227 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,227 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,227 INFO L791 eck$LassoCheckResult]: Stem: 6168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6140#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6123#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5673#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5674#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5989#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5990#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5918#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5722#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5723#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5654#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5655#L684 assume !(0 == ~M_E~0); 6091#L684-2 assume !(0 == ~T1_E~0); 5948#L689-1 assume !(0 == ~T2_E~0); 5949#L694-1 assume !(0 == ~T3_E~0); 5946#L699-1 assume !(0 == ~T4_E~0); 5947#L704-1 assume !(0 == ~T5_E~0); 5904#L709-1 assume !(0 == ~T6_E~0); 5849#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5850#L719-1 assume !(0 == ~E_1~0); 6068#L724-1 assume !(0 == ~E_2~0); 5626#L729-1 assume !(0 == ~E_3~0); 5627#L734-1 assume !(0 == ~E_4~0); 6120#L739-1 assume !(0 == ~E_5~0); 5809#L744-1 assume !(0 == ~E_6~0); 5810#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5587#L334 assume !(1 == ~m_pc~0); 5588#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5895#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5620#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5621#L849 assume !(0 != activate_threads_~tmp~1#1); 5783#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5717#L353 assume 1 == ~t1_pc~0; 5718#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5993#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5636#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5637#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5675#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5676#L372 assume !(1 == ~t2_pc~0); 5770#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5769#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5889#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6111#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5574#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5575#L391 assume 1 == ~t3_pc~0; 6102#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5496#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5703#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5894#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5787#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5788#L410 assume 1 == ~t4_pc~0; 6110#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6010#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6042#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6112#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5797#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5798#L429 assume !(1 == ~t5_pc~0); 5630#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5631#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5561#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5562#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6016#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5778#L448 assume 1 == ~t6_pc~0; 5666#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5667#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6078#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6137#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6165#L762 assume !(1 == ~M_E~0); 5829#L762-2 assume !(1 == ~T1_E~0); 5830#L767-1 assume !(1 == ~T2_E~0); 6142#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6036#L777-1 assume !(1 == ~T4_E~0); 5931#L782-1 assume !(1 == ~T5_E~0); 5658#L787-1 assume !(1 == ~T6_E~0); 5656#L792-1 assume !(1 == ~E_M~0); 5657#L797-1 assume !(1 == ~E_1~0); 5694#L802-1 assume !(1 == ~E_2~0); 5900#L807-1 assume !(1 == ~E_3~0); 5901#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6116#L817-1 assume !(1 == ~E_5~0); 5952#L822-1 assume !(1 == ~E_6~0); 5953#L827-1 assume { :end_inline_reset_delta_events } true; 5785#L1053-2 [2021-12-19 19:15:55,227 INFO L793 eck$LassoCheckResult]: Loop: 5785#L1053-2 assume !false; 5786#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5498#L659 assume !false; 5748#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5749#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5751#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6169#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6060#L570 assume !(0 != eval_~tmp~0#1); 6028#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5994#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5923#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5924#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5489#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5490#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5549#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5550#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6021#L709-3 assume !(0 == ~T6_E~0); 6006#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5821#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5542#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5543#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5981#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6026#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6027#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6114#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5556#L334-24 assume 1 == ~m_pc~0; 5557#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5692#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5999#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5530#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5531#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6022#L353-24 assume 1 == ~t1_pc~0; 6023#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6051#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6143#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6153#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5578#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5579#L372-24 assume !(1 == ~t2_pc~0); 5537#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5536#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5677#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5678#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 6131#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5854#L391-24 assume !(1 == ~t3_pc~0); 5856#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6069#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5932#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5910#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5747#L410-24 assume !(1 == ~t4_pc~0); 5622#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5623#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6044#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5793#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5652#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5653#L429-24 assume 1 == ~t5_pc~0; 5742#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5938#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5784#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5697#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5698#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5647#L448-24 assume !(1 == ~t6_pc~0); 5648#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 5641#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5642#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5942#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5908#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5909#L767-3 assume !(1 == ~T2_E~0); 6149#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6139#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5632#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5633#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6054#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5851#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5852#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6093#L807-3 assume !(1 == ~E_3~0); 5975#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5976#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6063#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6048#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5872#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5533#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5898#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5899#L1072 assume !(0 == start_simulation_~tmp~3#1); 5761#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5762#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5643#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5563#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5564#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5565#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6056#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6057#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5785#L1053-2 [2021-12-19 19:15:55,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2021-12-19 19:15:55,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326479281] [2021-12-19 19:15:55,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326479281] [2021-12-19 19:15:55,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326479281] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,245 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107484782] [2021-12-19 19:15:55,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,246 INFO L85 PathProgramCache]: Analyzing trace with hash -1270008291, now seen corresponding path program 1 times [2021-12-19 19:15:55,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375232558] [2021-12-19 19:15:55,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375232558] [2021-12-19 19:15:55,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375232558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,269 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,269 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,269 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537863264] [2021-12-19 19:15:55,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,270 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,270 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:55,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:55,271 INFO L87 Difference]: Start difference. First operand 681 states and 1016 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,279 INFO L93 Difference]: Finished difference Result 681 states and 1015 transitions. [2021-12-19 19:15:55,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:55,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1015 transitions. [2021-12-19 19:15:55,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1015 transitions. [2021-12-19 19:15:55,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:55,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:55,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1015 transitions. [2021-12-19 19:15:55,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,286 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1015 transitions. [2021-12-19 19:15:55,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1015 transitions. [2021-12-19 19:15:55,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:55,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4904552129221733) internal successors, (1015), 680 states have internal predecessors, (1015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1015 transitions. [2021-12-19 19:15:55,293 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1015 transitions. [2021-12-19 19:15:55,293 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1015 transitions. [2021-12-19 19:15:55,294 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:15:55,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1015 transitions. [2021-12-19 19:15:55,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,296 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,296 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,297 INFO L791 eck$LassoCheckResult]: Stem: 7537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7509#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7492#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7040#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7041#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7358#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7359#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7287#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7091#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7092#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7021#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7022#L684 assume !(0 == ~M_E~0); 7460#L684-2 assume !(0 == ~T1_E~0); 7317#L689-1 assume !(0 == ~T2_E~0); 7318#L694-1 assume !(0 == ~T3_E~0); 7315#L699-1 assume !(0 == ~T4_E~0); 7316#L704-1 assume !(0 == ~T5_E~0); 7273#L709-1 assume !(0 == ~T6_E~0); 7218#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7219#L719-1 assume !(0 == ~E_1~0); 7437#L724-1 assume !(0 == ~E_2~0); 6995#L729-1 assume !(0 == ~E_3~0); 6996#L734-1 assume !(0 == ~E_4~0); 7489#L739-1 assume !(0 == ~E_5~0); 7178#L744-1 assume !(0 == ~E_6~0); 7179#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6956#L334 assume !(1 == ~m_pc~0); 6957#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7264#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6989#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6990#L849 assume !(0 != activate_threads_~tmp~1#1); 7152#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7086#L353 assume 1 == ~t1_pc~0; 7087#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7362#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7005#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7006#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7044#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7045#L372 assume !(1 == ~t2_pc~0); 7139#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7138#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7258#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7480#L865 assume !(0 != activate_threads_~tmp___1~0#1); 6943#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6944#L391 assume 1 == ~t3_pc~0; 7470#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6863#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7072#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7262#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7156#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7157#L410 assume 1 == ~t4_pc~0; 7478#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7378#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7411#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7481#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7163#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7164#L429 assume !(1 == ~t5_pc~0); 6999#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7000#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6928#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6929#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7385#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7147#L448 assume 1 == ~t6_pc~0; 7035#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7036#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7382#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7447#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7506#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7534#L762 assume !(1 == ~M_E~0); 7198#L762-2 assume !(1 == ~T1_E~0); 7199#L767-1 assume !(1 == ~T2_E~0); 7511#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7405#L777-1 assume !(1 == ~T4_E~0); 7300#L782-1 assume !(1 == ~T5_E~0); 7027#L787-1 assume !(1 == ~T6_E~0); 7025#L792-1 assume !(1 == ~E_M~0); 7026#L797-1 assume !(1 == ~E_1~0); 7062#L802-1 assume !(1 == ~E_2~0); 7267#L807-1 assume !(1 == ~E_3~0); 7268#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7485#L817-1 assume !(1 == ~E_5~0); 7319#L822-1 assume !(1 == ~E_6~0); 7320#L827-1 assume { :end_inline_reset_delta_events } true; 7153#L1053-2 [2021-12-19 19:15:55,297 INFO L793 eck$LassoCheckResult]: Loop: 7153#L1053-2 assume !false; 7154#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6867#L659 assume !false; 7117#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7118#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7120#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7538#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7429#L570 assume !(0 != eval_~tmp~0#1); 7397#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7363#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7290#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7291#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6858#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6859#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6918#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6919#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7390#L709-3 assume !(0 == ~T6_E~0); 7373#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7187#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6911#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6912#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7350#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7395#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7396#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7483#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6925#L334-24 assume 1 == ~m_pc~0; 6926#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7061#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7368#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6897#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6898#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7392#L353-24 assume 1 == ~t1_pc~0; 7393#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7420#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7512#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7522#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6947#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6948#L372-24 assume 1 == ~t2_pc~0; 6904#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6905#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7046#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7047#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 7501#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7223#L391-24 assume 1 == ~t3_pc~0; 7224#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7438#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7439#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7302#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7281#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7116#L410-24 assume 1 == ~t4_pc~0; 7063#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6992#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7413#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7162#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7023#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7024#L429-24 assume 1 == ~t5_pc~0; 7111#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7307#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7155#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7066#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7067#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7018#L448-24 assume !(1 == ~t6_pc~0); 7019#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7010#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7011#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7422#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7311#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7312#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7277#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7278#L767-3 assume !(1 == ~T2_E~0); 7518#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7508#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7001#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7002#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7423#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7220#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7221#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7462#L807-3 assume !(1 == ~E_3~0); 7344#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7345#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7432#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7417#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7241#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6902#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7269#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7270#L1072 assume !(0 == start_simulation_~tmp~3#1); 7130#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7131#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6934#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 6935#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6936#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7425#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7426#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7153#L1053-2 [2021-12-19 19:15:55,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,298 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2021-12-19 19:15:55,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785870714] [2021-12-19 19:15:55,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,313 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785870714] [2021-12-19 19:15:55,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785870714] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,313 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,313 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,313 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [849501607] [2021-12-19 19:15:55,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,314 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 2 times [2021-12-19 19:15:55,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957692490] [2021-12-19 19:15:55,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957692490] [2021-12-19 19:15:55,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957692490] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268156352] [2021-12-19 19:15:55,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:55,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:55,335 INFO L87 Difference]: Start difference. First operand 681 states and 1015 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,344 INFO L93 Difference]: Finished difference Result 681 states and 1014 transitions. [2021-12-19 19:15:55,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:55,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1014 transitions. [2021-12-19 19:15:55,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1014 transitions. [2021-12-19 19:15:55,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2021-12-19 19:15:55,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2021-12-19 19:15:55,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1014 transitions. [2021-12-19 19:15:55,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,350 INFO L681 BuchiCegarLoop]: Abstraction has 681 states and 1014 transitions. [2021-12-19 19:15:55,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1014 transitions. [2021-12-19 19:15:55,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2021-12-19 19:15:55,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4889867841409692) internal successors, (1014), 680 states have internal predecessors, (1014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1014 transitions. [2021-12-19 19:15:55,357 INFO L704 BuchiCegarLoop]: Abstraction has 681 states and 1014 transitions. [2021-12-19 19:15:55,358 INFO L587 BuchiCegarLoop]: Abstraction has 681 states and 1014 transitions. [2021-12-19 19:15:55,358 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:15:55,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1014 transitions. [2021-12-19 19:15:55,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2021-12-19 19:15:55,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,360 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,361 INFO L791 eck$LassoCheckResult]: Stem: 8906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8878#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8861#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8409#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8410#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8727#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8728#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8656#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8460#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8461#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8390#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8391#L684 assume !(0 == ~M_E~0); 8829#L684-2 assume !(0 == ~T1_E~0); 8686#L689-1 assume !(0 == ~T2_E~0); 8687#L694-1 assume !(0 == ~T3_E~0); 8684#L699-1 assume !(0 == ~T4_E~0); 8685#L704-1 assume !(0 == ~T5_E~0); 8642#L709-1 assume !(0 == ~T6_E~0); 8587#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8588#L719-1 assume !(0 == ~E_1~0); 8806#L724-1 assume !(0 == ~E_2~0); 8364#L729-1 assume !(0 == ~E_3~0); 8365#L734-1 assume !(0 == ~E_4~0); 8858#L739-1 assume !(0 == ~E_5~0); 8547#L744-1 assume !(0 == ~E_6~0); 8548#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8325#L334 assume !(1 == ~m_pc~0); 8326#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8633#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8358#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8359#L849 assume !(0 != activate_threads_~tmp~1#1); 8521#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8455#L353 assume 1 == ~t1_pc~0; 8456#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8731#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8374#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8375#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8413#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8414#L372 assume !(1 == ~t2_pc~0); 8508#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8507#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8627#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8849#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8312#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8313#L391 assume 1 == ~t3_pc~0; 8839#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8232#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8441#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8631#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8525#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8526#L410 assume 1 == ~t4_pc~0; 8848#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8747#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8780#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8850#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8532#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8533#L429 assume !(1 == ~t5_pc~0); 8368#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8369#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8297#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8298#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8754#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8516#L448 assume 1 == ~t6_pc~0; 8404#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8405#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8751#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8816#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8875#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8903#L762 assume !(1 == ~M_E~0); 8567#L762-2 assume !(1 == ~T1_E~0); 8568#L767-1 assume !(1 == ~T2_E~0); 8880#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8774#L777-1 assume !(1 == ~T4_E~0); 8669#L782-1 assume !(1 == ~T5_E~0); 8396#L787-1 assume !(1 == ~T6_E~0); 8394#L792-1 assume !(1 == ~E_M~0); 8395#L797-1 assume !(1 == ~E_1~0); 8431#L802-1 assume !(1 == ~E_2~0); 8636#L807-1 assume !(1 == ~E_3~0); 8637#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8854#L817-1 assume !(1 == ~E_5~0); 8690#L822-1 assume !(1 == ~E_6~0); 8691#L827-1 assume { :end_inline_reset_delta_events } true; 8522#L1053-2 [2021-12-19 19:15:55,361 INFO L793 eck$LassoCheckResult]: Loop: 8522#L1053-2 assume !false; 8523#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8236#L659 assume !false; 8486#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8487#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8489#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8907#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8798#L570 assume !(0 != eval_~tmp~0#1); 8766#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8732#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8660#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8661#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8227#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8228#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8287#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8288#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8759#L709-3 assume !(0 == ~T6_E~0); 8742#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8556#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8280#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8281#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8719#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8764#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8765#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8852#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8294#L334-24 assume 1 == ~m_pc~0; 8295#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8430#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8737#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8266#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8267#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8761#L353-24 assume 1 == ~t1_pc~0; 8762#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8789#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8881#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8891#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8316#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8317#L372-24 assume 1 == ~t2_pc~0; 8273#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8274#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8416#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 8870#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8592#L391-24 assume 1 == ~t3_pc~0; 8593#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8807#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8671#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8650#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8485#L410-24 assume 1 == ~t4_pc~0; 8432#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8361#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8782#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8531#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8392#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8393#L429-24 assume 1 == ~t5_pc~0; 8480#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8676#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8524#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8435#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8436#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8387#L448-24 assume !(1 == ~t6_pc~0); 8388#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8379#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8380#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8791#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8680#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8681#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8646#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8647#L767-3 assume !(1 == ~T2_E~0); 8887#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8877#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8370#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8371#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8792#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8589#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8590#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8831#L807-3 assume !(1 == ~E_3~0); 8713#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8714#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8801#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8786#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8610#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8271#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8638#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8639#L1072 assume !(0 == start_simulation_~tmp~3#1); 8499#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8500#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8381#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8303#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8304#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8305#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8794#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8795#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8522#L1053-2 [2021-12-19 19:15:55,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,362 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2021-12-19 19:15:55,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867818444] [2021-12-19 19:15:55,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,362 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867818444] [2021-12-19 19:15:55,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867818444] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,383 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,383 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798352177] [2021-12-19 19:15:55,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,384 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 3 times [2021-12-19 19:15:55,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195148387] [2021-12-19 19:15:55,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195148387] [2021-12-19 19:15:55,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195148387] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,411 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,411 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,411 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51713702] [2021-12-19 19:15:55,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:55,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:55,413 INFO L87 Difference]: Start difference. First operand 681 states and 1014 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,496 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2021-12-19 19:15:55,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:55,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2021-12-19 19:15:55,502 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2021-12-19 19:15:55,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2021-12-19 19:15:55,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-19 19:15:55,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-19 19:15:55,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2021-12-19 19:15:55,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,508 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-19 19:15:55,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2021-12-19 19:15:55,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1169. [2021-12-19 19:15:55,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1169 states, 1169 states have (on average 1.485885372112917) internal successors, (1737), 1168 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1737 transitions. [2021-12-19 19:15:55,521 INFO L704 BuchiCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2021-12-19 19:15:55,521 INFO L587 BuchiCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2021-12-19 19:15:55,521 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:15:55,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1169 states and 1737 transitions. [2021-12-19 19:15:55,525 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2021-12-19 19:15:55,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,526 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,526 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,526 INFO L791 eck$LassoCheckResult]: Stem: 10804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10780#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10771#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10752#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10270#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10271#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10594#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10595#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10521#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10321#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10322#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10251#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10252#L684 assume !(0 == ~M_E~0); 10711#L684-2 assume !(0 == ~T1_E~0); 10552#L689-1 assume !(0 == ~T2_E~0); 10553#L694-1 assume !(0 == ~T3_E~0); 10550#L699-1 assume !(0 == ~T4_E~0); 10551#L704-1 assume !(0 == ~T5_E~0); 10506#L709-1 assume !(0 == ~T6_E~0); 10450#L714-1 assume !(0 == ~E_M~0); 10451#L719-1 assume !(0 == ~E_1~0); 10683#L724-1 assume !(0 == ~E_2~0); 10225#L729-1 assume !(0 == ~E_3~0); 10226#L734-1 assume !(0 == ~E_4~0); 10748#L739-1 assume !(0 == ~E_5~0); 10409#L744-1 assume !(0 == ~E_6~0); 10410#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10186#L334 assume !(1 == ~m_pc~0); 10187#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10497#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10219#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10220#L849 assume !(0 != activate_threads_~tmp~1#1); 10382#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10316#L353 assume 1 == ~t1_pc~0; 10317#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10600#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10235#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10236#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10274#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10275#L372 assume !(1 == ~t2_pc~0); 10369#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10368#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10491#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10738#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10173#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10174#L391 assume 1 == ~t3_pc~0; 10724#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10093#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10302#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10495#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10387#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10388#L410 assume 1 == ~t4_pc~0; 10735#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10618#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10652#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10739#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10394#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10395#L429 assume !(1 == ~t5_pc~0); 10229#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10230#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10158#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10159#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10625#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10377#L448 assume 1 == ~t6_pc~0; 10265#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10266#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10622#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10694#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10767#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10798#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10429#L762-2 assume !(1 == ~T1_E~0); 10430#L767-1 assume !(1 == ~T2_E~0); 10773#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10646#L777-1 assume !(1 == ~T4_E~0); 10534#L782-1 assume !(1 == ~T5_E~0); 10257#L787-1 assume !(1 == ~T6_E~0); 10255#L792-1 assume !(1 == ~E_M~0); 10256#L797-1 assume !(1 == ~E_1~0); 10292#L802-1 assume !(1 == ~E_2~0); 10500#L807-1 assume !(1 == ~E_3~0); 10501#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10744#L817-1 assume !(1 == ~E_5~0); 10795#L822-1 assume !(1 == ~E_6~0); 10753#L827-1 assume { :end_inline_reset_delta_events } true; 10383#L1053-2 [2021-12-19 19:15:55,527 INFO L793 eck$LassoCheckResult]: Loop: 10383#L1053-2 assume !false; 10384#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10824#L659 assume !false; 10823#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10821#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10815#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10814#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10812#L570 assume !(0 != eval_~tmp~0#1); 10811#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10810#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10808#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10809#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11168#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11167#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11166#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11165#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11164#L709-3 assume !(0 == ~T6_E~0); 11163#L714-3 assume !(0 == ~E_M~0); 11162#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11161#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10585#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10586#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10653#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11155#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10742#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10155#L334-24 assume 1 == ~m_pc~0; 10156#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10291#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11125#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11124#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11123#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11122#L353-24 assume !(1 == ~t1_pc~0); 11120#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11119#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11118#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11117#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11116#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11114#L372-24 assume 1 == ~t2_pc~0; 11110#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11108#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11106#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11097#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 10802#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10455#L391-24 assume 1 == ~t3_pc~0; 10456#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10684#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10685#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10536#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10514#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10346#L410-24 assume 1 == ~t4_pc~0; 10293#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10222#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10656#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10393#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10253#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10254#L429-24 assume 1 == ~t5_pc~0; 10341#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10542#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10655#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10296#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10297#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10248#L448-24 assume !(1 == ~t6_pc~0); 10249#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10240#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10241#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10666#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10546#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10547#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10751#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11059#L767-3 assume !(1 == ~T2_E~0); 11057#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11055#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11053#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11051#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11048#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10668#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11045#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11043#L807-3 assume !(1 == ~E_3~0); 11041#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11039#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11035#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11022#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10473#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10132#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10502#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10503#L1072 assume !(0 == start_simulation_~tmp~3#1); 10360#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10361#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10242#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10164#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10165#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10166#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10670#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10671#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10383#L1053-2 [2021-12-19 19:15:55,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2021-12-19 19:15:55,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693094003] [2021-12-19 19:15:55,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,528 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693094003] [2021-12-19 19:15:55,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693094003] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:55,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773447610] [2021-12-19 19:15:55,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,546 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,547 INFO L85 PathProgramCache]: Analyzing trace with hash 2068037533, now seen corresponding path program 1 times [2021-12-19 19:15:55,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942901560] [2021-12-19 19:15:55,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,547 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942901560] [2021-12-19 19:15:55,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942901560] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,566 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421477524] [2021-12-19 19:15:55,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,567 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:55,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:55,568 INFO L87 Difference]: Start difference. First operand 1169 states and 1737 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,610 INFO L93 Difference]: Finished difference Result 2112 states and 3111 transitions. [2021-12-19 19:15:55,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:55,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2112 states and 3111 transitions. [2021-12-19 19:15:55,619 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2006 [2021-12-19 19:15:55,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2112 states to 2112 states and 3111 transitions. [2021-12-19 19:15:55,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2112 [2021-12-19 19:15:55,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2112 [2021-12-19 19:15:55,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2112 states and 3111 transitions. [2021-12-19 19:15:55,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,629 INFO L681 BuchiCegarLoop]: Abstraction has 2112 states and 3111 transitions. [2021-12-19 19:15:55,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2112 states and 3111 transitions. [2021-12-19 19:15:55,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2112 to 2108. [2021-12-19 19:15:55,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2108 states, 2108 states have (on average 1.473908918406072) internal successors, (3107), 2107 states have internal predecessors, (3107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2108 states to 2108 states and 3107 transitions. [2021-12-19 19:15:55,655 INFO L704 BuchiCegarLoop]: Abstraction has 2108 states and 3107 transitions. [2021-12-19 19:15:55,655 INFO L587 BuchiCegarLoop]: Abstraction has 2108 states and 3107 transitions. [2021-12-19 19:15:55,655 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:15:55,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2108 states and 3107 transitions. [2021-12-19 19:15:55,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2002 [2021-12-19 19:15:55,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,662 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,662 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,662 INFO L791 eck$LassoCheckResult]: Stem: 14145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 14101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14084#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14064#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13560#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 13561#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13898#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13899#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13822#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13608#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13609#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13541#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13542#L684 assume !(0 == ~M_E~0); 14017#L684-2 assume !(0 == ~T1_E~0); 13855#L689-1 assume !(0 == ~T2_E~0); 13856#L694-1 assume !(0 == ~T3_E~0); 13853#L699-1 assume !(0 == ~T4_E~0); 13854#L704-1 assume !(0 == ~T5_E~0); 13808#L709-1 assume !(0 == ~T6_E~0); 13745#L714-1 assume !(0 == ~E_M~0); 13746#L719-1 assume !(0 == ~E_1~0); 13992#L724-1 assume !(0 == ~E_2~0); 13513#L729-1 assume !(0 == ~E_3~0); 13514#L734-1 assume !(0 == ~E_4~0); 14060#L739-1 assume !(0 == ~E_5~0); 13700#L744-1 assume !(0 == ~E_6~0); 13701#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13473#L334 assume !(1 == ~m_pc~0); 13474#L334-2 is_master_triggered_~__retres1~0#1 := 0; 13798#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13507#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13508#L849 assume !(0 != activate_threads_~tmp~1#1); 13674#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13604#L353 assume !(1 == ~t1_pc~0); 13605#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13903#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13523#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13524#L857 assume !(0 != activate_threads_~tmp___0~0#1); 13562#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13563#L372 assume !(1 == ~t2_pc~0); 13658#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13657#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13791#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14046#L865 assume !(0 != activate_threads_~tmp___1~0#1); 13462#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13463#L391 assume 1 == ~t3_pc~0; 14032#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13383#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13590#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13797#L873 assume !(0 != activate_threads_~tmp___2~0#1); 13678#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13679#L410 assume 1 == ~t4_pc~0; 14043#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13923#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13962#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14047#L881 assume !(0 != activate_threads_~tmp___3~0#1); 13688#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13689#L429 assume !(1 == ~t5_pc~0); 13517#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13518#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13447#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13448#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13932#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13667#L448 assume 1 == ~t6_pc~0; 13553#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13554#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13928#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14002#L897 assume !(0 != activate_threads_~tmp___5~0#1); 14081#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14135#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 13725#L762-2 assume !(1 == ~T1_E~0); 13726#L767-1 assume !(1 == ~T2_E~0); 14087#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13954#L777-1 assume !(1 == ~T4_E~0); 13836#L782-1 assume !(1 == ~T5_E~0); 13545#L787-1 assume !(1 == ~T6_E~0); 13543#L792-1 assume !(1 == ~E_M~0); 13544#L797-1 assume !(1 == ~E_1~0); 13581#L802-1 assume !(1 == ~E_2~0); 13804#L807-1 assume !(1 == ~E_3~0); 13805#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14054#L817-1 assume !(1 == ~E_5~0); 13859#L822-1 assume !(1 == ~E_6~0); 13860#L827-1 assume { :end_inline_reset_delta_events } true; 13676#L1053-2 [2021-12-19 19:15:55,662 INFO L793 eck$LassoCheckResult]: Loop: 13676#L1053-2 assume !false; 13677#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14093#L659 assume !false; 14094#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13930#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13639#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14146#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13981#L570 assume !(0 != eval_~tmp~0#1); 13946#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13904#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13905#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14565#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14860#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14859#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14858#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14857#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14856#L709-3 assume !(0 == ~T6_E~0); 14855#L714-3 assume !(0 == ~E_M~0); 14854#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14853#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14852#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14851#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14850#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14849#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14848#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14847#L334-24 assume 1 == ~m_pc~0; 14845#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14844#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14843#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14842#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14841#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14840#L353-24 assume !(1 == ~t1_pc~0); 14839#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 14838#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14837#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14836#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14835#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14834#L372-24 assume 1 == ~t2_pc~0; 14832#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14831#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14830#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14829#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 14828#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14827#L391-24 assume 1 == ~t3_pc~0; 14825#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14824#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14823#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14822#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14821#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14820#L410-24 assume !(1 == ~t4_pc~0); 14818#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14817#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14816#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14815#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14814#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14813#L429-24 assume 1 == ~t5_pc~0; 14811#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14810#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14809#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14808#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14807#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14806#L448-24 assume !(1 == ~t6_pc~0); 14804#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 14803#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14802#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14801#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14800#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14799#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14466#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14798#L767-3 assume !(1 == ~T2_E~0); 14797#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14796#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14795#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14794#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14793#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14288#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14792#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14791#L807-3 assume !(1 == ~E_3~0); 14790#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14789#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14788#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14787#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14737#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14731#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14159#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14158#L1072 assume !(0 == start_simulation_~tmp~3#1); 13649#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13650#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14687#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14686#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 14685#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14684#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14683#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14682#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 13676#L1053-2 [2021-12-19 19:15:55,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,663 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2021-12-19 19:15:55,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101647403] [2021-12-19 19:15:55,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,682 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101647403] [2021-12-19 19:15:55,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101647403] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,683 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,683 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647095024] [2021-12-19 19:15:55,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,683 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1194559838, now seen corresponding path program 1 times [2021-12-19 19:15:55,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171836681] [2021-12-19 19:15:55,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,701 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171836681] [2021-12-19 19:15:55,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171836681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,702 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,702 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269398176] [2021-12-19 19:15:55,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,702 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,702 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:55,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:55,703 INFO L87 Difference]: Start difference. First operand 2108 states and 3107 transitions. cyclomatic complexity: 1003 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:55,814 INFO L93 Difference]: Finished difference Result 4817 states and 7027 transitions. [2021-12-19 19:15:55,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:55,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4817 states and 7027 transitions. [2021-12-19 19:15:55,831 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4696 [2021-12-19 19:15:55,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4817 states to 4817 states and 7027 transitions. [2021-12-19 19:15:55,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4817 [2021-12-19 19:15:55,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4817 [2021-12-19 19:15:55,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4817 states and 7027 transitions. [2021-12-19 19:15:55,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:55,853 INFO L681 BuchiCegarLoop]: Abstraction has 4817 states and 7027 transitions. [2021-12-19 19:15:55,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4817 states and 7027 transitions. [2021-12-19 19:15:55,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4817 to 3871. [2021-12-19 19:15:55,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3871 states, 3871 states have (on average 1.4652544562128649) internal successors, (5672), 3870 states have internal predecessors, (5672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:55,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3871 states to 3871 states and 5672 transitions. [2021-12-19 19:15:55,896 INFO L704 BuchiCegarLoop]: Abstraction has 3871 states and 5672 transitions. [2021-12-19 19:15:55,896 INFO L587 BuchiCegarLoop]: Abstraction has 3871 states and 5672 transitions. [2021-12-19 19:15:55,896 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:15:55,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3871 states and 5672 transitions. [2021-12-19 19:15:55,904 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3764 [2021-12-19 19:15:55,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:55,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:55,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,905 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:55,906 INFO L791 eck$LassoCheckResult]: Stem: 21070#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 21027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21011#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20989#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20497#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 20498#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20822#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20823#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20746#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20546#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20547#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20477#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20478#L684 assume !(0 == ~M_E~0); 20946#L684-2 assume !(0 == ~T1_E~0); 20780#L689-1 assume !(0 == ~T2_E~0); 20781#L694-1 assume !(0 == ~T3_E~0); 20778#L699-1 assume !(0 == ~T4_E~0); 20779#L704-1 assume !(0 == ~T5_E~0); 20734#L709-1 assume !(0 == ~T6_E~0); 20680#L714-1 assume !(0 == ~E_M~0); 20681#L719-1 assume !(0 == ~E_1~0); 20915#L724-1 assume !(0 == ~E_2~0); 20449#L729-1 assume !(0 == ~E_3~0); 20450#L734-1 assume !(0 == ~E_4~0); 20985#L739-1 assume !(0 == ~E_5~0); 20636#L744-1 assume !(0 == ~E_6~0); 20637#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20408#L334 assume !(1 == ~m_pc~0); 20409#L334-2 is_master_triggered_~__retres1~0#1 := 0; 20724#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20443#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20444#L849 assume !(0 != activate_threads_~tmp~1#1); 20610#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20542#L353 assume !(1 == ~t1_pc~0); 20543#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20826#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20459#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20460#L857 assume !(0 != activate_threads_~tmp___0~0#1); 20499#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20500#L372 assume !(1 == ~t2_pc~0); 20595#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20594#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20718#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20972#L865 assume !(0 != activate_threads_~tmp___1~0#1); 20397#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20398#L391 assume !(1 == ~t3_pc~0); 20317#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20318#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20528#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20723#L873 assume !(0 != activate_threads_~tmp___2~0#1); 20614#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20615#L410 assume 1 == ~t4_pc~0; 20971#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20843#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20880#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20976#L881 assume !(0 != activate_threads_~tmp___3~0#1); 20624#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20625#L429 assume !(1 == ~t5_pc~0); 20453#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20454#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20382#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20383#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20849#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20605#L448 assume 1 == ~t6_pc~0; 20490#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20491#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20847#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20927#L897 assume !(0 != activate_threads_~tmp___5~0#1); 21008#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21057#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 20660#L762-2 assume !(1 == ~T1_E~0); 20661#L767-1 assume !(1 == ~T2_E~0); 21013#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21014#L777-1 assume !(1 == ~T4_E~0); 20759#L782-1 assume !(1 == ~T5_E~0); 20760#L787-1 assume !(1 == ~T6_E~0); 20479#L792-1 assume !(1 == ~E_M~0); 20480#L797-1 assume !(1 == ~E_1~0); 20929#L802-1 assume !(1 == ~E_2~0); 20930#L807-1 assume !(1 == ~E_3~0); 20982#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20983#L817-1 assume !(1 == ~E_5~0); 20784#L822-1 assume !(1 == ~E_6~0); 20785#L827-1 assume { :end_inline_reset_delta_events } true; 23701#L1053-2 [2021-12-19 19:15:55,906 INFO L793 eck$LassoCheckResult]: Loop: 23701#L1053-2 assume !false; 23689#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23686#L659 assume !false; 23683#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23678#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23667#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 21071#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20905#L570 assume !(0 != eval_~tmp~0#1); 20906#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23934#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23933#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23932#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23931#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23930#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23929#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23928#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23927#L709-3 assume !(0 == ~T6_E~0); 23925#L714-3 assume !(0 == ~E_M~0); 23922#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23920#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23918#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23916#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23914#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23912#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23910#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23908#L334-24 assume 1 == ~m_pc~0; 23905#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23903#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23901#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23899#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23896#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23894#L353-24 assume !(1 == ~t1_pc~0); 23892#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 23890#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23888#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23886#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23885#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23883#L372-24 assume 1 == ~t2_pc~0; 23880#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23878#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23876#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23874#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 23871#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23869#L391-24 assume !(1 == ~t3_pc~0); 23128#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 23866#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23864#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23862#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23859#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23857#L410-24 assume !(1 == ~t4_pc~0); 23854#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 23852#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23850#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23848#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23847#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23846#L429-24 assume 1 == ~t5_pc~0; 23844#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23843#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23842#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23841#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23840#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23839#L448-24 assume !(1 == ~t6_pc~0); 23837#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 23835#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23833#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23831#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23829#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23827#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20988#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23823#L767-3 assume !(1 == ~T2_E~0); 23821#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23819#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23817#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23815#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23812#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20897#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23809#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23807#L807-3 assume !(1 == ~E_3~0); 23805#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23803#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23800#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23798#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23791#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23784#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23782#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 23781#L1072 assume !(0 == start_simulation_~tmp~3#1); 21015#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23750#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23734#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23732#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 23730#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23728#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23716#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 23710#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 23701#L1053-2 [2021-12-19 19:15:55,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,907 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2021-12-19 19:15:55,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714859621] [2021-12-19 19:15:55,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,925 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714859621] [2021-12-19 19:15:55,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714859621] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,926 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,926 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180370467] [2021-12-19 19:15:55,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,926 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:55,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:55,927 INFO L85 PathProgramCache]: Analyzing trace with hash -906281377, now seen corresponding path program 1 times [2021-12-19 19:15:55,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:55,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408215839] [2021-12-19 19:15:55,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:55,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:55,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:55,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:55,945 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:55,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408215839] [2021-12-19 19:15:55,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408215839] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:55,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:55,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:55,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496449403] [2021-12-19 19:15:55,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:55,946 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:55,946 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:55,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:55,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:55,946 INFO L87 Difference]: Start difference. First operand 3871 states and 5672 transitions. cyclomatic complexity: 1805 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:56,065 INFO L93 Difference]: Finished difference Result 8888 states and 12913 transitions. [2021-12-19 19:15:56,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:56,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8888 states and 12913 transitions. [2021-12-19 19:15:56,126 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8750 [2021-12-19 19:15:56,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8888 states to 8888 states and 12913 transitions. [2021-12-19 19:15:56,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8888 [2021-12-19 19:15:56,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8888 [2021-12-19 19:15:56,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8888 states and 12913 transitions. [2021-12-19 19:15:56,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:56,164 INFO L681 BuchiCegarLoop]: Abstraction has 8888 states and 12913 transitions. [2021-12-19 19:15:56,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8888 states and 12913 transitions. [2021-12-19 19:15:56,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8888 to 7166. [2021-12-19 19:15:56,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7166 states, 7166 states have (on average 1.4586938319843707) internal successors, (10453), 7165 states have internal predecessors, (10453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7166 states to 7166 states and 10453 transitions. [2021-12-19 19:15:56,244 INFO L704 BuchiCegarLoop]: Abstraction has 7166 states and 10453 transitions. [2021-12-19 19:15:56,244 INFO L587 BuchiCegarLoop]: Abstraction has 7166 states and 10453 transitions. [2021-12-19 19:15:56,244 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:15:56,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7166 states and 10453 transitions. [2021-12-19 19:15:56,262 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7056 [2021-12-19 19:15:56,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:56,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:56,263 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,263 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,263 INFO L791 eck$LassoCheckResult]: Stem: 33850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 33806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 33787#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33763#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33262#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 33263#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33596#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33597#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33523#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33314#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33315#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33243#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33244#L684 assume !(0 == ~M_E~0); 33719#L684-2 assume !(0 == ~T1_E~0); 33556#L689-1 assume !(0 == ~T2_E~0); 33557#L694-1 assume !(0 == ~T3_E~0); 33554#L699-1 assume !(0 == ~T4_E~0); 33555#L704-1 assume !(0 == ~T5_E~0); 33509#L709-1 assume !(0 == ~T6_E~0); 33450#L714-1 assume !(0 == ~E_M~0); 33451#L719-1 assume !(0 == ~E_1~0); 33691#L724-1 assume !(0 == ~E_2~0); 33217#L729-1 assume !(0 == ~E_3~0); 33218#L734-1 assume !(0 == ~E_4~0); 33757#L739-1 assume !(0 == ~E_5~0); 33403#L744-1 assume !(0 == ~E_6~0); 33404#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33177#L334 assume !(1 == ~m_pc~0); 33178#L334-2 is_master_triggered_~__retres1~0#1 := 0; 33500#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33211#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33212#L849 assume !(0 != activate_threads_~tmp~1#1); 33377#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33310#L353 assume !(1 == ~t1_pc~0); 33311#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33600#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33227#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33228#L857 assume !(0 != activate_threads_~tmp___0~0#1); 33266#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33267#L372 assume !(1 == ~t2_pc~0); 33362#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33361#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33494#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33745#L865 assume !(0 != activate_threads_~tmp___1~0#1); 33164#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33165#L391 assume !(1 == ~t3_pc~0); 33084#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33085#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33296#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33498#L873 assume !(0 != activate_threads_~tmp___2~0#1); 33381#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33382#L410 assume !(1 == ~t4_pc~0); 33615#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33616#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33656#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33746#L881 assume !(0 != activate_threads_~tmp___3~0#1); 33388#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33389#L429 assume !(1 == ~t5_pc~0); 33221#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33222#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33149#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33150#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33624#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33370#L448 assume 1 == ~t6_pc~0; 33257#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33258#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33621#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33705#L897 assume !(0 != activate_threads_~tmp___5~0#1); 33784#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33836#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 33427#L762-2 assume !(1 == ~T1_E~0); 33428#L767-1 assume !(1 == ~T2_E~0); 33791#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33649#L777-1 assume !(1 == ~T4_E~0); 33536#L782-1 assume !(1 == ~T5_E~0); 33249#L787-1 assume !(1 == ~T6_E~0); 33247#L792-1 assume !(1 == ~E_M~0); 33248#L797-1 assume !(1 == ~E_1~0); 33284#L802-1 assume !(1 == ~E_2~0); 33503#L807-1 assume !(1 == ~E_3~0); 33504#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33753#L817-1 assume !(1 == ~E_5~0); 33560#L822-1 assume !(1 == ~E_6~0); 33561#L827-1 assume { :end_inline_reset_delta_events } true; 33378#L1053-2 [2021-12-19 19:15:56,264 INFO L793 eck$LassoCheckResult]: Loop: 33378#L1053-2 assume !false; 33379#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33089#L659 assume !false; 33340#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 33341#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 33343#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 33851#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33682#L570 assume !(0 != eval_~tmp~0#1); 33683#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40183#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40181#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40179#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40177#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40033#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40032#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40031#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40030#L709-3 assume !(0 == ~T6_E~0); 40029#L714-3 assume !(0 == ~E_M~0); 40028#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40027#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40025#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40022#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40020#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40018#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40016#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40014#L334-24 assume 1 == ~m_pc~0; 40011#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40009#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40007#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40005#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40003#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40001#L353-24 assume !(1 == ~t1_pc~0); 39999#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 39996#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39994#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39992#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39990#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39988#L372-24 assume 1 == ~t2_pc~0; 39985#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39869#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39825#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39824#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 39823#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33454#L391-24 assume !(1 == ~t3_pc~0); 33455#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 33692#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33693#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33539#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33516#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33339#L410-24 assume !(1 == ~t4_pc~0); 33213#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 33214#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33660#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33387#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33245#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33246#L429-24 assume 1 == ~t5_pc~0; 33334#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33544#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33380#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33290#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33291#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33240#L448-24 assume !(1 == ~t6_pc~0); 33241#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 33232#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33233#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33673#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33548#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33549#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33512#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33513#L767-3 assume !(1 == ~T2_E~0); 33807#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33786#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33223#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33224#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33674#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33452#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33453#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33721#L807-3 assume !(1 == ~E_3~0); 33582#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33583#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33686#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33664#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 33474#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 33123#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 33505#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 33506#L1072 assume !(0 == start_simulation_~tmp~3#1); 33353#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 33354#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 33234#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 33155#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 33156#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33157#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33678#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 33679#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 33378#L1053-2 [2021-12-19 19:15:56,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2021-12-19 19:15:56,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165842261] [2021-12-19 19:15:56,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,289 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165842261] [2021-12-19 19:15:56,289 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165842261] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,289 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:15:56,289 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319709011] [2021-12-19 19:15:56,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,290 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:56,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,290 INFO L85 PathProgramCache]: Analyzing trace with hash -906281377, now seen corresponding path program 2 times [2021-12-19 19:15:56,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323826835] [2021-12-19 19:15:56,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323826835] [2021-12-19 19:15:56,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323826835] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,306 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,306 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268604897] [2021-12-19 19:15:56,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,307 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:56,307 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:56,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:15:56,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:15:56,308 INFO L87 Difference]: Start difference. First operand 7166 states and 10453 transitions. cyclomatic complexity: 3291 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:56,498 INFO L93 Difference]: Finished difference Result 16939 states and 24854 transitions. [2021-12-19 19:15:56,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:15:56,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16939 states and 24854 transitions. [2021-12-19 19:15:56,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16736 [2021-12-19 19:15:56,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16939 states to 16939 states and 24854 transitions. [2021-12-19 19:15:56,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16939 [2021-12-19 19:15:56,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16939 [2021-12-19 19:15:56,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16939 states and 24854 transitions. [2021-12-19 19:15:56,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:56,685 INFO L681 BuchiCegarLoop]: Abstraction has 16939 states and 24854 transitions. [2021-12-19 19:15:56,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16939 states and 24854 transitions. [2021-12-19 19:15:56,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16939 to 7481. [2021-12-19 19:15:56,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7481 states, 7481 states have (on average 1.4393797620638953) internal successors, (10768), 7480 states have internal predecessors, (10768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:56,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7481 states to 7481 states and 10768 transitions. [2021-12-19 19:15:56,796 INFO L704 BuchiCegarLoop]: Abstraction has 7481 states and 10768 transitions. [2021-12-19 19:15:56,796 INFO L587 BuchiCegarLoop]: Abstraction has 7481 states and 10768 transitions. [2021-12-19 19:15:56,796 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:15:56,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7481 states and 10768 transitions. [2021-12-19 19:15:56,809 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7368 [2021-12-19 19:15:56,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:56,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:56,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:56,810 INFO L791 eck$LassoCheckResult]: Stem: 58041#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 57971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 57944#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57914#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57383#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 57384#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57731#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57732#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57652#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57435#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57436#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57362#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57363#L684 assume !(0 == ~M_E~0); 57862#L684-2 assume !(0 == ~T1_E~0); 57689#L689-1 assume !(0 == ~T2_E~0); 57690#L694-1 assume !(0 == ~T3_E~0); 57687#L699-1 assume !(0 == ~T4_E~0); 57688#L704-1 assume !(0 == ~T5_E~0); 57636#L709-1 assume !(0 == ~T6_E~0); 57572#L714-1 assume !(0 == ~E_M~0); 57573#L719-1 assume !(0 == ~E_1~0); 57830#L724-1 assume !(0 == ~E_2~0); 57336#L729-1 assume !(0 == ~E_3~0); 57337#L734-1 assume !(0 == ~E_4~0); 57908#L739-1 assume !(0 == ~E_5~0); 57527#L744-1 assume !(0 == ~E_6~0); 57528#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57296#L334 assume !(1 == ~m_pc~0); 57297#L334-2 is_master_triggered_~__retres1~0#1 := 0; 57627#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57330#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57331#L849 assume !(0 != activate_threads_~tmp~1#1); 57501#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57431#L353 assume !(1 == ~t1_pc~0); 57432#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 57736#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57346#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57347#L857 assume !(0 != activate_threads_~tmp___0~0#1); 57387#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57388#L372 assume !(1 == ~t2_pc~0); 57486#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 57485#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57621#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57895#L865 assume !(0 != activate_threads_~tmp___1~0#1); 57282#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57283#L391 assume !(1 == ~t3_pc~0); 57202#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 57203#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57417#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57625#L873 assume !(0 != activate_threads_~tmp___2~0#1); 57506#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57507#L410 assume !(1 == ~t4_pc~0); 57753#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 57754#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57792#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57896#L881 assume !(0 != activate_threads_~tmp___3~0#1); 57513#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57514#L429 assume !(1 == ~t5_pc~0); 57340#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 57341#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58034#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57761#L889 assume !(0 != activate_threads_~tmp___4~0#1); 57762#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57494#L448 assume 1 == ~t6_pc~0; 57378#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57379#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57758#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57842#L897 assume !(0 != activate_threads_~tmp___5~0#1); 57940#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58020#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 58021#L762-2 assume !(1 == ~T1_E~0); 62521#L767-1 assume !(1 == ~T2_E~0); 62520#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62519#L777-1 assume !(1 == ~T4_E~0); 62518#L782-1 assume !(1 == ~T5_E~0); 62517#L787-1 assume !(1 == ~T6_E~0); 62516#L792-1 assume !(1 == ~E_M~0); 57367#L797-1 assume !(1 == ~E_1~0); 62508#L802-1 assume !(1 == ~E_2~0); 62506#L807-1 assume !(1 == ~E_3~0); 62504#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 62502#L817-1 assume !(1 == ~E_5~0); 62500#L822-1 assume !(1 == ~E_6~0); 62497#L827-1 assume { :end_inline_reset_delta_events } true; 62493#L1053-2 [2021-12-19 19:15:56,811 INFO L793 eck$LassoCheckResult]: Loop: 62493#L1053-2 assume !false; 62355#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62353#L659 assume !false; 62350#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 62345#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 62338#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 62336#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62334#L570 assume !(0 != eval_~tmp~0#1); 62335#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64597#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64596#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64595#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64594#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64593#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64592#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64590#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64589#L709-3 assume !(0 == ~T6_E~0); 64586#L714-3 assume !(0 == ~E_M~0); 64584#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64582#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64580#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64578#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64576#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64573#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64519#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64516#L334-24 assume 1 == ~m_pc~0; 64512#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64507#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64504#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 64501#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64497#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64493#L353-24 assume !(1 == ~t1_pc~0); 64488#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 64486#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64483#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64479#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64475#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64471#L372-24 assume 1 == ~t2_pc~0; 64465#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64461#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64459#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64458#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 58035#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58036#L391-24 assume !(1 == ~t3_pc~0); 63880#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 63879#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63878#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63876#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63874#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63872#L410-24 assume !(1 == ~t4_pc~0); 60813#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 63870#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63869#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63868#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63867#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63866#L429-24 assume 1 == ~t5_pc~0; 63864#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63862#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63860#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63858#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63857#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63856#L448-24 assume !(1 == ~t6_pc~0); 63854#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 63853#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63852#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62576#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62574#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62572#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62567#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62565#L767-3 assume !(1 == ~T2_E~0); 62563#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62561#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62559#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62557#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62555#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62551#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62549#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62547#L807-3 assume !(1 == ~E_3~0); 62545#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62543#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62541#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62539#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 62534#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 62527#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 62525#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 62524#L1072 assume !(0 == start_simulation_~tmp~3#1); 62522#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 62509#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 62507#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 62505#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 62503#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62501#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62499#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 62498#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 62493#L1053-2 [2021-12-19 19:15:56,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2021-12-19 19:15:56,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805167760] [2021-12-19 19:15:56,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805167760] [2021-12-19 19:15:56,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805167760] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,834 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941782328] [2021-12-19 19:15:56,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,835 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:56,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:56,836 INFO L85 PathProgramCache]: Analyzing trace with hash -906281377, now seen corresponding path program 3 times [2021-12-19 19:15:56,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:56,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244215480] [2021-12-19 19:15:56,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:56,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:56,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:56,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:56,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:56,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244215480] [2021-12-19 19:15:56,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244215480] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:56,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:56,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:56,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259556699] [2021-12-19 19:15:56,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:56,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:56,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:56,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:56,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:56,855 INFO L87 Difference]: Start difference. First operand 7481 states and 10768 transitions. cyclomatic complexity: 3291 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:57,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:57,030 INFO L93 Difference]: Finished difference Result 17548 states and 25041 transitions. [2021-12-19 19:15:57,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:57,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17548 states and 25041 transitions. [2021-12-19 19:15:57,076 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17372 [2021-12-19 19:15:57,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17548 states to 17548 states and 25041 transitions. [2021-12-19 19:15:57,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17548 [2021-12-19 19:15:57,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17548 [2021-12-19 19:15:57,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17548 states and 25041 transitions. [2021-12-19 19:15:57,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:57,130 INFO L681 BuchiCegarLoop]: Abstraction has 17548 states and 25041 transitions. [2021-12-19 19:15:57,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17548 states and 25041 transitions. [2021-12-19 19:15:57,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17548 to 14292. [2021-12-19 19:15:57,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14292 states, 14292 states have (on average 1.431360201511335) internal successors, (20457), 14291 states have internal predecessors, (20457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:57,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14292 states to 14292 states and 20457 transitions. [2021-12-19 19:15:57,342 INFO L704 BuchiCegarLoop]: Abstraction has 14292 states and 20457 transitions. [2021-12-19 19:15:57,342 INFO L587 BuchiCegarLoop]: Abstraction has 14292 states and 20457 transitions. [2021-12-19 19:15:57,342 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:15:57,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14292 states and 20457 transitions. [2021-12-19 19:15:57,367 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14172 [2021-12-19 19:15:57,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:57,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:57,369 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:57,369 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:57,369 INFO L791 eck$LassoCheckResult]: Stem: 83052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 82999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 82979#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82954#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82418#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 82419#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82767#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82768#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82688#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82471#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82472#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82401#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82402#L684 assume !(0 == ~M_E~0); 82905#L684-2 assume !(0 == ~T1_E~0); 82723#L689-1 assume !(0 == ~T2_E~0); 82724#L694-1 assume !(0 == ~T3_E~0); 82721#L699-1 assume !(0 == ~T4_E~0); 82722#L704-1 assume !(0 == ~T5_E~0); 82674#L709-1 assume !(0 == ~T6_E~0); 82609#L714-1 assume !(0 == ~E_M~0); 82610#L719-1 assume !(0 == ~E_1~0); 82871#L724-1 assume !(0 == ~E_2~0); 82372#L729-1 assume !(0 == ~E_3~0); 82373#L734-1 assume !(0 == ~E_4~0); 82949#L739-1 assume !(0 == ~E_5~0); 82563#L744-1 assume !(0 == ~E_6~0); 82564#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82332#L334 assume !(1 == ~m_pc~0); 82333#L334-2 is_master_triggered_~__retres1~0#1 := 0; 82664#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82366#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82367#L849 assume !(0 != activate_threads_~tmp~1#1); 82537#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82467#L353 assume !(1 == ~t1_pc~0); 82468#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82771#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82382#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82383#L857 assume !(0 != activate_threads_~tmp___0~0#1); 82420#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82421#L372 assume !(1 == ~t2_pc~0); 82522#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82521#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82657#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82935#L865 assume !(0 != activate_threads_~tmp___1~0#1); 82321#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82322#L391 assume !(1 == ~t3_pc~0); 82243#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82244#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82451#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82663#L873 assume !(0 != activate_threads_~tmp___2~0#1); 82541#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82542#L410 assume !(1 == ~t4_pc~0); 82790#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82791#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82835#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82939#L881 assume !(0 != activate_threads_~tmp___3~0#1); 82550#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82551#L429 assume !(1 == ~t5_pc~0); 82376#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82377#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82306#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82307#L889 assume !(0 != activate_threads_~tmp___4~0#1); 82798#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82532#L448 assume !(1 == ~t6_pc~0); 82452#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82453#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82795#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82884#L897 assume !(0 != activate_threads_~tmp___5~0#1); 82976#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83039#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 83040#L762-2 assume !(1 == ~T1_E~0); 92844#L767-1 assume !(1 == ~T2_E~0); 92843#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92842#L777-1 assume !(1 == ~T4_E~0); 92841#L782-1 assume !(1 == ~T5_E~0); 92840#L787-1 assume !(1 == ~T6_E~0); 92839#L792-1 assume !(1 == ~E_M~0); 82404#L797-1 assume !(1 == ~E_1~0); 92838#L802-1 assume !(1 == ~E_2~0); 92837#L807-1 assume !(1 == ~E_3~0); 92836#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 92835#L817-1 assume !(1 == ~E_5~0); 92834#L822-1 assume !(1 == ~E_6~0); 82955#L827-1 assume { :end_inline_reset_delta_events } true; 82956#L1053-2 [2021-12-19 19:15:57,369 INFO L793 eck$LassoCheckResult]: Loop: 82956#L1053-2 assume !false; 93123#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93121#L659 assume !false; 93119#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 93112#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 93105#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 93103#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 93100#L570 assume !(0 != eval_~tmp~0#1); 93101#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96501#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96500#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 96498#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96496#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96494#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96491#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96490#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96489#L709-3 assume !(0 == ~T6_E~0); 96488#L714-3 assume !(0 == ~E_M~0); 96487#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96486#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96485#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96482#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96480#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96478#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 96476#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96473#L334-24 assume !(1 == ~m_pc~0); 96471#L334-26 is_master_triggered_~__retres1~0#1 := 0; 96419#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83047#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82272#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82273#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82808#L353-24 assume !(1 == ~t1_pc~0); 82809#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 83036#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96409#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96408#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82323#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82324#L372-24 assume 1 == ~t2_pc~0; 82281#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 82282#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82422#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82423#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 82972#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82613#L391-24 assume !(1 == ~t3_pc~0); 82614#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 83035#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96238#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82705#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82680#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82681#L410-24 assume !(1 == ~t4_pc~0); 93606#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 93604#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93602#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93601#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 93599#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93597#L429-24 assume 1 == ~t5_pc~0; 93595#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 93593#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93592#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 93329#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 93327#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93325#L448-24 assume !(1 == ~t6_pc~0); 88772#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 93322#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93320#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 93318#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 93317#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93315#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 92995#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93314#L767-3 assume !(1 == ~T2_E~0); 93306#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93304#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93303#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93301#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93299#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 92980#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93296#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93294#L807-3 assume !(1 == ~E_3~0); 93290#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93288#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 93286#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 93284#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 93278#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 93272#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 93270#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 93269#L1072 assume !(0 == start_simulation_~tmp~3#1); 93266#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 93244#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 93243#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 93241#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 93239#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93237#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93235#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 93234#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 82956#L1053-2 [2021-12-19 19:15:57,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:57,370 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2021-12-19 19:15:57,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:57,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502844059] [2021-12-19 19:15:57,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:57,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:57,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:57,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:57,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:57,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502844059] [2021-12-19 19:15:57,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502844059] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:57,394 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:57,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:15:57,395 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6202863] [2021-12-19 19:15:57,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:57,395 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:57,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:57,396 INFO L85 PathProgramCache]: Analyzing trace with hash 231347488, now seen corresponding path program 1 times [2021-12-19 19:15:57,396 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:57,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16866797] [2021-12-19 19:15:57,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:57,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:57,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:57,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:57,413 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:57,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16866797] [2021-12-19 19:15:57,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16866797] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:57,413 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:57,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:57,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142856309] [2021-12-19 19:15:57,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:57,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:57,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:57,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:15:57,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:15:57,415 INFO L87 Difference]: Start difference. First operand 14292 states and 20457 transitions. cyclomatic complexity: 6169 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:57,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:57,594 INFO L93 Difference]: Finished difference Result 21285 states and 30490 transitions. [2021-12-19 19:15:57,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:15:57,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21285 states and 30490 transitions. [2021-12-19 19:15:57,653 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21164 [2021-12-19 19:15:57,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21285 states to 21285 states and 30490 transitions. [2021-12-19 19:15:57,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21285 [2021-12-19 19:15:57,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21285 [2021-12-19 19:15:57,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21285 states and 30490 transitions. [2021-12-19 19:15:57,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:57,917 INFO L681 BuchiCegarLoop]: Abstraction has 21285 states and 30490 transitions. [2021-12-19 19:15:57,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21285 states and 30490 transitions. [2021-12-19 19:15:58,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21285 to 14922. [2021-12-19 19:15:58,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14922 states, 14922 states have (on average 1.434727248358129) internal successors, (21409), 14921 states have internal predecessors, (21409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14922 states to 14922 states and 21409 transitions. [2021-12-19 19:15:58,140 INFO L704 BuchiCegarLoop]: Abstraction has 14922 states and 21409 transitions. [2021-12-19 19:15:58,140 INFO L587 BuchiCegarLoop]: Abstraction has 14922 states and 21409 transitions. [2021-12-19 19:15:58,140 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:15:58,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14922 states and 21409 transitions. [2021-12-19 19:15:58,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14816 [2021-12-19 19:15:58,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:58,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:58,181 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,181 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:58,181 INFO L791 eck$LassoCheckResult]: Stem: 118641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 118580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 118565#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118536#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118001#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 118002#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118352#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118353#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118274#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118056#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118057#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 117985#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 117986#L684 assume !(0 == ~M_E~0); 118490#L684-2 assume !(0 == ~T1_E~0); 118307#L689-1 assume !(0 == ~T2_E~0); 118308#L694-1 assume !(0 == ~T3_E~0); 118305#L699-1 assume !(0 == ~T4_E~0); 118306#L704-1 assume !(0 == ~T5_E~0); 118259#L709-1 assume !(0 == ~T6_E~0); 118191#L714-1 assume !(0 == ~E_M~0); 118192#L719-1 assume !(0 == ~E_1~0); 118453#L724-1 assume !(0 == ~E_2~0); 117955#L729-1 assume !(0 == ~E_3~0); 117956#L734-1 assume !(0 == ~E_4~0); 118527#L739-1 assume !(0 == ~E_5~0); 118146#L744-1 assume !(0 == ~E_6~0); 118147#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117916#L334 assume !(1 == ~m_pc~0); 117917#L334-2 is_master_triggered_~__retres1~0#1 := 0; 118248#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117949#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117950#L849 assume !(0 != activate_threads_~tmp~1#1); 118119#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118052#L353 assume !(1 == ~t1_pc~0); 118053#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118357#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117965#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 117966#L857 assume !(0 != activate_threads_~tmp___0~0#1); 118003#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118004#L372 assume !(1 == ~t2_pc~0); 118106#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118105#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118241#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118514#L865 assume !(0 != activate_threads_~tmp___1~0#1); 117905#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117906#L391 assume !(1 == ~t3_pc~0); 117827#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 117828#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118036#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118247#L873 assume !(0 != activate_threads_~tmp___2~0#1); 118124#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118125#L410 assume !(1 == ~t4_pc~0); 118378#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118379#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118419#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118518#L881 assume !(0 != activate_threads_~tmp___3~0#1); 118133#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118134#L429 assume !(1 == ~t5_pc~0); 117959#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 117960#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117890#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117891#L889 assume !(0 != activate_threads_~tmp___4~0#1); 118387#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118114#L448 assume !(1 == ~t6_pc~0); 118037#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 118038#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118384#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 118467#L897 assume !(0 != activate_threads_~tmp___5~0#1); 118561#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118628#L762 assume !(1 == ~M_E~0); 118171#L762-2 assume !(1 == ~T1_E~0); 118172#L767-1 assume !(1 == ~T2_E~0); 118567#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118413#L777-1 assume !(1 == ~T4_E~0); 118289#L782-1 assume !(1 == ~T5_E~0); 117989#L787-1 assume !(1 == ~T6_E~0); 117987#L792-1 assume !(1 == ~E_M~0); 117988#L797-1 assume !(1 == ~E_1~0); 118024#L802-1 assume !(1 == ~E_2~0); 118254#L807-1 assume !(1 == ~E_3~0); 118255#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 118524#L817-1 assume !(1 == ~E_5~0); 118311#L822-1 assume !(1 == ~E_6~0); 118312#L827-1 assume { :end_inline_reset_delta_events } true; 118537#L1053-2 [2021-12-19 19:15:58,182 INFO L793 eck$LassoCheckResult]: Loop: 118537#L1053-2 assume !false; 124577#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124449#L659 assume !false; 124567#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 124539#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 124529#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 124522#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 124515#L570 assume !(0 != eval_~tmp~0#1); 124516#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 132309#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132308#L684-3 assume !(0 == ~M_E~0); 132307#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132306#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132305#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132304#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132303#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132302#L709-3 assume !(0 == ~T6_E~0); 132298#L714-3 assume !(0 == ~E_M~0); 132296#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132294#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132291#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132289#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132287#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132286#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132285#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132284#L334-24 assume 1 == ~m_pc~0; 132282#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 132280#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132278#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 132276#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132274#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132272#L353-24 assume !(1 == ~t1_pc~0); 132270#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 132268#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132266#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132264#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132262#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132260#L372-24 assume !(1 == ~t2_pc~0); 132258#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 132255#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132253#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132251#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 132249#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132247#L391-24 assume !(1 == ~t3_pc~0); 132244#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 132242#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132240#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132238#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132236#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132234#L410-24 assume !(1 == ~t4_pc~0); 122879#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 132231#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132229#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132227#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132225#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132223#L429-24 assume 1 == ~t5_pc~0; 132218#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132219#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132694#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 132693#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118026#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117978#L448-24 assume !(1 == ~t6_pc~0); 117979#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 117971#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117972#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 118432#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 118302#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118303#L762-3 assume !(1 == ~M_E~0); 118262#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118263#L767-3 assume !(1 == ~T2_E~0); 118581#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118564#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117961#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117962#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 118434#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 118193#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118194#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 118491#L807-3 assume !(1 == ~E_3~0); 118338#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118339#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118446#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 118426#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 118217#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 117863#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118252#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 118253#L1072 assume !(0 == start_simulation_~tmp~3#1); 118615#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 124630#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 124625#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 124620#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 124614#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 124607#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 124599#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 124591#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 118537#L1053-2 [2021-12-19 19:15:58,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2021-12-19 19:15:58,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678032705] [2021-12-19 19:15:58,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678032705] [2021-12-19 19:15:58,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678032705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,294 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79491040] [2021-12-19 19:15:58,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,295 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:58,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:58,295 INFO L85 PathProgramCache]: Analyzing trace with hash -621916960, now seen corresponding path program 1 times [2021-12-19 19:15:58,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:58,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534092079] [2021-12-19 19:15:58,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:58,296 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:58,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:58,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:58,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:58,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534092079] [2021-12-19 19:15:58,312 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534092079] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:58,312 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:58,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:58,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152004954] [2021-12-19 19:15:58,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:58,312 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:58,312 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:58,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:58,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:58,313 INFO L87 Difference]: Start difference. First operand 14922 states and 21409 transitions. cyclomatic complexity: 6489 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:58,421 INFO L93 Difference]: Finished difference Result 23852 states and 34093 transitions. [2021-12-19 19:15:58,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:58,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23852 states and 34093 transitions. [2021-12-19 19:15:58,502 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23664 [2021-12-19 19:15:58,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23852 states to 23852 states and 34093 transitions. [2021-12-19 19:15:58,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23852 [2021-12-19 19:15:58,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23852 [2021-12-19 19:15:58,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23852 states and 34093 transitions. [2021-12-19 19:15:58,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:58,602 INFO L681 BuchiCegarLoop]: Abstraction has 23852 states and 34093 transitions. [2021-12-19 19:15:58,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23852 states and 34093 transitions. [2021-12-19 19:15:58,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23852 to 17065. [2021-12-19 19:15:58,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17065 states, 17065 states have (on average 1.4331087020216817) internal successors, (24456), 17064 states have internal predecessors, (24456), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:58,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17065 states to 17065 states and 24456 transitions. [2021-12-19 19:15:58,964 INFO L704 BuchiCegarLoop]: Abstraction has 17065 states and 24456 transitions. [2021-12-19 19:15:58,964 INFO L587 BuchiCegarLoop]: Abstraction has 17065 states and 24456 transitions. [2021-12-19 19:15:58,964 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:15:58,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17065 states and 24456 transitions. [2021-12-19 19:15:59,003 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16896 [2021-12-19 19:15:59,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:59,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:59,006 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,006 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,006 INFO L791 eck$LassoCheckResult]: Stem: 157456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 157388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 157368#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157338#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156785#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 156786#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157144#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157145#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157058#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156842#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156843#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 156769#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 156770#L684 assume !(0 == ~M_E~0); 157285#L684-2 assume !(0 == ~T1_E~0); 157096#L689-1 assume !(0 == ~T2_E~0); 157097#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 157451#L699-1 assume !(0 == ~T4_E~0); 157491#L704-1 assume !(0 == ~T5_E~0); 157490#L709-1 assume !(0 == ~T6_E~0); 156982#L714-1 assume !(0 == ~E_M~0); 156983#L719-1 assume !(0 == ~E_1~0); 157255#L724-1 assume !(0 == ~E_2~0); 156742#L729-1 assume !(0 == ~E_3~0); 156743#L734-1 assume !(0 == ~E_4~0); 157488#L739-1 assume !(0 == ~E_5~0); 156934#L744-1 assume !(0 == ~E_6~0); 156935#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157256#L334 assume !(1 == ~m_pc~0); 157485#L334-2 is_master_triggered_~__retres1~0#1 := 0; 157484#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157483#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156907#L849 assume !(0 != activate_threads_~tmp~1#1); 156908#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157482#L353 assume !(1 == ~t1_pc~0); 157481#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157150#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157151#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 157113#L857 assume !(0 != activate_threads_~tmp___0~0#1); 157114#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 157382#L372 assume !(1 == ~t2_pc~0); 157383#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157480#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157479#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 157478#L865 assume !(0 != activate_threads_~tmp___1~0#1); 156689#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156690#L391 assume !(1 == ~t3_pc~0); 157299#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 157476#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157475#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 157474#L873 assume !(0 != activate_threads_~tmp___2~0#1); 156912#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156913#L410 assume !(1 == ~t4_pc~0); 157313#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157215#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157216#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 157472#L881 assume !(0 != activate_threads_~tmp___3~0#1); 156919#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 156920#L429 assume !(1 == ~t5_pc~0); 156746#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 156747#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157470#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 157467#L889 assume !(0 != activate_threads_~tmp___4~0#1); 157205#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 157206#L448 assume !(1 == ~t6_pc~0); 157465#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 157175#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 157176#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 157268#L897 assume !(0 != activate_threads_~tmp___5~0#1); 157434#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157435#L762 assume !(1 == ~M_E~0); 157463#L762-2 assume !(1 == ~T1_E~0); 157406#L767-1 assume !(1 == ~T2_E~0); 157407#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157207#L777-1 assume !(1 == ~T4_E~0); 157072#L782-1 assume !(1 == ~T5_E~0); 156775#L787-1 assume !(1 == ~T6_E~0); 156773#L792-1 assume !(1 == ~E_M~0); 156774#L797-1 assume !(1 == ~E_1~0); 156809#L802-1 assume !(1 == ~E_2~0); 157037#L807-1 assume !(1 == ~E_3~0); 157038#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 157326#L817-1 assume !(1 == ~E_5~0); 157098#L822-1 assume !(1 == ~E_6~0); 157099#L827-1 assume { :end_inline_reset_delta_events } true; 157339#L1053-2 [2021-12-19 19:15:59,007 INFO L793 eck$LassoCheckResult]: Loop: 157339#L1053-2 assume !false; 168392#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 168390#L659 assume !false; 168389#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 168384#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 168377#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 168375#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 168373#L570 assume !(0 != eval_~tmp~0#1); 168374#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 172652#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 172617#L684-3 assume !(0 == ~M_E~0); 172611#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 172604#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 172547#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 172546#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 172545#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 172544#L709-3 assume !(0 == ~T6_E~0); 172543#L714-3 assume !(0 == ~E_M~0); 172542#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 172539#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 172537#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 172535#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 172533#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 172531#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 172529#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172527#L334-24 assume 1 == ~m_pc~0; 172524#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 172522#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 172520#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 172518#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 172516#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172514#L353-24 assume !(1 == ~t1_pc~0); 172511#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 172509#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172507#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 172505#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 172503#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172501#L372-24 assume 1 == ~t2_pc~0; 172498#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 172496#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172494#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 172492#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 172490#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172488#L391-24 assume !(1 == ~t3_pc~0); 171889#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 172484#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172482#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 172480#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172478#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172476#L410-24 assume !(1 == ~t4_pc~0); 172467#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 172474#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172472#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172470#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172468#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172465#L429-24 assume !(1 == ~t5_pc~0); 172462#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 172459#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172456#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172453#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 172450#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172448#L448-24 assume !(1 == ~t6_pc~0); 168910#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 172443#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172440#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172437#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 172435#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172433#L762-3 assume !(1 == ~M_E~0); 164348#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 172431#L767-3 assume !(1 == ~T2_E~0); 172351#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157367#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156748#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 156749#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 172045#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 172042#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 171991#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 171989#L807-3 assume !(1 == ~E_3~0); 171987#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 171985#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 171984#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 171983#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 171978#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 171971#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 171969#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 163188#L1072 assume !(0 == start_simulation_~tmp~3#1); 163189#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 168485#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 168481#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 168479#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 168477#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 168476#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 168475#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 168474#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 157339#L1053-2 [2021-12-19 19:15:59,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,007 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2021-12-19 19:15:59,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171433855] [2021-12-19 19:15:59,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171433855] [2021-12-19 19:15:59,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171433855] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027051283] [2021-12-19 19:15:59,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,028 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:59,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1631849122, now seen corresponding path program 1 times [2021-12-19 19:15:59,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116293599] [2021-12-19 19:15:59,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116293599] [2021-12-19 19:15:59,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116293599] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007561530] [2021-12-19 19:15:59,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,045 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:59,045 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:59,045 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:59,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:59,045 INFO L87 Difference]: Start difference. First operand 17065 states and 24456 transitions. cyclomatic complexity: 7393 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:59,190 INFO L93 Difference]: Finished difference Result 21698 states and 30911 transitions. [2021-12-19 19:15:59,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:59,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21698 states and 30911 transitions. [2021-12-19 19:15:59,258 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21584 [2021-12-19 19:15:59,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21698 states to 21698 states and 30911 transitions. [2021-12-19 19:15:59,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21698 [2021-12-19 19:15:59,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21698 [2021-12-19 19:15:59,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21698 states and 30911 transitions. [2021-12-19 19:15:59,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:59,325 INFO L681 BuchiCegarLoop]: Abstraction has 21698 states and 30911 transitions. [2021-12-19 19:15:59,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21698 states and 30911 transitions. [2021-12-19 19:15:59,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21698 to 14922. [2021-12-19 19:15:59,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14922 states, 14922 states have (on average 1.428159764106688) internal successors, (21311), 14921 states have internal predecessors, (21311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14922 states to 14922 states and 21311 transitions. [2021-12-19 19:15:59,548 INFO L704 BuchiCegarLoop]: Abstraction has 14922 states and 21311 transitions. [2021-12-19 19:15:59,548 INFO L587 BuchiCegarLoop]: Abstraction has 14922 states and 21311 transitions. [2021-12-19 19:15:59,548 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:15:59,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14922 states and 21311 transitions. [2021-12-19 19:15:59,571 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14816 [2021-12-19 19:15:59,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:15:59,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:15:59,575 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:15:59,576 INFO L791 eck$LassoCheckResult]: Stem: 196186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 196128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 196110#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196083#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 195559#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 195560#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 195907#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 195908#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 195830#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 195616#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 195617#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 195542#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195543#L684 assume !(0 == ~M_E~0); 196039#L684-2 assume !(0 == ~T1_E~0); 195864#L689-1 assume !(0 == ~T2_E~0); 195865#L694-1 assume !(0 == ~T3_E~0); 195862#L699-1 assume !(0 == ~T4_E~0); 195863#L704-1 assume !(0 == ~T5_E~0); 195813#L709-1 assume !(0 == ~T6_E~0); 195750#L714-1 assume !(0 == ~E_M~0); 195751#L719-1 assume !(0 == ~E_1~0); 196009#L724-1 assume !(0 == ~E_2~0); 195514#L729-1 assume !(0 == ~E_3~0); 195515#L734-1 assume !(0 == ~E_4~0); 196076#L739-1 assume !(0 == ~E_5~0); 195704#L744-1 assume !(0 == ~E_6~0); 195705#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195475#L334 assume !(1 == ~m_pc~0); 195476#L334-2 is_master_triggered_~__retres1~0#1 := 0; 195803#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 195508#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 195509#L849 assume !(0 != activate_threads_~tmp~1#1); 195679#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195612#L353 assume !(1 == ~t1_pc~0); 195613#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 195912#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 195524#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 195525#L857 assume !(0 != activate_threads_~tmp___0~0#1); 195563#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 195564#L372 assume !(1 == ~t2_pc~0); 195666#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 195665#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 195796#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196067#L865 assume !(0 != activate_threads_~tmp___1~0#1); 195462#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195463#L391 assume !(1 == ~t3_pc~0); 195382#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 195383#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 195596#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 195800#L873 assume !(0 != activate_threads_~tmp___2~0#1); 195683#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 195684#L410 assume !(1 == ~t4_pc~0); 195930#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 195931#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195971#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 196068#L881 assume !(0 != activate_threads_~tmp___3~0#1); 195690#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 195691#L429 assume !(1 == ~t5_pc~0); 195518#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 195519#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 195446#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 195447#L889 assume !(0 != activate_threads_~tmp___4~0#1); 195938#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 195674#L448 assume !(1 == ~t6_pc~0); 195597#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 195598#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 195935#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 196021#L897 assume !(0 != activate_threads_~tmp___5~0#1); 196107#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 196167#L762 assume !(1 == ~M_E~0); 195729#L762-2 assume !(1 == ~T1_E~0); 195730#L767-1 assume !(1 == ~T2_E~0); 196112#L772-1 assume !(1 == ~T3_E~0); 195962#L777-1 assume !(1 == ~T4_E~0); 195844#L782-1 assume !(1 == ~T5_E~0); 195548#L787-1 assume !(1 == ~T6_E~0); 195546#L792-1 assume !(1 == ~E_M~0); 195547#L797-1 assume !(1 == ~E_1~0); 195581#L802-1 assume !(1 == ~E_2~0); 195807#L807-1 assume !(1 == ~E_3~0); 195808#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 196072#L817-1 assume !(1 == ~E_5~0); 195866#L822-1 assume !(1 == ~E_6~0); 195867#L827-1 assume { :end_inline_reset_delta_events } true; 196084#L1053-2 [2021-12-19 19:15:59,576 INFO L793 eck$LassoCheckResult]: Loop: 196084#L1053-2 assume !false; 202966#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 202961#L659 assume !false; 202957#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 202927#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 202915#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 202909#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 202901#L570 assume !(0 != eval_~tmp~0#1); 202902#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210095#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 210092#L684-3 assume !(0 == ~M_E~0); 210090#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 210088#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 210086#L694-3 assume !(0 == ~T3_E~0); 210084#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 210082#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 210079#L709-3 assume !(0 == ~T6_E~0); 210077#L714-3 assume !(0 == ~E_M~0); 210075#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 210074#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 210073#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 210072#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 210071#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 210070#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 210069#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210067#L334-24 assume !(1 == ~m_pc~0); 210065#L334-26 is_master_triggered_~__retres1~0#1 := 0; 210062#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210060#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210058#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 210056#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210054#L353-24 assume !(1 == ~t1_pc~0); 210052#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 210050#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210048#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210046#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 210044#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210042#L372-24 assume 1 == ~t2_pc~0; 210039#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 210037#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210035#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 210033#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 210030#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210028#L391-24 assume !(1 == ~t3_pc~0); 202906#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 209735#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209734#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 209733#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 209306#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 195642#L410-24 assume !(1 == ~t4_pc~0); 195510#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 195511#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195977#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 195689#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 195544#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 195545#L429-24 assume !(1 == ~t5_pc~0); 195638#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 195976#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 195682#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 195585#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 195586#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 195537#L448-24 assume !(1 == ~t6_pc~0); 195538#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 195529#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 195530#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 195989#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 195856#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 195857#L762-3 assume !(1 == ~M_E~0); 195816#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 195817#L767-3 assume !(1 == ~T2_E~0); 196129#L772-3 assume !(1 == ~T3_E~0); 196109#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 195520#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 195521#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 195990#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 195752#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 195753#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 196041#L807-3 assume !(1 == ~E_3~0); 195893#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 195894#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 196003#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 196004#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 207223#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 207214#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 207196#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 196356#L1072 assume !(0 == start_simulation_~tmp~3#1); 196357#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 203048#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 203043#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 203038#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 203034#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 203026#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 203021#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 203016#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 196084#L1053-2 [2021-12-19 19:15:59,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,576 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2021-12-19 19:15:59,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894391232] [2021-12-19 19:15:59,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,598 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894391232] [2021-12-19 19:15:59,599 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894391232] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,599 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,599 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,599 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035842214] [2021-12-19 19:15:59,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,599 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:15:59,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:15:59,600 INFO L85 PathProgramCache]: Analyzing trace with hash 1577626403, now seen corresponding path program 1 times [2021-12-19 19:15:59,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:15:59,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241897242] [2021-12-19 19:15:59,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:15:59,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:15:59,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:15:59,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:15:59,615 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:15:59,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241897242] [2021-12-19 19:15:59,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241897242] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:15:59,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:15:59,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:15:59,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525274992] [2021-12-19 19:15:59,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:15:59,616 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:15:59,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:15:59,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:15:59,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:15:59,617 INFO L87 Difference]: Start difference. First operand 14922 states and 21311 transitions. cyclomatic complexity: 6391 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:15:59,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:15:59,804 INFO L93 Difference]: Finished difference Result 23588 states and 33443 transitions. [2021-12-19 19:15:59,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:15:59,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23588 states and 33443 transitions. [2021-12-19 19:15:59,865 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23400 [2021-12-19 19:15:59,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23588 states to 23588 states and 33443 transitions. [2021-12-19 19:15:59,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23588 [2021-12-19 19:15:59,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23588 [2021-12-19 19:15:59,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23588 states and 33443 transitions. [2021-12-19 19:15:59,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:15:59,919 INFO L681 BuchiCegarLoop]: Abstraction has 23588 states and 33443 transitions. [2021-12-19 19:15:59,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23588 states and 33443 transitions. [2021-12-19 19:16:00,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23588 to 17049. [2021-12-19 19:16:00,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17049 states, 17049 states have (on average 1.4216669599389993) internal successors, (24238), 17048 states have internal predecessors, (24238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17049 states to 17049 states and 24238 transitions. [2021-12-19 19:16:00,172 INFO L704 BuchiCegarLoop]: Abstraction has 17049 states and 24238 transitions. [2021-12-19 19:16:00,172 INFO L587 BuchiCegarLoop]: Abstraction has 17049 states and 24238 transitions. [2021-12-19 19:16:00,172 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:16:00,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17049 states and 24238 transitions. [2021-12-19 19:16:00,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16880 [2021-12-19 19:16:00,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:00,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:00,208 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,208 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,208 INFO L791 eck$LassoCheckResult]: Stem: 234759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 234694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 234669#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 234635#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 234081#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 234082#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 234436#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 234437#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 234351#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 234135#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 234136#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 234065#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234066#L684 assume !(0 == ~M_E~0); 234585#L684-2 assume !(0 == ~T1_E~0); 234385#L689-1 assume !(0 == ~T2_E~0); 234386#L694-1 assume !(0 == ~T3_E~0); 234383#L699-1 assume !(0 == ~T4_E~0); 234384#L704-1 assume !(0 == ~T5_E~0); 234335#L709-1 assume !(0 == ~T6_E~0); 234274#L714-1 assume !(0 == ~E_M~0); 234275#L719-1 assume !(0 == ~E_1~0); 234550#L724-1 assume !(0 == ~E_2~0); 234035#L729-1 assume !(0 == ~E_3~0); 234036#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 234626#L739-1 assume !(0 == ~E_5~0); 234627#L744-1 assume !(0 == ~E_6~0); 234805#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233995#L334 assume !(1 == ~m_pc~0); 233996#L334-2 is_master_triggered_~__retres1~0#1 := 0; 234326#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 234029#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 234030#L849 assume !(0 != activate_threads_~tmp~1#1); 234800#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234799#L353 assume !(1 == ~t1_pc~0); 234798#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 234441#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 234442#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 234403#L857 assume !(0 != activate_threads_~tmp___0~0#1); 234083#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 234084#L372 assume !(1 == ~t2_pc~0); 234188#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 234187#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234320#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234613#L865 assume !(0 != activate_threads_~tmp___1~0#1); 234614#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234793#L391 assume !(1 == ~t3_pc~0); 233904#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 233905#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 234115#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 234325#L873 assume !(0 != activate_threads_~tmp___2~0#1); 234543#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 234789#L410 assume !(1 == ~t4_pc~0); 234460#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 234461#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 234505#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234787#L881 assume !(0 != activate_threads_~tmp___3~0#1); 234216#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 234217#L429 assume !(1 == ~t5_pc~0); 234039#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 234040#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 234806#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 234467#L889 assume !(0 != activate_threads_~tmp___4~0#1); 234468#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 234494#L448 assume !(1 == ~t6_pc~0); 234779#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 234778#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 234777#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 234662#L897 assume !(0 != activate_threads_~tmp___5~0#1); 234663#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 234738#L762 assume !(1 == ~M_E~0); 234254#L762-2 assume !(1 == ~T1_E~0); 234255#L767-1 assume !(1 == ~T2_E~0); 234672#L772-1 assume !(1 == ~T3_E~0); 234495#L777-1 assume !(1 == ~T4_E~0); 234496#L782-1 assume !(1 == ~T5_E~0); 234774#L787-1 assume !(1 == ~T6_E~0); 234773#L792-1 assume !(1 == ~E_M~0); 234772#L797-1 assume !(1 == ~E_1~0); 234771#L802-1 assume !(1 == ~E_2~0); 234770#L807-1 assume !(1 == ~E_3~0); 234769#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 234622#L817-1 assume !(1 == ~E_5~0); 234387#L822-1 assume !(1 == ~E_6~0); 234388#L827-1 assume { :end_inline_reset_delta_events } true; 234636#L1053-2 [2021-12-19 19:16:00,208 INFO L793 eck$LassoCheckResult]: Loop: 234636#L1053-2 assume !false; 245072#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 245067#L659 assume !false; 245064#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 245058#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 245048#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 245043#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 245037#L570 assume !(0 != eval_~tmp~0#1); 245033#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245029#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245025#L684-3 assume !(0 == ~M_E~0); 245022#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 245017#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 245013#L694-3 assume !(0 == ~T3_E~0); 245009#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 244980#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244976#L709-3 assume !(0 == ~T6_E~0); 244971#L714-3 assume !(0 == ~E_M~0); 244953#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244949#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 244946#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 244944#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 241731#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 241732#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 241725#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 241726#L334-24 assume !(1 == ~m_pc~0); 241718#L334-26 is_master_triggered_~__retres1~0#1 := 0; 241717#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 241709#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 241710#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 241701#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 241702#L353-24 assume !(1 == ~t1_pc~0); 241695#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 241696#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241689#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 241690#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 241681#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 241682#L372-24 assume !(1 == ~t2_pc~0); 244943#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 241673#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241674#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 241669#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 241670#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241664#L391-24 assume !(1 == ~t3_pc~0); 235545#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 241659#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241660#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 241653#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 241654#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241647#L410-24 assume !(1 == ~t4_pc~0); 241058#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 241641#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 241642#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 241637#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 241638#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241632#L429-24 assume !(1 == ~t5_pc~0); 241634#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 241624#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241625#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 241619#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 241618#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 241337#L448-24 assume !(1 == ~t6_pc~0); 241335#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 241334#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 241332#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 241330#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 241328#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 241326#L762-3 assume !(1 == ~M_E~0); 241323#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 241322#L767-3 assume !(1 == ~T2_E~0); 241321#L772-3 assume !(1 == ~T3_E~0); 241320#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 241319#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 241318#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 241317#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 241316#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 241315#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 241314#L807-3 assume !(1 == ~E_3~0); 241312#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 241153#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 241148#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 241145#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 241029#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 241021#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 241020#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 238078#L1072 assume !(0 == start_simulation_~tmp~3#1); 238079#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 245146#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 245138#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 245130#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 245122#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 245113#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 245106#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 245098#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 234636#L1053-2 [2021-12-19 19:16:00,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2021-12-19 19:16:00,209 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845113552] [2021-12-19 19:16:00,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,209 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,231 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [845113552] [2021-12-19 19:16:00,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [845113552] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,231 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,231 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,231 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032909400] [2021-12-19 19:16:00,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,232 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:00,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1817893732, now seen corresponding path program 1 times [2021-12-19 19:16:00,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338562724] [2021-12-19 19:16:00,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,232 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338562724] [2021-12-19 19:16:00,263 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338562724] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,263 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,263 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120058425] [2021-12-19 19:16:00,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,263 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:00,263 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:00,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:00,263 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:00,263 INFO L87 Difference]: Start difference. First operand 17049 states and 24238 transitions. cyclomatic complexity: 7191 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:00,377 INFO L93 Difference]: Finished difference Result 21286 states and 30073 transitions. [2021-12-19 19:16:00,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:00,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21286 states and 30073 transitions. [2021-12-19 19:16:00,438 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21164 [2021-12-19 19:16:00,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21286 states to 21286 states and 30073 transitions. [2021-12-19 19:16:00,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21286 [2021-12-19 19:16:00,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21286 [2021-12-19 19:16:00,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21286 states and 30073 transitions. [2021-12-19 19:16:00,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:00,502 INFO L681 BuchiCegarLoop]: Abstraction has 21286 states and 30073 transitions. [2021-12-19 19:16:00,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21286 states and 30073 transitions. [2021-12-19 19:16:00,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21286 to 14922. [2021-12-19 19:16:00,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14922 states, 14922 states have (on average 1.4146227047312692) internal successors, (21109), 14921 states have internal predecessors, (21109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14922 states to 14922 states and 21109 transitions. [2021-12-19 19:16:00,760 INFO L704 BuchiCegarLoop]: Abstraction has 14922 states and 21109 transitions. [2021-12-19 19:16:00,760 INFO L587 BuchiCegarLoop]: Abstraction has 14922 states and 21109 transitions. [2021-12-19 19:16:00,760 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:16:00,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14922 states and 21109 transitions. [2021-12-19 19:16:00,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14816 [2021-12-19 19:16:00,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:00,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:00,795 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,795 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:00,795 INFO L791 eck$LassoCheckResult]: Stem: 273068#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 272995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 272975#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 272950#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 272425#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 272426#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 272775#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 272776#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 272696#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 272478#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272479#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 272409#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272410#L684 assume !(0 == ~M_E~0); 272899#L684-2 assume !(0 == ~T1_E~0); 272729#L689-1 assume !(0 == ~T2_E~0); 272730#L694-1 assume !(0 == ~T3_E~0); 272727#L699-1 assume !(0 == ~T4_E~0); 272728#L704-1 assume !(0 == ~T5_E~0); 272682#L709-1 assume !(0 == ~T6_E~0); 272621#L714-1 assume !(0 == ~E_M~0); 272622#L719-1 assume !(0 == ~E_1~0); 272868#L724-1 assume !(0 == ~E_2~0); 272379#L729-1 assume !(0 == ~E_3~0); 272380#L734-1 assume !(0 == ~E_4~0); 272943#L739-1 assume !(0 == ~E_5~0); 272571#L744-1 assume !(0 == ~E_6~0); 272572#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272338#L334 assume !(1 == ~m_pc~0); 272339#L334-2 is_master_triggered_~__retres1~0#1 := 0; 272672#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272373#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 272374#L849 assume !(0 != activate_threads_~tmp~1#1); 272545#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272474#L353 assume !(1 == ~t1_pc~0); 272475#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 272780#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272389#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272390#L857 assume !(0 != activate_threads_~tmp___0~0#1); 272427#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272428#L372 assume !(1 == ~t2_pc~0); 272530#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 272529#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272665#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272927#L865 assume !(0 != activate_threads_~tmp___1~0#1); 272327#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272328#L391 assume !(1 == ~t3_pc~0); 272249#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 272250#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272458#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272671#L873 assume !(0 != activate_threads_~tmp___2~0#1); 272549#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272550#L410 assume !(1 == ~t4_pc~0); 272796#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 272797#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272833#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272931#L881 assume !(0 != activate_threads_~tmp___3~0#1); 272558#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272559#L429 assume !(1 == ~t5_pc~0); 272383#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 272384#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272312#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272313#L889 assume !(0 != activate_threads_~tmp___4~0#1); 272803#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272540#L448 assume !(1 == ~t6_pc~0); 272459#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 272460#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272801#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272882#L897 assume !(0 != activate_threads_~tmp___5~0#1); 272970#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273044#L762 assume !(1 == ~M_E~0); 272599#L762-2 assume !(1 == ~T1_E~0); 272600#L767-1 assume !(1 == ~T2_E~0); 272977#L772-1 assume !(1 == ~T3_E~0); 272827#L777-1 assume !(1 == ~T4_E~0); 272709#L782-1 assume !(1 == ~T5_E~0); 272413#L787-1 assume !(1 == ~T6_E~0); 272411#L792-1 assume !(1 == ~E_M~0); 272412#L797-1 assume !(1 == ~E_1~0); 272447#L802-1 assume !(1 == ~E_2~0); 272677#L807-1 assume !(1 == ~E_3~0); 272678#L812-1 assume !(1 == ~E_4~0); 272938#L817-1 assume !(1 == ~E_5~0); 272733#L822-1 assume !(1 == ~E_6~0); 272734#L827-1 assume { :end_inline_reset_delta_events } true; 272951#L1053-2 [2021-12-19 19:16:00,796 INFO L793 eck$LassoCheckResult]: Loop: 272951#L1053-2 assume !false; 286188#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 286186#L659 assume !false; 286184#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 285700#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273070#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273069#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 272859#L570 assume !(0 != eval_~tmp~0#1); 272860#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286941#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 286939#L684-3 assume !(0 == ~M_E~0); 286937#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 286935#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 286933#L694-3 assume !(0 == ~T3_E~0); 286931#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 286929#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 286927#L709-3 assume !(0 == ~T6_E~0); 286925#L714-3 assume !(0 == ~E_M~0); 286923#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 286920#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 286918#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 286916#L734-3 assume !(0 == ~E_4~0); 286914#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 286912#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 286910#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286909#L334-24 assume 1 == ~m_pc~0; 286904#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 286902#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 286900#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 272280#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272281#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272811#L353-24 assume !(1 == ~t1_pc~0); 272812#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 272983#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272984#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 273001#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 272329#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272330#L372-24 assume 1 == ~t2_pc~0; 272287#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 272288#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272429#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272430#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 272964#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286665#L391-24 assume !(1 == ~t3_pc~0); 285923#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 286658#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272939#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272940#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 286033#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281279#L410-24 assume !(1 == ~t4_pc~0); 281275#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 281273#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281271#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 281269#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 281267#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281265#L429-24 assume 1 == ~t5_pc~0; 281262#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 281258#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281254#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281250#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 281247#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281244#L448-24 assume !(1 == ~t6_pc~0); 280284#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 281240#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281237#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 281234#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 281231#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281228#L762-3 assume !(1 == ~M_E~0); 278976#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 281181#L767-3 assume !(1 == ~T2_E~0); 281110#L772-3 assume !(1 == ~T3_E~0); 281106#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 281102#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 281098#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 281087#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 281086#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 281085#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 281084#L807-3 assume !(1 == ~E_3~0); 281083#L812-3 assume !(1 == ~E_4~0); 281075#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 281073#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 281063#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273318#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273311#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273264#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 273258#L1072 assume !(0 == start_simulation_~tmp~3#1); 273259#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 286203#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 286202#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 286201#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 286200#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 286199#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 286198#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 286197#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 272951#L1053-2 [2021-12-19 19:16:00,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,796 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2021-12-19 19:16:00,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430091154] [2021-12-19 19:16:00,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:00,808 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:00,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:00,844 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:00,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:00,844 INFO L85 PathProgramCache]: Analyzing trace with hash -691179489, now seen corresponding path program 1 times [2021-12-19 19:16:00,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:00,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944039697] [2021-12-19 19:16:00,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:00,845 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:00,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:00,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:00,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:00,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944039697] [2021-12-19 19:16:00,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944039697] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:00,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:00,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:00,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442579673] [2021-12-19 19:16:00,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:00,865 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:00,865 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:00,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:00,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:00,866 INFO L87 Difference]: Start difference. First operand 14922 states and 21109 transitions. cyclomatic complexity: 6189 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:00,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:00,912 INFO L93 Difference]: Finished difference Result 17065 states and 24106 transitions. [2021-12-19 19:16:00,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:00,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17065 states and 24106 transitions. [2021-12-19 19:16:00,965 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16896 [2021-12-19 19:16:00,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17065 states to 17065 states and 24106 transitions. [2021-12-19 19:16:00,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17065 [2021-12-19 19:16:01,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17065 [2021-12-19 19:16:01,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17065 states and 24106 transitions. [2021-12-19 19:16:01,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:01,015 INFO L681 BuchiCegarLoop]: Abstraction has 17065 states and 24106 transitions. [2021-12-19 19:16:01,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17065 states and 24106 transitions. [2021-12-19 19:16:01,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17065 to 17065. [2021-12-19 19:16:01,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17065 states, 17065 states have (on average 1.4125988866100205) internal successors, (24106), 17064 states have internal predecessors, (24106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17065 states to 17065 states and 24106 transitions. [2021-12-19 19:16:01,165 INFO L704 BuchiCegarLoop]: Abstraction has 17065 states and 24106 transitions. [2021-12-19 19:16:01,165 INFO L587 BuchiCegarLoop]: Abstraction has 17065 states and 24106 transitions. [2021-12-19 19:16:01,166 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:16:01,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17065 states and 24106 transitions. [2021-12-19 19:16:01,211 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16896 [2021-12-19 19:16:01,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:01,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:01,214 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,214 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,218 INFO L791 eck$LassoCheckResult]: Stem: 305058#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 305004#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 304983#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 304956#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 304419#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 304420#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304760#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 304761#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 304681#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304474#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304475#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 304403#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 304404#L684 assume !(0 == ~M_E~0); 304903#L684-2 assume !(0 == ~T1_E~0); 304715#L689-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 304716#L694-1 assume !(0 == ~T3_E~0); 304713#L699-1 assume !(0 == ~T4_E~0); 304714#L704-1 assume !(0 == ~T5_E~0); 304668#L709-1 assume !(0 == ~T6_E~0); 304606#L714-1 assume !(0 == ~E_M~0); 304607#L719-1 assume !(0 == ~E_1~0); 304867#L724-1 assume !(0 == ~E_2~0); 304372#L729-1 assume !(0 == ~E_3~0); 304373#L734-1 assume !(0 == ~E_4~0); 305096#L739-1 assume !(0 == ~E_5~0); 304561#L744-1 assume !(0 == ~E_6~0); 304562#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 304870#L334 assume !(1 == ~m_pc~0); 305093#L334-2 is_master_triggered_~__retres1~0#1 := 0; 305092#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 305091#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 304534#L849 assume !(0 != activate_threads_~tmp~1#1); 304535#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 305090#L353 assume !(1 == ~t1_pc~0); 305089#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304764#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 304765#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 304733#L857 assume !(0 != activate_threads_~tmp___0~0#1); 304421#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304422#L372 assume !(1 == ~t2_pc~0); 304521#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 304520#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304651#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304933#L865 assume !(0 != activate_threads_~tmp___1~0#1); 304934#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 305082#L391 assume !(1 == ~t3_pc~0); 304243#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 304244#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 304454#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 304657#L873 assume !(0 != activate_threads_~tmp___2~0#1); 304860#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 305078#L410 assume !(1 == ~t4_pc~0); 304784#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 304785#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304830#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 305076#L881 assume !(0 != activate_threads_~tmp___3~0#1); 304548#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304549#L429 assume !(1 == ~t5_pc~0); 304376#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 304377#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304307#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 304308#L889 assume !(0 != activate_threads_~tmp___4~0#1); 304793#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 304820#L448 assume !(1 == ~t6_pc~0); 305068#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 304789#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304790#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304882#L897 assume !(0 != activate_threads_~tmp___5~0#1); 305066#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 305065#L762 assume !(1 == ~M_E~0); 305064#L762-2 assume !(1 == ~T1_E~0); 305022#L767-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 304986#L772-1 assume !(1 == ~T3_E~0); 304821#L777-1 assume !(1 == ~T4_E~0); 304695#L782-1 assume !(1 == ~T5_E~0); 304407#L787-1 assume !(1 == ~T6_E~0); 304405#L792-1 assume !(1 == ~E_M~0); 304406#L797-1 assume !(1 == ~E_1~0); 304442#L802-1 assume !(1 == ~E_2~0); 304663#L807-1 assume !(1 == ~E_3~0); 304664#L812-1 assume !(1 == ~E_4~0); 304944#L817-1 assume !(1 == ~E_5~0); 304720#L822-1 assume !(1 == ~E_6~0); 304721#L827-1 assume { :end_inline_reset_delta_events } true; 304957#L1053-2 [2021-12-19 19:16:01,218 INFO L793 eck$LassoCheckResult]: Loop: 304957#L1053-2 assume !false; 310883#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 310881#L659 assume !false; 310879#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 310874#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 310867#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 310864#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 310861#L570 assume !(0 != eval_~tmp~0#1); 310862#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 313042#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 313038#L684-3 assume !(0 == ~M_E~0); 313034#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 313028#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 313029#L694-3 assume !(0 == ~T3_E~0); 313053#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 313050#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 313047#L709-3 assume !(0 == ~T6_E~0); 313044#L714-3 assume !(0 == ~E_M~0); 313040#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 313036#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 313031#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 313025#L734-3 assume !(0 == ~E_4~0); 313021#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 312777#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 312776#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312775#L334-24 assume 1 == ~m_pc~0; 312773#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 312695#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312689#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 312688#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 312687#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312686#L353-24 assume !(1 == ~t1_pc~0); 312684#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 312680#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312676#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 312673#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312670#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312667#L372-24 assume 1 == ~t2_pc~0; 312661#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 312657#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312658#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 312918#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 312647#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312645#L391-24 assume !(1 == ~t3_pc~0); 312643#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 312640#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312637#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 312635#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 312633#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 311738#L410-24 assume !(1 == ~t4_pc~0); 311737#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 311735#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311732#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 311730#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 311728#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311726#L429-24 assume !(1 == ~t5_pc~0); 311724#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 311753#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311747#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 311713#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 311657#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 310981#L448-24 assume !(1 == ~t6_pc~0); 310979#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 310977#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 310975#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 310973#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 310971#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 310969#L762-3 assume !(1 == ~M_E~0); 309209#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 310968#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 310966#L772-3 assume !(1 == ~T3_E~0); 310965#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 310964#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 310963#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 310962#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 310960#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 310958#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 310956#L807-3 assume !(1 == ~E_3~0); 310954#L812-3 assume !(1 == ~E_4~0); 310952#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 310950#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 310948#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 310943#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 310936#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 310934#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 310933#L1072 assume !(0 == start_simulation_~tmp~3#1); 310931#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 310918#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 310916#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 310915#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 310914#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 310913#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 310912#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 310911#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 304957#L1053-2 [2021-12-19 19:16:01,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,219 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2021-12-19 19:16:01,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300454958] [2021-12-19 19:16:01,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,242 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300454958] [2021-12-19 19:16:01,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300454958] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,242 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,243 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:01,243 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306772008] [2021-12-19 19:16:01,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,243 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:01,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1662305312, now seen corresponding path program 1 times [2021-12-19 19:16:01,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959531292] [2021-12-19 19:16:01,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,263 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959531292] [2021-12-19 19:16:01,263 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959531292] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:01,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811788150] [2021-12-19 19:16:01,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:01,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:01,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:01,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:01,266 INFO L87 Difference]: Start difference. First operand 17065 states and 24106 transitions. cyclomatic complexity: 7043 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:01,341 INFO L93 Difference]: Finished difference Result 21710 states and 30601 transitions. [2021-12-19 19:16:01,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:01,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21710 states and 30601 transitions. [2021-12-19 19:16:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21584 [2021-12-19 19:16:01,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21710 states to 21710 states and 30601 transitions. [2021-12-19 19:16:01,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21710 [2021-12-19 19:16:01,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21710 [2021-12-19 19:16:01,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21710 states and 30601 transitions. [2021-12-19 19:16:01,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:01,539 INFO L681 BuchiCegarLoop]: Abstraction has 21710 states and 30601 transitions. [2021-12-19 19:16:01,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21710 states and 30601 transitions. [2021-12-19 19:16:01,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21710 to 14922. [2021-12-19 19:16:01,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14922 states, 14922 states have (on average 1.4124112049323148) internal successors, (21076), 14921 states have internal predecessors, (21076), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14922 states to 14922 states and 21076 transitions. [2021-12-19 19:16:01,675 INFO L704 BuchiCegarLoop]: Abstraction has 14922 states and 21076 transitions. [2021-12-19 19:16:01,676 INFO L587 BuchiCegarLoop]: Abstraction has 14922 states and 21076 transitions. [2021-12-19 19:16:01,676 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:16:01,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14922 states and 21076 transitions. [2021-12-19 19:16:01,709 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14816 [2021-12-19 19:16:01,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:01,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:01,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,711 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:01,711 INFO L791 eck$LassoCheckResult]: Stem: 343831#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 343773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 343756#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 343731#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 343204#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 343205#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 343554#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 343555#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 343475#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 343258#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 343259#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 343188#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 343189#L684 assume !(0 == ~M_E~0); 343685#L684-2 assume !(0 == ~T1_E~0); 343510#L689-1 assume !(0 == ~T2_E~0); 343511#L694-1 assume !(0 == ~T3_E~0); 343508#L699-1 assume !(0 == ~T4_E~0); 343509#L704-1 assume !(0 == ~T5_E~0); 343461#L709-1 assume !(0 == ~T6_E~0); 343398#L714-1 assume !(0 == ~E_M~0); 343399#L719-1 assume !(0 == ~E_1~0); 343656#L724-1 assume !(0 == ~E_2~0); 343157#L729-1 assume !(0 == ~E_3~0); 343158#L734-1 assume !(0 == ~E_4~0); 343722#L739-1 assume !(0 == ~E_5~0); 343350#L744-1 assume !(0 == ~E_6~0); 343351#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343117#L334 assume !(1 == ~m_pc~0); 343118#L334-2 is_master_triggered_~__retres1~0#1 := 0; 343450#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343151#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 343152#L849 assume !(0 != activate_threads_~tmp~1#1); 343324#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343254#L353 assume !(1 == ~t1_pc~0); 343255#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 343558#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343167#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 343168#L857 assume !(0 != activate_threads_~tmp___0~0#1); 343206#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343207#L372 assume !(1 == ~t2_pc~0); 343309#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 343308#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343443#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 343713#L865 assume !(0 != activate_threads_~tmp___1~0#1); 343106#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343107#L391 assume !(1 == ~t3_pc~0); 343027#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 343028#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343238#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 343449#L873 assume !(0 != activate_threads_~tmp___2~0#1); 343328#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343329#L410 assume !(1 == ~t4_pc~0); 343574#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 343575#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 343616#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343715#L881 assume !(0 != activate_threads_~tmp___3~0#1); 343337#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 343338#L429 assume !(1 == ~t5_pc~0); 343161#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 343162#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343091#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343092#L889 assume !(0 != activate_threads_~tmp___4~0#1); 343582#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343319#L448 assume !(1 == ~t6_pc~0); 343239#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 343240#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343580#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 343752#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343818#L762 assume !(1 == ~M_E~0); 343378#L762-2 assume !(1 == ~T1_E~0); 343379#L767-1 assume !(1 == ~T2_E~0); 343759#L772-1 assume !(1 == ~T3_E~0); 343608#L777-1 assume !(1 == ~T4_E~0); 343490#L782-1 assume !(1 == ~T5_E~0); 343192#L787-1 assume !(1 == ~T6_E~0); 343190#L792-1 assume !(1 == ~E_M~0); 343191#L797-1 assume !(1 == ~E_1~0); 343226#L802-1 assume !(1 == ~E_2~0); 343456#L807-1 assume !(1 == ~E_3~0); 343457#L812-1 assume !(1 == ~E_4~0); 343720#L817-1 assume !(1 == ~E_5~0); 343514#L822-1 assume !(1 == ~E_6~0); 343515#L827-1 assume { :end_inline_reset_delta_events } true; 343732#L1053-2 [2021-12-19 19:16:01,712 INFO L793 eck$LassoCheckResult]: Loop: 343732#L1053-2 assume !false; 356580#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 353625#L659 assume !false; 356571#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 356566#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 356559#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 356557#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 356556#L570 assume !(0 != eval_~tmp~0#1); 343595#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343559#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343481#L684-3 assume !(0 == ~M_E~0); 343482#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 343021#L689-3 assume !(0 == ~T2_E~0); 343022#L694-3 assume !(0 == ~T3_E~0); 343079#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 343080#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 343588#L709-3 assume !(0 == ~T6_E~0); 343571#L714-3 assume !(0 == ~E_M~0); 343365#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343073#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 343074#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 343548#L734-3 assume !(0 == ~E_4~0); 343593#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 343594#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 343716#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343086#L334-24 assume 1 == ~m_pc~0; 343087#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 343223#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343562#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 343057#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 343058#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343589#L353-24 assume !(1 == ~t1_pc~0); 343590#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 357859#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357857#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 343780#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343108#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343109#L372-24 assume !(1 == ~t2_pc~0); 343068#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 343067#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 357801#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 343744#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 343745#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 343826#L391-24 assume !(1 == ~t3_pc~0); 357321#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 357315#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357310#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 357305#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 357300#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357294#L410-24 assume !(1 == ~t4_pc~0); 351104#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 357283#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357278#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 357273#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 357268#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 357261#L429-24 assume 1 == ~t5_pc~0; 357257#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 357251#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 357245#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 357239#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 357235#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350340#L448-24 assume !(1 == ~t6_pc~0); 350338#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 350337#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350335#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350333#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 350331#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350329#L762-3 assume !(1 == ~M_E~0); 350009#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 350326#L767-3 assume !(1 == ~T2_E~0); 350324#L772-3 assume !(1 == ~T3_E~0); 350322#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 350320#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 350318#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 350316#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 350314#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 350312#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 350311#L807-3 assume !(1 == ~E_3~0); 350310#L812-3 assume !(1 == ~E_4~0); 350309#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 350308#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 350307#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 350305#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 350299#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 350298#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 350296#L1072 assume !(0 == start_simulation_~tmp~3#1); 350297#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 356597#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 356593#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 356591#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 356589#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 356587#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 356584#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 356582#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 343732#L1053-2 [2021-12-19 19:16:01,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,712 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2021-12-19 19:16:01,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,712 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68445061] [2021-12-19 19:16:01,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,713 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:01,718 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:01,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:01,747 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:01,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:01,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1115845790, now seen corresponding path program 1 times [2021-12-19 19:16:01,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:01,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038732347] [2021-12-19 19:16:01,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:01,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:01,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:01,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:01,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:01,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038732347] [2021-12-19 19:16:01,765 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038732347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:01,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:01,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:01,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821246882] [2021-12-19 19:16:01,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:01,767 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:01,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:01,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:01,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:01,768 INFO L87 Difference]: Start difference. First operand 14922 states and 21076 transitions. cyclomatic complexity: 6156 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:01,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:01,869 INFO L93 Difference]: Finished difference Result 26241 states and 36830 transitions. [2021-12-19 19:16:01,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:01,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26241 states and 36830 transitions. [2021-12-19 19:16:01,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26056 [2021-12-19 19:16:02,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26241 states to 26241 states and 36830 transitions. [2021-12-19 19:16:02,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26241 [2021-12-19 19:16:02,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26241 [2021-12-19 19:16:02,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26241 states and 36830 transitions. [2021-12-19 19:16:02,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:02,121 INFO L681 BuchiCegarLoop]: Abstraction has 26241 states and 36830 transitions. [2021-12-19 19:16:02,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26241 states and 36830 transitions. [2021-12-19 19:16:02,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26241 to 26209. [2021-12-19 19:16:02,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26209 states, 26209 states have (on average 1.4040215193254226) internal successors, (36798), 26208 states have internal predecessors, (36798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:02,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26209 states to 26209 states and 36798 transitions. [2021-12-19 19:16:02,548 INFO L704 BuchiCegarLoop]: Abstraction has 26209 states and 36798 transitions. [2021-12-19 19:16:02,562 INFO L587 BuchiCegarLoop]: Abstraction has 26209 states and 36798 transitions. [2021-12-19 19:16:02,562 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:16:02,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26209 states and 36798 transitions. [2021-12-19 19:16:02,623 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26024 [2021-12-19 19:16:02,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:02,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:02,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:02,655 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:02,655 INFO L791 eck$LassoCheckResult]: Stem: 385047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 384985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 384965#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 384937#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 384370#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 384371#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 384734#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 384735#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 384645#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 384426#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 384427#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 384354#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 384355#L684 assume !(0 == ~M_E~0); 384882#L684-2 assume !(0 == ~T1_E~0); 384687#L689-1 assume !(0 == ~T2_E~0); 384688#L694-1 assume !(0 == ~T3_E~0); 384685#L699-1 assume !(0 == ~T4_E~0); 384686#L704-1 assume !(0 == ~T5_E~0); 384629#L709-1 assume !(0 == ~T6_E~0); 384562#L714-1 assume !(0 == ~E_M~0); 384563#L719-1 assume !(0 == ~E_1~0); 384845#L724-1 assume !(0 == ~E_2~0); 384326#L729-1 assume 0 == ~E_3~0;~E_3~0 := 1; 384327#L734-1 assume !(0 == ~E_4~0); 384930#L739-1 assume !(0 == ~E_5~0); 384931#L744-1 assume !(0 == ~E_6~0); 385088#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 384286#L334 assume !(1 == ~m_pc~0); 384287#L334-2 is_master_triggered_~__retres1~0#1 := 0; 384620#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 384320#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 384321#L849 assume !(0 != activate_threads_~tmp~1#1); 385083#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 385082#L353 assume !(1 == ~t1_pc~0); 385081#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 384739#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 384740#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 384704#L857 assume !(0 != activate_threads_~tmp___0~0#1); 384374#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 384375#L372 assume !(1 == ~t2_pc~0); 384478#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 384477#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 384613#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 384916#L865 assume !(0 != activate_threads_~tmp___1~0#1); 384917#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 385076#L391 assume !(1 == ~t3_pc~0); 384194#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 384195#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 384407#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 384617#L873 assume !(0 != activate_threads_~tmp___2~0#1); 384839#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 385072#L410 assume !(1 == ~t4_pc~0); 384758#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 384759#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 384807#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 385070#L881 assume !(0 != activate_threads_~tmp___3~0#1); 384503#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 384504#L429 assume !(1 == ~t5_pc~0); 384331#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 384332#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 385090#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 384766#L889 assume !(0 != activate_threads_~tmp___4~0#1); 384767#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 384794#L448 assume !(1 == ~t6_pc~0); 385062#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 385061#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 385060#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 384960#L897 assume !(0 != activate_threads_~tmp___5~0#1); 384961#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 385027#L762 assume !(1 == ~M_E~0); 384541#L762-2 assume !(1 == ~T1_E~0); 384542#L767-1 assume !(1 == ~T2_E~0); 384968#L772-1 assume !(1 == ~T3_E~0); 384795#L777-1 assume !(1 == ~T4_E~0); 384796#L782-1 assume !(1 == ~T5_E~0); 384360#L787-1 assume !(1 == ~T6_E~0); 384358#L792-1 assume !(1 == ~E_M~0); 384359#L797-1 assume !(1 == ~E_1~0); 384394#L802-1 assume !(1 == ~E_2~0); 384623#L807-1 assume 1 == ~E_3~0;~E_3~0 := 2; 384624#L812-1 assume !(1 == ~E_4~0); 384924#L817-1 assume !(1 == ~E_5~0); 384689#L822-1 assume !(1 == ~E_6~0); 384690#L827-1 assume { :end_inline_reset_delta_events } true; 384938#L1053-2 [2021-12-19 19:16:02,655 INFO L793 eck$LassoCheckResult]: Loop: 384938#L1053-2 assume !false; 393388#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 393382#L659 assume !false; 393379#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 393288#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 393281#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 393279#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 393277#L570 assume !(0 != eval_~tmp~0#1); 393278#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 396235#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396233#L684-3 assume !(0 == ~M_E~0); 396231#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396228#L689-3 assume !(0 == ~T2_E~0); 396225#L694-3 assume !(0 == ~T3_E~0); 396221#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 396218#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 396215#L709-3 assume !(0 == ~T6_E~0); 396212#L714-3 assume !(0 == ~E_M~0); 396209#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 396206#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 396202#L729-3 assume !(0 == ~E_3~0); 396203#L734-3 assume !(0 == ~E_4~0); 396360#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 396358#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 396356#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396353#L334-24 assume 1 == ~m_pc~0; 396350#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 396348#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396346#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396344#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 396342#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396340#L353-24 assume !(1 == ~t1_pc~0); 396338#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 396336#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396334#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396332#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 396330#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396327#L372-24 assume 1 == ~t2_pc~0; 396324#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 396322#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396320#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396318#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 394551#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393960#L391-24 assume !(1 == ~t3_pc~0); 393958#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 393956#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393954#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393952#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393948#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393946#L410-24 assume !(1 == ~t4_pc~0); 391143#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 393940#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393936#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393934#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393932#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 393931#L429-24 assume 1 == ~t5_pc~0; 393930#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 393928#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393926#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 393923#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 393922#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393914#L448-24 assume !(1 == ~t6_pc~0); 390737#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 393911#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393908#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393906#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 393904#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 393902#L762-3 assume !(1 == ~M_E~0); 393181#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 385276#L767-3 assume !(1 == ~T2_E~0); 385270#L772-3 assume !(1 == ~T3_E~0); 385264#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 385258#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 385252#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 385245#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 385239#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 385233#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 385226#L807-3 assume !(1 == ~E_3~0); 385221#L812-3 assume !(1 == ~E_4~0); 385217#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 385214#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 385211#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 385205#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 385184#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 385180#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 385137#L1072 assume !(0 == start_simulation_~tmp~3#1); 385138#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 393435#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 393433#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 393431#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 393412#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 393409#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 393404#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 393403#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 384938#L1053-2 [2021-12-19 19:16:02,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:02,656 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2021-12-19 19:16:02,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:02,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844860420] [2021-12-19 19:16:02,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:02,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:02,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:02,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:02,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:02,678 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844860420] [2021-12-19 19:16:02,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844860420] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:02,678 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:02,678 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:02,678 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756593490] [2021-12-19 19:16:02,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:02,678 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:02,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:02,679 INFO L85 PathProgramCache]: Analyzing trace with hash 1762801307, now seen corresponding path program 1 times [2021-12-19 19:16:02,679 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:02,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757914754] [2021-12-19 19:16:02,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:02,679 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:02,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:02,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:02,699 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:02,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757914754] [2021-12-19 19:16:02,700 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757914754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:02,700 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:02,700 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:02,700 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905054613] [2021-12-19 19:16:02,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:02,700 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:02,700 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:02,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:02,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:02,701 INFO L87 Difference]: Start difference. First operand 26209 states and 36798 transitions. cyclomatic complexity: 10591 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:02,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:02,873 INFO L93 Difference]: Finished difference Result 37538 states and 52621 transitions. [2021-12-19 19:16:02,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:02,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37538 states and 52621 transitions. [2021-12-19 19:16:03,022 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36140 [2021-12-19 19:16:03,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37538 states to 37538 states and 52621 transitions. [2021-12-19 19:16:03,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37538 [2021-12-19 19:16:03,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37538 [2021-12-19 19:16:03,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37538 states and 52621 transitions. [2021-12-19 19:16:03,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:03,288 INFO L681 BuchiCegarLoop]: Abstraction has 37538 states and 52621 transitions. [2021-12-19 19:16:03,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37538 states and 52621 transitions. [2021-12-19 19:16:03,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37538 to 26146. [2021-12-19 19:16:03,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26146 states, 26146 states have (on average 1.4028532089038477) internal successors, (36679), 26145 states have internal predecessors, (36679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:03,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26146 states to 26146 states and 36679 transitions. [2021-12-19 19:16:03,528 INFO L704 BuchiCegarLoop]: Abstraction has 26146 states and 36679 transitions. [2021-12-19 19:16:03,528 INFO L587 BuchiCegarLoop]: Abstraction has 26146 states and 36679 transitions. [2021-12-19 19:16:03,528 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:16:03,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26146 states and 36679 transitions. [2021-12-19 19:16:03,595 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26024 [2021-12-19 19:16:03,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:03,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:03,599 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,599 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,606 INFO L791 eck$LassoCheckResult]: Stem: 448753#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 448690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 448678#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 448649#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 448128#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 448129#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 448472#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 448473#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 448394#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 448183#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 448184#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 448112#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 448113#L684 assume !(0 == ~M_E~0); 448603#L684-2 assume !(0 == ~T1_E~0); 448427#L689-1 assume !(0 == ~T2_E~0); 448428#L694-1 assume !(0 == ~T3_E~0); 448425#L699-1 assume !(0 == ~T4_E~0); 448426#L704-1 assume !(0 == ~T5_E~0); 448379#L709-1 assume !(0 == ~T6_E~0); 448317#L714-1 assume !(0 == ~E_M~0); 448318#L719-1 assume !(0 == ~E_1~0); 448574#L724-1 assume !(0 == ~E_2~0); 448085#L729-1 assume !(0 == ~E_3~0); 448086#L734-1 assume !(0 == ~E_4~0); 448644#L739-1 assume !(0 == ~E_5~0); 448272#L744-1 assume !(0 == ~E_6~0); 448273#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 448045#L334 assume !(1 == ~m_pc~0); 448046#L334-2 is_master_triggered_~__retres1~0#1 := 0; 448370#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 448079#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 448080#L849 assume !(0 != activate_threads_~tmp~1#1); 448246#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 448179#L353 assume !(1 == ~t1_pc~0); 448180#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 448477#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 448095#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 448096#L857 assume !(0 != activate_threads_~tmp___0~0#1); 448132#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 448133#L372 assume !(1 == ~t2_pc~0); 448231#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 448230#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 448364#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 448632#L865 assume !(0 != activate_threads_~tmp___1~0#1); 448032#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 448033#L391 assume !(1 == ~t3_pc~0); 447953#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 447954#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 448164#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 448368#L873 assume !(0 != activate_threads_~tmp___2~0#1); 448251#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 448252#L410 assume !(1 == ~t4_pc~0); 448492#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 448493#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 448537#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 448633#L881 assume !(0 != activate_threads_~tmp___3~0#1); 448258#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 448259#L429 assume !(1 == ~t5_pc~0); 448089#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 448090#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 448017#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 448018#L889 assume !(0 != activate_threads_~tmp___4~0#1); 448500#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 448239#L448 assume !(1 == ~t6_pc~0); 448165#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 448166#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 448497#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 448586#L897 assume !(0 != activate_threads_~tmp___5~0#1); 448674#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448735#L762 assume !(1 == ~M_E~0); 448296#L762-2 assume !(1 == ~T1_E~0); 448297#L767-1 assume !(1 == ~T2_E~0); 448681#L772-1 assume !(1 == ~T3_E~0); 448527#L777-1 assume !(1 == ~T4_E~0); 448407#L782-1 assume !(1 == ~T5_E~0); 448118#L787-1 assume !(1 == ~T6_E~0); 448116#L792-1 assume !(1 == ~E_M~0); 448117#L797-1 assume !(1 == ~E_1~0); 448151#L802-1 assume !(1 == ~E_2~0); 448373#L807-1 assume !(1 == ~E_3~0); 448374#L812-1 assume !(1 == ~E_4~0); 448639#L817-1 assume !(1 == ~E_5~0); 448429#L822-1 assume !(1 == ~E_6~0); 448430#L827-1 assume { :end_inline_reset_delta_events } true; 448650#L1053-2 [2021-12-19 19:16:03,606 INFO L793 eck$LassoCheckResult]: Loop: 448650#L1053-2 assume !false; 465663#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 465659#L659 assume !false; 465656#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 465648#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 465640#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 465637#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 465633#L570 assume !(0 != eval_~tmp~0#1); 465634#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 448478#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 448397#L684-3 assume !(0 == ~M_E~0); 448398#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 447949#L689-3 assume !(0 == ~T2_E~0); 447950#L694-3 assume !(0 == ~T3_E~0); 448007#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 448008#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 448507#L709-3 assume !(0 == ~T6_E~0); 448488#L714-3 assume !(0 == ~E_M~0); 448283#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 448001#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 448002#L729-3 assume !(0 == ~E_3~0); 448464#L734-3 assume !(0 == ~E_4~0); 448514#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 448515#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 448635#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 448014#L334-24 assume 1 == ~m_pc~0; 448015#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 448150#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 448483#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 447985#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 447986#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 448510#L353-24 assume !(1 == ~t1_pc~0); 448511#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 448683#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 448684#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 448696#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 448036#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 448037#L372-24 assume !(1 == ~t2_pc~0); 447996#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 447995#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 448134#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 448135#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 448668#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 448321#L391-24 assume !(1 == ~t3_pc~0); 448322#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 473082#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 473080#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 473078#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 473076#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 473074#L410-24 assume !(1 == ~t4_pc~0); 471524#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 473071#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 473069#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 473065#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 473063#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472600#L429-24 assume 1 == ~t5_pc~0; 472598#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 472599#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472709#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 472588#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 472586#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 462500#L448-24 assume !(1 == ~t6_pc~0); 462498#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 462496#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 462471#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 462463#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 462453#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462445#L762-3 assume !(1 == ~M_E~0); 457417#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 462433#L767-3 assume !(1 == ~T2_E~0); 462424#L772-3 assume !(1 == ~T3_E~0); 462415#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 462407#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 462400#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 462391#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 462382#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 462373#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 462364#L807-3 assume !(1 == ~E_3~0); 462357#L812-3 assume !(1 == ~E_4~0); 462351#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 462346#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 462341#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 462281#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 462265#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 462261#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 448844#L1072 assume !(0 == start_simulation_~tmp~3#1); 448845#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 465709#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 465707#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 465705#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 465703#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 465701#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 465699#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 465697#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 448650#L1053-2 [2021-12-19 19:16:03,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,608 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2021-12-19 19:16:03,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859944582] [2021-12-19 19:16:03,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:03,635 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:03,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:03,664 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:03,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,665 INFO L85 PathProgramCache]: Analyzing trace with hash 2003068636, now seen corresponding path program 1 times [2021-12-19 19:16:03,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831154733] [2021-12-19 19:16:03,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:03,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:03,702 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:03,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831154733] [2021-12-19 19:16:03,702 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831154733] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:03,702 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:03,702 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:03,703 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735551268] [2021-12-19 19:16:03,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:03,703 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:03,704 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:03,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:03,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:03,704 INFO L87 Difference]: Start difference. First operand 26146 states and 36679 transitions. cyclomatic complexity: 10535 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:03,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:03,916 INFO L93 Difference]: Finished difference Result 46970 states and 65267 transitions. [2021-12-19 19:16:03,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:16:03,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46970 states and 65267 transitions. [2021-12-19 19:16:04,249 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 46816 [2021-12-19 19:16:04,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46970 states to 46970 states and 65267 transitions. [2021-12-19 19:16:04,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46970 [2021-12-19 19:16:04,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46970 [2021-12-19 19:16:04,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46970 states and 65267 transitions. [2021-12-19 19:16:04,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,395 INFO L681 BuchiCegarLoop]: Abstraction has 46970 states and 65267 transitions. [2021-12-19 19:16:04,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46970 states and 65267 transitions. [2021-12-19 19:16:04,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46970 to 26338. [2021-12-19 19:16:04,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26338 states, 26338 states have (on average 1.399916470498899) internal successors, (36871), 26337 states have internal predecessors, (36871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26338 states to 26338 states and 36871 transitions. [2021-12-19 19:16:04,707 INFO L704 BuchiCegarLoop]: Abstraction has 26338 states and 36871 transitions. [2021-12-19 19:16:04,707 INFO L587 BuchiCegarLoop]: Abstraction has 26338 states and 36871 transitions. [2021-12-19 19:16:04,707 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:16:04,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26338 states and 36871 transitions. [2021-12-19 19:16:04,782 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26216 [2021-12-19 19:16:04,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,785 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,785 INFO L791 eck$LassoCheckResult]: Stem: 521894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 521837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 521819#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521788#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521260#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 521261#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 521610#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 521611#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 521529#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 521316#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 521317#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 521244#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 521245#L684 assume !(0 == ~M_E~0); 521738#L684-2 assume !(0 == ~T1_E~0); 521564#L689-1 assume !(0 == ~T2_E~0); 521565#L694-1 assume !(0 == ~T3_E~0); 521562#L699-1 assume !(0 == ~T4_E~0); 521563#L704-1 assume !(0 == ~T5_E~0); 521515#L709-1 assume !(0 == ~T6_E~0); 521449#L714-1 assume !(0 == ~E_M~0); 521450#L719-1 assume !(0 == ~E_1~0); 521706#L724-1 assume !(0 == ~E_2~0); 521216#L729-1 assume !(0 == ~E_3~0); 521217#L734-1 assume !(0 == ~E_4~0); 521780#L739-1 assume !(0 == ~E_5~0); 521407#L744-1 assume !(0 == ~E_6~0); 521408#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 521176#L334 assume !(1 == ~m_pc~0); 521177#L334-2 is_master_triggered_~__retres1~0#1 := 0; 521505#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 521210#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 521211#L849 assume !(0 != activate_threads_~tmp~1#1); 521381#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 521312#L353 assume !(1 == ~t1_pc~0); 521313#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 521616#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521226#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 521227#L857 assume !(0 != activate_threads_~tmp___0~0#1); 521264#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 521265#L372 assume !(1 == ~t2_pc~0); 521366#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 521365#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 521498#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 521766#L865 assume !(0 != activate_threads_~tmp___1~0#1); 521163#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 521164#L391 assume !(1 == ~t3_pc~0); 521085#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 521086#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 521297#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 521502#L873 assume !(0 != activate_threads_~tmp___2~0#1); 521386#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 521387#L410 assume !(1 == ~t4_pc~0); 521631#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 521632#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521673#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 521767#L881 assume !(0 != activate_threads_~tmp___3~0#1); 521393#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 521394#L429 assume !(1 == ~t5_pc~0); 521220#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 521221#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 521148#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 521149#L889 assume !(0 != activate_threads_~tmp___4~0#1); 521640#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 521374#L448 assume !(1 == ~t6_pc~0); 521298#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 521299#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 521636#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 521718#L897 assume !(0 != activate_threads_~tmp___5~0#1); 521815#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 521877#L762 assume !(1 == ~M_E~0); 521428#L762-2 assume !(1 == ~T1_E~0); 521429#L767-1 assume !(1 == ~T2_E~0); 521821#L772-1 assume !(1 == ~T3_E~0); 521664#L777-1 assume !(1 == ~T4_E~0); 521543#L782-1 assume !(1 == ~T5_E~0); 521250#L787-1 assume !(1 == ~T6_E~0); 521248#L792-1 assume !(1 == ~E_M~0); 521249#L797-1 assume !(1 == ~E_1~0); 521283#L802-1 assume !(1 == ~E_2~0); 521509#L807-1 assume !(1 == ~E_3~0); 521510#L812-1 assume !(1 == ~E_4~0); 521774#L817-1 assume !(1 == ~E_5~0); 521566#L822-1 assume !(1 == ~E_6~0); 521567#L827-1 assume { :end_inline_reset_delta_events } true; 521789#L1053-2 [2021-12-19 19:16:04,786 INFO L793 eck$LassoCheckResult]: Loop: 521789#L1053-2 assume !false; 545917#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 545886#L659 assume !false; 545879#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 545864#L518 assume !(0 == ~m_st~0); 545865#L522 assume !(0 == ~t1_st~0); 545860#L526 assume !(0 == ~t2_st~0); 545861#L530 assume !(0 == ~t3_st~0); 545863#L534 assume !(0 == ~t4_st~0); 545858#L538 assume !(0 == ~t5_st~0); 545859#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 545862#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 533268#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 533269#L570 assume !(0 != eval_~tmp~0#1); 545811#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 546170#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 546169#L684-3 assume !(0 == ~M_E~0); 546168#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 546167#L689-3 assume !(0 == ~T2_E~0); 546166#L694-3 assume !(0 == ~T3_E~0); 546165#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 546164#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 546163#L709-3 assume !(0 == ~T6_E~0); 546162#L714-3 assume !(0 == ~E_M~0); 546161#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 546160#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 546159#L729-3 assume !(0 == ~E_3~0); 546158#L734-3 assume !(0 == ~E_4~0); 546157#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 546156#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 546155#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 546154#L334-24 assume 1 == ~m_pc~0; 546152#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 546151#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 546150#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 546149#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 546148#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 546147#L353-24 assume !(1 == ~t1_pc~0); 546146#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 546145#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 546144#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 546143#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 546142#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 546141#L372-24 assume 1 == ~t2_pc~0; 546139#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 546138#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 546137#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 546136#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 546135#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 545503#L391-24 assume !(1 == ~t3_pc~0); 545501#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 545499#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 545497#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 545495#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 545493#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 545491#L410-24 assume !(1 == ~t4_pc~0); 542842#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 545489#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 545487#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 545485#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 545483#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 545481#L429-24 assume 1 == ~t5_pc~0; 545478#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 545474#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 545470#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 545466#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 545463#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 545461#L448-24 assume !(1 == ~t6_pc~0); 534263#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 545459#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 545457#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 545455#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 545453#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 545451#L762-3 assume !(1 == ~M_E~0); 545450#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 545434#L767-3 assume !(1 == ~T2_E~0); 545435#L772-3 assume !(1 == ~T3_E~0); 545415#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 545416#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 545399#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 545400#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 545357#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 545358#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 545343#L807-3 assume !(1 == ~E_3~0); 545344#L812-3 assume !(1 == ~E_4~0); 545334#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 545335#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 545330#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 545331#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 521971#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 521967#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 521942#L1072 assume !(0 == start_simulation_~tmp~3#1); 521943#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 546089#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 545952#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 545950#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 545948#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 545945#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 545944#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 545933#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 521789#L1053-2 [2021-12-19 19:16:04,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,799 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2021-12-19 19:16:04,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474915260] [2021-12-19 19:16:04,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:04,808 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:04,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:04,844 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:04,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,844 INFO L85 PathProgramCache]: Analyzing trace with hash -505289686, now seen corresponding path program 1 times [2021-12-19 19:16:04,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,845 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081586398] [2021-12-19 19:16:04,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,845 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081586398] [2021-12-19 19:16:04,886 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081586398] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,886 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:04,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793234089] [2021-12-19 19:16:04,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,886 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,887 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:04,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:04,887 INFO L87 Difference]: Start difference. First operand 26338 states and 36871 transitions. cyclomatic complexity: 10535 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,126 INFO L93 Difference]: Finished difference Result 51529 states and 71475 transitions. [2021-12-19 19:16:05,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-19 19:16:05,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51529 states and 71475 transitions. [2021-12-19 19:16:05,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51328 [2021-12-19 19:16:05,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51529 states to 51529 states and 71475 transitions. [2021-12-19 19:16:05,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51529 [2021-12-19 19:16:05,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51529 [2021-12-19 19:16:05,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51529 states and 71475 transitions. [2021-12-19 19:16:05,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,654 INFO L681 BuchiCegarLoop]: Abstraction has 51529 states and 71475 transitions. [2021-12-19 19:16:05,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51529 states and 71475 transitions. [2021-12-19 19:16:05,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51529 to 27445. [2021-12-19 19:16:05,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27445 states, 27445 states have (on average 1.3837857533248314) internal successors, (37978), 27444 states have internal predecessors, (37978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27445 states to 27445 states and 37978 transitions. [2021-12-19 19:16:05,950 INFO L704 BuchiCegarLoop]: Abstraction has 27445 states and 37978 transitions. [2021-12-19 19:16:05,950 INFO L587 BuchiCegarLoop]: Abstraction has 27445 states and 37978 transitions. [2021-12-19 19:16:05,950 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:16:05,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27445 states and 37978 transitions. [2021-12-19 19:16:06,027 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27320 [2021-12-19 19:16:06,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:06,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:06,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,031 INFO L791 eck$LassoCheckResult]: Stem: 599786#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 599731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 599709#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 599681#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 599144#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 599145#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 599499#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 599500#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 599415#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 599203#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 599204#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 599128#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 599129#L684 assume !(0 == ~M_E~0); 599636#L684-2 assume !(0 == ~T1_E~0); 599452#L689-1 assume !(0 == ~T2_E~0); 599453#L694-1 assume !(0 == ~T3_E~0); 599450#L699-1 assume !(0 == ~T4_E~0); 599451#L704-1 assume !(0 == ~T5_E~0); 599399#L709-1 assume !(0 == ~T6_E~0); 599336#L714-1 assume !(0 == ~E_M~0); 599337#L719-1 assume !(0 == ~E_1~0); 599604#L724-1 assume !(0 == ~E_2~0); 599098#L729-1 assume !(0 == ~E_3~0); 599099#L734-1 assume !(0 == ~E_4~0); 599674#L739-1 assume !(0 == ~E_5~0); 599289#L744-1 assume !(0 == ~E_6~0); 599290#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599059#L334 assume !(1 == ~m_pc~0); 599060#L334-2 is_master_triggered_~__retres1~0#1 := 0; 599390#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 599092#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 599093#L849 assume !(0 != activate_threads_~tmp~1#1); 599263#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 599199#L353 assume !(1 == ~t1_pc~0); 599200#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 599503#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 599108#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 599109#L857 assume !(0 != activate_threads_~tmp___0~0#1); 599148#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 599149#L372 assume !(1 == ~t2_pc~0); 599250#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 599273#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 599800#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 599799#L865 assume !(0 != activate_threads_~tmp___1~0#1); 599046#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 599047#L391 assume !(1 == ~t3_pc~0); 598966#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 598967#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 599184#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 599387#L873 assume !(0 != activate_threads_~tmp___2~0#1); 599267#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 599268#L410 assume !(1 == ~t4_pc~0); 599521#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 599522#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 599568#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 599664#L881 assume !(0 != activate_threads_~tmp___3~0#1); 599275#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 599276#L429 assume !(1 == ~t5_pc~0); 599102#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 599103#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 599030#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 599031#L889 assume !(0 != activate_threads_~tmp___4~0#1); 599530#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 599258#L448 assume !(1 == ~t6_pc~0); 599185#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 599186#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 599526#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 599617#L897 assume !(0 != activate_threads_~tmp___5~0#1); 599703#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 599769#L762 assume !(1 == ~M_E~0); 599313#L762-2 assume !(1 == ~T1_E~0); 599314#L767-1 assume !(1 == ~T2_E~0); 599712#L772-1 assume !(1 == ~T3_E~0); 599559#L777-1 assume !(1 == ~T4_E~0); 599430#L782-1 assume !(1 == ~T5_E~0); 599134#L787-1 assume !(1 == ~T6_E~0); 599132#L792-1 assume !(1 == ~E_M~0); 599133#L797-1 assume !(1 == ~E_1~0); 599170#L802-1 assume !(1 == ~E_2~0); 599393#L807-1 assume !(1 == ~E_3~0); 599394#L812-1 assume !(1 == ~E_4~0); 599669#L817-1 assume !(1 == ~E_5~0); 599454#L822-1 assume !(1 == ~E_6~0); 599455#L827-1 assume { :end_inline_reset_delta_events } true; 599682#L1053-2 [2021-12-19 19:16:06,031 INFO L793 eck$LassoCheckResult]: Loop: 599682#L1053-2 assume !false; 612364#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 610984#L659 assume !false; 612361#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 612354#L518 assume !(0 == ~m_st~0); 612355#L522 assume !(0 == ~t1_st~0); 612350#L526 assume !(0 == ~t2_st~0); 612351#L530 assume !(0 == ~t3_st~0); 612353#L534 assume !(0 == ~t4_st~0); 612348#L538 assume !(0 == ~t5_st~0); 612349#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 612352#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 625291#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 625289#L570 assume !(0 != eval_~tmp~0#1); 625287#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 625241#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 625238#L684-3 assume !(0 == ~M_E~0); 625236#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 625234#L689-3 assume !(0 == ~T2_E~0); 625232#L694-3 assume !(0 == ~T3_E~0); 625230#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 625229#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 625220#L709-3 assume !(0 == ~T6_E~0); 625217#L714-3 assume !(0 == ~E_M~0); 625214#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 625211#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 625208#L729-3 assume !(0 == ~E_3~0); 625206#L734-3 assume !(0 == ~E_4~0); 625203#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 625200#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 625196#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 625194#L334-24 assume !(1 == ~m_pc~0); 625192#L334-26 is_master_triggered_~__retres1~0#1 := 0; 625189#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 625187#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 625185#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625183#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 625181#L353-24 assume !(1 == ~t1_pc~0); 625179#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 625176#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625174#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 625172#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 625170#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 625169#L372-24 assume !(1 == ~t2_pc~0); 625167#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 625165#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 625163#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 625161#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 625159#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 625157#L391-24 assume !(1 == ~t3_pc~0); 611672#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 625154#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 625152#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 625150#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 625148#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 625146#L410-24 assume !(1 == ~t4_pc~0); 610160#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 625143#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 625141#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 625138#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 625135#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 625132#L429-24 assume !(1 == ~t5_pc~0); 625128#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 625122#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625117#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 625112#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 625106#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 625102#L448-24 assume !(1 == ~t6_pc~0); 611011#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 625094#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 625090#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 625086#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 625075#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 625069#L762-3 assume !(1 == ~M_E~0); 610193#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 625060#L767-3 assume !(1 == ~T2_E~0); 625055#L772-3 assume !(1 == ~T3_E~0); 625041#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 625036#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 625032#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 625029#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 625026#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 625022#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 625019#L807-3 assume !(1 == ~E_3~0); 599484#L812-3 assume !(1 == ~E_4~0); 599485#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 599598#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 599576#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 599358#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 599005#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 599395#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 599396#L1072 assume !(0 == start_simulation_~tmp~3#1); 599761#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 612374#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 612373#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 612372#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 612371#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 612370#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 612369#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 612367#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 599682#L1053-2 [2021-12-19 19:16:06,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,038 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2021-12-19 19:16:06,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544975453] [2021-12-19 19:16:06,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:06,047 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:06,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:06,081 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:06,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,082 INFO L85 PathProgramCache]: Analyzing trace with hash -928327377, now seen corresponding path program 1 times [2021-12-19 19:16:06,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426706058] [2021-12-19 19:16:06,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426706058] [2021-12-19 19:16:06,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426706058] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,142 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:06,142 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612947543] [2021-12-19 19:16:06,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,142 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:06,143 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:06,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:06,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:06,144 INFO L87 Difference]: Start difference. First operand 27445 states and 37978 transitions. cyclomatic complexity: 10535 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:06,425 INFO L93 Difference]: Finished difference Result 78960 states and 108327 transitions. [2021-12-19 19:16:06,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:06,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78960 states and 108327 transitions. [2021-12-19 19:16:07,026 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 78648 [2021-12-19 19:16:07,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78960 states to 78960 states and 108327 transitions. [2021-12-19 19:16:07,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78960 [2021-12-19 19:16:07,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78960 [2021-12-19 19:16:07,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78960 states and 108327 transitions. [2021-12-19 19:16:07,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:07,272 INFO L681 BuchiCegarLoop]: Abstraction has 78960 states and 108327 transitions. [2021-12-19 19:16:07,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78960 states and 108327 transitions. [2021-12-19 19:16:07,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78960 to 28552. [2021-12-19 19:16:07,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28552 states, 28552 states have (on average 1.3689058559820677) internal successors, (39085), 28551 states have internal predecessors, (39085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28552 states to 28552 states and 39085 transitions. [2021-12-19 19:16:07,619 INFO L704 BuchiCegarLoop]: Abstraction has 28552 states and 39085 transitions. [2021-12-19 19:16:07,619 INFO L587 BuchiCegarLoop]: Abstraction has 28552 states and 39085 transitions. [2021-12-19 19:16:07,619 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:16:07,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28552 states and 39085 transitions. [2021-12-19 19:16:07,678 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28424 [2021-12-19 19:16:07,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:07,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:07,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,682 INFO L791 eck$LassoCheckResult]: Stem: 706256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 706183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 706152#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 706118#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 705561#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 705562#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 705926#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 705927#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 705836#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 705617#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 705618#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 705545#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 705546#L684 assume !(0 == ~M_E~0); 706066#L684-2 assume !(0 == ~T1_E~0); 705876#L689-1 assume !(0 == ~T2_E~0); 705877#L694-1 assume !(0 == ~T3_E~0); 705874#L699-1 assume !(0 == ~T4_E~0); 705875#L704-1 assume !(0 == ~T5_E~0); 705823#L709-1 assume !(0 == ~T6_E~0); 705757#L714-1 assume !(0 == ~E_M~0); 705758#L719-1 assume !(0 == ~E_1~0); 706028#L724-1 assume !(0 == ~E_2~0); 705515#L729-1 assume !(0 == ~E_3~0); 705516#L734-1 assume !(0 == ~E_4~0); 706111#L739-1 assume !(0 == ~E_5~0); 705713#L744-1 assume !(0 == ~E_6~0); 705714#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 705475#L334 assume !(1 == ~m_pc~0); 705476#L334-2 is_master_triggered_~__retres1~0#1 := 0; 705812#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 706120#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 705684#L849 assume !(0 != activate_threads_~tmp~1#1); 705685#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 705613#L353 assume !(1 == ~t1_pc~0); 705614#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 705930#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 705525#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 705526#L857 assume !(0 != activate_threads_~tmp___0~0#1); 705563#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 705564#L372 assume !(1 == ~t2_pc~0); 705669#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 705696#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 706275#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 706273#L865 assume !(0 != activate_threads_~tmp___1~0#1); 705464#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 705465#L391 assume !(1 == ~t3_pc~0); 705386#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 705387#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 705598#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 705811#L873 assume !(0 != activate_threads_~tmp___2~0#1); 705690#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 705691#L410 assume !(1 == ~t4_pc~0); 705948#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 705949#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 705997#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 706101#L881 assume !(0 != activate_threads_~tmp___3~0#1); 705700#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 705701#L429 assume !(1 == ~t5_pc~0); 705519#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 705520#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 705449#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 705450#L889 assume !(0 != activate_threads_~tmp___4~0#1); 705956#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 705679#L448 assume !(1 == ~t6_pc~0); 705599#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 705600#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 705953#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 706046#L897 assume !(0 != activate_threads_~tmp___5~0#1); 706146#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 706227#L762 assume !(1 == ~M_E~0); 705737#L762-2 assume !(1 == ~T1_E~0); 705738#L767-1 assume !(1 == ~T2_E~0); 706155#L772-1 assume !(1 == ~T3_E~0); 705989#L777-1 assume !(1 == ~T4_E~0); 705852#L782-1 assume !(1 == ~T5_E~0); 705549#L787-1 assume !(1 == ~T6_E~0); 705547#L792-1 assume !(1 == ~E_M~0); 705548#L797-1 assume !(1 == ~E_1~0); 705586#L802-1 assume !(1 == ~E_2~0); 705818#L807-1 assume !(1 == ~E_3~0); 705819#L812-1 assume !(1 == ~E_4~0); 706109#L817-1 assume !(1 == ~E_5~0); 705880#L822-1 assume !(1 == ~E_6~0); 705881#L827-1 assume { :end_inline_reset_delta_events } true; 706119#L1053-2 [2021-12-19 19:16:07,683 INFO L793 eck$LassoCheckResult]: Loop: 706119#L1053-2 assume !false; 731824#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 721522#L659 assume !false; 731823#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 731822#L518 assume !(0 == ~m_st~0); 731821#L522 assume !(0 == ~t1_st~0); 731820#L526 assume !(0 == ~t2_st~0); 731818#L530 assume !(0 == ~t3_st~0); 731816#L534 assume !(0 == ~t4_st~0); 731814#L538 assume !(0 == ~t5_st~0); 731811#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 731808#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 731807#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 731801#L570 assume !(0 != eval_~tmp~0#1); 731776#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 731774#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 731772#L684-3 assume !(0 == ~M_E~0); 731770#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 731768#L689-3 assume !(0 == ~T2_E~0); 731766#L694-3 assume !(0 == ~T3_E~0); 731764#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 731751#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 731541#L709-3 assume !(0 == ~T6_E~0); 731539#L714-3 assume !(0 == ~E_M~0); 731537#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 731536#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 731535#L729-3 assume !(0 == ~E_3~0); 731533#L734-3 assume !(0 == ~E_4~0); 731531#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 731530#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 731525#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 731526#L334-24 assume !(1 == ~m_pc~0); 731520#L334-26 is_master_triggered_~__retres1~0#1 := 0; 731521#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 731512#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 731513#L849-24 assume !(0 != activate_threads_~tmp~1#1); 733809#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 733808#L353-24 assume !(1 == ~t1_pc~0); 733807#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 733806#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 733804#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 733802#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 733800#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 733797#L372-24 assume !(1 == ~t2_pc~0); 731484#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 731481#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 731478#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 731475#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 731474#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 731302#L391-24 assume !(1 == ~t3_pc~0); 731300#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 731298#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 731296#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 731294#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 731292#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 731289#L410-24 assume !(1 == ~t4_pc~0); 728056#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 731283#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 731103#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 731088#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 731010#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 730952#L429-24 assume 1 == ~t5_pc~0; 730950#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 730951#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 730965#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 730939#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 730937#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 730935#L448-24 assume !(1 == ~t6_pc~0); 715073#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 730931#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 730929#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 730928#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 730926#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 730894#L762-3 assume !(1 == ~M_E~0); 706452#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 706453#L767-3 assume !(1 == ~T2_E~0); 706440#L772-3 assume !(1 == ~T3_E~0); 706441#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 706428#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 706429#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 706417#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 706418#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 731867#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 731865#L807-3 assume !(1 == ~E_3~0); 706398#L812-3 assume !(1 == ~E_4~0); 706399#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 706393#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 706390#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 706391#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 731845#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 706365#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 706366#L1072 assume !(0 == start_simulation_~tmp~3#1); 731838#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 731831#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 731830#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 731829#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 731828#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 731827#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 731826#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 731825#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 706119#L1053-2 [2021-12-19 19:16:07,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,683 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2021-12-19 19:16:07,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788007995] [2021-12-19 19:16:07,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:07,688 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:07,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:07,882 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:07,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,883 INFO L85 PathProgramCache]: Analyzing trace with hash -813573330, now seen corresponding path program 1 times [2021-12-19 19:16:07,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022109521] [2021-12-19 19:16:07,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:07,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:07,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:07,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022109521] [2021-12-19 19:16:07,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022109521] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:07,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:07,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:07,898 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691495691] [2021-12-19 19:16:07,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:07,899 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:07,899 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:07,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:07,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:07,900 INFO L87 Difference]: Start difference. First operand 28552 states and 39085 transitions. cyclomatic complexity: 10535 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:08,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:08,057 INFO L93 Difference]: Finished difference Result 53360 states and 72249 transitions. [2021-12-19 19:16:08,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:08,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53360 states and 72249 transitions. [2021-12-19 19:16:08,289 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 53200 [2021-12-19 19:16:08,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53360 states to 53360 states and 72249 transitions. [2021-12-19 19:16:08,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53360 [2021-12-19 19:16:08,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53360 [2021-12-19 19:16:08,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53360 states and 72249 transitions. [2021-12-19 19:16:08,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:08,488 INFO L681 BuchiCegarLoop]: Abstraction has 53360 states and 72249 transitions. [2021-12-19 19:16:08,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53360 states and 72249 transitions. [2021-12-19 19:16:09,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53360 to 50304. [2021-12-19 19:16:09,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50304 states, 50304 states have (on average 1.3586394720101782) internal successors, (68345), 50303 states have internal predecessors, (68345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:09,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50304 states to 50304 states and 68345 transitions. [2021-12-19 19:16:09,266 INFO L704 BuchiCegarLoop]: Abstraction has 50304 states and 68345 transitions. [2021-12-19 19:16:09,266 INFO L587 BuchiCegarLoop]: Abstraction has 50304 states and 68345 transitions. [2021-12-19 19:16:09,266 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:16:09,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50304 states and 68345 transitions. [2021-12-19 19:16:09,415 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 50144 [2021-12-19 19:16:09,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:09,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:09,419 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:09,419 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:09,419 INFO L791 eck$LassoCheckResult]: Stem: 788169#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 788096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 788070#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 788038#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 787480#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 787481#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 787841#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 787842#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 787756#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 787535#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 787536#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 787464#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 787465#L684 assume !(0 == ~M_E~0); 787989#L684-2 assume !(0 == ~T1_E~0); 787794#L689-1 assume !(0 == ~T2_E~0); 787795#L694-1 assume !(0 == ~T3_E~0); 787792#L699-1 assume !(0 == ~T4_E~0); 787793#L704-1 assume !(0 == ~T5_E~0); 787737#L709-1 assume !(0 == ~T6_E~0); 787670#L714-1 assume !(0 == ~E_M~0); 787671#L719-1 assume !(0 == ~E_1~0); 787954#L724-1 assume !(0 == ~E_2~0); 787435#L729-1 assume !(0 == ~E_3~0); 787436#L734-1 assume !(0 == ~E_4~0); 788030#L739-1 assume !(0 == ~E_5~0); 787628#L744-1 assume !(0 == ~E_6~0); 787629#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 787395#L334 assume !(1 == ~m_pc~0); 787396#L334-2 is_master_triggered_~__retres1~0#1 := 0; 787727#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 788187#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 787601#L849 assume !(0 != activate_threads_~tmp~1#1); 787602#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 787531#L353 assume !(1 == ~t1_pc~0); 787532#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 787845#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 787445#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 787446#L857 assume !(0 != activate_threads_~tmp___0~0#1); 787484#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 787485#L372 assume !(1 == ~t2_pc~0); 787587#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 787611#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 788184#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 788183#L865 assume !(0 != activate_threads_~tmp___1~0#1); 787384#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 787385#L391 assume !(1 == ~t3_pc~0); 787302#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 787303#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 787516#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 787724#L873 assume !(0 != activate_threads_~tmp___2~0#1); 787606#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 787607#L410 assume !(1 == ~t4_pc~0); 787863#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 787864#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 787915#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 788020#L881 assume !(0 != activate_threads_~tmp___3~0#1); 787613#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 787614#L429 assume !(1 == ~t5_pc~0); 787439#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 787440#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 787366#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 787367#L889 assume !(0 != activate_threads_~tmp___4~0#1); 787875#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 787596#L448 assume !(1 == ~t6_pc~0); 787517#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 787518#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 787872#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 787970#L897 assume !(0 != activate_threads_~tmp___5~0#1); 788065#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 788148#L762 assume !(1 == ~M_E~0); 787649#L762-2 assume !(1 == ~T1_E~0); 787650#L767-1 assume !(1 == ~T2_E~0); 788073#L772-1 assume !(1 == ~T3_E~0); 787908#L777-1 assume !(1 == ~T4_E~0); 787771#L782-1 assume !(1 == ~T5_E~0); 787470#L787-1 assume !(1 == ~T6_E~0); 787468#L792-1 assume !(1 == ~E_M~0); 787469#L797-1 assume !(1 == ~E_1~0); 787503#L802-1 assume !(1 == ~E_2~0); 787730#L807-1 assume !(1 == ~E_3~0); 787731#L812-1 assume !(1 == ~E_4~0); 788025#L817-1 assume !(1 == ~E_5~0); 787796#L822-1 assume !(1 == ~E_6~0); 787797#L827-1 assume { :end_inline_reset_delta_events } true; 788039#L1053-2 [2021-12-19 19:16:09,420 INFO L793 eck$LassoCheckResult]: Loop: 788039#L1053-2 assume !false; 797837#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 797793#L659 assume !false; 797834#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 797830#L518 assume !(0 == ~m_st~0); 797831#L522 assume !(0 == ~t1_st~0); 826091#L526 assume !(0 == ~t2_st~0); 826092#L530 assume !(0 == ~t3_st~0); 826094#L534 assume !(0 == ~t4_st~0); 826089#L538 assume !(0 == ~t5_st~0); 826090#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 826093#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 826297#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 826296#L570 assume !(0 != eval_~tmp~0#1); 826295#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 826294#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 826293#L684-3 assume !(0 == ~M_E~0); 826292#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 826290#L689-3 assume !(0 == ~T2_E~0); 826288#L694-3 assume !(0 == ~T3_E~0); 826286#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 826284#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 826282#L709-3 assume !(0 == ~T6_E~0); 826280#L714-3 assume !(0 == ~E_M~0); 826278#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 826276#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 826274#L729-3 assume !(0 == ~E_3~0); 826272#L734-3 assume !(0 == ~E_4~0); 826270#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 826268#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 826266#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 826264#L334-24 assume 1 == ~m_pc~0; 826260#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 826261#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 836360#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 836358#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 788141#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 787888#L353-24 assume !(1 == ~t1_pc~0); 787889#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 788079#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 788080#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 788105#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 787386#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 787387#L372-24 assume 1 == ~t2_pc~0; 787343#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 787344#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 787486#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 787487#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 788059#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 787674#L391-24 assume !(1 == ~t3_pc~0); 787675#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 788144#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 836275#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 836274#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 836273#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 801504#L410-24 assume !(1 == ~t4_pc~0); 801503#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 801502#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 801500#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 801499#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 801498#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 801497#L429-24 assume !(1 == ~t5_pc~0); 801493#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 801491#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 801489#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 801487#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 801484#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 801482#L448-24 assume !(1 == ~t6_pc~0); 796510#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 801479#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 801475#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 801473#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 801471#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 801469#L762-3 assume !(1 == ~M_E~0); 798376#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 801465#L767-3 assume !(1 == ~T2_E~0); 801463#L772-3 assume !(1 == ~T3_E~0); 801462#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 801460#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 801458#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 801456#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 801454#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 801450#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 797876#L807-3 assume !(1 == ~E_3~0); 797874#L812-3 assume !(1 == ~E_4~0); 797872#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 797870#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 797868#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 797865#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 797863#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 797861#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 797859#L1072 assume !(0 == start_simulation_~tmp~3#1); 797856#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 797853#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 797852#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 797850#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 797848#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 797846#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 797844#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 797842#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 788039#L1053-2 [2021-12-19 19:16:09,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:09,420 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2021-12-19 19:16:09,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:09,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612745031] [2021-12-19 19:16:09,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:09,421 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:09,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:09,425 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:09,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:09,439 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:09,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:09,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1544843051, now seen corresponding path program 1 times [2021-12-19 19:16:09,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:09,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892029657] [2021-12-19 19:16:09,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:09,440 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:09,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:09,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:09,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:09,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892029657] [2021-12-19 19:16:09,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892029657] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:09,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:09,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:09,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583301352] [2021-12-19 19:16:09,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:09,472 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:09,472 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:09,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:09,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:09,473 INFO L87 Difference]: Start difference. First operand 50304 states and 68345 transitions. cyclomatic complexity: 18043 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:09,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:09,822 INFO L93 Difference]: Finished difference Result 98096 states and 132464 transitions. [2021-12-19 19:16:09,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:09,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98096 states and 132464 transitions. [2021-12-19 19:16:10,235 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 97936 [2021-12-19 19:16:10,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98096 states to 98096 states and 132464 transitions. [2021-12-19 19:16:10,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98096 [2021-12-19 19:16:10,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98096 [2021-12-19 19:16:10,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98096 states and 132464 transitions. [2021-12-19 19:16:11,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:11,011 INFO L681 BuchiCegarLoop]: Abstraction has 98096 states and 132464 transitions. [2021-12-19 19:16:11,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98096 states and 132464 transitions. [2021-12-19 19:16:11,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98096 to 51408. [2021-12-19 19:16:11,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51408 states, 51408 states have (on average 1.3450046685340804) internal successors, (69144), 51407 states have internal predecessors, (69144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:11,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51408 states to 51408 states and 69144 transitions. [2021-12-19 19:16:11,592 INFO L704 BuchiCegarLoop]: Abstraction has 51408 states and 69144 transitions. [2021-12-19 19:16:11,592 INFO L587 BuchiCegarLoop]: Abstraction has 51408 states and 69144 transitions. [2021-12-19 19:16:11,592 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:16:11,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51408 states and 69144 transitions. [2021-12-19 19:16:11,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51248 [2021-12-19 19:16:11,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:11,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:11,738 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:11,738 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:11,739 INFO L791 eck$LassoCheckResult]: Stem: 936567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 936502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 936482#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 936452#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 935893#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 935894#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 936252#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 936253#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 936167#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 935947#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 935948#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 935877#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 935878#L684 assume !(0 == ~M_E~0); 936394#L684-2 assume !(0 == ~T1_E~0); 936205#L689-1 assume !(0 == ~T2_E~0); 936206#L694-1 assume !(0 == ~T3_E~0); 936203#L699-1 assume !(0 == ~T4_E~0); 936204#L704-1 assume !(0 == ~T5_E~0); 936154#L709-1 assume !(0 == ~T6_E~0); 936084#L714-1 assume !(0 == ~E_M~0); 936085#L719-1 assume !(0 == ~E_1~0); 936359#L724-1 assume !(0 == ~E_2~0); 935848#L729-1 assume !(0 == ~E_3~0); 935849#L734-1 assume !(0 == ~E_4~0); 936442#L739-1 assume !(0 == ~E_5~0); 936042#L744-1 assume !(0 == ~E_6~0); 936043#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 935807#L334 assume !(1 == ~m_pc~0); 935808#L334-2 is_master_triggered_~__retres1~0#1 := 0; 936143#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936578#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 936015#L849 assume !(0 != activate_threads_~tmp~1#1); 936016#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 935943#L353 assume !(1 == ~t1_pc~0); 935944#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 936256#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 935858#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 935859#L857 assume !(0 != activate_threads_~tmp___0~0#1); 935895#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 935896#L372 assume !(1 == ~t2_pc~0); 936001#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 936025#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 936575#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 936574#L865 assume !(0 != activate_threads_~tmp___1~0#1); 935796#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 935797#L391 assume !(1 == ~t3_pc~0); 935718#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 935719#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 935928#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 936142#L873 assume !(0 != activate_threads_~tmp___2~0#1); 936020#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 936021#L410 assume !(1 == ~t4_pc~0); 936275#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 936276#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 936323#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 936432#L881 assume !(0 != activate_threads_~tmp___3~0#1); 936029#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 936030#L429 assume !(1 == ~t5_pc~0); 935852#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 935853#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 935781#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 935782#L889 assume !(0 != activate_threads_~tmp___4~0#1); 936284#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 936010#L448 assume !(1 == ~t6_pc~0); 935929#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 935930#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 936281#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 936374#L897 assume !(0 != activate_threads_~tmp___5~0#1); 936477#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 936543#L762 assume !(1 == ~M_E~0); 936064#L762-2 assume !(1 == ~T1_E~0); 936065#L767-1 assume !(1 == ~T2_E~0); 936485#L772-1 assume !(1 == ~T3_E~0); 936318#L777-1 assume !(1 == ~T4_E~0); 936183#L782-1 assume !(1 == ~T5_E~0); 935881#L787-1 assume !(1 == ~T6_E~0); 935879#L792-1 assume !(1 == ~E_M~0); 935880#L797-1 assume !(1 == ~E_1~0); 935916#L802-1 assume !(1 == ~E_2~0); 936148#L807-1 assume !(1 == ~E_3~0); 936149#L812-1 assume !(1 == ~E_4~0); 936440#L817-1 assume !(1 == ~E_5~0); 936207#L822-1 assume !(1 == ~E_6~0); 936208#L827-1 assume { :end_inline_reset_delta_events } true; 936453#L1053-2 [2021-12-19 19:16:11,739 INFO L793 eck$LassoCheckResult]: Loop: 936453#L1053-2 assume !false; 948565#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 948457#L659 assume !false; 948562#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 948559#L518 assume !(0 == ~m_st~0); 948560#L522 assume !(0 == ~t1_st~0); 948756#L526 assume !(0 == ~t2_st~0); 948757#L530 assume !(0 == ~t3_st~0); 948759#L534 assume !(0 == ~t4_st~0); 948754#L538 assume !(0 == ~t5_st~0); 948755#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 948758#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 958517#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 958516#L570 assume !(0 != eval_~tmp~0#1); 958515#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 958513#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 958511#L684-3 assume !(0 == ~M_E~0); 958509#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 958506#L689-3 assume !(0 == ~T2_E~0); 958504#L694-3 assume !(0 == ~T3_E~0); 958502#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 958501#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 958500#L709-3 assume !(0 == ~T6_E~0); 958499#L714-3 assume !(0 == ~E_M~0); 958498#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 958497#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 958495#L729-3 assume !(0 == ~E_3~0); 958493#L734-3 assume !(0 == ~E_4~0); 958489#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 958487#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 958485#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 958483#L334-24 assume 1 == ~m_pc~0; 958478#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 958476#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 958474#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 958472#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 958470#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 958468#L353-24 assume !(1 == ~t1_pc~0); 958466#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 958464#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 958463#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 958459#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 958457#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 958455#L372-24 assume 1 == ~t2_pc~0; 958453#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 958454#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 958520#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 947854#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 947445#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 946672#L391-24 assume !(1 == ~t3_pc~0); 946670#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 946669#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 946668#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 946667#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 946665#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 946662#L410-24 assume !(1 == ~t4_pc~0); 939140#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 946649#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 946644#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 946641#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 946637#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 946204#L429-24 assume 1 == ~t5_pc~0; 946202#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 946200#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 946198#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 945935#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 945908#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 941607#L448-24 assume !(1 == ~t6_pc~0); 938157#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 941600#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 941601#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 941594#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 941595#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 936696#L762-3 assume !(1 == ~M_E~0); 936690#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 936686#L767-3 assume !(1 == ~T2_E~0); 936682#L772-3 assume !(1 == ~T3_E~0); 936678#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 936674#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 936670#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 936665#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 936660#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 936656#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 936653#L807-3 assume !(1 == ~E_3~0); 936650#L812-3 assume !(1 == ~E_4~0); 936648#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 936646#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 936644#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 936641#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 936642#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 946528#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 946526#L1072 assume !(0 == start_simulation_~tmp~3#1); 946527#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 948580#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 948578#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 948576#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 948574#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 948571#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 948569#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 948567#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 936453#L1053-2 [2021-12-19 19:16:11,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:11,740 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2021-12-19 19:16:11,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:11,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378302748] [2021-12-19 19:16:11,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:11,740 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:11,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:11,745 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:11,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:11,757 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:11,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:11,757 INFO L85 PathProgramCache]: Analyzing trace with hash -388490582, now seen corresponding path program 1 times [2021-12-19 19:16:11,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:11,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438865402] [2021-12-19 19:16:11,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:11,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:11,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:11,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:11,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:11,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438865402] [2021-12-19 19:16:11,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438865402] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:11,791 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:11,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:11,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948307603] [2021-12-19 19:16:11,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:11,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:11,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:11,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:11,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:11,793 INFO L87 Difference]: Start difference. First operand 51408 states and 69144 transitions. cyclomatic complexity: 17738 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:12,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:12,089 INFO L93 Difference]: Finished difference Result 78272 states and 105359 transitions. [2021-12-19 19:16:12,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:12,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78272 states and 105359 transitions. [2021-12-19 19:16:12,698 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 78048 [2021-12-19 19:16:12,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78272 states to 78272 states and 105359 transitions. [2021-12-19 19:16:12,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78272 [2021-12-19 19:16:12,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78272 [2021-12-19 19:16:12,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78272 states and 105359 transitions. [2021-12-19 19:16:12,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:12,896 INFO L681 BuchiCegarLoop]: Abstraction has 78272 states and 105359 transitions. [2021-12-19 19:16:12,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78272 states and 105359 transitions. [2021-12-19 19:16:13,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78272 to 51504. [2021-12-19 19:16:13,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51504 states, 51504 states have (on average 1.3350225225225225) internal successors, (68759), 51503 states have internal predecessors, (68759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:13,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51504 states to 51504 states and 68759 transitions. [2021-12-19 19:16:13,409 INFO L704 BuchiCegarLoop]: Abstraction has 51504 states and 68759 transitions. [2021-12-19 19:16:13,409 INFO L587 BuchiCegarLoop]: Abstraction has 51504 states and 68759 transitions. [2021-12-19 19:16:13,409 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:16:13,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51504 states and 68759 transitions. [2021-12-19 19:16:13,748 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51344 [2021-12-19 19:16:13,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:13,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:13,751 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:13,751 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:13,751 INFO L791 eck$LassoCheckResult]: Stem: 1066252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1066187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1066163#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1066129#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1065588#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1065589#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1065944#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1065945#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1065859#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1065641#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1065642#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1065572#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1065573#L684 assume !(0 == ~M_E~0); 1066082#L684-2 assume !(0 == ~T1_E~0); 1065896#L689-1 assume !(0 == ~T2_E~0); 1065897#L694-1 assume !(0 == ~T3_E~0); 1065894#L699-1 assume !(0 == ~T4_E~0); 1065895#L704-1 assume !(0 == ~T5_E~0); 1065845#L709-1 assume !(0 == ~T6_E~0); 1065780#L714-1 assume !(0 == ~E_M~0); 1065781#L719-1 assume !(0 == ~E_1~0); 1066047#L724-1 assume !(0 == ~E_2~0); 1065542#L729-1 assume !(0 == ~E_3~0); 1065543#L734-1 assume !(0 == ~E_4~0); 1066123#L739-1 assume !(0 == ~E_5~0); 1065737#L744-1 assume !(0 == ~E_6~0); 1065738#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1065502#L334 assume !(1 == ~m_pc~0); 1065503#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1065834#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1066266#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1065709#L849 assume !(0 != activate_threads_~tmp~1#1); 1065710#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1065637#L353 assume !(1 == ~t1_pc~0); 1065638#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1065948#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065552#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1065553#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1065590#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1065591#L372 assume !(1 == ~t2_pc~0); 1065695#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1065719#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1066263#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1066262#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1065491#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065492#L391 assume !(1 == ~t3_pc~0); 1065412#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1065413#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1065622#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1065833#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1065714#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1065715#L410 assume !(1 == ~t4_pc~0); 1065965#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1065966#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1066010#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1066113#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1065723#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1065724#L429 assume !(1 == ~t5_pc~0); 1065546#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1065547#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1065476#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1065477#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1065974#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1065704#L448 assume !(1 == ~t6_pc~0); 1065623#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1065624#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1065970#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1066062#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1066158#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1066234#L762 assume !(1 == ~M_E~0); 1065759#L762-2 assume !(1 == ~T1_E~0); 1065760#L767-1 assume !(1 == ~T2_E~0); 1066169#L772-1 assume !(1 == ~T3_E~0); 1066004#L777-1 assume !(1 == ~T4_E~0); 1065873#L782-1 assume !(1 == ~T5_E~0); 1065576#L787-1 assume !(1 == ~T6_E~0); 1065574#L792-1 assume !(1 == ~E_M~0); 1065575#L797-1 assume !(1 == ~E_1~0); 1065611#L802-1 assume !(1 == ~E_2~0); 1065839#L807-1 assume !(1 == ~E_3~0); 1065840#L812-1 assume !(1 == ~E_4~0); 1066119#L817-1 assume !(1 == ~E_5~0); 1065898#L822-1 assume !(1 == ~E_6~0); 1065899#L827-1 assume { :end_inline_reset_delta_events } true; 1066130#L1053-2 [2021-12-19 19:16:13,751 INFO L793 eck$LassoCheckResult]: Loop: 1066130#L1053-2 assume !false; 1095238#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1095236#L659 assume !false; 1095234#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1095231#L518 assume !(0 == ~m_st~0); 1095232#L522 assume !(0 == ~t1_st~0); 1098677#L526 assume !(0 == ~t2_st~0); 1098678#L530 assume !(0 == ~t3_st~0); 1098680#L534 assume !(0 == ~t4_st~0); 1098675#L538 assume !(0 == ~t5_st~0); 1098676#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1098679#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1101429#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1101427#L570 assume !(0 != eval_~tmp~0#1); 1101425#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1101423#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1101421#L684-3 assume !(0 == ~M_E~0); 1101419#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1101417#L689-3 assume !(0 == ~T2_E~0); 1101415#L694-3 assume !(0 == ~T3_E~0); 1101413#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1101411#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1101409#L709-3 assume !(0 == ~T6_E~0); 1101407#L714-3 assume !(0 == ~E_M~0); 1101405#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1101403#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1101401#L729-3 assume !(0 == ~E_3~0); 1101399#L734-3 assume !(0 == ~E_4~0); 1101397#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1101395#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1101393#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1101390#L334-24 assume 1 == ~m_pc~0; 1101387#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1101385#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1101381#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1101378#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1101379#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102561#L353-24 assume !(1 == ~t1_pc~0); 1102557#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1102555#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1102553#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1102551#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1102549#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1102361#L372-24 assume !(1 == ~t2_pc~0); 1102358#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1102357#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1102356#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1102350#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1079820#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1079717#L391-24 assume !(1 == ~t3_pc~0); 1079714#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1079710#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1079706#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1079702#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1079698#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1079695#L410-24 assume !(1 == ~t4_pc~0); 1078604#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1079692#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1079689#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1079686#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1079683#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1079680#L429-24 assume 1 == ~t5_pc~0; 1079674#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1079668#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1079662#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1079657#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1079653#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1079650#L448-24 assume !(1 == ~t6_pc~0); 1078641#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1079646#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1079643#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1079639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1079636#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1079633#L762-3 assume !(1 == ~M_E~0); 1079430#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1079631#L767-3 assume !(1 == ~T2_E~0); 1079628#L772-3 assume !(1 == ~T3_E~0); 1079624#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1079620#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1079616#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1079610#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1079607#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1079604#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1079601#L807-3 assume !(1 == ~E_3~0); 1079599#L812-3 assume !(1 == ~E_4~0); 1079594#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1079590#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1079584#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1079573#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1079566#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1079559#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1079549#L1072 assume !(0 == start_simulation_~tmp~3#1); 1079550#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1100918#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1100917#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1100916#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1100915#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1100913#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1100912#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1100911#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1066130#L1053-2 [2021-12-19 19:16:13,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:13,752 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2021-12-19 19:16:13,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:13,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530055495] [2021-12-19 19:16:13,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:13,752 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:13,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:13,757 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:13,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:13,769 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:13,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:13,769 INFO L85 PathProgramCache]: Analyzing trace with hash -57410961, now seen corresponding path program 1 times [2021-12-19 19:16:13,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:13,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565373714] [2021-12-19 19:16:13,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:13,770 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:13,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:13,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:13,801 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:13,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565373714] [2021-12-19 19:16:13,801 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565373714] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:13,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:13,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:13,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425672628] [2021-12-19 19:16:13,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:13,801 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:13,802 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:13,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:13,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:13,802 INFO L87 Difference]: Start difference. First operand 51504 states and 68759 transitions. cyclomatic complexity: 17257 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:14,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:14,011 INFO L93 Difference]: Finished difference Result 64376 states and 85190 transitions. [2021-12-19 19:16:14,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:14,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64376 states and 85190 transitions. [2021-12-19 19:16:14,244 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 64184 [2021-12-19 19:16:14,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64376 states to 64376 states and 85190 transitions. [2021-12-19 19:16:14,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64376 [2021-12-19 19:16:14,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64376 [2021-12-19 19:16:14,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64376 states and 85190 transitions. [2021-12-19 19:16:14,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:14,451 INFO L681 BuchiCegarLoop]: Abstraction has 64376 states and 85190 transitions. [2021-12-19 19:16:14,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64376 states and 85190 transitions. [2021-12-19 19:16:15,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64376 to 51600. [2021-12-19 19:16:15,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51600 states, 51600 states have (on average 1.3216666666666668) internal successors, (68198), 51599 states have internal predecessors, (68198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:15,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51600 states to 51600 states and 68198 transitions. [2021-12-19 19:16:15,317 INFO L704 BuchiCegarLoop]: Abstraction has 51600 states and 68198 transitions. [2021-12-19 19:16:15,317 INFO L587 BuchiCegarLoop]: Abstraction has 51600 states and 68198 transitions. [2021-12-19 19:16:15,317 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:16:15,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51600 states and 68198 transitions. [2021-12-19 19:16:15,463 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51440 [2021-12-19 19:16:15,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:15,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:15,466 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:15,467 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:15,467 INFO L791 eck$LassoCheckResult]: Stem: 1182203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1182125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1182096#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1182060#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1181481#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1181482#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1181848#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1181849#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1181760#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1181535#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1181536#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1181465#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1181466#L684 assume !(0 == ~M_E~0); 1182002#L684-2 assume !(0 == ~T1_E~0); 1181802#L689-1 assume !(0 == ~T2_E~0); 1181803#L694-1 assume !(0 == ~T3_E~0); 1181800#L699-1 assume !(0 == ~T4_E~0); 1181801#L704-1 assume !(0 == ~T5_E~0); 1181744#L709-1 assume !(0 == ~T6_E~0); 1181676#L714-1 assume !(0 == ~E_M~0); 1181677#L719-1 assume !(0 == ~E_1~0); 1181957#L724-1 assume !(0 == ~E_2~0); 1181437#L729-1 assume !(0 == ~E_3~0); 1181438#L734-1 assume !(0 == ~E_4~0); 1182054#L739-1 assume !(0 == ~E_5~0); 1181631#L744-1 assume !(0 == ~E_6~0); 1181632#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1181396#L334 assume !(1 == ~m_pc~0); 1181397#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1181733#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1182222#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1181603#L849 assume !(0 != activate_threads_~tmp~1#1); 1181604#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1181531#L353 assume !(1 == ~t1_pc~0); 1181532#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1181852#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1181447#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1181448#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1181485#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1181486#L372 assume !(1 == ~t2_pc~0); 1181588#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1181613#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1182219#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1182218#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1181385#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1181386#L391 assume !(1 == ~t3_pc~0); 1181304#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1181305#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1181516#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1181730#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1181608#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1181609#L410 assume !(1 == ~t4_pc~0); 1181869#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1181870#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1181918#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1182044#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1181615#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1181616#L429 assume !(1 == ~t5_pc~0); 1181441#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1181442#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1181368#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1181369#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1181881#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1181598#L448 assume !(1 == ~t6_pc~0); 1181517#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1181518#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1181879#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1181976#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1182089#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182182#L762 assume !(1 == ~M_E~0); 1181655#L762-2 assume !(1 == ~T1_E~0); 1181656#L767-1 assume !(1 == ~T2_E~0); 1182100#L772-1 assume !(1 == ~T3_E~0); 1181910#L777-1 assume !(1 == ~T4_E~0); 1181778#L782-1 assume !(1 == ~T5_E~0); 1181471#L787-1 assume !(1 == ~T6_E~0); 1181469#L792-1 assume !(1 == ~E_M~0); 1181470#L797-1 assume !(1 == ~E_1~0); 1181503#L802-1 assume !(1 == ~E_2~0); 1181736#L807-1 assume !(1 == ~E_3~0); 1181737#L812-1 assume !(1 == ~E_4~0); 1182050#L817-1 assume !(1 == ~E_5~0); 1181804#L822-1 assume !(1 == ~E_6~0); 1181805#L827-1 assume { :end_inline_reset_delta_events } true; 1182061#L1053-2 [2021-12-19 19:16:15,467 INFO L793 eck$LassoCheckResult]: Loop: 1182061#L1053-2 assume !false; 1194872#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1194818#L659 assume !false; 1194865#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1194862#L518 assume !(0 == ~m_st~0); 1194863#L522 assume !(0 == ~t1_st~0); 1208230#L526 assume !(0 == ~t2_st~0); 1208231#L530 assume !(0 == ~t3_st~0); 1208233#L534 assume !(0 == ~t4_st~0); 1208228#L538 assume !(0 == ~t5_st~0); 1208229#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1208232#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1208612#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1208586#L570 assume !(0 != eval_~tmp~0#1); 1208587#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1208580#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1208581#L684-3 assume !(0 == ~M_E~0); 1208565#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1208566#L689-3 assume !(0 == ~T2_E~0); 1208560#L694-3 assume !(0 == ~T3_E~0); 1208561#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1208554#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1208555#L709-3 assume !(0 == ~T6_E~0); 1208547#L714-3 assume !(0 == ~E_M~0); 1208548#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1208540#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1208541#L729-3 assume !(0 == ~E_3~0); 1208534#L734-3 assume !(0 == ~E_4~0); 1208535#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1208529#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1208530#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1208522#L334-24 assume 1 == ~m_pc~0; 1208523#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1208514#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1208515#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1208506#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1208507#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1208499#L353-24 assume !(1 == ~t1_pc~0); 1208500#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1208491#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1208492#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1208483#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1208484#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1208475#L372-24 assume !(1 == ~t2_pc~0); 1208476#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1208542#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1208543#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1208455#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1208456#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1203104#L391-24 assume !(1 == ~t3_pc~0); 1203102#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1203093#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203083#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1203077#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1198617#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1195069#L410-24 assume !(1 == ~t4_pc~0); 1195063#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1195057#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1195051#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1195044#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 1195039#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1195036#L429-24 assume 1 == ~t5_pc~0; 1195028#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1195019#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1195010#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1195001#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1194995#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1194989#L448-24 assume !(1 == ~t6_pc~0); 1188364#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1194981#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1194975#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1194970#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1194965#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1194960#L762-3 assume !(1 == ~M_E~0); 1194955#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1194952#L767-3 assume !(1 == ~T2_E~0); 1194949#L772-3 assume !(1 == ~T3_E~0); 1194946#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1194942#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1194939#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1194936#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1194933#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1194930#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1194927#L807-3 assume !(1 == ~E_3~0); 1194925#L812-3 assume !(1 == ~E_4~0); 1194923#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1194921#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1194919#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1194916#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1194914#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1194912#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1194908#L1072 assume !(0 == start_simulation_~tmp~3#1); 1194905#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1194901#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1194898#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1194895#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1194892#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1194889#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1194885#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1194881#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1182061#L1053-2 [2021-12-19 19:16:15,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:15,468 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 10 times [2021-12-19 19:16:15,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:15,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723397080] [2021-12-19 19:16:15,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:15,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:15,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:15,473 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:15,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:15,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:15,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:15,487 INFO L85 PathProgramCache]: Analyzing trace with hash 366235761, now seen corresponding path program 1 times [2021-12-19 19:16:15,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:15,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174545280] [2021-12-19 19:16:15,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:15,487 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:15,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:15,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:15,517 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:15,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174545280] [2021-12-19 19:16:15,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174545280] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:15,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:15,517 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:15,517 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404440007] [2021-12-19 19:16:15,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:15,518 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:15,518 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:15,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:15,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:15,518 INFO L87 Difference]: Start difference. First operand 51600 states and 68198 transitions. cyclomatic complexity: 16600 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:15,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:15,818 INFO L93 Difference]: Finished difference Result 85300 states and 113061 transitions. [2021-12-19 19:16:15,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:15,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85300 states and 113061 transitions. [2021-12-19 19:16:16,150 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 85076 [2021-12-19 19:16:16,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85300 states to 85300 states and 113061 transitions. [2021-12-19 19:16:16,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85300 [2021-12-19 19:16:16,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85300 [2021-12-19 19:16:16,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85300 states and 113061 transitions. [2021-12-19 19:16:16,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:16,463 INFO L681 BuchiCegarLoop]: Abstraction has 85300 states and 113061 transitions. [2021-12-19 19:16:16,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85300 states and 113061 transitions. [2021-12-19 19:16:17,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85300 to 52728. [2021-12-19 19:16:17,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52728 states, 52728 states have (on average 1.308849188287058) internal successors, (69013), 52727 states have internal predecessors, (69013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:17,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52728 states to 52728 states and 69013 transitions. [2021-12-19 19:16:17,456 INFO L704 BuchiCegarLoop]: Abstraction has 52728 states and 69013 transitions. [2021-12-19 19:16:17,456 INFO L587 BuchiCegarLoop]: Abstraction has 52728 states and 69013 transitions. [2021-12-19 19:16:17,456 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-19 19:16:17,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52728 states and 69013 transitions. [2021-12-19 19:16:17,613 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52568 [2021-12-19 19:16:17,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:17,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:17,618 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:17,618 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:17,618 INFO L791 eck$LassoCheckResult]: Stem: 1319060#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1318995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1318968#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1318942#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1318392#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1318393#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1318751#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1318752#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1318664#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1318447#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1318448#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1318378#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1318379#L684 assume !(0 == ~M_E~0); 1318889#L684-2 assume !(0 == ~T1_E~0); 1318704#L689-1 assume !(0 == ~T2_E~0); 1318705#L694-1 assume !(0 == ~T3_E~0); 1318702#L699-1 assume !(0 == ~T4_E~0); 1318703#L704-1 assume !(0 == ~T5_E~0); 1318649#L709-1 assume !(0 == ~T6_E~0); 1318582#L714-1 assume !(0 == ~E_M~0); 1318583#L719-1 assume !(0 == ~E_1~0); 1318854#L724-1 assume !(0 == ~E_2~0); 1318349#L729-1 assume !(0 == ~E_3~0); 1318350#L734-1 assume !(0 == ~E_4~0); 1318934#L739-1 assume !(0 == ~E_5~0); 1318539#L744-1 assume !(0 == ~E_6~0); 1318540#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1318309#L334 assume !(1 == ~m_pc~0); 1318310#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1318638#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1319075#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1318512#L849 assume !(0 != activate_threads_~tmp~1#1); 1318513#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1318443#L353 assume !(1 == ~t1_pc~0); 1318444#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1318756#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1318359#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1318360#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1318396#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1318397#L372 assume !(1 == ~t2_pc~0); 1318498#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1318522#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1319072#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1319071#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1318298#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318299#L391 assume !(1 == ~t3_pc~0); 1318220#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318221#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1318428#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1318635#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1318517#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1318518#L410 assume !(1 == ~t4_pc~0); 1318772#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1318773#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1318815#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1318922#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1318524#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1318525#L429 assume !(1 == ~t5_pc~0); 1318353#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1318354#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1318283#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1318284#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1318782#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1318507#L448 assume !(1 == ~t6_pc~0); 1318429#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1318430#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1318779#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1318868#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1318964#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1319041#L762 assume !(1 == ~M_E~0); 1318562#L762-2 assume !(1 == ~T1_E~0); 1318563#L767-1 assume !(1 == ~T2_E~0); 1318973#L772-1 assume !(1 == ~T3_E~0); 1318809#L777-1 assume !(1 == ~T4_E~0); 1318682#L782-1 assume !(1 == ~T5_E~0); 1318382#L787-1 assume !(1 == ~T6_E~0); 1318380#L792-1 assume !(1 == ~E_M~0); 1318381#L797-1 assume !(1 == ~E_1~0); 1318416#L802-1 assume !(1 == ~E_2~0); 1318643#L807-1 assume !(1 == ~E_3~0); 1318644#L812-1 assume !(1 == ~E_4~0); 1318930#L817-1 assume !(1 == ~E_5~0); 1318706#L822-1 assume !(1 == ~E_6~0); 1318707#L827-1 assume { :end_inline_reset_delta_events } true; 1318943#L1053-2 [2021-12-19 19:16:17,618 INFO L793 eck$LassoCheckResult]: Loop: 1318943#L1053-2 assume !false; 1341286#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1341282#L659 assume !false; 1341279#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1341223#L518 assume !(0 == ~m_st~0); 1341224#L522 assume !(0 == ~t1_st~0); 1341509#L526 assume !(0 == ~t2_st~0); 1341510#L530 assume !(0 == ~t3_st~0); 1341511#L534 assume !(0 == ~t4_st~0); 1341507#L538 assume !(0 == ~t5_st~0); 1341508#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1341499#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1341489#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1341476#L570 assume !(0 != eval_~tmp~0#1); 1341477#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1347848#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1347847#L684-3 assume !(0 == ~M_E~0); 1347846#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1347845#L689-3 assume !(0 == ~T2_E~0); 1347844#L694-3 assume !(0 == ~T3_E~0); 1347843#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1347842#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1347841#L709-3 assume !(0 == ~T6_E~0); 1347840#L714-3 assume !(0 == ~E_M~0); 1347839#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1347838#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1347837#L729-3 assume !(0 == ~E_3~0); 1347836#L734-3 assume !(0 == ~E_4~0); 1347835#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1347834#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1347833#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1347832#L334-24 assume 1 == ~m_pc~0; 1347830#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1347829#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1347828#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1347826#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1347825#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1347824#L353-24 assume !(1 == ~t1_pc~0); 1347823#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1347822#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1347821#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1347820#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1347819#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1347818#L372-24 assume !(1 == ~t2_pc~0); 1347816#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1347814#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1347812#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1347810#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1347809#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1347808#L391-24 assume !(1 == ~t3_pc~0); 1346457#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1347807#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1347806#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1347805#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1347804#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1347803#L410-24 assume !(1 == ~t4_pc~0); 1338995#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1347802#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1347801#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1347800#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 1347799#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1347798#L429-24 assume 1 == ~t5_pc~0; 1347796#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1347794#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1347792#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1347790#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1347789#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1320623#L448-24 assume !(1 == ~t6_pc~0); 1320621#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1320619#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1320617#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1320615#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 1320613#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1320611#L762-3 assume !(1 == ~M_E~0); 1320605#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1320601#L767-3 assume !(1 == ~T2_E~0); 1320597#L772-3 assume !(1 == ~T3_E~0); 1320593#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1320589#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1320585#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1320579#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1320580#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1327796#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1320567#L807-3 assume !(1 == ~E_3~0); 1320564#L812-3 assume !(1 == ~E_4~0); 1320562#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1320560#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1320557#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1320555#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1320548#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1320547#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1320545#L1072 assume !(0 == start_simulation_~tmp~3#1); 1320546#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1341318#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1341316#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1341314#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1341312#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1341308#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1341306#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1341304#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1318943#L1053-2 [2021-12-19 19:16:17,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:17,619 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 11 times [2021-12-19 19:16:17,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:17,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772693773] [2021-12-19 19:16:17,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:17,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:17,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:17,631 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:17,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:17,645 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:17,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:17,645 INFO L85 PathProgramCache]: Analyzing trace with hash 1752439155, now seen corresponding path program 1 times [2021-12-19 19:16:17,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:17,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880431758] [2021-12-19 19:16:17,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:17,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:17,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:17,651 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:17,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:17,661 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:17,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:17,661 INFO L85 PathProgramCache]: Analyzing trace with hash 1048827451, now seen corresponding path program 1 times [2021-12-19 19:16:17,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:17,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192713470] [2021-12-19 19:16:17,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:17,662 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:17,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:17,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:17,682 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:17,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192713470] [2021-12-19 19:16:17,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192713470] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:17,682 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:17,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:17,682 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912333800] [2021-12-19 19:16:17,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:18,857 INFO L210 LassoAnalysis]: Preferences: [2021-12-19 19:16:18,858 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-19 19:16:18,858 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-19 19:16:18,858 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-19 19:16:18,858 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-12-19 19:16:18,858 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:18,858 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-19 19:16:18,858 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-19 19:16:18,858 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration30_Loop [2021-12-19 19:16:18,858 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-19 19:16:18,859 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-19 19:16:18,876 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,881 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,882 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,884 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,886 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,888 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,890 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,892 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,893 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,894 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,898 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,902 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,903 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,904 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,905 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,906 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,908 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,910 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,911 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,912 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,915 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,918 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,920 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,923 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,926 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,931 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,934 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,936 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,939 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,946 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,952 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,954 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,956 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,958 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,962 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,964 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,967 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,971 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,973 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,975 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,976 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,980 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,981 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,982 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,984 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,986 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,988 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:18,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:19,315 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-19 19:16:19,318 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-12-19 19:16:19,320 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,320 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,336 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,337 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-12-19 19:16:19,341 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,341 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,383 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,383 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___3~0#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0, ULTIMATE.start_activate_threads_~tmp___3~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,404 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,404 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,404 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,405 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,422 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-12-19 19:16:19,431 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,431 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,456 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,456 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,476 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,476 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,476 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,481 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,482 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-12-19 19:16:19,484 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,484 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,507 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,507 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,538 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,538 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,538 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,539 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,540 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-12-19 19:16:19,542 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,542 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,559 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,560 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,576 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,577 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,577 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,577 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,578 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-12-19 19:16:19,580 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,580 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,600 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,601 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,630 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,631 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,631 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,632 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,632 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-12-19 19:16:19,644 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,644 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,656 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,657 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-1} Honda state: {~E_4~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,672 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,672 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,672 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,673 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,673 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-12-19 19:16:19,675 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,675 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,682 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,682 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,697 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,697 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,698 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,698 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,699 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-12-19 19:16:19,701 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,701 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,722 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,722 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,739 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,739 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,739 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,740 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,741 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-12-19 19:16:19,742 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,742 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,763 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,763 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,778 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,778 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,778 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,779 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,779 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-12-19 19:16:19,781 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,781 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,801 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,801 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_5~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_5~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,816 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,816 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,817 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,817 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,818 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-12-19 19:16:19,820 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,820 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,832 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,832 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0, ULTIMATE.start_stop_simulation_#res#1=0, ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0, ULTIMATE.start_stop_simulation_#res#1=0, ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,846 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,847 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,847 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,848 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,848 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-12-19 19:16:19,850 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,850 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,857 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,857 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,872 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2021-12-19 19:16:19,872 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,872 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,873 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,874 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-12-19 19:16:19,875 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,875 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,887 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,887 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,904 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2021-12-19 19:16:19,904 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,904 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,905 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,906 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-12-19 19:16:19,907 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,907 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:19,924 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:19,924 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:19,957 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:19,957 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:19,957 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:19,958 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:19,971 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-12-19 19:16:19,974 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:19,975 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,003 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,003 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,026 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,026 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,027 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,027 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2021-12-19 19:16:20,050 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,050 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,061 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,061 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=4} Honda state: {~t1_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,076 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,076 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,076 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,077 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,078 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-12-19 19:16:20,079 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,079 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,087 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,087 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet6#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,101 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2021-12-19 19:16:20,102 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,102 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,103 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,103 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2021-12-19 19:16:20,105 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,105 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,125 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,125 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,140 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2021-12-19 19:16:20,140 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,140 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,141 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,143 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2021-12-19 19:16:20,144 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,144 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,165 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,165 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0, ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0, ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,179 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2021-12-19 19:16:20,180 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,180 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,181 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,419 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2021-12-19 19:16:20,427 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,427 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,447 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,448 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret18#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret18#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,464 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2021-12-19 19:16:20,465 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,465 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,466 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,467 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2021-12-19 19:16:20,468 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,468 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,478 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,479 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,493 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2021-12-19 19:16:20,494 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,494 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,494 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,495 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2021-12-19 19:16:20,496 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,497 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,512 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,512 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,526 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2021-12-19 19:16:20,527 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,527 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,528 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,528 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2021-12-19 19:16:20,530 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,530 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,545 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,545 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,559 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,560 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,560 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,561 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,562 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2021-12-19 19:16:20,563 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,564 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,579 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,579 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___5~0#1=0, ULTIMATE.start_is_transmit6_triggered_#res#1=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___5~0#1=0, ULTIMATE.start_is_transmit6_triggered_#res#1=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,595 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,596 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,596 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,597 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,597 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2021-12-19 19:16:20,599 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,599 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,610 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-12-19 19:16:20,610 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=1, ULTIMATE.start_activate_threads_~tmp___4~0#1=1, ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1=1} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=1, ULTIMATE.start_activate_threads_~tmp___4~0#1=1, ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-12-19 19:16:20,626 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,627 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,627 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,629 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,630 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-12-19 19:16:20,630 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,636 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2021-12-19 19:16:20,651 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,651 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,651 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:20,652 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:20,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2021-12-19 19:16:20,654 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-12-19 19:16:20,654 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-12-19 19:16:20,675 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-12-19 19:16:20,690 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:20,690 INFO L210 LassoAnalysis]: Preferences: [2021-12-19 19:16:20,691 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-12-19 19:16:20,691 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-12-19 19:16:20,691 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-12-19 19:16:20,691 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-12-19 19:16:20,691 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:20,691 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-12-19 19:16:20,691 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-12-19 19:16:20,691 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration30_Loop [2021-12-19 19:16:20,691 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-12-19 19:16:20,691 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-12-19 19:16:20,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,711 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,716 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,720 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,722 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,723 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,725 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,726 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,727 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,732 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,734 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,735 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,737 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,739 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,740 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,741 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,746 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,751 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,752 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,754 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,756 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,757 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,761 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,764 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,768 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,769 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,773 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,775 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,783 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,786 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,788 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,790 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,791 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,793 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,796 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,801 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,802 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,807 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,811 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,814 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,818 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,820 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,825 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,826 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,831 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,836 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,838 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,841 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,843 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,844 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,846 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,847 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,849 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,852 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,856 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,859 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,861 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:20,865 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-12-19 19:16:21,346 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-12-19 19:16:21,350 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-12-19 19:16:21,350 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,351 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,352 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,354 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,361 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,361 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,362 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,362 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,362 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,363 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2021-12-19 19:16:21,364 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,364 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,381 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,397 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,397 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,397 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,398 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,413 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,420 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,420 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,420 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,420 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:21,420 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,421 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:21,421 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,427 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2021-12-19 19:16:21,436 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,454 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,454 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,454 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,455 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,476 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2021-12-19 19:16:21,477 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,483 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,483 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,483 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,483 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,483 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,484 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,484 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,507 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,554 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,554 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,554 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,563 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,564 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2021-12-19 19:16:21,576 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,581 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,581 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,582 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,582 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,582 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,583 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,583 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,603 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,620 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,620 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,620 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,621 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,622 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2021-12-19 19:16:21,624 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,631 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,631 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,631 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,631 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,632 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,632 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,632 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,645 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,682 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,683 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,683 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,684 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,684 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2021-12-19 19:16:21,686 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,693 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,693 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,693 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,693 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:21,693 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,694 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:21,694 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,695 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,718 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2021-12-19 19:16:21,718 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,718 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,720 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,722 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2021-12-19 19:16:21,723 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,730 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,731 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,731 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,731 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,731 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,731 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,731 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,745 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,768 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2021-12-19 19:16:21,769 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,769 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,770 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,770 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2021-12-19 19:16:21,772 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,779 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,779 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,779 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,779 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,779 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,780 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,780 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,793 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,817 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,817 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,817 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,818 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,821 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,822 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2021-12-19 19:16:21,827 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,828 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,828 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,828 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,828 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,828 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,828 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,829 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,852 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2021-12-19 19:16:21,853 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,853 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,853 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,854 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2021-12-19 19:16:21,855 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,861 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,861 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,861 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,861 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,861 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,862 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,862 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,871 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,886 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,886 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,887 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,887 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,889 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2021-12-19 19:16:21,890 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,896 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,897 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,897 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,897 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,897 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,897 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,897 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,898 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,920 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2021-12-19 19:16:21,921 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,921 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,922 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,924 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2021-12-19 19:16:21,925 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,930 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,931 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,931 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,931 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:21,931 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,932 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:21,932 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,940 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:21,959 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:21,959 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:21,959 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:21,960 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:21,961 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2021-12-19 19:16:21,962 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:21,967 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:21,968 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:21,968 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:21,968 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:21,968 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:21,968 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:21,968 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:21,995 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,018 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,019 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,019 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,020 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,020 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2021-12-19 19:16:22,023 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,028 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,028 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,028 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,029 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,029 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,029 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,029 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,030 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,045 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,045 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,045 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,046 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,047 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2021-12-19 19:16:22,048 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,055 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,056 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,056 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,056 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,056 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,064 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,065 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,079 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,100 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,101 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,101 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,102 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,103 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2021-12-19 19:16:22,104 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,110 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,110 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,110 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,110 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2021-12-19 19:16:22,110 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,111 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2021-12-19 19:16:22,111 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,112 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,127 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2021-12-19 19:16:22,128 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,128 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,129 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,129 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2021-12-19 19:16:22,130 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,136 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,136 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,136 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,136 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,136 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,137 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,137 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,137 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,153 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,153 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,153 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,154 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,156 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2021-12-19 19:16:22,158 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,163 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,164 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,164 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,164 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,164 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,164 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,164 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,165 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,180 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2021-12-19 19:16:22,180 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,180 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,181 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,182 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2021-12-19 19:16:22,183 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,189 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,189 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,189 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,189 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,189 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,191 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,191 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,192 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,207 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2021-12-19 19:16:22,207 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,208 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,208 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,212 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2021-12-19 19:16:22,214 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,220 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,220 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,220 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,220 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,220 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,221 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,221 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,228 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,243 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2021-12-19 19:16:22,243 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,243 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,244 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,245 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2021-12-19 19:16:22,246 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,251 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,252 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,252 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,252 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,252 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,252 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,252 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,253 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,268 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2021-12-19 19:16:22,268 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,268 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,269 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,270 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2021-12-19 19:16:22,272 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,278 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,278 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,278 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,278 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,278 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,278 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,278 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,290 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,305 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,306 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,306 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,307 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2021-12-19 19:16:22,309 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,315 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,315 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,316 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,316 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,316 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,316 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,316 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,343 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,372 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,372 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,372 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,374 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,374 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2021-12-19 19:16:22,376 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,381 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,381 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,381 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,381 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,381 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,381 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,382 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,382 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,397 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,397 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,397 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,398 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,400 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2021-12-19 19:16:22,401 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,406 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,406 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,406 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,406 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,406 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,407 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,407 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,422 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-12-19 19:16:22,437 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,437 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,437 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,438 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,439 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2021-12-19 19:16:22,440 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-12-19 19:16:22,445 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-12-19 19:16:22,445 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-12-19 19:16:22,445 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-12-19 19:16:22,445 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-12-19 19:16:22,445 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-12-19 19:16:22,446 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-12-19 19:16:22,446 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-12-19 19:16:22,461 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-12-19 19:16:22,463 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-12-19 19:16:22,463 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-12-19 19:16:22,464 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:22,464 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:22,465 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:22,466 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2021-12-19 19:16:22,467 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-12-19 19:16:22,467 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-12-19 19:16:22,467 INFO L513 LassoAnalysis]: Proved termination. [2021-12-19 19:16:22,467 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2021-12-19 19:16:22,482 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:22,483 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-12-19 19:16:22,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:22,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:22,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 2 conjunts are in the unsatisfiable core [2021-12-19 19:16:22,567 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-19 19:16:22,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:22,721 INFO L263 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-19 19:16:22,722 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-19 19:16:22,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:23,001 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2021-12-19 19:16:23,002 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 52728 states and 69013 transitions. cyclomatic complexity: 16287 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:23,429 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 52728 states and 69013 transitions. cyclomatic complexity: 16287. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 105938 states and 139280 transitions. Complement of second has 4 states. [2021-12-19 19:16:23,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-12-19 19:16:23,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:23,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 970 transitions. [2021-12-19 19:16:23,432 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 970 transitions. Stem has 84 letters. Loop has 100 letters. [2021-12-19 19:16:23,434 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:23,434 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 970 transitions. Stem has 184 letters. Loop has 100 letters. [2021-12-19 19:16:23,435 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:23,435 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 970 transitions. Stem has 84 letters. Loop has 200 letters. [2021-12-19 19:16:23,436 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-12-19 19:16:23,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105938 states and 139280 transitions. [2021-12-19 19:16:24,119 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2021-12-19 19:16:24,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52568 [2021-12-19 19:16:24,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105938 states to 105938 states and 139280 transitions. [2021-12-19 19:16:24,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52729 [2021-12-19 19:16:24,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53018 [2021-12-19 19:16:24,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105938 states and 139280 transitions. [2021-12-19 19:16:24,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:24,505 INFO L681 BuchiCegarLoop]: Abstraction has 105938 states and 139280 transitions. [2021-12-19 19:16:24,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105938 states and 139280 transitions. [2021-12-19 19:16:25,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105938 to 105649. [2021-12-19 19:16:25,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105649 states, 105649 states have (on average 1.3134719684994651) internal successors, (138767), 105648 states have internal predecessors, (138767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105649 states to 105649 states and 138767 transitions. [2021-12-19 19:16:25,913 INFO L704 BuchiCegarLoop]: Abstraction has 105649 states and 138767 transitions. [2021-12-19 19:16:25,913 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,914 INFO L87 Difference]: Start difference. First operand 105649 states and 138767 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:26,257 INFO L93 Difference]: Finished difference Result 112145 states and 146223 transitions. [2021-12-19 19:16:26,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:26,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112145 states and 146223 transitions. [2021-12-19 19:16:26,723 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 55816 [2021-12-19 19:16:27,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112145 states to 112145 states and 146223 transitions. [2021-12-19 19:16:27,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55977 [2021-12-19 19:16:27,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55977 [2021-12-19 19:16:27,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112145 states and 146223 transitions. [2021-12-19 19:16:27,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:27,058 INFO L681 BuchiCegarLoop]: Abstraction has 112145 states and 146223 transitions. [2021-12-19 19:16:27,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112145 states and 146223 transitions. [2021-12-19 19:16:28,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112145 to 105649. [2021-12-19 19:16:28,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105649 states, 105649 states have (on average 1.3098372914083427) internal successors, (138383), 105648 states have internal predecessors, (138383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:28,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105649 states to 105649 states and 138383 transitions. [2021-12-19 19:16:28,560 INFO L704 BuchiCegarLoop]: Abstraction has 105649 states and 138383 transitions. [2021-12-19 19:16:28,560 INFO L587 BuchiCegarLoop]: Abstraction has 105649 states and 138383 transitions. [2021-12-19 19:16:28,561 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-19 19:16:28,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105649 states and 138383 transitions. [2021-12-19 19:16:28,839 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52568 [2021-12-19 19:16:28,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:28,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:28,853 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,853 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,854 INFO L791 eck$LassoCheckResult]: Stem: 1696906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1696779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1696725#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1696657#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1695585#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1695586#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1696279#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1696280#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1696115#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1695688#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1695689#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1695557#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1695558#L684 assume !(0 == ~M_E~0); 1696561#L684-2 assume !(0 == ~T1_E~0); 1696188#L689-1 assume !(0 == ~T2_E~0); 1696189#L694-1 assume !(0 == ~T3_E~0); 1696186#L699-1 assume !(0 == ~T4_E~0); 1696187#L704-1 assume !(0 == ~T5_E~0); 1696082#L709-1 assume !(0 == ~T6_E~0); 1695952#L714-1 assume !(0 == ~E_M~0); 1695953#L719-1 assume !(0 == ~E_1~0); 1696491#L724-1 assume !(0 == ~E_2~0); 1695508#L729-1 assume !(0 == ~E_3~0); 1695509#L734-1 assume !(0 == ~E_4~0); 1696645#L739-1 assume !(0 == ~E_5~0); 1695869#L744-1 assume !(0 == ~E_6~0); 1695870#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1695432#L334 assume !(1 == ~m_pc~0); 1695433#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1696065#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1696662#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1695817#L849 assume !(0 != activate_threads_~tmp~1#1); 1695818#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1695682#L353 assume !(1 == ~t1_pc~0); 1695683#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1696286#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1695525#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1695526#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1695591#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1695592#L372 assume !(1 == ~t2_pc~0); 1695790#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1695836#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1696932#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1696931#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1695408#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1695409#L391 assume !(1 == ~t3_pc~0); 1695256#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1695257#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1695655#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1696060#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1695826#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1695827#L410 assume !(1 == ~t4_pc~0); 1696321#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1696322#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1696415#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1696622#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1695839#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1695840#L429 assume !(1 == ~t5_pc~0); 1695514#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1695515#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1696933#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1696339#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1696340#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1695805#L448 assume !(1 == ~t6_pc~0); 1695656#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1695657#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1696329#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1696521#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1696719#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1696865#L762 assume !(1 == ~M_E~0); 1695911#L762-2 assume !(1 == ~T1_E~0); 1695912#L767-1 assume !(1 == ~T2_E~0); 1696733#L772-1 assume !(1 == ~T3_E~0); 1696396#L777-1 assume !(1 == ~T4_E~0); 1696144#L782-1 assume !(1 == ~T5_E~0); 1695565#L787-1 assume !(1 == ~T6_E~0); 1695563#L792-1 assume !(1 == ~E_M~0); 1695564#L797-1 assume !(1 == ~E_1~0); 1695628#L802-1 assume !(1 == ~E_2~0); 1696070#L807-1 assume !(1 == ~E_3~0); 1696071#L812-1 assume !(1 == ~E_4~0); 1696636#L817-1 assume !(1 == ~E_5~0); 1696190#L822-1 assume !(1 == ~E_6~0); 1696191#L827-1 assume { :end_inline_reset_delta_events } true; 1696658#L1053-2 assume !false; 1763295#L1054 [2021-12-19 19:16:28,861 INFO L793 eck$LassoCheckResult]: Loop: 1763295#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1784129#L659 assume !false; 1784121#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1784114#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1784101#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1784090#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1784081#L570 assume 0 != eval_~tmp~0#1; 1784073#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1784064#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 1784065#L74 assume 0 == ~m_pc~0; 1799345#L99-1 assume !false; 1799344#L86 ~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1799343#L334-3 assume !(1 == ~m_pc~0); 1799342#L334-5 is_master_triggered_~__retres1~0#1 := 0; 1799340#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1799338#L346-1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1799336#L849-3 assume !(0 != activate_threads_~tmp~1#1); 1799334#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1799332#L353-3 assume !(1 == ~t1_pc~0); 1799327#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1799307#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1799305#L365-1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1799302#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 1799299#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1799296#L372-3 assume 1 == ~t2_pc~0; 1799280#L373-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1799276#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1799272#L384-1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1799267#L865-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1799262#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1799258#L391-3 assume !(1 == ~t3_pc~0); 1799085#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1799252#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1799237#L403-1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1799235#L873-3 assume !(0 != activate_threads_~tmp___2~0#1); 1799232#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1799229#L410-3 assume !(1 == ~t4_pc~0); 1796921#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1799224#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1799221#L422-1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1799219#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 1799216#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1799212#L429-3 assume !(1 == ~t5_pc~0); 1799208#L429-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1799203#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1799198#L441-1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1799192#L889-3 assume !(0 != activate_threads_~tmp___4~0#1); 1799186#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1776188#L448-3 assume !(1 == ~t6_pc~0); 1776186#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1776184#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1776182#L460-1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1776175#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 1776173#L897-5 assume { :end_inline_activate_threads } true; 1776171#L914 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1776039#L107 assume { :end_inline_master } true; 1776037#L575 assume !(0 == ~t1_st~0); 1776033#L589 assume !(0 == ~t2_st~0); 1776029#L603 assume !(0 == ~t3_st~0); 1776026#L617 assume !(0 == ~t4_st~0); 1776024#L631 assume !(0 == ~t5_st~0); 1776067#L645 assume !(0 == ~t6_st~0); 1776062#L659 assume !false; 1776060#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1776058#L518 assume !(0 == ~m_st~0); 1776056#L522 assume !(0 == ~t1_st~0); 1776052#L526 assume !(0 == ~t2_st~0); 1776053#L530 assume !(0 == ~t3_st~0); 1776055#L534 assume !(0 == ~t4_st~0); 1776050#L538 assume !(0 == ~t5_st~0); 1776051#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1776054#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1776726#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1776724#L570 assume !(0 != eval_~tmp~0#1); 1776722#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1776720#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1776718#L684-3 assume !(0 == ~M_E~0); 1776716#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1776714#L689-3 assume !(0 == ~T2_E~0); 1776712#L694-3 assume !(0 == ~T3_E~0); 1776710#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1776708#L704-3 assume !(0 == ~T5_E~0); 1776705#L709-3 assume !(0 == ~T6_E~0); 1776703#L714-3 assume !(0 == ~E_M~0); 1776701#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1776699#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1776697#L729-3 assume !(0 == ~E_3~0); 1776695#L734-3 assume !(0 == ~E_4~0); 1776693#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1776691#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1776689#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1776687#L334-24 assume 1 == ~m_pc~0; 1776681#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1776682#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1776675#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1776676#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1780193#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1780192#L353-24 assume !(1 == ~t1_pc~0); 1780191#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1780190#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1780189#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1780188#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1780187#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1780185#L372-24 assume !(1 == ~t2_pc~0); 1780184#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1780204#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1780202#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1780177#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1780175#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1780174#L391-24 assume !(1 == ~t3_pc~0); 1777238#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1780171#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1780170#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1780169#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1780167#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1780162#L410-24 assume !(1 == ~t4_pc~0); 1778912#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1780145#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1780137#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1780117#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 1780110#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1780104#L429-24 assume 1 == ~t5_pc~0; 1780091#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1780079#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1780068#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1779809#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1779775#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1695553#L448-24 assume !(1 == ~t6_pc~0); 1695554#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1695533#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1695534#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1696450#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 1696171#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1696172#L762-3 assume !(1 == ~M_E~0); 1696656#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1793578#L767-3 assume !(1 == ~T2_E~0); 1793574#L772-3 assume !(1 == ~T3_E~0); 1793572#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1793570#L782-3 assume !(1 == ~T5_E~0); 1771589#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1771586#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1771584#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1771582#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1771407#L807-3 assume !(1 == ~E_3~0); 1771404#L812-3 assume !(1 == ~E_4~0); 1771402#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1771400#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1771398#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1771396#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1771394#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1771393#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1771391#L1072 assume !(0 == start_simulation_~tmp~3#1); 1771392#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1784211#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1784203#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1784197#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1784191#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1784185#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1784182#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1784165#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1784147#L1053-2 assume !false; 1763295#L1054 [2021-12-19 19:16:28,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,862 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 1 times [2021-12-19 19:16:28,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796564985] [2021-12-19 19:16:28,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,874 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:28,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,887 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:28,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1697568925, now seen corresponding path program 1 times [2021-12-19 19:16:28,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,888 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496866129] [2021-12-19 19:16:28,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:28,910 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:28,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:28,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496866129] [2021-12-19 19:16:28,910 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496866129] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:28,910 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:28,910 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:28,910 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835825438] [2021-12-19 19:16:28,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:28,911 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:28,911 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:28,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:28,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:28,911 INFO L87 Difference]: Start difference. First operand 105649 states and 138383 transitions. cyclomatic complexity: 32738 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:29,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:29,867 INFO L93 Difference]: Finished difference Result 196929 states and 256223 transitions. [2021-12-19 19:16:29,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:29,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196929 states and 256223 transitions. [2021-12-19 19:16:30,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 98032 [2021-12-19 19:16:31,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196929 states to 196929 states and 256223 transitions. [2021-12-19 19:16:31,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98257 [2021-12-19 19:16:31,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98257 [2021-12-19 19:16:31,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196929 states and 256223 transitions. [2021-12-19 19:16:31,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:31,585 INFO L681 BuchiCegarLoop]: Abstraction has 196929 states and 256223 transitions. [2021-12-19 19:16:31,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196929 states and 256223 transitions. [2021-12-19 19:16:33,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196929 to 189633. [2021-12-19 19:16:33,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 189633 states, 189633 states have (on average 1.3086277177495478) internal successors, (248159), 189632 states have internal predecessors, (248159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:33,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189633 states to 189633 states and 248159 transitions. [2021-12-19 19:16:33,655 INFO L704 BuchiCegarLoop]: Abstraction has 189633 states and 248159 transitions. [2021-12-19 19:16:33,655 INFO L587 BuchiCegarLoop]: Abstraction has 189633 states and 248159 transitions. [2021-12-19 19:16:33,655 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-19 19:16:33,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 189633 states and 248159 transitions. [2021-12-19 19:16:34,151 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 94384 [2021-12-19 19:16:34,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:34,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:34,172 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:34,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:34,173 INFO L791 eck$LassoCheckResult]: Stem: 1999605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1999421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1999366#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1999294#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1998173#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1998174#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1998871#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1998872#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1998701#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1998276#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1998277#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1998145#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1998146#L684 assume !(0 == ~M_E~0); 1999174#L684-2 assume !(0 == ~T1_E~0); 1998777#L689-1 assume !(0 == ~T2_E~0); 1998778#L694-1 assume !(0 == ~T3_E~0); 1998775#L699-1 assume !(0 == ~T4_E~0); 1998776#L704-1 assume !(0 == ~T5_E~0); 1998668#L709-1 assume !(0 == ~T6_E~0); 1998541#L714-1 assume !(0 == ~E_M~0); 1998542#L719-1 assume !(0 == ~E_1~0); 1999098#L724-1 assume !(0 == ~E_2~0); 1998094#L729-1 assume !(0 == ~E_3~0); 1998095#L734-1 assume !(0 == ~E_4~0); 1999277#L739-1 assume !(0 == ~E_5~0); 1998455#L744-1 assume !(0 == ~E_6~0); 1998456#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1998018#L334 assume !(1 == ~m_pc~0); 1998019#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1998650#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1999299#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1998407#L849 assume !(0 != activate_threads_~tmp~1#1); 1998408#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1998270#L353 assume !(1 == ~t1_pc~0); 1998271#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1998878#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1998111#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1998112#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1998179#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1998180#L372 assume !(1 == ~t2_pc~0); 1998379#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1998424#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1999638#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1999637#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1997993#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1997994#L391 assume !(1 == ~t3_pc~0); 1997840#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1997841#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1998243#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1998645#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1998416#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1998417#L410 assume !(1 == ~t4_pc~0); 1998911#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1998912#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1999015#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1999247#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1998427#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1998428#L429 assume !(1 == ~t5_pc~0); 1998100#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1998101#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1999639#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1998930#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1998931#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1998395#L448 assume !(1 == ~t6_pc~0); 1998244#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1998245#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1998920#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1999133#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1999353#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1999541#L762 assume !(1 == ~M_E~0); 1998496#L762-2 assume !(1 == ~T1_E~0); 1998497#L767-1 assume !(1 == ~T2_E~0); 1999374#L772-1 assume !(1 == ~T3_E~0); 1998995#L777-1 assume !(1 == ~T4_E~0); 1998732#L782-1 assume !(1 == ~T5_E~0); 1998153#L787-1 assume !(1 == ~T6_E~0); 1998151#L792-1 assume !(1 == ~E_M~0); 1998152#L797-1 assume !(1 == ~E_1~0); 1998217#L802-1 assume !(1 == ~E_2~0); 1998656#L807-1 assume !(1 == ~E_3~0); 1998657#L812-1 assume !(1 == ~E_4~0); 1999264#L817-1 assume !(1 == ~E_5~0); 1998779#L822-1 assume !(1 == ~E_6~0); 1998780#L827-1 assume { :end_inline_reset_delta_events } true; 1999295#L1053-2 assume !false; 2068858#L1054 [2021-12-19 19:16:34,173 INFO L793 eck$LassoCheckResult]: Loop: 2068858#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2117678#L659 assume !false; 2148952#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2148950#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2148947#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2148945#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2148943#L570 assume 0 != eval_~tmp~0#1; 2148942#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2148939#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 2148940#L74 assume 0 == ~m_pc~0; 2186474#L99-1 assume !false; 2186472#L86 ~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1999625#L334-3 assume !(1 == ~m_pc~0); 1999267#L334-5 is_master_triggered_~__retres1~0#1 := 0; 1998196#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1998197#L346-1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1998996#L849-3 assume !(0 != activate_threads_~tmp~1#1); 1999349#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1999354#L353-3 assume !(1 == ~t1_pc~0); 1999355#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 2187103#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2187100#L365-1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2187098#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 2187096#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2187094#L372-3 assume !(1 == ~t2_pc~0); 1999412#L372-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1999413#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2186064#L384-1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2186062#L865-3 assume !(0 != activate_threads_~tmp___1~0#1); 1998983#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1999127#L391-3 assume !(1 == ~t3_pc~0); 2169813#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 2169811#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2169783#L403-1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2169777#L873-3 assume !(0 != activate_threads_~tmp___2~0#1); 2169773#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2169771#L410-3 assume !(1 == ~t4_pc~0); 2147721#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 2169755#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2169748#L422-1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2169744#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 2169741#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2169697#L429-3 assume !(1 == ~t5_pc~0); 2169645#L429-5 is_transmit5_triggered_~__retres1~5#1 := 0; 2169733#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2169698#L441-1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2169561#L889-3 assume !(0 != activate_threads_~tmp___4~0#1); 2169459#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2167321#L448-3 assume !(1 == ~t6_pc~0); 2167319#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 2167317#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2167316#L460-1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2167315#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 2167314#L897-5 assume { :end_inline_activate_threads } true; 2167311#L914 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 2167129#L107 assume { :end_inline_master } true; 2167126#L575 assume !(0 == ~t1_st~0); 2167122#L589 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2119333#L606 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 2167068#L154 assume 0 == ~t2_pc~0; 2176859#L165-1 assume !false; 2176858#L166 ~t2_pc~0 := 1;~t2_st~0 := 2; 2119331#L179 assume { :end_inline_transmit2 } true; 2119326#L603 assume !(0 == ~t3_st~0); 2119324#L617 assume !(0 == ~t4_st~0); 2125093#L631 assume !(0 == ~t5_st~0); 2125090#L645 assume !(0 == ~t6_st~0); 2125088#L659 assume !false; 2152672#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2152669#L518 assume !(0 == ~m_st~0); 2152667#L522 assume !(0 == ~t1_st~0); 2152664#L526 assume !(0 == ~t2_st~0); 2152663#L530 assume !(0 == ~t3_st~0); 2152662#L534 assume !(0 == ~t4_st~0); 2152661#L538 assume !(0 == ~t5_st~0); 2152659#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 2152658#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2152657#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2152655#L570 assume !(0 != eval_~tmp~0#1); 2152654#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2152653#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2152651#L684-3 assume !(0 == ~M_E~0); 2152649#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2152647#L689-3 assume !(0 == ~T2_E~0); 2152645#L694-3 assume !(0 == ~T3_E~0); 2152643#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2152641#L704-3 assume !(0 == ~T5_E~0); 2152637#L709-3 assume !(0 == ~T6_E~0); 2152633#L714-3 assume !(0 == ~E_M~0); 2152631#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2152629#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2152627#L729-3 assume !(0 == ~E_3~0); 2152626#L734-3 assume !(0 == ~E_4~0); 2152625#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2152624#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2152622#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2152620#L334-24 assume 1 == ~m_pc~0; 2152617#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2152614#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2152612#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2152609#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2152607#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2152604#L353-24 assume !(1 == ~t1_pc~0); 2152602#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 2152600#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2152597#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2152595#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 2152593#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2152591#L372-24 assume !(1 == ~t2_pc~0); 2152587#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2152585#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2152583#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2152580#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2141352#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2141349#L391-24 assume !(1 == ~t3_pc~0); 2141348#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 2141347#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2141345#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2141342#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 2141339#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2141335#L410-24 assume !(1 == ~t4_pc~0); 2137411#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2141324#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2141319#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2141301#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 2141293#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2141289#L429-24 assume !(1 == ~t5_pc~0); 2141284#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 2141280#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2141278#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2141276#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 2141273#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2141268#L448-24 assume !(1 == ~t6_pc~0); 2113789#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2141261#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2141258#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2141254#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 2141252#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2141248#L762-3 assume !(1 == ~M_E~0); 2141055#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2141240#L767-3 assume !(1 == ~T2_E~0); 2141236#L772-3 assume !(1 == ~T3_E~0); 2141232#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2141226#L782-3 assume !(1 == ~T5_E~0); 2141224#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2141220#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2141216#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2141213#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2141210#L807-3 assume !(1 == ~E_3~0); 2141208#L812-3 assume !(1 == ~E_4~0); 2141206#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2141204#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2141200#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2141197#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2141193#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2141190#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2141186#L1072 assume !(0 == start_simulation_~tmp~3#1); 2141187#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2149094#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2149092#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2149090#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2149088#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2149087#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2149086#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2149085#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 2149083#L1053-2 assume !false; 2068858#L1054 [2021-12-19 19:16:34,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:34,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 2 times [2021-12-19 19:16:34,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:34,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737759099] [2021-12-19 19:16:34,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:34,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:34,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:34,179 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:34,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:34,205 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:34,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:34,206 INFO L85 PathProgramCache]: Analyzing trace with hash -128072748, now seen corresponding path program 1 times [2021-12-19 19:16:34,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:34,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807418569] [2021-12-19 19:16:34,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:34,206 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:34,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:34,235 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:34,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:34,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807418569] [2021-12-19 19:16:34,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807418569] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:34,236 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:34,236 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:34,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881445405] [2021-12-19 19:16:34,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:34,237 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:34,237 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:34,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:34,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:34,238 INFO L87 Difference]: Start difference. First operand 189633 states and 248159 transitions. cyclomatic complexity: 58530 Second operand has 3 states, 3 states have (on average 55.333333333333336) internal successors, (166), 3 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:35,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:35,203 INFO L93 Difference]: Finished difference Result 186177 states and 241373 transitions. [2021-12-19 19:16:35,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:35,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186177 states and 241373 transitions. [2021-12-19 19:16:35,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 92656 [2021-12-19 19:16:36,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186177 states to 186177 states and 241373 transitions. [2021-12-19 19:16:36,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92881 [2021-12-19 19:16:36,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92881 [2021-12-19 19:16:36,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186177 states and 241373 transitions. [2021-12-19 19:16:36,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-12-19 19:16:36,323 INFO L681 BuchiCegarLoop]: Abstraction has 186177 states and 241373 transitions. [2021-12-19 19:16:36,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186177 states and 241373 transitions. [2021-12-19 19:16:38,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186177 to 186177. [2021-12-19 19:16:38,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186177 states, 186177 states have (on average 1.2964705629589046) internal successors, (241373), 186176 states have internal predecessors, (241373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:38,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186177 states to 186177 states and 241373 transitions. [2021-12-19 19:16:38,908 INFO L704 BuchiCegarLoop]: Abstraction has 186177 states and 241373 transitions. [2021-12-19 19:16:38,908 INFO L587 BuchiCegarLoop]: Abstraction has 186177 states and 241373 transitions. [2021-12-19 19:16:38,908 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-19 19:16:38,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186177 states and 241373 transitions. [2021-12-19 19:16:39,353 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 92656 [2021-12-19 19:16:39,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:39,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:39,374 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:39,375 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:39,375 INFO L791 eck$LassoCheckResult]: Stem: 2375373#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2375200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2375151#L1016 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2375082#L468 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2373990#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2373991#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2374683#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2374684#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2374518#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2374092#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2374093#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2373965#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2373966#L684 assume !(0 == ~M_E~0); 2374974#L684-2 assume !(0 == ~T1_E~0); 2374590#L689-1 assume !(0 == ~T2_E~0); 2374591#L694-1 assume !(0 == ~T3_E~0); 2374588#L699-1 assume !(0 == ~T4_E~0); 2374589#L704-1 assume !(0 == ~T5_E~0); 2374486#L709-1 assume !(0 == ~T6_E~0); 2374353#L714-1 assume !(0 == ~E_M~0); 2374354#L719-1 assume !(0 == ~E_1~0); 2374902#L724-1 assume !(0 == ~E_2~0); 2373910#L729-1 assume !(0 == ~E_3~0); 2373911#L734-1 assume !(0 == ~E_4~0); 2375068#L739-1 assume !(0 == ~E_5~0); 2374268#L744-1 assume !(0 == ~E_6~0); 2374269#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2373835#L334 assume !(1 == ~m_pc~0); 2373836#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2374465#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2375085#L346 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2374217#L849 assume !(0 != activate_threads_~tmp~1#1); 2374218#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2374086#L353 assume !(1 == ~t1_pc~0); 2374087#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2374690#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2373927#L365 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2373928#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2373996#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2373997#L372 assume !(1 == ~t2_pc~0); 2374190#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2374233#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2375401#L384 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2375400#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2373815#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2373816#L391 assume !(1 == ~t3_pc~0); 2373656#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2373657#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2374059#L403 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2374461#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2374225#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2374226#L410 assume !(1 == ~t4_pc~0); 2374725#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2374726#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2374821#L422 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2375048#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2374237#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2374238#L429 assume !(1 == ~t5_pc~0); 2373916#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2373917#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2375402#L441 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2374740#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2374741#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2374208#L448 assume !(1 == ~t6_pc~0); 2374060#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2374061#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2374736#L460 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2374928#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2375140#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2375309#L762 assume !(1 == ~M_E~0); 2374312#L762-2 assume !(1 == ~T1_E~0); 2374313#L767-1 assume !(1 == ~T2_E~0); 2375159#L772-1 assume !(1 == ~T3_E~0); 2374806#L777-1 assume !(1 == ~T4_E~0); 2374548#L782-1 assume !(1 == ~T5_E~0); 2373969#L787-1 assume !(1 == ~T6_E~0); 2373967#L792-1 assume !(1 == ~E_M~0); 2373968#L797-1 assume !(1 == ~E_1~0); 2374036#L802-1 assume !(1 == ~E_2~0); 2374472#L807-1 assume !(1 == ~E_3~0); 2374473#L812-1 assume !(1 == ~E_4~0); 2375061#L817-1 assume !(1 == ~E_5~0); 2374592#L822-1 assume !(1 == ~E_6~0); 2374593#L827-1 assume { :end_inline_reset_delta_events } true; 2375083#L1053-2 assume !false; 2399853#L1054 [2021-12-19 19:16:39,375 INFO L793 eck$LassoCheckResult]: Loop: 2399853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2484321#L659 assume !false; 2484320#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2484319#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2484318#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2484317#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2484316#L570 assume 0 != eval_~tmp~0#1; 2484314#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2484311#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 2484309#L74 assume 0 == ~m_pc~0; 2484306#L99-1 assume !false; 2484305#L86 ~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2484303#L334-3 assume 1 == ~m_pc~0; 2484301#L335-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2484302#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2484304#L346-1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2484294#L849-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2484293#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2484291#L353-3 assume !(1 == ~t1_pc~0); 2484289#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 2484287#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2484285#L365-1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2484283#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 2484281#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2484279#L372-3 assume 1 == ~t2_pc~0; 2484277#L373-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2484232#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2484273#L384-1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2484271#L865-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2484224#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484268#L391-3 assume !(1 == ~t3_pc~0); 2484127#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 2484263#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2484261#L403-1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2484257#L873-3 assume !(0 != activate_threads_~tmp___2~0#1); 2484255#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2471594#L410-3 assume !(1 == ~t4_pc~0); 2471590#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 2471584#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2471576#L422-1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2471571#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 2471565#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2471558#L429-3 assume !(1 == ~t5_pc~0); 2471551#L429-5 is_transmit5_triggered_~__retres1~5#1 := 0; 2471543#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2471533#L441-1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2471523#L889-3 assume !(0 != activate_threads_~tmp___4~0#1); 2471515#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2471509#L448-3 assume !(1 == ~t6_pc~0); 2469527#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 2471496#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2471487#L460-1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2471480#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 2471474#L897-5 assume { :end_inline_activate_threads } true; 2471469#L914 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 2471465#L107 assume { :end_inline_master } true; 2471461#L575 assume !(0 == ~t1_st~0); 2471456#L589 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2471431#L606 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 2471447#L154 assume 0 == ~t2_pc~0; 2471440#L165-1 assume !false; 2471435#L166 ~t2_pc~0 := 1;~t2_st~0 := 2; 2471429#L179 assume { :end_inline_transmit2 } true; 2471427#L603 assume !(0 == ~t3_st~0); 2471424#L617 assume !(0 == ~t4_st~0); 2471420#L631 assume !(0 == ~t5_st~0); 2471417#L645 assume !(0 == ~t6_st~0); 2471416#L659 assume !false; 2485831#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2485830#L518 assume !(0 == ~m_st~0); 2484178#L522 assume !(0 == ~t1_st~0); 2484179#L526 assume !(0 == ~t2_st~0); 2484176#L530 assume !(0 == ~t3_st~0); 2484177#L534 assume !(0 == ~t4_st~0); 2484173#L538 assume !(0 == ~t5_st~0); 2484175#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 2484170#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2484171#L556 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2509964#L570 assume !(0 != eval_~tmp~0#1); 2509962#L674 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2509960#L468-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2509958#L684-3 assume !(0 == ~M_E~0); 2509952#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2509946#L689-3 assume !(0 == ~T2_E~0); 2509943#L694-3 assume !(0 == ~T3_E~0); 2509940#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2509931#L704-3 assume !(0 == ~T5_E~0); 2509928#L709-3 assume !(0 == ~T6_E~0); 2509924#L714-3 assume !(0 == ~E_M~0); 2509919#L719-3 assume !(0 == ~E_1~0); 2509912#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2509905#L729-3 assume !(0 == ~E_3~0); 2509899#L734-3 assume !(0 == ~E_4~0); 2509897#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2509885#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2507769#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2507766#L334-24 assume 1 == ~m_pc~0; 2507763#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2507761#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2507759#L346-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2507756#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2507754#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2507752#L353-24 assume !(1 == ~t1_pc~0); 2507750#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 2507746#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2507744#L365-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2507742#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 2507740#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2507737#L372-24 assume 1 == ~t2_pc~0; 2507734#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2507732#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2507442#L384-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2498532#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2498530#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2498528#L391-24 assume !(1 == ~t3_pc~0); 2495138#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 2498527#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2498525#L403-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2498524#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 2498523#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2498521#L410-24 assume !(1 == ~t4_pc~0); 2490824#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2498520#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2498519#L422-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2498518#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 2498517#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2498515#L429-24 assume !(1 == ~t5_pc~0); 2498512#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 2498511#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2498509#L441-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2498507#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 2498505#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2498504#L448-24 assume !(1 == ~t6_pc~0); 2495247#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2498501#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2498500#L460-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2498499#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 2498497#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2494792#L762-3 assume !(1 == ~M_E~0); 2494788#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2494786#L767-3 assume !(1 == ~T2_E~0); 2494784#L772-3 assume !(1 == ~T3_E~0); 2494782#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2494780#L782-3 assume !(1 == ~T5_E~0); 2494778#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2494775#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2494773#L797-3 assume !(1 == ~E_1~0); 2494771#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2494764#L807-3 assume !(1 == ~E_3~0); 2494761#L812-3 assume !(1 == ~E_4~0); 2494760#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2494758#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2494756#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2494752#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2494750#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2494748#L556-1 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2494745#L1072 assume !(0 == start_simulation_~tmp~3#1); 2494741#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2494739#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2494737#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2494736#L556-2 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2494735#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2494734#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2494733#L1035 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2494732#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 2494731#L1053-2 assume !false; 2399853#L1054 [2021-12-19 19:16:39,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:39,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 3 times [2021-12-19 19:16:39,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:39,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089785276] [2021-12-19 19:16:39,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:39,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:39,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:39,381 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:39,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:39,390 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:39,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:39,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1259085819, now seen corresponding path program 1 times [2021-12-19 19:16:39,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:39,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054630182] [2021-12-19 19:16:39,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:39,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:39,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:39,404 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:39,404 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:39,404 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054630182] [2021-12-19 19:16:39,404 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054630182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:39,404 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:39,404 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:39,405 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938075077] [2021-12-19 19:16:39,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:39,405 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:39,405 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:39,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:39,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:39,405 INFO L87 Difference]: Start difference. First operand 186177 states and 241373 transitions. cyclomatic complexity: 55200 Second operand has 3 states, 3 states have (on average 55.333333333333336) internal successors, (166), 3 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)