./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:16:00,632 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:16:00,634 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:16:00,705 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:16:00,708 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:16:00,711 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:16:00,713 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:16:00,716 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:16:00,717 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:16:00,721 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:16:00,722 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:16:00,723 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:16:00,723 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:16:00,725 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:16:00,726 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:16:00,731 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:16:00,732 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:16:00,733 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:16:00,736 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:16:00,741 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:16:00,743 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:16:00,744 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:16:00,745 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:16:00,746 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:16:00,751 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:16:00,752 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:16:00,752 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:16:00,753 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:16:00,754 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:16:00,754 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:16:00,754 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:16:00,755 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:16:00,756 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:16:00,757 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:16:00,758 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:16:00,759 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:16:00,759 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:16:00,759 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:16:00,760 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:16:00,760 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:16:00,761 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:16:00,762 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:16:00,793 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:16:00,794 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:16:00,794 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:16:00,794 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:16:00,796 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:16:00,796 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:16:00,796 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:16:00,796 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:16:00,796 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:16:00,796 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:16:00,797 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:16:00,797 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:16:00,798 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:16:00,798 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:16:00,798 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:16:00,798 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:16:00,798 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:16:00,798 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:16:00,799 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:16:00,799 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:16:00,799 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:16:00,799 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:16:00,799 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:16:00,800 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:16:00,800 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:16:00,800 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:16:00,800 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:16:00,800 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:16:00,800 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:16:00,801 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:16:00,801 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:16:00,801 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:16:00,802 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:16:00,802 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2021-12-19 19:16:00,989 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:16:01,015 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:16:01,018 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:16:01,019 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:16:01,020 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:16:01,021 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-12-19 19:16:01,080 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/645a992a8/51ff61ef9e644289b157fdb535cc8add/FLAGae04b79b9 [2021-12-19 19:16:01,533 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:16:01,534 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-12-19 19:16:01,544 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/645a992a8/51ff61ef9e644289b157fdb535cc8add/FLAGae04b79b9 [2021-12-19 19:16:01,559 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/645a992a8/51ff61ef9e644289b157fdb535cc8add [2021-12-19 19:16:01,561 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:16:01,562 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:16:01,564 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:01,564 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:16:01,567 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:16:01,567 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:01,568 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4523383b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01, skipping insertion in model container [2021-12-19 19:16:01,568 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:01,574 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:16:01,618 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:16:01,761 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2021-12-19 19:16:01,829 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:01,837 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:16:01,846 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2021-12-19 19:16:01,907 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:01,930 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:16:01,931 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01 WrapperNode [2021-12-19 19:16:01,931 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:01,932 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:01,932 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:16:01,932 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:16:01,940 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:01,967 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,039 INFO L137 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2370 [2021-12-19 19:16:02,039 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:02,040 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:16:02,040 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:16:02,040 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:16:02,048 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,048 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,056 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,056 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,093 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,118 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,122 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,136 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:16:02,137 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:16:02,137 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:16:02,137 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:16:02,138 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (1/1) ... [2021-12-19 19:16:02,145 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:02,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:02,167 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:02,195 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:16:02,206 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:16:02,206 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:16:02,206 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:16:02,206 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:16:02,286 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:16:02,288 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:16:03,524 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:16:03,537 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:16:03,538 INFO L301 CfgBuilder]: Removed 11 assume(true) statements. [2021-12-19 19:16:03,540 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:03 BoogieIcfgContainer [2021-12-19 19:16:03,540 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:16:03,541 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:16:03,541 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:16:03,545 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:16:03,546 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:03,546 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:16:01" (1/3) ... [2021-12-19 19:16:03,547 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@576963e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:03, skipping insertion in model container [2021-12-19 19:16:03,547 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:03,547 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:01" (2/3) ... [2021-12-19 19:16:03,548 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@576963e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:03, skipping insertion in model container [2021-12-19 19:16:03,548 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:03,548 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:03" (3/3) ... [2021-12-19 19:16:03,549 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2021-12-19 19:16:03,583 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:16:03,583 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:16:03,583 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:16:03,583 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:16:03,584 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:16:03,584 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:16:03,584 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:16:03,584 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:16:03,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:03,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2021-12-19 19:16:03,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:03,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:03,696 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,696 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,696 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:16:03,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:03,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2021-12-19 19:16:03,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:03,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:03,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,720 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:03,727 INFO L791 eck$LassoCheckResult]: Stem: 486#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 925#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 417#L1278true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512#L602true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1006#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 66#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 105#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 711#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 966#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 51#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 281#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 855#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 298#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108#L866true assume !(0 == ~M_E~0); 970#L866-2true assume !(0 == ~T1_E~0); 440#L871-1true assume !(0 == ~T2_E~0); 837#L876-1true assume !(0 == ~T3_E~0); 830#L881-1true assume !(0 == ~T4_E~0); 455#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 276#L891-1true assume !(0 == ~T6_E~0); 443#L896-1true assume !(0 == ~T7_E~0); 575#L901-1true assume !(0 == ~T8_E~0); 466#L906-1true assume !(0 == ~E_M~0); 851#L911-1true assume !(0 == ~E_1~0); 304#L916-1true assume !(0 == ~E_2~0); 577#L921-1true assume !(0 == ~E_3~0); 732#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 864#L931-1true assume !(0 == ~E_5~0); 891#L936-1true assume !(0 == ~E_6~0); 978#L941-1true assume !(0 == ~E_7~0); 307#L946-1true assume !(0 == ~E_8~0); 775#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 896#L430true assume !(1 == ~m_pc~0); 679#L430-2true is_master_triggered_~__retres1~0#1 := 0; 20#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 381#L442true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 817#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 559#L449true assume 1 == ~t1_pc~0; 580#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 813#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L461true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 902#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 477#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346#L468true assume !(1 == ~t2_pc~0); 226#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 428#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280#L480true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 219#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 21#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894#L487true assume 1 == ~t3_pc~0; 818#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#L499true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 262#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343#L506true assume !(1 == ~t4_pc~0); 848#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 971#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752#L518true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 819#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 337#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227#L525true assume 1 == ~t5_pc~0; 188#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 310#L537true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 955#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 140#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334#L544true assume !(1 == ~t6_pc~0); 228#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 495#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998#L556true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 792#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 696#L563true assume 1 == ~t7_pc~0; 514#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368#L575true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 277#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 112#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 496#L582true assume 1 == ~t8_pc~0; 73#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 821#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 981#L594true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 253#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 190#L1137-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 561#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 816#L964-2true assume !(1 == ~T1_E~0); 141#L969-1true assume !(1 == ~T2_E~0); 745#L974-1true assume !(1 == ~T3_E~0); 597#L979-1true assume !(1 == ~T4_E~0); 950#L984-1true assume !(1 == ~T5_E~0); 231#L989-1true assume !(1 == ~T6_E~0); 449#L994-1true assume !(1 == ~T7_E~0); 163#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 566#L1004-1true assume !(1 == ~E_M~0); 33#L1009-1true assume !(1 == ~E_1~0); 157#L1014-1true assume !(1 == ~E_2~0); 549#L1019-1true assume !(1 == ~E_3~0); 791#L1024-1true assume !(1 == ~E_4~0); 120#L1029-1true assume !(1 == ~E_5~0); 172#L1034-1true assume !(1 == ~E_6~0); 982#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 760#L1044-1true assume !(1 == ~E_8~0); 286#L1049-1true assume { :end_inline_reset_delta_events } true; 104#L1315-2true [2021-12-19 19:16:03,729 INFO L793 eck$LassoCheckResult]: Loop: 104#L1315-2true assume !false; 873#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173#L841true assume false; 617#L856true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 987#L602-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 826#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 176#L871-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 265#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 184#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 666#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 323#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 452#L896-3true assume !(0 == ~T7_E~0); 240#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 325#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 587#L911-3true assume 0 == ~E_1~0;~E_1~0 := 1; 505#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 200#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 488#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 583#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 245#L936-3true assume !(0 == ~E_6~0); 336#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 586#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 177#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 865#L430-30true assume !(1 == ~m_pc~0); 625#L430-32true is_master_triggered_~__retres1~0#1 := 0; 250#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75#L442-10true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 531#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 917#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539#L449-30true assume !(1 == ~t1_pc~0); 929#L449-32true is_transmit1_triggered_~__retres1~1#1 := 0; 31#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447#L461-10true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 230#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 382#L468-30true assume !(1 == ~t2_pc~0); 800#L468-32true is_transmit2_triggered_~__retres1~2#1 := 0; 593#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 898#L480-10true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318#L1089-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 773#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222#L487-30true assume 1 == ~t3_pc~0; 211#L488-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 843#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306#L499-10true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 803#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 557#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272#L506-30true assume 1 == ~t4_pc~0; 983#L507-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 288#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 301#L518-10true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614#L1105-30true assume !(0 != activate_threads_~tmp___3~0#1); 223#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 972#L525-30true assume 1 == ~t5_pc~0; 690#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 920#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63#L537-10true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 672#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 225#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96#L544-30true assume !(1 == ~t6_pc~0); 741#L544-32true is_transmit6_triggered_~__retres1~6#1 := 0; 868#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992#L556-10true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 702#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 994#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 662#L563-30true assume !(1 == ~t7_pc~0); 165#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 90#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 939#L575-10true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 909#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 640#L582-30true assume 1 == ~t8_pc~0; 585#L583-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 274#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 693#L594-10true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 904#L1137-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 102#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 209#L969-3true assume !(1 == ~T2_E~0); 98#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 921#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 349#L984-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 986#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 122#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 824#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 474#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 59#L1009-3true assume !(1 == ~E_1~0); 543#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 331#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 968#L1024-3true assume 1 == ~E_4~0;~E_4~0 := 2; 320#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 302#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 548#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 578#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 117#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 453#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 687#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 425#L710-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 136#L1334true assume !(0 == start_simulation_~tmp~3#1); 812#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 146#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 335#L710-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 918#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 735#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 497#L1297true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 710#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 104#L1315-2true [2021-12-19 19:16:03,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,737 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2021-12-19 19:16:03,744 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345264036] [2021-12-19 19:16:03,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:03,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:03,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:03,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345264036] [2021-12-19 19:16:03,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345264036] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:03,951 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:03,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:03,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293920994] [2021-12-19 19:16:03,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:03,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:03,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:03,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1133148117, now seen corresponding path program 1 times [2021-12-19 19:16:03,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:03,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660693176] [2021-12-19 19:16:03,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:03,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:03,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,031 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660693176] [2021-12-19 19:16:04,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [660693176] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,031 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,031 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:04,032 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848444489] [2021-12-19 19:16:04,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,033 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,034 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:04,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:04,088 INFO L87 Difference]: Start difference. First operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:04,162 INFO L93 Difference]: Finished difference Result 1004 states and 1496 transitions. [2021-12-19 19:16:04,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:04,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1496 transitions. [2021-12-19 19:16:04,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 998 states and 1490 transitions. [2021-12-19 19:16:04,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:04,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:04,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1490 transitions. [2021-12-19 19:16:04,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,205 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-19 19:16:04,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1490 transitions. [2021-12-19 19:16:04,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:04,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1490 transitions. [2021-12-19 19:16:04,278 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-19 19:16:04,279 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-19 19:16:04,279 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:16:04,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1490 transitions. [2021-12-19 19:16:04,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,287 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,287 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,288 INFO L791 eck$LassoCheckResult]: Stem: 2789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2716#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2717#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2569#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2570#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2155#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2156#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2237#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2948#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2125#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2126#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2533#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2558#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2241#L866 assume !(0 == ~M_E~0); 2242#L866-2 assume !(0 == ~T1_E~0); 2744#L871-1 assume !(0 == ~T2_E~0); 2745#L876-1 assume !(0 == ~T3_E~0); 2995#L881-1 assume !(0 == ~T4_E~0); 2754#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2524#L891-1 assume !(0 == ~T6_E~0); 2525#L896-1 assume !(0 == ~T7_E~0); 2747#L901-1 assume !(0 == ~T8_E~0); 2765#L906-1 assume !(0 == ~E_M~0); 2766#L911-1 assume !(0 == ~E_1~0); 2567#L916-1 assume !(0 == ~E_2~0); 2568#L921-1 assume !(0 == ~E_3~0); 2861#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2960#L931-1 assume !(0 == ~E_5~0); 3000#L936-1 assume !(0 == ~E_6~0); 3007#L941-1 assume !(0 == ~E_7~0); 2573#L946-1 assume !(0 == ~E_8~0); 2574#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L430 assume !(1 == ~m_pc~0); 2432#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2060#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2061#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2674#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2684#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L449 assume 1 == ~t1_pc~0; 2846#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2245#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2019#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2020#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2629#L468 assume !(1 == ~t2_pc~0); 2044#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2043#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2532#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2439#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2062#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063#L487 assume 1 == ~t3_pc~0; 2992#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2159#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2160#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2834#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2498#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2499#L506 assume !(1 == ~t4_pc~0); 2625#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2670#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2970#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2971#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2620#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2450#L525 assume 1 == ~t5_pc~0; 2385#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2104#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2577#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2578#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2301#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2302#L544 assume !(1 == ~t6_pc~0); 2451#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2452#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2796#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2086#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2087#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2936#L563 assume 1 == ~t7_pc~0; 2814#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2114#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2115#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2526#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2246#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2247#L582 assume 1 == ~t8_pc~0; 2170#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2171#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2993#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2487#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2389#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2390#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2848#L964-2 assume !(1 == ~T1_E~0); 2303#L969-1 assume !(1 == ~T2_E~0); 2304#L974-1 assume !(1 == ~T3_E~0); 2873#L979-1 assume !(1 == ~T4_E~0); 2874#L984-1 assume !(1 == ~T5_E~0); 2457#L989-1 assume !(1 == ~T6_E~0); 2458#L994-1 assume !(1 == ~T7_E~0); 2343#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2344#L1004-1 assume !(1 == ~E_M~0); 2088#L1009-1 assume !(1 == ~E_1~0); 2089#L1014-1 assume !(1 == ~E_2~0); 2332#L1019-1 assume !(1 == ~E_3~0); 2837#L1024-1 assume !(1 == ~E_4~0); 2265#L1029-1 assume !(1 == ~E_5~0); 2266#L1034-1 assume !(1 == ~E_6~0); 2360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2974#L1044-1 assume !(1 == ~E_8~0); 2542#L1049-1 assume { :end_inline_reset_delta_events } true; 2235#L1315-2 [2021-12-19 19:16:04,288 INFO L793 eck$LassoCheckResult]: Loop: 2235#L1315-2 assume !false; 2236#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2022#L841 assume !false; 2361#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2137#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2057#L724 assume !(0 != eval_~tmp~0#1); 2059#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2887#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2068#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2069#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2364#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2365#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2378#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2379#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2602#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2603#L896-3 assume !(0 == ~T7_E~0); 2470#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2471#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2604#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2807#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2410#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2411#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2791#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2477#L936-3 assume !(0 == ~E_6~0); 2478#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2619#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2366#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2367#L430-30 assume 1 == ~m_pc~0; 2391#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2392#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2175#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2176#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2825#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2829#L449-30 assume 1 == ~t1_pc~0; 2394#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2084#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2085#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2456#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2168#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2169#L468-30 assume 1 == ~t2_pc~0; 2260#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2261#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2870#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2593#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2594#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2444#L487-30 assume 1 == ~t3_pc~0; 2425#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2240#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2571#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2572#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2844#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2518#L506-30 assume !(1 == ~t4_pc~0); 2519#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2545#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2546#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2563#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2445#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2446#L525-30 assume 1 == ~t5_pc~0; 2931#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2932#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2150#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2151#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2449#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2219#L544-30 assume 1 == ~t6_pc~0; 2027#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3001#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2941#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2942#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2918#L563-30 assume 1 == ~t7_pc~0; 2189#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2190#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2208#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2534#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2535#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2905#L582-30 assume 1 == ~t8_pc~0; 2867#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2287#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2522#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2935#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3008#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2093#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2094#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2231#L969-3 assume !(1 == ~T2_E~0); 2222#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2634#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2635#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2268#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2269#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2778#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2140#L1009-3 assume !(1 == ~E_1~0); 2141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2615#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2616#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2597#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2564#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2565#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2836#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2258#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2259#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2388#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2725#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2292#L1334 assume !(0 == start_simulation_~tmp~3#1); 2294#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2312#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2023#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2024#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2618#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2962#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2797#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2798#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2235#L1315-2 [2021-12-19 19:16:04,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,289 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2021-12-19 19:16:04,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038667142] [2021-12-19 19:16:04,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,379 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038667142] [2021-12-19 19:16:04,381 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038667142] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,381 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,381 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,382 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1516698969] [2021-12-19 19:16:04,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,383 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:04,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,385 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 1 times [2021-12-19 19:16:04,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736831452] [2021-12-19 19:16:04,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,386 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,517 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736831452] [2021-12-19 19:16:04,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736831452] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,518 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,518 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555657622] [2021-12-19 19:16:04,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,519 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,519 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:04,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:04,520 INFO L87 Difference]: Start difference. First operand 998 states and 1490 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:04,541 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2021-12-19 19:16:04,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:04,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1489 transitions. [2021-12-19 19:16:04,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1489 transitions. [2021-12-19 19:16:04,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:04,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:04,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1489 transitions. [2021-12-19 19:16:04,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,556 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-19 19:16:04,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1489 transitions. [2021-12-19 19:16:04,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:04,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1489 transitions. [2021-12-19 19:16:04,571 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-19 19:16:04,572 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-19 19:16:04,572 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:16:04,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1489 transitions. [2021-12-19 19:16:04,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,582 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,582 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,583 INFO L791 eck$LassoCheckResult]: Stem: 4792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4719#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4720#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4572#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4573#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4158#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4159#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4240#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4951#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4128#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4129#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4536#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4561#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4244#L866 assume !(0 == ~M_E~0); 4245#L866-2 assume !(0 == ~T1_E~0); 4747#L871-1 assume !(0 == ~T2_E~0); 4748#L876-1 assume !(0 == ~T3_E~0); 4998#L881-1 assume !(0 == ~T4_E~0); 4757#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4527#L891-1 assume !(0 == ~T6_E~0); 4528#L896-1 assume !(0 == ~T7_E~0); 4750#L901-1 assume !(0 == ~T8_E~0); 4768#L906-1 assume !(0 == ~E_M~0); 4769#L911-1 assume !(0 == ~E_1~0); 4570#L916-1 assume !(0 == ~E_2~0); 4571#L921-1 assume !(0 == ~E_3~0); 4864#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4963#L931-1 assume !(0 == ~E_5~0); 5003#L936-1 assume !(0 == ~E_6~0); 5010#L941-1 assume !(0 == ~E_7~0); 4576#L946-1 assume !(0 == ~E_8~0); 4577#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4982#L430 assume !(1 == ~m_pc~0); 4435#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4063#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4064#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4677#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4687#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4848#L449 assume 1 == ~t1_pc~0; 4849#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4248#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4022#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4023#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4783#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4632#L468 assume !(1 == ~t2_pc~0); 4047#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4046#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4535#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4442#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4065#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L487 assume 1 == ~t3_pc~0; 4995#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4162#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4163#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4837#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4501#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4502#L506 assume !(1 == ~t4_pc~0); 4628#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4673#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4973#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4623#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4453#L525 assume 1 == ~t5_pc~0; 4388#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4107#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4580#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4581#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4304#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4305#L544 assume !(1 == ~t6_pc~0); 4454#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4455#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4799#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4089#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4090#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4939#L563 assume 1 == ~t7_pc~0; 4817#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4118#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4529#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4249#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4250#L582 assume 1 == ~t8_pc~0; 4173#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4174#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4996#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4490#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4392#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4393#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4851#L964-2 assume !(1 == ~T1_E~0); 4306#L969-1 assume !(1 == ~T2_E~0); 4307#L974-1 assume !(1 == ~T3_E~0); 4876#L979-1 assume !(1 == ~T4_E~0); 4877#L984-1 assume !(1 == ~T5_E~0); 4460#L989-1 assume !(1 == ~T6_E~0); 4461#L994-1 assume !(1 == ~T7_E~0); 4346#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4347#L1004-1 assume !(1 == ~E_M~0); 4091#L1009-1 assume !(1 == ~E_1~0); 4092#L1014-1 assume !(1 == ~E_2~0); 4335#L1019-1 assume !(1 == ~E_3~0); 4840#L1024-1 assume !(1 == ~E_4~0); 4268#L1029-1 assume !(1 == ~E_5~0); 4269#L1034-1 assume !(1 == ~E_6~0); 4363#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4977#L1044-1 assume !(1 == ~E_8~0); 4545#L1049-1 assume { :end_inline_reset_delta_events } true; 4238#L1315-2 [2021-12-19 19:16:04,584 INFO L793 eck$LassoCheckResult]: Loop: 4238#L1315-2 assume !false; 4239#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4025#L841 assume !false; 4364#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4300#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4140#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4060#L724 assume !(0 != eval_~tmp~0#1); 4062#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4890#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4071#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4072#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4367#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4368#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4381#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4382#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4605#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4606#L896-3 assume !(0 == ~T7_E~0); 4473#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4474#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4607#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4810#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4413#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4414#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4794#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4480#L936-3 assume !(0 == ~E_6~0); 4481#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4622#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4369#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4370#L430-30 assume 1 == ~m_pc~0; 4394#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4395#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4178#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4179#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4828#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4832#L449-30 assume 1 == ~t1_pc~0; 4397#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4087#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4088#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4459#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4171#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4172#L468-30 assume 1 == ~t2_pc~0; 4263#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4264#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4873#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4596#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4597#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4447#L487-30 assume !(1 == ~t3_pc~0); 4242#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4243#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4574#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4575#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4847#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4521#L506-30 assume !(1 == ~t4_pc~0); 4522#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4548#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4549#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4566#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 4448#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4449#L525-30 assume 1 == ~t5_pc~0; 4934#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4935#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4153#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4154#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4452#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4222#L544-30 assume !(1 == ~t6_pc~0); 4032#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4031#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5004#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4944#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4945#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4921#L563-30 assume 1 == ~t7_pc~0; 4192#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4193#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4211#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4537#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4538#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L582-30 assume !(1 == ~t8_pc~0); 4289#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4290#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4525#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4938#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5011#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4096#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4097#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4234#L969-3 assume !(1 == ~T2_E~0); 4225#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4226#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4637#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4638#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4271#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4272#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4781#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4143#L1009-3 assume !(1 == ~E_1~0); 4144#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4618#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4619#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4600#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4567#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4568#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4839#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4261#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4262#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4391#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4728#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4295#L1334 assume !(0 == start_simulation_~tmp~3#1); 4297#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4315#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4026#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4027#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4621#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4965#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4800#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4801#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4238#L1315-2 [2021-12-19 19:16:04,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2021-12-19 19:16:04,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902994455] [2021-12-19 19:16:04,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,645 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902994455] [2021-12-19 19:16:04,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902994455] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860659294] [2021-12-19 19:16:04,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:04,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1452394673, now seen corresponding path program 1 times [2021-12-19 19:16:04,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340003581] [2021-12-19 19:16:04,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,649 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,720 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340003581] [2021-12-19 19:16:04,720 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340003581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,720 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886054036] [2021-12-19 19:16:04,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,721 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,721 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:04,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:04,722 INFO L87 Difference]: Start difference. First operand 998 states and 1489 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:04,737 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2021-12-19 19:16:04,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:04,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1488 transitions. [2021-12-19 19:16:04,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1488 transitions. [2021-12-19 19:16:04,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:04,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:04,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1488 transitions. [2021-12-19 19:16:04,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,770 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-19 19:16:04,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1488 transitions. [2021-12-19 19:16:04,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:04,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1488 transitions. [2021-12-19 19:16:04,783 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-19 19:16:04,784 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-19 19:16:04,784 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:16:04,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1488 transitions. [2021-12-19 19:16:04,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,793 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,793 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,793 INFO L791 eck$LassoCheckResult]: Stem: 6795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6722#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6723#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6575#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6576#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6161#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6162#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6243#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6954#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6131#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6132#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6539#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6564#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6247#L866 assume !(0 == ~M_E~0); 6248#L866-2 assume !(0 == ~T1_E~0); 6750#L871-1 assume !(0 == ~T2_E~0); 6751#L876-1 assume !(0 == ~T3_E~0); 7001#L881-1 assume !(0 == ~T4_E~0); 6760#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6530#L891-1 assume !(0 == ~T6_E~0); 6531#L896-1 assume !(0 == ~T7_E~0); 6753#L901-1 assume !(0 == ~T8_E~0); 6771#L906-1 assume !(0 == ~E_M~0); 6772#L911-1 assume !(0 == ~E_1~0); 6573#L916-1 assume !(0 == ~E_2~0); 6574#L921-1 assume !(0 == ~E_3~0); 6867#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6966#L931-1 assume !(0 == ~E_5~0); 7006#L936-1 assume !(0 == ~E_6~0); 7013#L941-1 assume !(0 == ~E_7~0); 6579#L946-1 assume !(0 == ~E_8~0); 6580#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6985#L430 assume !(1 == ~m_pc~0); 6438#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6066#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6067#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6680#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6690#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6851#L449 assume 1 == ~t1_pc~0; 6852#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6251#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6025#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6026#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6786#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6635#L468 assume !(1 == ~t2_pc~0); 6050#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6049#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6538#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6445#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6068#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6069#L487 assume 1 == ~t3_pc~0; 6998#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6166#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6840#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6504#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6505#L506 assume !(1 == ~t4_pc~0); 6631#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6976#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6977#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6626#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6456#L525 assume 1 == ~t5_pc~0; 6391#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6583#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6584#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6307#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6308#L544 assume !(1 == ~t6_pc~0); 6457#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6458#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6802#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6092#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6093#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6942#L563 assume 1 == ~t7_pc~0; 6820#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6120#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6121#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6532#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6252#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6253#L582 assume 1 == ~t8_pc~0; 6176#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6177#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6493#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6395#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6396#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6854#L964-2 assume !(1 == ~T1_E~0); 6309#L969-1 assume !(1 == ~T2_E~0); 6310#L974-1 assume !(1 == ~T3_E~0); 6879#L979-1 assume !(1 == ~T4_E~0); 6880#L984-1 assume !(1 == ~T5_E~0); 6463#L989-1 assume !(1 == ~T6_E~0); 6464#L994-1 assume !(1 == ~T7_E~0); 6349#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6350#L1004-1 assume !(1 == ~E_M~0); 6094#L1009-1 assume !(1 == ~E_1~0); 6095#L1014-1 assume !(1 == ~E_2~0); 6338#L1019-1 assume !(1 == ~E_3~0); 6843#L1024-1 assume !(1 == ~E_4~0); 6271#L1029-1 assume !(1 == ~E_5~0); 6272#L1034-1 assume !(1 == ~E_6~0); 6366#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6980#L1044-1 assume !(1 == ~E_8~0); 6548#L1049-1 assume { :end_inline_reset_delta_events } true; 6241#L1315-2 [2021-12-19 19:16:04,793 INFO L793 eck$LassoCheckResult]: Loop: 6241#L1315-2 assume !false; 6242#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6028#L841 assume !false; 6367#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6302#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6303#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6143#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6063#L724 assume !(0 != eval_~tmp~0#1); 6065#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6893#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6074#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6075#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6370#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6371#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6384#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6385#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6608#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6609#L896-3 assume !(0 == ~T7_E~0); 6476#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6477#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6610#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6813#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6416#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6417#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6797#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6483#L936-3 assume !(0 == ~E_6~0); 6484#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6625#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6372#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6373#L430-30 assume 1 == ~m_pc~0; 6397#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6398#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6181#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6182#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6831#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6835#L449-30 assume 1 == ~t1_pc~0; 6400#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6090#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6091#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6462#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6174#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6175#L468-30 assume 1 == ~t2_pc~0; 6266#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6267#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6876#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6599#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6600#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6450#L487-30 assume !(1 == ~t3_pc~0); 6245#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6246#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6577#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6578#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6850#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6524#L506-30 assume !(1 == ~t4_pc~0); 6525#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6551#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6552#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6569#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 6451#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6452#L525-30 assume 1 == ~t5_pc~0; 6937#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6938#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6156#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6157#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6455#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6225#L544-30 assume 1 == ~t6_pc~0; 6033#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6034#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7007#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6947#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6948#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6924#L563-30 assume 1 == ~t7_pc~0; 6195#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6196#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6214#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6540#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6541#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6911#L582-30 assume !(1 == ~t8_pc~0); 6292#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6293#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6528#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6941#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7014#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6099#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6100#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6237#L969-3 assume !(1 == ~T2_E~0); 6228#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6229#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6640#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6641#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6274#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6275#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6784#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6146#L1009-3 assume !(1 == ~E_1~0); 6147#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6621#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6622#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6603#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6570#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6842#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6264#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6394#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6731#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6298#L1334 assume !(0 == start_simulation_~tmp~3#1); 6300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6318#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6029#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6030#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6624#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6968#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6803#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6804#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6241#L1315-2 [2021-12-19 19:16:04,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,795 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2021-12-19 19:16:04,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144188716] [2021-12-19 19:16:04,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144188716] [2021-12-19 19:16:04,838 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144188716] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,838 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990947601] [2021-12-19 19:16:04,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,842 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:04,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,842 INFO L85 PathProgramCache]: Analyzing trace with hash -15808656, now seen corresponding path program 1 times [2021-12-19 19:16:04,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321462251] [2021-12-19 19:16:04,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321462251] [2021-12-19 19:16:04,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321462251] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642641811] [2021-12-19 19:16:04,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,899 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:04,899 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:04,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:04,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:04,901 INFO L87 Difference]: Start difference. First operand 998 states and 1488 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:04,917 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2021-12-19 19:16:04,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:04,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1487 transitions. [2021-12-19 19:16:04,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1487 transitions. [2021-12-19 19:16:04,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:04,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:04,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1487 transitions. [2021-12-19 19:16:04,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:04,930 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-19 19:16:04,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1487 transitions. [2021-12-19 19:16:04,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:04,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:04,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1487 transitions. [2021-12-19 19:16:04,945 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-19 19:16:04,945 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-19 19:16:04,945 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:16:04,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1487 transitions. [2021-12-19 19:16:04,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:04,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:04,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:04,950 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,950 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:04,951 INFO L791 eck$LassoCheckResult]: Stem: 8798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8725#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8726#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8578#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8579#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8164#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8165#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8957#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8134#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8135#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8542#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8567#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8250#L866 assume !(0 == ~M_E~0); 8251#L866-2 assume !(0 == ~T1_E~0); 8753#L871-1 assume !(0 == ~T2_E~0); 8754#L876-1 assume !(0 == ~T3_E~0); 9004#L881-1 assume !(0 == ~T4_E~0); 8763#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8533#L891-1 assume !(0 == ~T6_E~0); 8534#L896-1 assume !(0 == ~T7_E~0); 8756#L901-1 assume !(0 == ~T8_E~0); 8774#L906-1 assume !(0 == ~E_M~0); 8775#L911-1 assume !(0 == ~E_1~0); 8576#L916-1 assume !(0 == ~E_2~0); 8577#L921-1 assume !(0 == ~E_3~0); 8870#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8969#L931-1 assume !(0 == ~E_5~0); 9009#L936-1 assume !(0 == ~E_6~0); 9016#L941-1 assume !(0 == ~E_7~0); 8582#L946-1 assume !(0 == ~E_8~0); 8583#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L430 assume !(1 == ~m_pc~0); 8441#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8069#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8070#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8683#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8693#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8854#L449 assume 1 == ~t1_pc~0; 8855#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8254#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8028#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8029#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8789#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8638#L468 assume !(1 == ~t2_pc~0); 8053#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8052#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8541#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8448#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8071#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8072#L487 assume 1 == ~t3_pc~0; 9001#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8168#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8169#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8843#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8507#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8508#L506 assume !(1 == ~t4_pc~0); 8634#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8679#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8979#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8980#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8459#L525 assume 1 == ~t5_pc~0; 8394#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8586#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8587#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8310#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8311#L544 assume !(1 == ~t6_pc~0); 8460#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8461#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8805#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8095#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8096#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8945#L563 assume 1 == ~t7_pc~0; 8823#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8123#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8124#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8535#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8255#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8256#L582 assume 1 == ~t8_pc~0; 8179#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8180#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9002#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8496#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8398#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8399#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8857#L964-2 assume !(1 == ~T1_E~0); 8312#L969-1 assume !(1 == ~T2_E~0); 8313#L974-1 assume !(1 == ~T3_E~0); 8882#L979-1 assume !(1 == ~T4_E~0); 8883#L984-1 assume !(1 == ~T5_E~0); 8466#L989-1 assume !(1 == ~T6_E~0); 8467#L994-1 assume !(1 == ~T7_E~0); 8352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8353#L1004-1 assume !(1 == ~E_M~0); 8097#L1009-1 assume !(1 == ~E_1~0); 8098#L1014-1 assume !(1 == ~E_2~0); 8341#L1019-1 assume !(1 == ~E_3~0); 8846#L1024-1 assume !(1 == ~E_4~0); 8274#L1029-1 assume !(1 == ~E_5~0); 8275#L1034-1 assume !(1 == ~E_6~0); 8369#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8983#L1044-1 assume !(1 == ~E_8~0); 8551#L1049-1 assume { :end_inline_reset_delta_events } true; 8244#L1315-2 [2021-12-19 19:16:04,951 INFO L793 eck$LassoCheckResult]: Loop: 8244#L1315-2 assume !false; 8245#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8031#L841 assume !false; 8370#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8305#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8306#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8146#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8066#L724 assume !(0 != eval_~tmp~0#1); 8068#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8896#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8077#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8078#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8373#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8387#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8388#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8611#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8612#L896-3 assume !(0 == ~T7_E~0); 8479#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8480#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8613#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8816#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8419#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8420#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8800#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8486#L936-3 assume !(0 == ~E_6~0); 8487#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8628#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8376#L430-30 assume 1 == ~m_pc~0; 8400#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8401#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8184#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8185#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8834#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8838#L449-30 assume 1 == ~t1_pc~0; 8403#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8093#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8094#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8465#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8178#L468-30 assume 1 == ~t2_pc~0; 8269#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8270#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8879#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8602#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8603#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8453#L487-30 assume 1 == ~t3_pc~0; 8434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8249#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8580#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8581#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8853#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8527#L506-30 assume !(1 == ~t4_pc~0); 8528#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8554#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8555#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8572#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 8454#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8455#L525-30 assume 1 == ~t5_pc~0; 8940#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8941#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8159#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8160#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8458#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8228#L544-30 assume 1 == ~t6_pc~0; 8036#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8037#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9010#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8950#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8951#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8927#L563-30 assume 1 == ~t7_pc~0; 8198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8217#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8543#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8544#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8914#L582-30 assume !(1 == ~t8_pc~0); 8295#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 8296#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8531#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8944#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9017#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8102#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8103#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8240#L969-3 assume !(1 == ~T2_E~0); 8231#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8232#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8643#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8644#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8277#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8278#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8787#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8149#L1009-3 assume !(1 == ~E_1~0); 8150#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8624#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8625#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8606#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8573#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8574#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8845#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8267#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8268#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8397#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8734#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8301#L1334 assume !(0 == start_simulation_~tmp~3#1); 8303#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8321#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8032#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8033#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8627#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8971#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8806#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8807#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8244#L1315-2 [2021-12-19 19:16:04,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,952 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2021-12-19 19:16:04,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918122603] [2021-12-19 19:16:04,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:04,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:04,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:04,991 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:04,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918122603] [2021-12-19 19:16:04,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918122603] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:04,991 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:04,991 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:04,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556024802] [2021-12-19 19:16:04,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:04,992 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:04,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:04,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2141664367, now seen corresponding path program 1 times [2021-12-19 19:16:04,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:04,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406425583] [2021-12-19 19:16:04,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:04,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406425583] [2021-12-19 19:16:05,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406425583] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,061 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,061 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175659075] [2021-12-19 19:16:05,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:05,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:05,063 INFO L87 Difference]: Start difference. First operand 998 states and 1487 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,078 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2021-12-19 19:16:05,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:05,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2021-12-19 19:16:05,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1486 transitions. [2021-12-19 19:16:05,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:05,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:05,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1486 transitions. [2021-12-19 19:16:05,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,092 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-19 19:16:05,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1486 transitions. [2021-12-19 19:16:05,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:05,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1486 transitions. [2021-12-19 19:16:05,107 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-19 19:16:05,107 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-19 19:16:05,107 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:16:05,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1486 transitions. [2021-12-19 19:16:05,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,114 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,114 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,115 INFO L791 eck$LassoCheckResult]: Stem: 10801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10728#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10729#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10581#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10582#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10167#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10168#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10249#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10960#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10137#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10138#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10545#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10570#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10253#L866 assume !(0 == ~M_E~0); 10254#L866-2 assume !(0 == ~T1_E~0); 10756#L871-1 assume !(0 == ~T2_E~0); 10757#L876-1 assume !(0 == ~T3_E~0); 11007#L881-1 assume !(0 == ~T4_E~0); 10766#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10536#L891-1 assume !(0 == ~T6_E~0); 10537#L896-1 assume !(0 == ~T7_E~0); 10759#L901-1 assume !(0 == ~T8_E~0); 10777#L906-1 assume !(0 == ~E_M~0); 10778#L911-1 assume !(0 == ~E_1~0); 10579#L916-1 assume !(0 == ~E_2~0); 10580#L921-1 assume !(0 == ~E_3~0); 10873#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10972#L931-1 assume !(0 == ~E_5~0); 11012#L936-1 assume !(0 == ~E_6~0); 11019#L941-1 assume !(0 == ~E_7~0); 10585#L946-1 assume !(0 == ~E_8~0); 10586#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10991#L430 assume !(1 == ~m_pc~0); 10444#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10686#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10696#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10857#L449 assume 1 == ~t1_pc~0; 10858#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10257#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10031#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10032#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10792#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10641#L468 assume !(1 == ~t2_pc~0); 10056#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10055#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10544#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10451#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10075#L487 assume 1 == ~t3_pc~0; 11004#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10171#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10172#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10846#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10510#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10511#L506 assume !(1 == ~t4_pc~0); 10637#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10682#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10982#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10983#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10632#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10462#L525 assume 1 == ~t5_pc~0; 10397#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10116#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10589#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10590#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10313#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10314#L544 assume !(1 == ~t6_pc~0); 10463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10808#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10098#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10099#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10948#L563 assume 1 == ~t7_pc~0; 10826#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10126#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10127#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10538#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10258#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10259#L582 assume 1 == ~t8_pc~0; 10182#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10183#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11005#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10499#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10401#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10402#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10860#L964-2 assume !(1 == ~T1_E~0); 10315#L969-1 assume !(1 == ~T2_E~0); 10316#L974-1 assume !(1 == ~T3_E~0); 10885#L979-1 assume !(1 == ~T4_E~0); 10886#L984-1 assume !(1 == ~T5_E~0); 10469#L989-1 assume !(1 == ~T6_E~0); 10470#L994-1 assume !(1 == ~T7_E~0); 10355#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10356#L1004-1 assume !(1 == ~E_M~0); 10100#L1009-1 assume !(1 == ~E_1~0); 10101#L1014-1 assume !(1 == ~E_2~0); 10344#L1019-1 assume !(1 == ~E_3~0); 10849#L1024-1 assume !(1 == ~E_4~0); 10277#L1029-1 assume !(1 == ~E_5~0); 10278#L1034-1 assume !(1 == ~E_6~0); 10372#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10986#L1044-1 assume !(1 == ~E_8~0); 10554#L1049-1 assume { :end_inline_reset_delta_events } true; 10247#L1315-2 [2021-12-19 19:16:05,115 INFO L793 eck$LassoCheckResult]: Loop: 10247#L1315-2 assume !false; 10248#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10034#L841 assume !false; 10373#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10308#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10309#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10149#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10069#L724 assume !(0 != eval_~tmp~0#1); 10071#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10899#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10376#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10377#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10614#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10615#L896-3 assume !(0 == ~T7_E~0); 10482#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10483#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10616#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10819#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10422#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10423#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10803#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L936-3 assume !(0 == ~E_6~0); 10490#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10631#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10378#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10379#L430-30 assume 1 == ~m_pc~0; 10403#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10404#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10187#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10188#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10837#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10841#L449-30 assume 1 == ~t1_pc~0; 10406#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10097#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10180#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10181#L468-30 assume 1 == ~t2_pc~0; 10272#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10273#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10882#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10605#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10606#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10456#L487-30 assume 1 == ~t3_pc~0; 10437#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10252#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10583#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10584#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10856#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10530#L506-30 assume !(1 == ~t4_pc~0); 10531#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10557#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10558#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10575#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 10457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10458#L525-30 assume !(1 == ~t5_pc~0); 10945#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10944#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10162#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10163#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10231#L544-30 assume 1 == ~t6_pc~0; 10039#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10040#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11013#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10953#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10954#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10930#L563-30 assume 1 == ~t7_pc~0; 10201#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10202#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10220#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10546#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10547#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10917#L582-30 assume !(1 == ~t8_pc~0); 10298#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10299#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10534#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10947#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11020#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10105#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10106#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10243#L969-3 assume !(1 == ~T2_E~0); 10234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10646#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10647#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10280#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10281#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10790#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10152#L1009-3 assume !(1 == ~E_1~0); 10153#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10627#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10628#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10609#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10576#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10577#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10848#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10270#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10271#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10400#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10737#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10304#L1334 assume !(0 == start_simulation_~tmp~3#1); 10306#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10324#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10035#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10036#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10630#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10974#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10809#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10810#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10247#L1315-2 [2021-12-19 19:16:05,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2021-12-19 19:16:05,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815102299] [2021-12-19 19:16:05,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815102299] [2021-12-19 19:16:05,143 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815102299] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,143 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,143 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,143 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401778889] [2021-12-19 19:16:05,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,145 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:05,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1033535728, now seen corresponding path program 1 times [2021-12-19 19:16:05,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080499474] [2021-12-19 19:16:05,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,183 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080499474] [2021-12-19 19:16:05,185 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080499474] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,185 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,185 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741086673] [2021-12-19 19:16:05,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,186 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,186 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:05,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:05,188 INFO L87 Difference]: Start difference. First operand 998 states and 1486 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,207 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2021-12-19 19:16:05,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:05,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1485 transitions. [2021-12-19 19:16:05,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1485 transitions. [2021-12-19 19:16:05,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:05,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:05,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1485 transitions. [2021-12-19 19:16:05,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,222 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-19 19:16:05,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1485 transitions. [2021-12-19 19:16:05,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:05,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1485 transitions. [2021-12-19 19:16:05,237 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-19 19:16:05,237 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-19 19:16:05,237 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:16:05,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1485 transitions. [2021-12-19 19:16:05,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,242 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,243 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,243 INFO L791 eck$LassoCheckResult]: Stem: 12804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12731#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12732#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12584#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12585#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12170#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12171#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12252#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12963#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12140#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12141#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12548#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12573#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12256#L866 assume !(0 == ~M_E~0); 12257#L866-2 assume !(0 == ~T1_E~0); 12759#L871-1 assume !(0 == ~T2_E~0); 12760#L876-1 assume !(0 == ~T3_E~0); 13010#L881-1 assume !(0 == ~T4_E~0); 12769#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12539#L891-1 assume !(0 == ~T6_E~0); 12540#L896-1 assume !(0 == ~T7_E~0); 12762#L901-1 assume !(0 == ~T8_E~0); 12780#L906-1 assume !(0 == ~E_M~0); 12781#L911-1 assume !(0 == ~E_1~0); 12582#L916-1 assume !(0 == ~E_2~0); 12583#L921-1 assume !(0 == ~E_3~0); 12876#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12975#L931-1 assume !(0 == ~E_5~0); 13015#L936-1 assume !(0 == ~E_6~0); 13022#L941-1 assume !(0 == ~E_7~0); 12588#L946-1 assume !(0 == ~E_8~0); 12589#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12994#L430 assume !(1 == ~m_pc~0); 12447#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12075#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12076#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12689#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12699#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12860#L449 assume 1 == ~t1_pc~0; 12861#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12260#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12034#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12035#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12795#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12644#L468 assume !(1 == ~t2_pc~0); 12059#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12058#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12547#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12454#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12077#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12078#L487 assume 1 == ~t3_pc~0; 13007#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12174#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12175#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12849#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12513#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12514#L506 assume !(1 == ~t4_pc~0); 12640#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12685#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12985#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12986#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12635#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12465#L525 assume 1 == ~t5_pc~0; 12400#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12119#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12592#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12316#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12317#L544 assume !(1 == ~t6_pc~0); 12466#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12811#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12101#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12102#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12951#L563 assume 1 == ~t7_pc~0; 12829#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12129#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12130#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12541#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12261#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12262#L582 assume 1 == ~t8_pc~0; 12185#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12186#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13008#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12502#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12404#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12405#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12863#L964-2 assume !(1 == ~T1_E~0); 12318#L969-1 assume !(1 == ~T2_E~0); 12319#L974-1 assume !(1 == ~T3_E~0); 12888#L979-1 assume !(1 == ~T4_E~0); 12889#L984-1 assume !(1 == ~T5_E~0); 12472#L989-1 assume !(1 == ~T6_E~0); 12473#L994-1 assume !(1 == ~T7_E~0); 12358#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12359#L1004-1 assume !(1 == ~E_M~0); 12103#L1009-1 assume !(1 == ~E_1~0); 12104#L1014-1 assume !(1 == ~E_2~0); 12347#L1019-1 assume !(1 == ~E_3~0); 12852#L1024-1 assume !(1 == ~E_4~0); 12280#L1029-1 assume !(1 == ~E_5~0); 12281#L1034-1 assume !(1 == ~E_6~0); 12375#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12989#L1044-1 assume !(1 == ~E_8~0); 12557#L1049-1 assume { :end_inline_reset_delta_events } true; 12250#L1315-2 [2021-12-19 19:16:05,243 INFO L793 eck$LassoCheckResult]: Loop: 12250#L1315-2 assume !false; 12251#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12037#L841 assume !false; 12376#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12311#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12312#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12152#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12072#L724 assume !(0 != eval_~tmp~0#1); 12074#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12902#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12083#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12084#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12379#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12380#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12393#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12394#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12617#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12618#L896-3 assume !(0 == ~T7_E~0); 12485#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12486#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12619#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12822#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12425#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12426#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12806#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12492#L936-3 assume !(0 == ~E_6~0); 12493#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12634#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12381#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12382#L430-30 assume 1 == ~m_pc~0; 12406#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12407#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12190#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12191#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12840#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12844#L449-30 assume 1 == ~t1_pc~0; 12409#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12099#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12100#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12471#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12183#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12184#L468-30 assume 1 == ~t2_pc~0; 12275#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12276#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12885#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12608#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12609#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12459#L487-30 assume 1 == ~t3_pc~0; 12440#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12255#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12586#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12587#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12859#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12533#L506-30 assume !(1 == ~t4_pc~0); 12534#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12560#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12561#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12578#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 12460#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12461#L525-30 assume 1 == ~t5_pc~0; 12946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12165#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12166#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12464#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12234#L544-30 assume 1 == ~t6_pc~0; 12042#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12043#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13016#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12956#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12957#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12933#L563-30 assume 1 == ~t7_pc~0; 12204#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12223#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12549#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12550#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12920#L582-30 assume 1 == ~t8_pc~0; 12882#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12302#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12537#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12950#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13023#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12108#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12109#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12246#L969-3 assume !(1 == ~T2_E~0); 12237#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12238#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12649#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12650#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12283#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12284#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12793#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12155#L1009-3 assume !(1 == ~E_1~0); 12156#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12630#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12631#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12612#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12579#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12580#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12851#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12274#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12403#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12740#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12307#L1334 assume !(0 == start_simulation_~tmp~3#1); 12309#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12327#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12038#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12039#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12633#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12977#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12812#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12813#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12250#L1315-2 [2021-12-19 19:16:05,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,251 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2021-12-19 19:16:05,251 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645417418] [2021-12-19 19:16:05,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,275 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645417418] [2021-12-19 19:16:05,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645417418] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,276 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,276 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,276 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426258361] [2021-12-19 19:16:05,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,277 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:05,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,277 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 2 times [2021-12-19 19:16:05,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867720241] [2021-12-19 19:16:05,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,278 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867720241] [2021-12-19 19:16:05,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867720241] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,313 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,313 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,313 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796338071] [2021-12-19 19:16:05,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,314 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,314 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:05,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:05,315 INFO L87 Difference]: Start difference. First operand 998 states and 1485 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,331 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2021-12-19 19:16:05,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:05,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1484 transitions. [2021-12-19 19:16:05,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1484 transitions. [2021-12-19 19:16:05,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:05,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:05,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1484 transitions. [2021-12-19 19:16:05,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,345 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-19 19:16:05,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1484 transitions. [2021-12-19 19:16:05,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:05,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1484 transitions. [2021-12-19 19:16:05,361 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-19 19:16:05,361 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-19 19:16:05,361 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:16:05,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1484 transitions. [2021-12-19 19:16:05,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,366 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,367 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,367 INFO L791 eck$LassoCheckResult]: Stem: 14807#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14734#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14735#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14587#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14588#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14173#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14174#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14255#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14966#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14143#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14144#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14551#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14576#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14259#L866 assume !(0 == ~M_E~0); 14260#L866-2 assume !(0 == ~T1_E~0); 14762#L871-1 assume !(0 == ~T2_E~0); 14763#L876-1 assume !(0 == ~T3_E~0); 15013#L881-1 assume !(0 == ~T4_E~0); 14772#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14542#L891-1 assume !(0 == ~T6_E~0); 14543#L896-1 assume !(0 == ~T7_E~0); 14765#L901-1 assume !(0 == ~T8_E~0); 14783#L906-1 assume !(0 == ~E_M~0); 14784#L911-1 assume !(0 == ~E_1~0); 14585#L916-1 assume !(0 == ~E_2~0); 14586#L921-1 assume !(0 == ~E_3~0); 14879#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14978#L931-1 assume !(0 == ~E_5~0); 15018#L936-1 assume !(0 == ~E_6~0); 15025#L941-1 assume !(0 == ~E_7~0); 14591#L946-1 assume !(0 == ~E_8~0); 14592#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14997#L430 assume !(1 == ~m_pc~0); 14450#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14078#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14079#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14692#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14702#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14863#L449 assume 1 == ~t1_pc~0; 14864#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14263#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14037#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14038#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14798#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14647#L468 assume !(1 == ~t2_pc~0); 14062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14550#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14457#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14080#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14081#L487 assume 1 == ~t3_pc~0; 15010#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14177#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14178#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14852#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14516#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14517#L506 assume !(1 == ~t4_pc~0); 14643#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14688#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14988#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14989#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14638#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14468#L525 assume 1 == ~t5_pc~0; 14403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14122#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14595#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14596#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14320#L544 assume !(1 == ~t6_pc~0); 14469#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14470#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14814#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14104#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14105#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14954#L563 assume 1 == ~t7_pc~0; 14832#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14132#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14133#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14544#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14264#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14265#L582 assume 1 == ~t8_pc~0; 14188#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14189#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15011#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14505#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14407#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14408#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 14866#L964-2 assume !(1 == ~T1_E~0); 14321#L969-1 assume !(1 == ~T2_E~0); 14322#L974-1 assume !(1 == ~T3_E~0); 14891#L979-1 assume !(1 == ~T4_E~0); 14892#L984-1 assume !(1 == ~T5_E~0); 14475#L989-1 assume !(1 == ~T6_E~0); 14476#L994-1 assume !(1 == ~T7_E~0); 14361#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14362#L1004-1 assume !(1 == ~E_M~0); 14106#L1009-1 assume !(1 == ~E_1~0); 14107#L1014-1 assume !(1 == ~E_2~0); 14350#L1019-1 assume !(1 == ~E_3~0); 14855#L1024-1 assume !(1 == ~E_4~0); 14283#L1029-1 assume !(1 == ~E_5~0); 14284#L1034-1 assume !(1 == ~E_6~0); 14378#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14992#L1044-1 assume !(1 == ~E_8~0); 14560#L1049-1 assume { :end_inline_reset_delta_events } true; 14253#L1315-2 [2021-12-19 19:16:05,367 INFO L793 eck$LassoCheckResult]: Loop: 14253#L1315-2 assume !false; 14254#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14040#L841 assume !false; 14379#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14155#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14075#L724 assume !(0 != eval_~tmp~0#1); 14077#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14905#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14086#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14087#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14382#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14383#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14396#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14397#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14620#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14621#L896-3 assume !(0 == ~T7_E~0); 14488#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14489#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14622#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14825#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14428#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14429#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14809#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14495#L936-3 assume !(0 == ~E_6~0); 14496#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14637#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14384#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14385#L430-30 assume 1 == ~m_pc~0; 14409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14193#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14194#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14843#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14847#L449-30 assume 1 == ~t1_pc~0; 14412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14102#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14103#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14474#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14186#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14187#L468-30 assume 1 == ~t2_pc~0; 14278#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14888#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14611#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14612#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14462#L487-30 assume !(1 == ~t3_pc~0); 14257#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 14258#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14589#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14590#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14862#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14536#L506-30 assume !(1 == ~t4_pc~0); 14537#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14563#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14564#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14581#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 14463#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14464#L525-30 assume 1 == ~t5_pc~0; 14949#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14950#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14169#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14467#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14237#L544-30 assume 1 == ~t6_pc~0; 14045#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14046#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15019#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14959#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14960#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L563-30 assume !(1 == ~t7_pc~0); 14209#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14208#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14552#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14553#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14923#L582-30 assume !(1 == ~t8_pc~0); 14304#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14305#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14540#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14953#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15026#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14111#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14112#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14249#L969-3 assume !(1 == ~T2_E~0); 14240#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14241#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14652#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14653#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14286#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14287#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14796#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14158#L1009-3 assume !(1 == ~E_1~0); 14159#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14633#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14634#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14615#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14582#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14583#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14854#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14406#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14743#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14310#L1334 assume !(0 == start_simulation_~tmp~3#1); 14312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14330#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14041#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14042#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14636#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14980#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14815#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14816#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14253#L1315-2 [2021-12-19 19:16:05,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,368 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2021-12-19 19:16:05,368 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198447474] [2021-12-19 19:16:05,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,369 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,392 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198447474] [2021-12-19 19:16:05,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198447474] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,393 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,393 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390332773] [2021-12-19 19:16:05,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,394 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:05,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1882721649, now seen corresponding path program 1 times [2021-12-19 19:16:05,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077463596] [2021-12-19 19:16:05,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077463596] [2021-12-19 19:16:05,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077463596] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130902673] [2021-12-19 19:16:05,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,432 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,433 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:05,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:05,434 INFO L87 Difference]: Start difference. First operand 998 states and 1484 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,450 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2021-12-19 19:16:05,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:05,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1483 transitions. [2021-12-19 19:16:05,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1483 transitions. [2021-12-19 19:16:05,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-19 19:16:05,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-19 19:16:05,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1483 transitions. [2021-12-19 19:16:05,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,466 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-19 19:16:05,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1483 transitions. [2021-12-19 19:16:05,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-19 19:16:05,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1483 transitions. [2021-12-19 19:16:05,483 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-19 19:16:05,483 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-19 19:16:05,483 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:16:05,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1483 transitions. [2021-12-19 19:16:05,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-19 19:16:05,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,488 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,488 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,488 INFO L791 eck$LassoCheckResult]: Stem: 16810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16737#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16738#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16590#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16591#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16176#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16177#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16258#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16969#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16146#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16147#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16554#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16579#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16262#L866 assume !(0 == ~M_E~0); 16263#L866-2 assume !(0 == ~T1_E~0); 16765#L871-1 assume !(0 == ~T2_E~0); 16766#L876-1 assume !(0 == ~T3_E~0); 17016#L881-1 assume !(0 == ~T4_E~0); 16775#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16545#L891-1 assume !(0 == ~T6_E~0); 16546#L896-1 assume !(0 == ~T7_E~0); 16768#L901-1 assume !(0 == ~T8_E~0); 16786#L906-1 assume !(0 == ~E_M~0); 16787#L911-1 assume !(0 == ~E_1~0); 16588#L916-1 assume !(0 == ~E_2~0); 16589#L921-1 assume !(0 == ~E_3~0); 16882#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16981#L931-1 assume !(0 == ~E_5~0); 17021#L936-1 assume !(0 == ~E_6~0); 17028#L941-1 assume !(0 == ~E_7~0); 16594#L946-1 assume !(0 == ~E_8~0); 16595#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17000#L430 assume !(1 == ~m_pc~0); 16453#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16081#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16082#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16695#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16705#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16866#L449 assume 1 == ~t1_pc~0; 16867#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16266#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16040#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16041#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16801#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16650#L468 assume !(1 == ~t2_pc~0); 16065#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16064#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16553#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16083#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16084#L487 assume 1 == ~t3_pc~0; 17013#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16180#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16181#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16855#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16519#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16520#L506 assume !(1 == ~t4_pc~0); 16646#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16691#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16641#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16471#L525 assume 1 == ~t5_pc~0; 16406#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16125#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16598#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16599#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16322#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16323#L544 assume !(1 == ~t6_pc~0); 16472#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16473#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16817#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16107#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16108#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16957#L563 assume 1 == ~t7_pc~0; 16835#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16135#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16136#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16267#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16268#L582 assume 1 == ~t8_pc~0; 16191#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16192#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17014#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16410#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16411#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 16869#L964-2 assume !(1 == ~T1_E~0); 16324#L969-1 assume !(1 == ~T2_E~0); 16325#L974-1 assume !(1 == ~T3_E~0); 16894#L979-1 assume !(1 == ~T4_E~0); 16895#L984-1 assume !(1 == ~T5_E~0); 16478#L989-1 assume !(1 == ~T6_E~0); 16479#L994-1 assume !(1 == ~T7_E~0); 16364#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16365#L1004-1 assume !(1 == ~E_M~0); 16109#L1009-1 assume !(1 == ~E_1~0); 16110#L1014-1 assume !(1 == ~E_2~0); 16353#L1019-1 assume !(1 == ~E_3~0); 16858#L1024-1 assume !(1 == ~E_4~0); 16286#L1029-1 assume !(1 == ~E_5~0); 16287#L1034-1 assume !(1 == ~E_6~0); 16381#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16995#L1044-1 assume !(1 == ~E_8~0); 16563#L1049-1 assume { :end_inline_reset_delta_events } true; 16256#L1315-2 [2021-12-19 19:16:05,489 INFO L793 eck$LassoCheckResult]: Loop: 16256#L1315-2 assume !false; 16257#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16043#L841 assume !false; 16382#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16317#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16318#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16158#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16078#L724 assume !(0 != eval_~tmp~0#1); 16080#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16908#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16089#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16090#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16385#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16386#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16399#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16400#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16623#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16624#L896-3 assume !(0 == ~T7_E~0); 16491#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16492#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16625#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16828#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16431#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16432#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16812#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16498#L936-3 assume !(0 == ~E_6~0); 16499#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16640#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16388#L430-30 assume 1 == ~m_pc~0; 16412#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16413#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16196#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16197#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16846#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16850#L449-30 assume !(1 == ~t1_pc~0); 16416#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 16105#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16106#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16477#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16189#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16190#L468-30 assume 1 == ~t2_pc~0; 16281#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16282#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16891#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16614#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16615#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16465#L487-30 assume !(1 == ~t3_pc~0); 16260#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16261#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16592#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16593#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16865#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16539#L506-30 assume !(1 == ~t4_pc~0); 16540#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16566#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16567#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16584#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 16466#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16467#L525-30 assume 1 == ~t5_pc~0; 16952#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16953#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16171#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16172#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16470#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16240#L544-30 assume 1 == ~t6_pc~0; 16048#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16049#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17022#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16962#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16963#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16939#L563-30 assume 1 == ~t7_pc~0; 16210#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16211#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16229#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16555#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16556#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16926#L582-30 assume !(1 == ~t8_pc~0); 16307#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 16308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16543#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16956#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17029#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16114#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16115#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16252#L969-3 assume !(1 == ~T2_E~0); 16243#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16244#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16655#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16656#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16799#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16161#L1009-3 assume !(1 == ~E_1~0); 16162#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16636#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16637#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16618#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16585#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16586#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16857#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16279#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16280#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16409#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16746#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16313#L1334 assume !(0 == start_simulation_~tmp~3#1); 16315#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16333#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16044#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16045#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16639#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16983#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16818#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16819#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16256#L1315-2 [2021-12-19 19:16:05,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,489 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2021-12-19 19:16:05,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918336349] [2021-12-19 19:16:05,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,543 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918336349] [2021-12-19 19:16:05,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918336349] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,543 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501310053] [2021-12-19 19:16:05,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,544 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:05,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,545 INFO L85 PathProgramCache]: Analyzing trace with hash -952835855, now seen corresponding path program 1 times [2021-12-19 19:16:05,545 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415080879] [2021-12-19 19:16:05,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415080879] [2021-12-19 19:16:05,587 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415080879] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,587 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921672109] [2021-12-19 19:16:05,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,588 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,588 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:05,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:05,589 INFO L87 Difference]: Start difference. First operand 998 states and 1483 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,688 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2021-12-19 19:16:05,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:05,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1816 states and 2689 transitions. [2021-12-19 19:16:05,699 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2021-12-19 19:16:05,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1816 states to 1816 states and 2689 transitions. [2021-12-19 19:16:05,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1816 [2021-12-19 19:16:05,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1816 [2021-12-19 19:16:05,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1816 states and 2689 transitions. [2021-12-19 19:16:05,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,710 INFO L681 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-19 19:16:05,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1816 states and 2689 transitions. [2021-12-19 19:16:05,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1816 to 1816. [2021-12-19 19:16:05,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1816 states to 1816 states and 2689 transitions. [2021-12-19 19:16:05,740 INFO L704 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-19 19:16:05,740 INFO L587 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-19 19:16:05,740 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:16:05,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1816 states and 2689 transitions. [2021-12-19 19:16:05,747 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2021-12-19 19:16:05,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:05,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:05,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:05,749 INFO L791 eck$LassoCheckResult]: Stem: 19638#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19563#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19564#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19416#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19000#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19001#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19082#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19800#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18970#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18971#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19378#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19404#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19086#L866 assume !(0 == ~M_E~0); 19087#L866-2 assume !(0 == ~T1_E~0); 19591#L871-1 assume !(0 == ~T2_E~0); 19592#L876-1 assume !(0 == ~T3_E~0); 19848#L881-1 assume !(0 == ~T4_E~0); 19602#L886-1 assume !(0 == ~T5_E~0); 19369#L891-1 assume !(0 == ~T6_E~0); 19370#L896-1 assume !(0 == ~T7_E~0); 19594#L901-1 assume !(0 == ~T8_E~0); 19614#L906-1 assume !(0 == ~E_M~0); 19615#L911-1 assume !(0 == ~E_1~0); 19413#L916-1 assume !(0 == ~E_2~0); 19414#L921-1 assume !(0 == ~E_3~0); 19712#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19812#L931-1 assume !(0 == ~E_5~0); 19853#L936-1 assume !(0 == ~E_6~0); 19861#L941-1 assume !(0 == ~E_7~0); 19419#L946-1 assume !(0 == ~E_8~0); 19420#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19831#L430 assume !(1 == ~m_pc~0); 19277#L430-2 is_master_triggered_~__retres1~0#1 := 0; 18905#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18906#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19520#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19530#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19695#L449 assume 1 == ~t1_pc~0; 19696#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19090#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18864#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18865#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19629#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19475#L468 assume !(1 == ~t2_pc~0); 18889#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18888#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19377#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19284#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 18907#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18908#L487 assume 1 == ~t3_pc~0; 19844#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19004#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19005#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19684#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19343#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19344#L506 assume !(1 == ~t4_pc~0); 19471#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19516#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19822#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19823#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19466#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19295#L525 assume 1 == ~t5_pc~0; 19230#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18949#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19423#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19424#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19146#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19147#L544 assume !(1 == ~t6_pc~0); 19296#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19297#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19645#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18931#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 18932#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19788#L563 assume 1 == ~t7_pc~0; 19663#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18959#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18960#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19371#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19091#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19092#L582 assume 1 == ~t8_pc~0; 19015#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19016#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19845#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19332#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19234#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19235#L964 assume !(1 == ~M_E~0); 19698#L964-2 assume !(1 == ~T1_E~0); 20095#L969-1 assume !(1 == ~T2_E~0); 20090#L974-1 assume !(1 == ~T3_E~0); 20086#L979-1 assume !(1 == ~T4_E~0); 20082#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19302#L989-1 assume !(1 == ~T6_E~0); 19303#L994-1 assume !(1 == ~T7_E~0); 19188#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19189#L1004-1 assume !(1 == ~E_M~0); 18933#L1009-1 assume !(1 == ~E_1~0); 18934#L1014-1 assume !(1 == ~E_2~0); 19177#L1019-1 assume !(1 == ~E_3~0); 19687#L1024-1 assume !(1 == ~E_4~0); 19110#L1029-1 assume !(1 == ~E_5~0); 19111#L1034-1 assume !(1 == ~E_6~0); 19205#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19826#L1044-1 assume !(1 == ~E_8~0); 19387#L1049-1 assume { :end_inline_reset_delta_events } true; 19388#L1315-2 [2021-12-19 19:16:05,750 INFO L793 eck$LassoCheckResult]: Loop: 19388#L1315-2 assume !false; 19890#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19889#L841 assume !false; 19888#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19883#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19878#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19877#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19875#L724 assume !(0 != eval_~tmp~0#1); 19874#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19873#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19872#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19846#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19209#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19210#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19223#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19224#L886-3 assume !(0 == ~T5_E~0); 19448#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19449#L896-3 assume !(0 == ~T7_E~0); 19315#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19316#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19450#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19656#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19255#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19256#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19640#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19322#L936-3 assume !(0 == ~E_6~0); 19323#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19465#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19211#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19212#L430-30 assume 1 == ~m_pc~0; 19236#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19237#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19020#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19021#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19675#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19679#L449-30 assume 1 == ~t1_pc~0; 19239#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18929#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18930#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19301#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19013#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19014#L468-30 assume 1 == ~t2_pc~0; 19105#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19106#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19721#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19439#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19440#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19289#L487-30 assume 1 == ~t3_pc~0; 19270#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19085#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19417#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19418#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19694#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19363#L506-30 assume !(1 == ~t4_pc~0); 19364#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19391#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19392#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19409#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 19290#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19291#L525-30 assume 1 == ~t5_pc~0; 19783#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19784#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18995#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18996#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19774#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20401#L544-30 assume !(1 == ~t6_pc~0); 20400#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20398#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20397#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20396#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19871#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19769#L563-30 assume 1 == ~t7_pc~0; 19034#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19035#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19053#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19379#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19380#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19756#L582-30 assume 1 == ~t8_pc~0; 19718#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19132#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19367#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19787#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19862#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18938#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18939#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19076#L969-3 assume !(1 == ~T2_E~0); 19067#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19068#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19480#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19481#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19113#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19114#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19627#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18985#L1009-3 assume !(1 == ~E_1~0); 18986#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19461#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19462#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19443#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19410#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19411#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19686#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19103#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19104#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19233#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19572#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19137#L1334 assume !(0 == start_simulation_~tmp~3#1); 19139#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19157#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18868#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18869#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 19464#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19814#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19646#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19647#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19388#L1315-2 [2021-12-19 19:16:05,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,750 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2021-12-19 19:16:05,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442653190] [2021-12-19 19:16:05,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442653190] [2021-12-19 19:16:05,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442653190] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039231454] [2021-12-19 19:16:05,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:05,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:05,790 INFO L85 PathProgramCache]: Analyzing trace with hash -779318671, now seen corresponding path program 1 times [2021-12-19 19:16:05,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:05,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678451230] [2021-12-19 19:16:05,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:05,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:05,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:05,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:05,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:05,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678451230] [2021-12-19 19:16:05,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678451230] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:05,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:05,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:05,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245437553] [2021-12-19 19:16:05,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:05,826 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:05,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:05,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:05,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:05,827 INFO L87 Difference]: Start difference. First operand 1816 states and 2689 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:05,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:05,947 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2021-12-19 19:16:05,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:05,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3306 states and 4884 transitions. [2021-12-19 19:16:05,961 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2021-12-19 19:16:05,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3306 states to 3306 states and 4884 transitions. [2021-12-19 19:16:05,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3306 [2021-12-19 19:16:05,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3306 [2021-12-19 19:16:05,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3306 states and 4884 transitions. [2021-12-19 19:16:05,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:05,981 INFO L681 BuchiCegarLoop]: Abstraction has 3306 states and 4884 transitions. [2021-12-19 19:16:05,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3306 states and 4884 transitions. [2021-12-19 19:16:06,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3306 to 3304. [2021-12-19 19:16:06,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3304 states to 3304 states and 4882 transitions. [2021-12-19 19:16:06,037 INFO L704 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2021-12-19 19:16:06,037 INFO L587 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2021-12-19 19:16:06,037 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:16:06,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3304 states and 4882 transitions. [2021-12-19 19:16:06,045 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2021-12-19 19:16:06,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:06,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:06,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,047 INFO L791 eck$LassoCheckResult]: Stem: 24780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 24702#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24703#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24553#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24554#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24133#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24134#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24215#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24965#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24103#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24104#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24517#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24542#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24219#L866 assume !(0 == ~M_E~0); 24220#L866-2 assume !(0 == ~T1_E~0); 24732#L871-1 assume !(0 == ~T2_E~0); 24733#L876-1 assume !(0 == ~T3_E~0); 25023#L881-1 assume !(0 == ~T4_E~0); 24744#L886-1 assume !(0 == ~T5_E~0); 24508#L891-1 assume !(0 == ~T6_E~0); 24509#L896-1 assume !(0 == ~T7_E~0); 24736#L901-1 assume !(0 == ~T8_E~0); 24756#L906-1 assume !(0 == ~E_M~0); 24757#L911-1 assume !(0 == ~E_1~0); 24551#L916-1 assume !(0 == ~E_2~0); 24552#L921-1 assume !(0 == ~E_3~0); 24860#L926-1 assume !(0 == ~E_4~0); 24977#L931-1 assume !(0 == ~E_5~0); 25033#L936-1 assume !(0 == ~E_6~0); 25043#L941-1 assume !(0 == ~E_7~0); 24557#L946-1 assume !(0 == ~E_8~0); 24558#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25005#L430 assume !(1 == ~m_pc~0); 24413#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24037#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24038#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24659#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24669#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24840#L449 assume 1 == ~t1_pc~0; 24841#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24224#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23996#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23997#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 24771#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24613#L468 assume !(1 == ~t2_pc~0); 24021#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24020#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24516#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24421#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24039#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24040#L487 assume 1 == ~t3_pc~0; 25020#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24137#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24138#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24829#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24482#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24483#L506 assume !(1 == ~t4_pc~0); 24609#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24655#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24604#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24434#L525 assume 1 == ~t5_pc~0; 24366#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24082#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24561#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24562#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24280#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24281#L544 assume !(1 == ~t6_pc~0); 24435#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24436#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24788#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24063#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24064#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24953#L563 assume 1 == ~t7_pc~0; 24807#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24092#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24093#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24510#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24225#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24226#L582 assume 1 == ~t8_pc~0; 24148#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24149#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25021#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24471#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24370#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24371#L964 assume !(1 == ~M_E~0); 24843#L964-2 assume !(1 == ~T1_E~0); 25141#L969-1 assume !(1 == ~T2_E~0); 24986#L974-1 assume !(1 == ~T3_E~0); 24987#L979-1 assume !(1 == ~T4_E~0); 25058#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24441#L989-1 assume !(1 == ~T6_E~0); 24442#L994-1 assume !(1 == ~T7_E~0); 24323#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24324#L1004-1 assume !(1 == ~E_M~0); 24065#L1009-1 assume !(1 == ~E_1~0); 24066#L1014-1 assume !(1 == ~E_2~0); 25131#L1019-1 assume !(1 == ~E_3~0); 25119#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25117#L1029-1 assume !(1 == ~E_5~0); 25115#L1034-1 assume !(1 == ~E_6~0); 25113#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25111#L1044-1 assume !(1 == ~E_8~0); 25109#L1049-1 assume { :end_inline_reset_delta_events } true; 25102#L1315-2 [2021-12-19 19:16:06,048 INFO L793 eck$LassoCheckResult]: Loop: 25102#L1315-2 assume !false; 25097#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L841 assume !false; 25095#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25090#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25085#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25084#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25082#L724 assume !(0 != eval_~tmp~0#1); 25081#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25080#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25078#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25079#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26591#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26590#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26589#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26588#L886-3 assume !(0 == ~T5_E~0); 26586#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26583#L896-3 assume !(0 == ~T7_E~0); 26581#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26578#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26574#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26571#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26568#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26564#L926-3 assume !(0 == ~E_4~0); 26562#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26558#L936-3 assume !(0 == ~E_6~0); 26555#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26553#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26551#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26549#L430-30 assume 1 == ~m_pc~0; 26546#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26541#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26503#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26450#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26447#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26445#L449-30 assume !(1 == ~t1_pc~0); 26442#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 26440#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26438#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26436#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26433#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26432#L468-30 assume 1 == ~t2_pc~0; 26429#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26426#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26395#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26392#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26383#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26375#L487-30 assume 1 == ~t3_pc~0; 24406#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24218#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24555#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24556#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24839#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24502#L506-30 assume !(1 == ~t4_pc~0); 24503#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 24529#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24530#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24547#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 24429#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24430#L525-30 assume 1 == ~t5_pc~0; 24946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24128#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24129#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24433#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24197#L544-30 assume 1 == ~t6_pc~0; 24004#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24005#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25035#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24958#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24959#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24928#L563-30 assume 1 == ~t7_pc~0; 24167#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24168#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24186#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24518#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24519#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24910#L582-30 assume 1 == ~t8_pc~0; 24912#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25319#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25317#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25315#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25294#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25256#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24071#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25242#L969-3 assume !(1 == ~T2_E~0); 25239#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25230#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25217#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25205#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25198#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25192#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25187#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25181#L1009-3 assume !(1 == ~E_1~0); 25177#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25174#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25166#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25163#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25162#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25161#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25160#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25159#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25148#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25140#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25139#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25138#L1334 assume !(0 == start_simulation_~tmp~3#1); 24923#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25128#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25118#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25116#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25114#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25112#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25110#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25108#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25102#L1315-2 [2021-12-19 19:16:06,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,048 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2021-12-19 19:16:06,048 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940107106] [2021-12-19 19:16:06,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,085 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,085 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940107106] [2021-12-19 19:16:06,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940107106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,085 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,086 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:06,086 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207702035] [2021-12-19 19:16:06,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,086 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:06,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,087 INFO L85 PathProgramCache]: Analyzing trace with hash -830163917, now seen corresponding path program 1 times [2021-12-19 19:16:06,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285854384] [2021-12-19 19:16:06,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,113 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,113 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285854384] [2021-12-19 19:16:06,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285854384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,114 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,114 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:06,114 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781169357] [2021-12-19 19:16:06,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,115 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:06,115 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:06,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:06,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:06,115 INFO L87 Difference]: Start difference. First operand 3304 states and 4882 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:06,357 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2021-12-19 19:16:06,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:06,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9486 states and 13948 transitions. [2021-12-19 19:16:06,395 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9108 [2021-12-19 19:16:06,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9486 states to 9486 states and 13948 transitions. [2021-12-19 19:16:06,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9486 [2021-12-19 19:16:06,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9486 [2021-12-19 19:16:06,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9486 states and 13948 transitions. [2021-12-19 19:16:06,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:06,455 INFO L681 BuchiCegarLoop]: Abstraction has 9486 states and 13948 transitions. [2021-12-19 19:16:06,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9486 states and 13948 transitions. [2021-12-19 19:16:06,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9486 to 3424. [2021-12-19 19:16:06,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3424 states to 3424 states and 5002 transitions. [2021-12-19 19:16:06,550 INFO L704 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2021-12-19 19:16:06,550 INFO L587 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2021-12-19 19:16:06,550 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:16:06,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3424 states and 5002 transitions. [2021-12-19 19:16:06,559 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3270 [2021-12-19 19:16:06,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:06,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:06,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,560 INFO L791 eck$LassoCheckResult]: Stem: 37602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 37603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37524#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37525#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37359#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 37360#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36936#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36937#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37019#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37795#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36906#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36907#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37325#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37348#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37023#L866 assume !(0 == ~M_E~0); 37024#L866-2 assume !(0 == ~T1_E~0); 37553#L871-1 assume !(0 == ~T2_E~0); 37554#L876-1 assume !(0 == ~T3_E~0); 37865#L881-1 assume !(0 == ~T4_E~0); 37564#L886-1 assume !(0 == ~T5_E~0); 37314#L891-1 assume !(0 == ~T6_E~0); 37315#L896-1 assume !(0 == ~T7_E~0); 37556#L901-1 assume !(0 == ~T8_E~0); 37577#L906-1 assume !(0 == ~E_M~0); 37578#L911-1 assume !(0 == ~E_1~0); 37357#L916-1 assume !(0 == ~E_2~0); 37358#L921-1 assume !(0 == ~E_3~0); 37685#L926-1 assume !(0 == ~E_4~0); 37811#L931-1 assume !(0 == ~E_5~0); 37876#L936-1 assume !(0 == ~E_6~0); 37892#L941-1 assume !(0 == ~E_7~0); 37364#L946-1 assume !(0 == ~E_8~0); 37365#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37840#L430 assume !(1 == ~m_pc~0); 37220#L430-2 is_master_triggered_~__retres1~0#1 := 0; 36842#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36843#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37483#L1073 assume !(0 != activate_threads_~tmp~1#1); 37484#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37668#L449 assume 1 == ~t1_pc~0; 37669#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37027#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36799#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36800#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 37592#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37423#L468 assume !(1 == ~t2_pc~0); 36826#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36825#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37322#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37227#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 36844#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36845#L487 assume 1 == ~t3_pc~0; 37860#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36940#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36941#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37653#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 37287#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37288#L506 assume !(1 == ~t4_pc~0); 37417#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37465#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37826#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37827#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 37412#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37236#L525 assume 1 == ~t5_pc~0; 37172#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36885#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37367#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37368#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 37083#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37084#L544 assume !(1 == ~t6_pc~0); 37237#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37238#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37609#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36866#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 36867#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37782#L563 assume 1 == ~t7_pc~0; 37628#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36895#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36896#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37321#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 37030#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37031#L582 assume 1 == ~t8_pc~0; 36951#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36952#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37861#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37275#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 37173#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37174#L964 assume !(1 == ~M_E~0); 37672#L964-2 assume !(1 == ~T1_E~0); 37085#L969-1 assume !(1 == ~T2_E~0); 37086#L974-1 assume !(1 == ~T3_E~0); 37703#L979-1 assume !(1 == ~T4_E~0); 37704#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37243#L989-1 assume !(1 == ~T6_E~0); 37244#L994-1 assume !(1 == ~T7_E~0); 37129#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37130#L1004-1 assume !(1 == ~E_M~0); 36868#L1009-1 assume !(1 == ~E_1~0); 36869#L1014-1 assume !(1 == ~E_2~0); 38102#L1019-1 assume !(1 == ~E_3~0); 38078#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 38061#L1029-1 assume !(1 == ~E_5~0); 38040#L1034-1 assume !(1 == ~E_6~0); 38026#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38015#L1044-1 assume !(1 == ~E_8~0); 38006#L1049-1 assume { :end_inline_reset_delta_events } true; 37999#L1315-2 [2021-12-19 19:16:06,561 INFO L793 eck$LassoCheckResult]: Loop: 37999#L1315-2 assume !false; 37994#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37993#L841 assume !false; 37992#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37987#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37982#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37981#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37979#L724 assume !(0 != eval_~tmp~0#1); 37978#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37977#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37976#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37863#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37148#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37149#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37162#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37163#L886-3 assume !(0 == ~T5_E~0); 37392#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37393#L896-3 assume !(0 == ~T7_E~0); 37256#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37257#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37394#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37621#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37194#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37195#L926-3 assume !(0 == ~E_4~0); 37604#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40079#L936-3 assume !(0 == ~E_6~0); 40075#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37695#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37150#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37151#L430-30 assume 1 == ~m_pc~0; 37175#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37176#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36956#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36957#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40018#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40016#L449-30 assume !(1 == ~t1_pc~0); 40012#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 40010#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40008#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40006#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40004#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40002#L468-30 assume 1 == ~t2_pc~0; 39998#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39996#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39994#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39992#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39990#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39988#L487-30 assume !(1 == ~t3_pc~0); 39984#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 39982#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39980#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39978#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39976#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39974#L506-30 assume 1 == ~t4_pc~0; 39970#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39968#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39966#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39964#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 39963#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39962#L525-30 assume 1 == ~t5_pc~0; 39960#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39959#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39958#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39957#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39956#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39955#L544-30 assume 1 == ~t6_pc~0; 39953#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39952#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39951#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37787#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37788#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37756#L563-30 assume 1 == ~t7_pc~0; 36967#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36968#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36990#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37323#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37324#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37739#L582-30 assume !(1 == ~t8_pc~0); 37740#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38459#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38457#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38428#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38426#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38424#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36871#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38368#L969-3 assume !(1 == ~T2_E~0); 38366#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38364#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38347#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38343#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38332#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38330#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38329#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38327#L1009-3 assume !(1 == ~E_1~0); 38307#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38306#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38284#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38280#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38278#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38276#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38274#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38111#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38109#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 38107#L1334 assume !(0 == start_simulation_~tmp~3#1); 37753#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38077#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38060#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 38039#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38025#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38014#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 38005#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 37999#L1315-2 [2021-12-19 19:16:06,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,561 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2021-12-19 19:16:06,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086355907] [2021-12-19 19:16:06,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086355907] [2021-12-19 19:16:06,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086355907] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:06,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956573537] [2021-12-19 19:16:06,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,584 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:06,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1404058164, now seen corresponding path program 1 times [2021-12-19 19:16:06,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686450423] [2021-12-19 19:16:06,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,625 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686450423] [2021-12-19 19:16:06,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686450423] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,625 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,625 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:06,625 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463656399] [2021-12-19 19:16:06,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,626 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:06,626 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:06,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:06,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:06,627 INFO L87 Difference]: Start difference. First operand 3424 states and 5002 transitions. cyclomatic complexity: 1582 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:06,697 INFO L93 Difference]: Finished difference Result 6378 states and 9252 transitions. [2021-12-19 19:16:06,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:06,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6378 states and 9252 transitions. [2021-12-19 19:16:06,720 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6221 [2021-12-19 19:16:06,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6378 states to 6378 states and 9252 transitions. [2021-12-19 19:16:06,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6378 [2021-12-19 19:16:06,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6378 [2021-12-19 19:16:06,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6378 states and 9252 transitions. [2021-12-19 19:16:06,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:06,751 INFO L681 BuchiCegarLoop]: Abstraction has 6378 states and 9252 transitions. [2021-12-19 19:16:06,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6378 states and 9252 transitions. [2021-12-19 19:16:06,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6378 to 6370. [2021-12-19 19:16:06,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6370 states, 6370 states have (on average 1.451177394034537) internal successors, (9244), 6369 states have internal predecessors, (9244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:06,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6370 states to 6370 states and 9244 transitions. [2021-12-19 19:16:06,854 INFO L704 BuchiCegarLoop]: Abstraction has 6370 states and 9244 transitions. [2021-12-19 19:16:06,854 INFO L587 BuchiCegarLoop]: Abstraction has 6370 states and 9244 transitions. [2021-12-19 19:16:06,854 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:16:06,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6370 states and 9244 transitions. [2021-12-19 19:16:06,868 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6213 [2021-12-19 19:16:06,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:06,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:06,870 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,870 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:06,870 INFO L791 eck$LassoCheckResult]: Stem: 47424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 47425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 47338#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47339#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47170#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 47171#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46745#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46746#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46826#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47636#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46715#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46716#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47132#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47159#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46830#L866 assume !(0 == ~M_E~0); 46831#L866-2 assume !(0 == ~T1_E~0); 47373#L871-1 assume !(0 == ~T2_E~0); 47374#L876-1 assume !(0 == ~T3_E~0); 47706#L881-1 assume !(0 == ~T4_E~0); 47384#L886-1 assume !(0 == ~T5_E~0); 47123#L891-1 assume !(0 == ~T6_E~0); 47124#L896-1 assume !(0 == ~T7_E~0); 47376#L901-1 assume !(0 == ~T8_E~0); 47396#L906-1 assume !(0 == ~E_M~0); 47397#L911-1 assume !(0 == ~E_1~0); 47168#L916-1 assume !(0 == ~E_2~0); 47169#L921-1 assume !(0 == ~E_3~0); 47512#L926-1 assume !(0 == ~E_4~0); 47651#L931-1 assume !(0 == ~E_5~0); 47722#L936-1 assume !(0 == ~E_6~0); 47743#L941-1 assume !(0 == ~E_7~0); 47174#L946-1 assume !(0 == ~E_8~0); 47175#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47680#L430 assume !(1 == ~m_pc~0); 47025#L430-2 is_master_triggered_~__retres1~0#1 := 0; 47601#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47782#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47303#L1073 assume !(0 != activate_threads_~tmp~1#1); 47304#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47494#L449 assume !(1 == ~t1_pc~0); 46833#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46834#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46608#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46609#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 47412#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47236#L468 assume !(1 == ~t2_pc~0); 46633#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46632#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47131#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47033#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 46651#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46652#L487 assume 1 == ~t3_pc~0; 47703#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46749#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46750#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47480#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 47098#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47099#L506 assume !(1 == ~t4_pc~0); 47232#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47282#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47668#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47669#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 47226#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47044#L525 assume 1 == ~t5_pc~0; 46977#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46693#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47179#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47180#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 46890#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46891#L544 assume !(1 == ~t6_pc~0); 47045#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47046#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47432#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46675#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 46676#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47615#L563 assume 1 == ~t7_pc~0; 47450#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46703#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46704#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47125#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 46835#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46836#L582 assume 1 == ~t8_pc~0; 46760#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46761#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47704#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47085#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 46981#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46982#L964 assume !(1 == ~M_E~0); 47496#L964-2 assume !(1 == ~T1_E~0); 50673#L969-1 assume !(1 == ~T2_E~0); 50671#L974-1 assume !(1 == ~T3_E~0); 50669#L979-1 assume !(1 == ~T4_E~0); 50666#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50667#L989-1 assume !(1 == ~T6_E~0); 51239#L994-1 assume !(1 == ~T7_E~0); 51237#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51235#L1004-1 assume !(1 == ~E_M~0); 51233#L1009-1 assume !(1 == ~E_1~0); 51230#L1014-1 assume !(1 == ~E_2~0); 51228#L1019-1 assume !(1 == ~E_3~0); 51226#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46854#L1029-1 assume !(1 == ~E_5~0); 46855#L1034-1 assume !(1 == ~E_6~0); 46951#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 47672#L1044-1 assume !(1 == ~E_8~0); 47141#L1049-1 assume { :end_inline_reset_delta_events } true; 47142#L1315-2 [2021-12-19 19:16:06,870 INFO L793 eck$LassoCheckResult]: Loop: 47142#L1315-2 assume !false; 48002#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47888#L841 assume !false; 47991#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 47941#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 47902#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 47895#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47884#L724 assume !(0 != eval_~tmp~0#1); 47886#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52797#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52796#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52795#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52794#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52793#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52792#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52791#L886-3 assume !(0 == ~T5_E~0); 52790#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52789#L896-3 assume !(0 == ~T7_E~0); 52788#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47207#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47208#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47443#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47002#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47003#L926-3 assume !(0 == ~E_4~0); 47426#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51768#L936-3 assume !(0 == ~E_6~0); 51767#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51766#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51765#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51764#L430-30 assume !(1 == ~m_pc~0); 51762#L430-32 is_master_triggered_~__retres1~0#1 := 0; 51760#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51758#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51757#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 51755#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51754#L449-30 assume !(1 == ~t1_pc~0); 51753#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 51752#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51751#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51750#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51749#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51748#L468-30 assume 1 == ~t2_pc~0; 51746#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51745#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51744#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47196#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47197#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47038#L487-30 assume 1 == ~t3_pc~0; 47018#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46829#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47172#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47173#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47490#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47117#L506-30 assume !(1 == ~t4_pc~0); 47118#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 47145#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47146#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47164#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 47039#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47040#L525-30 assume 1 == ~t5_pc~0; 47609#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47610#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46740#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46741#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47043#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46808#L544-30 assume 1 == ~t6_pc~0; 46616#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46617#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47727#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47622#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47623#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47590#L563-30 assume 1 == ~t7_pc~0; 46778#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46779#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46797#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47133#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47134#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47569#L582-30 assume !(1 == ~t8_pc~0); 46874#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 46875#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47121#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47613#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47747#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46682#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46683#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46820#L969-3 assume !(1 == ~T2_E~0); 46811#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46812#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47241#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47242#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46857#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46858#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47410#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46730#L1009-3 assume !(1 == ~E_1~0); 46731#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47221#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47222#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47200#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47165#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47166#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47482#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46847#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46848#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 46980#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 47800#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 46881#L1334 assume !(0 == start_simulation_~tmp~3#1); 46883#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48028#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48019#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48017#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 48015#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48011#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48009#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 48007#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 47142#L1315-2 [2021-12-19 19:16:06,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,871 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2021-12-19 19:16:06,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093877291] [2021-12-19 19:16:06,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,871 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093877291] [2021-12-19 19:16:06,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093877291] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,896 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:06,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105110582] [2021-12-19 19:16:06,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,896 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:06,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:06,897 INFO L85 PathProgramCache]: Analyzing trace with hash -1979928649, now seen corresponding path program 1 times [2021-12-19 19:16:06,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:06,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733912382] [2021-12-19 19:16:06,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:06,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:06,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:06,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:06,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:06,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733912382] [2021-12-19 19:16:06,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733912382] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:06,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:06,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:06,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987038928] [2021-12-19 19:16:06,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:06,921 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:06,921 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:06,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:06,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:06,922 INFO L87 Difference]: Start difference. First operand 6370 states and 9244 transitions. cyclomatic complexity: 2882 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:07,121 INFO L93 Difference]: Finished difference Result 15178 states and 21822 transitions. [2021-12-19 19:16:07,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:07,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15178 states and 21822 transitions. [2021-12-19 19:16:07,190 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14990 [2021-12-19 19:16:07,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15178 states to 15178 states and 21822 transitions. [2021-12-19 19:16:07,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15178 [2021-12-19 19:16:07,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15178 [2021-12-19 19:16:07,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15178 states and 21822 transitions. [2021-12-19 19:16:07,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:07,269 INFO L681 BuchiCegarLoop]: Abstraction has 15178 states and 21822 transitions. [2021-12-19 19:16:07,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15178 states and 21822 transitions. [2021-12-19 19:16:07,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15178 to 12222. [2021-12-19 19:16:07,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12222 states, 12222 states have (on average 1.4419898543609884) internal successors, (17624), 12221 states have internal predecessors, (17624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12222 states to 12222 states and 17624 transitions. [2021-12-19 19:16:07,555 INFO L704 BuchiCegarLoop]: Abstraction has 12222 states and 17624 transitions. [2021-12-19 19:16:07,555 INFO L587 BuchiCegarLoop]: Abstraction has 12222 states and 17624 transitions. [2021-12-19 19:16:07,555 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:16:07,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12222 states and 17624 transitions. [2021-12-19 19:16:07,608 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12062 [2021-12-19 19:16:07,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:07,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:07,610 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,610 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:07,610 INFO L791 eck$LassoCheckResult]: Stem: 68972#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 68973#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 68893#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68894#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68731#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 68732#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68303#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68304#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68384#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69170#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68273#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68274#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68698#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68720#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68390#L866 assume !(0 == ~M_E~0); 68391#L866-2 assume !(0 == ~T1_E~0); 68925#L871-1 assume !(0 == ~T2_E~0); 68926#L876-1 assume !(0 == ~T3_E~0); 69242#L881-1 assume !(0 == ~T4_E~0); 68936#L886-1 assume !(0 == ~T5_E~0); 68687#L891-1 assume !(0 == ~T6_E~0); 68688#L896-1 assume !(0 == ~T7_E~0); 68928#L901-1 assume !(0 == ~T8_E~0); 68948#L906-1 assume !(0 == ~E_M~0); 68949#L911-1 assume !(0 == ~E_1~0); 68729#L916-1 assume !(0 == ~E_2~0); 68730#L921-1 assume !(0 == ~E_3~0); 69063#L926-1 assume !(0 == ~E_4~0); 69185#L931-1 assume !(0 == ~E_5~0); 69249#L936-1 assume !(0 == ~E_6~0); 69259#L941-1 assume !(0 == ~E_7~0); 68736#L946-1 assume !(0 == ~E_8~0); 68737#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69217#L430 assume !(1 == ~m_pc~0); 68594#L430-2 is_master_triggered_~__retres1~0#1 := 0; 69142#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69286#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68859#L1073 assume !(0 != activate_threads_~tmp~1#1); 68860#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69045#L449 assume !(1 == ~t1_pc~0); 68393#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68394#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68166#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68167#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 68963#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68793#L468 assume !(1 == ~t2_pc~0); 68191#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68190#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68695#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68599#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 68209#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68210#L487 assume !(1 == ~t3_pc~0); 68330#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68307#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68308#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69030#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 68663#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68664#L506 assume !(1 == ~t4_pc~0); 68789#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68842#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69201#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69202#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 68782#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68610#L525 assume 1 == ~t5_pc~0; 68543#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68251#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68739#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68740#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 68450#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68451#L544 assume !(1 == ~t6_pc~0); 68611#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68612#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68979#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68233#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 68234#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69156#L563 assume 1 == ~t7_pc~0; 68999#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68261#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68262#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68689#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 68395#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68396#L582 assume 1 == ~t8_pc~0; 68318#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68319#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69239#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68652#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 68544#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68545#L964 assume !(1 == ~M_E~0); 69048#L964-2 assume !(1 == ~T1_E~0); 68452#L969-1 assume !(1 == ~T2_E~0); 68453#L974-1 assume !(1 == ~T3_E~0); 69077#L979-1 assume !(1 == ~T4_E~0); 69078#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76050#L989-1 assume !(1 == ~T6_E~0); 79375#L994-1 assume !(1 == ~T7_E~0); 79374#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 79373#L1004-1 assume !(1 == ~E_M~0); 79372#L1009-1 assume !(1 == ~E_1~0); 68485#L1014-1 assume !(1 == ~E_2~0); 68486#L1019-1 assume !(1 == ~E_3~0); 69035#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69225#L1029-1 assume !(1 == ~E_5~0); 78401#L1034-1 assume !(1 == ~E_6~0); 78399#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 78397#L1044-1 assume !(1 == ~E_8~0); 78396#L1049-1 assume { :end_inline_reset_delta_events } true; 78390#L1315-2 [2021-12-19 19:16:07,611 INFO L793 eck$LassoCheckResult]: Loop: 78390#L1315-2 assume !false; 78134#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77611#L841 assume !false; 77607#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 77600#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 77595#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 77587#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77408#L724 assume !(0 != eval_~tmp~0#1); 77409#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78663#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78662#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78658#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78656#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78654#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78653#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78648#L886-3 assume !(0 == ~T5_E~0); 78643#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78638#L896-3 assume !(0 == ~T7_E~0); 78637#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78636#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78635#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78634#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78633#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78632#L926-3 assume !(0 == ~E_4~0); 78631#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78630#L936-3 assume !(0 == ~E_6~0); 78629#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78628#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78627#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78626#L430-30 assume 1 == ~m_pc~0; 78625#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 78623#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78621#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78618#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78617#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78616#L449-30 assume !(1 == ~t1_pc~0); 78614#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 78613#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78612#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78611#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78610#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78606#L468-30 assume 1 == ~t2_pc~0; 78603#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78601#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78599#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78596#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78594#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78592#L487-30 assume !(1 == ~t3_pc~0); 75820#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 78589#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78587#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78585#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78583#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78581#L506-30 assume 1 == ~t4_pc~0; 78577#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78575#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78573#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78571#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 78569#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78567#L525-30 assume 1 == ~t5_pc~0; 78565#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78563#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78561#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78559#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78557#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78555#L544-30 assume 1 == ~t6_pc~0; 78551#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78549#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78547#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78545#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78543#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78541#L563-30 assume 1 == ~t7_pc~0; 78537#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78535#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78533#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78531#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78529#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78527#L582-30 assume !(1 == ~t8_pc~0); 78523#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 78521#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78519#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78517#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78515#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78513#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 68238#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78509#L969-3 assume !(1 == ~T2_E~0); 78507#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78505#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78503#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76342#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78499#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78497#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78495#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78493#L1009-3 assume !(1 == ~E_1~0); 78491#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78490#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78486#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69281#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78483#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78482#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78481#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78480#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 78473#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 78470#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 78469#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 78468#L1334 assume !(0 == start_simulation_~tmp~3#1); 69129#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 78414#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 78405#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 78403#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 78402#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78400#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78398#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 78395#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 78390#L1315-2 [2021-12-19 19:16:07,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2021-12-19 19:16:07,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041803080] [2021-12-19 19:16:07,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:07,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:07,642 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:07,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041803080] [2021-12-19 19:16:07,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041803080] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:07,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:07,643 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:07,643 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312529262] [2021-12-19 19:16:07,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:07,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:07,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:07,645 INFO L85 PathProgramCache]: Analyzing trace with hash 1404058164, now seen corresponding path program 2 times [2021-12-19 19:16:07,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:07,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415424253] [2021-12-19 19:16:07,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:07,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:07,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:07,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:07,674 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:07,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415424253] [2021-12-19 19:16:07,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415424253] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:07,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:07,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:07,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266106291] [2021-12-19 19:16:07,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:07,675 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:07,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:07,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:07,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:07,676 INFO L87 Difference]: Start difference. First operand 12222 states and 17624 transitions. cyclomatic complexity: 5410 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:07,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:07,961 INFO L93 Difference]: Finished difference Result 28638 states and 40994 transitions. [2021-12-19 19:16:07,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:07,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28638 states and 40994 transitions. [2021-12-19 19:16:08,088 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28415 [2021-12-19 19:16:08,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28638 states to 28638 states and 40994 transitions. [2021-12-19 19:16:08,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28638 [2021-12-19 19:16:08,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28638 [2021-12-19 19:16:08,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28638 states and 40994 transitions. [2021-12-19 19:16:08,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:08,286 INFO L681 BuchiCegarLoop]: Abstraction has 28638 states and 40994 transitions. [2021-12-19 19:16:08,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28638 states and 40994 transitions. [2021-12-19 19:16:08,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28638 to 23043. [2021-12-19 19:16:08,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23043 states, 23043 states have (on average 1.4357071561862604) internal successors, (33083), 23042 states have internal predecessors, (33083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:08,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23043 states to 23043 states and 33083 transitions. [2021-12-19 19:16:08,914 INFO L704 BuchiCegarLoop]: Abstraction has 23043 states and 33083 transitions. [2021-12-19 19:16:08,914 INFO L587 BuchiCegarLoop]: Abstraction has 23043 states and 33083 transitions. [2021-12-19 19:16:08,914 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:16:08,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23043 states and 33083 transitions. [2021-12-19 19:16:09,051 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22876 [2021-12-19 19:16:09,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:09,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:09,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:09,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:09,054 INFO L791 eck$LassoCheckResult]: Stem: 109864#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 109865#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 109781#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109782#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109606#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 109607#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109170#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109171#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109252#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110104#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109141#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 109142#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 109568#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 109594#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109258#L866 assume !(0 == ~M_E~0); 109259#L866-2 assume !(0 == ~T1_E~0); 109812#L871-1 assume !(0 == ~T2_E~0); 109813#L876-1 assume !(0 == ~T3_E~0); 110205#L881-1 assume !(0 == ~T4_E~0); 109825#L886-1 assume !(0 == ~T5_E~0); 109559#L891-1 assume !(0 == ~T6_E~0); 109560#L896-1 assume !(0 == ~T7_E~0); 109815#L901-1 assume !(0 == ~T8_E~0); 109836#L906-1 assume !(0 == ~E_M~0); 109837#L911-1 assume !(0 == ~E_1~0); 109604#L916-1 assume !(0 == ~E_2~0); 109605#L921-1 assume !(0 == ~E_3~0); 109967#L926-1 assume !(0 == ~E_4~0); 110125#L931-1 assume !(0 == ~E_5~0); 110229#L936-1 assume !(0 == ~E_6~0); 110258#L941-1 assume !(0 == ~E_7~0); 109610#L946-1 assume !(0 == ~E_8~0); 109611#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110167#L430 assume !(1 == ~m_pc~0); 109460#L430-2 is_master_triggered_~__retres1~0#1 := 0; 109077#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109078#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109729#L1073 assume !(0 != activate_threads_~tmp~1#1); 109745#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109943#L449 assume !(1 == ~t1_pc~0); 109261#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 109262#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109036#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 109037#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 109852#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109673#L468 assume !(1 == ~t2_pc~0); 109061#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109060#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109567#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109467#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 109079#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109080#L487 assume !(1 == ~t3_pc~0); 109197#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 109174#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109175#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 109922#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 109533#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109534#L506 assume !(1 == ~t4_pc~0); 109669#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109722#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110144#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110145#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 109661#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109479#L525 assume !(1 == ~t5_pc~0); 109119#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 109120#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109615#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109616#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 109321#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109322#L544 assume !(1 == ~t6_pc~0); 109480#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 109481#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109871#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 109103#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 109104#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110086#L563 assume 1 == ~t7_pc~0; 109889#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109130#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109131#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109561#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 109263#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 109264#L582 assume 1 == ~t8_pc~0; 109185#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109186#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110196#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 109521#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 109414#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109415#L964 assume !(1 == ~M_E~0); 109945#L964-2 assume !(1 == ~T1_E~0); 109323#L969-1 assume !(1 == ~T2_E~0); 109324#L974-1 assume !(1 == ~T3_E~0); 109984#L979-1 assume !(1 == ~T4_E~0); 109985#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 109486#L989-1 assume !(1 == ~T6_E~0); 109487#L994-1 assume !(1 == ~T7_E~0); 109365#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109366#L1004-1 assume !(1 == ~E_M~0); 109105#L1009-1 assume !(1 == ~E_1~0); 109106#L1014-1 assume !(1 == ~E_2~0); 109929#L1019-1 assume !(1 == ~E_3~0); 109930#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 109282#L1029-1 assume !(1 == ~E_5~0); 109283#L1034-1 assume !(1 == ~E_6~0); 110300#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 110301#L1044-1 assume !(1 == ~E_8~0); 109576#L1049-1 assume { :end_inline_reset_delta_events } true; 109577#L1315-2 [2021-12-19 19:16:09,054 INFO L793 eck$LassoCheckResult]: Loop: 109577#L1315-2 assume !false; 120634#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 120632#L841 assume !false; 120631#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 120622#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 120616#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 120614#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 120610#L724 assume !(0 != eval_~tmp~0#1); 120611#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123183#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123182#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 123181#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123180#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 123179#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123178#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123177#L886-3 assume !(0 == ~T5_E~0); 123176#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123175#L896-3 assume !(0 == ~T7_E~0); 123174#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 123173#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 123172#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123171#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123170#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123169#L926-3 assume !(0 == ~E_4~0); 123168#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123167#L936-3 assume !(0 == ~E_6~0); 123166#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 123165#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 123164#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123163#L430-30 assume 1 == ~m_pc~0; 123161#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 123159#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123157#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123155#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123154#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123153#L449-30 assume !(1 == ~t1_pc~0); 123152#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 123151#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123150#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123144#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123143#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123142#L468-30 assume !(1 == ~t2_pc~0); 123141#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 123139#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123138#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123136#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123134#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109472#L487-30 assume !(1 == ~t3_pc~0); 109473#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 122402#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122401#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 122400#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122399#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122398#L506-30 assume !(1 == ~t4_pc~0); 122397#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 122395#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122394#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122393#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 122392#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110295#L525-30 assume !(1 == ~t5_pc~0); 110201#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 110202#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109165#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109166#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 109478#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109234#L544-30 assume 1 == ~t6_pc~0; 109044#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 109045#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110235#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110091#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 110092#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110059#L563-30 assume 1 == ~t7_pc~0; 109203#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109204#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109223#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109569#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109570#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110035#L582-30 assume 1 == ~t8_pc~0; 109975#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109305#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109557#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110084#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110263#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109110#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 109111#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109246#L969-3 assume !(1 == ~T2_E~0); 109237#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109238#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109678#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 109679#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 109285#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 109286#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109850#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 109156#L1009-3 assume !(1 == ~E_1~0); 109157#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121552#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121550#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 117783#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121545#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 121542#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 121538#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 121536#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 121520#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 121515#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 121500#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 109312#L1334 assume !(0 == start_simulation_~tmp~3#1); 109314#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 120809#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 120799#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 120797#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 120795#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 120793#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 120791#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 120790#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 109577#L1315-2 [2021-12-19 19:16:09,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:09,055 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2021-12-19 19:16:09,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:09,055 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637211148] [2021-12-19 19:16:09,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:09,055 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:09,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:09,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:09,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:09,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637211148] [2021-12-19 19:16:09,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637211148] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:09,088 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:09,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:09,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184719048] [2021-12-19 19:16:09,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:09,088 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:09,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:09,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1963777546, now seen corresponding path program 1 times [2021-12-19 19:16:09,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:09,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531812691] [2021-12-19 19:16:09,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:09,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:09,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:09,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:09,114 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:09,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531812691] [2021-12-19 19:16:09,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531812691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:09,115 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:09,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:09,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245936021] [2021-12-19 19:16:09,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:09,115 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:09,116 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:09,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:09,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:09,116 INFO L87 Difference]: Start difference. First operand 23043 states and 33083 transitions. cyclomatic complexity: 10048 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:09,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:09,532 INFO L93 Difference]: Finished difference Result 53612 states and 76474 transitions. [2021-12-19 19:16:09,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:09,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53612 states and 76474 transitions. [2021-12-19 19:16:09,722 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 53318 [2021-12-19 19:16:09,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53612 states to 53612 states and 76474 transitions. [2021-12-19 19:16:09,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53612 [2021-12-19 19:16:10,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53612 [2021-12-19 19:16:10,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53612 states and 76474 transitions. [2021-12-19 19:16:10,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:10,059 INFO L681 BuchiCegarLoop]: Abstraction has 53612 states and 76474 transitions. [2021-12-19 19:16:10,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53612 states and 76474 transitions. [2021-12-19 19:16:10,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53612 to 43470. [2021-12-19 19:16:10,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43470 states, 43470 states have (on average 1.4304117782378651) internal successors, (62180), 43469 states have internal predecessors, (62180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:10,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43470 states to 43470 states and 62180 transitions. [2021-12-19 19:16:10,634 INFO L704 BuchiCegarLoop]: Abstraction has 43470 states and 62180 transitions. [2021-12-19 19:16:10,634 INFO L587 BuchiCegarLoop]: Abstraction has 43470 states and 62180 transitions. [2021-12-19 19:16:10,634 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:16:10,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43470 states and 62180 transitions. [2021-12-19 19:16:10,887 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43288 [2021-12-19 19:16:10,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:10,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:10,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:10,890 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:10,892 INFO L791 eck$LassoCheckResult]: Stem: 186525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 186526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 186434#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186435#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186270#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 186271#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 185836#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 185837#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 185917#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186744#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 185807#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 185808#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 186232#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 186258#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 185923#L866 assume !(0 == ~M_E~0); 185924#L866-2 assume !(0 == ~T1_E~0); 186468#L871-1 assume !(0 == ~T2_E~0); 186469#L876-1 assume !(0 == ~T3_E~0); 186836#L881-1 assume !(0 == ~T4_E~0); 186482#L886-1 assume !(0 == ~T5_E~0); 186223#L891-1 assume !(0 == ~T6_E~0); 186224#L896-1 assume !(0 == ~T7_E~0); 186471#L901-1 assume !(0 == ~T8_E~0); 186497#L906-1 assume !(0 == ~E_M~0); 186498#L911-1 assume !(0 == ~E_1~0); 186268#L916-1 assume !(0 == ~E_2~0); 186269#L921-1 assume !(0 == ~E_3~0); 186611#L926-1 assume !(0 == ~E_4~0); 186761#L931-1 assume !(0 == ~E_5~0); 186850#L936-1 assume !(0 == ~E_6~0); 186870#L941-1 assume !(0 == ~E_7~0); 186274#L946-1 assume !(0 == ~E_8~0); 186275#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186794#L430 assume !(1 == ~m_pc~0); 186124#L430-2 is_master_triggered_~__retres1~0#1 := 0; 185742#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185743#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 186388#L1073 assume !(0 != activate_threads_~tmp~1#1); 186400#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186589#L449 assume !(1 == ~t1_pc~0); 185926#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185927#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185701#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 185702#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 186512#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186335#L468 assume !(1 == ~t2_pc~0); 185726#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185725#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186231#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186132#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 185744#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185745#L487 assume !(1 == ~t3_pc~0); 185863#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185840#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185841#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186574#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 186198#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186199#L506 assume !(1 == ~t4_pc~0); 186330#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186384#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186778#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186779#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 186324#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186144#L525 assume !(1 == ~t5_pc~0); 185784#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185785#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186279#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 186280#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 185985#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185986#L544 assume !(1 == ~t6_pc~0); 186145#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 186146#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186533#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 185768#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 185769#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186726#L563 assume !(1 == ~t7_pc~0); 186530#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 185795#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 185796#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 186225#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 185928#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 185929#L582 assume 1 == ~t8_pc~0; 185851#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 185852#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186827#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 186185#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 186078#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186079#L964 assume !(1 == ~M_E~0); 186591#L964-2 assume !(1 == ~T1_E~0); 185987#L969-1 assume !(1 == ~T2_E~0); 185988#L974-1 assume !(1 == ~T3_E~0); 186627#L979-1 assume !(1 == ~T4_E~0); 186628#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 198979#L989-1 assume !(1 == ~T6_E~0); 186475#L994-1 assume !(1 == ~T7_E~0); 186476#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 186597#L1004-1 assume !(1 == ~E_M~0); 186598#L1009-1 assume !(1 == ~E_1~0); 186018#L1014-1 assume !(1 == ~E_2~0); 186019#L1019-1 assume !(1 == ~E_3~0); 186806#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 185947#L1029-1 assume !(1 == ~E_5~0); 185948#L1034-1 assume !(1 == ~E_6~0); 186897#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 186898#L1044-1 assume !(1 == ~E_8~0); 186240#L1049-1 assume { :end_inline_reset_delta_events } true; 186241#L1315-2 [2021-12-19 19:16:10,892 INFO L793 eck$LassoCheckResult]: Loop: 186241#L1315-2 assume !false; 223007#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 223005#L841 assume !false; 223004#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 222999#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 222985#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 222983#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 222980#L724 assume !(0 != eval_~tmp~0#1); 222981#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 225064#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 225061#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 225059#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 225056#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 225053#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 225050#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 224855#L886-3 assume !(0 == ~T5_E~0); 224854#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 224853#L896-3 assume !(0 == ~T7_E~0); 224852#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 224851#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 224850#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 224849#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 224847#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 224846#L926-3 assume !(0 == ~E_4~0); 224845#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 224844#L936-3 assume !(0 == ~E_6~0); 224843#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 224842#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 224841#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224839#L430-30 assume 1 == ~m_pc~0; 224837#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 224838#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224840#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224830#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 224828#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224826#L449-30 assume !(1 == ~t1_pc~0); 224824#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 224822#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224820#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224818#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 224816#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224814#L468-30 assume 1 == ~t2_pc~0; 224811#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 224809#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224807#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224805#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 224803#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224801#L487-30 assume !(1 == ~t3_pc~0); 205661#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 224798#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224796#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 224794#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 224790#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224788#L506-30 assume !(1 == ~t4_pc~0); 224786#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 224783#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224780#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 224778#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 224776#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224773#L525-30 assume !(1 == ~t5_pc~0); 203735#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 224770#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224768#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 224766#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 224764#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224761#L544-30 assume !(1 == ~t6_pc~0); 224759#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 224756#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224754#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 224752#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 224751#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 224750#L563-30 assume !(1 == ~t7_pc~0); 197123#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 224749#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 224747#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 224746#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 224745#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 224744#L582-30 assume 1 == ~t8_pc~0; 224741#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 224738#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 224734#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 224733#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 224732#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224728#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199064#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 224725#L969-3 assume !(1 == ~T2_E~0); 224723#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 224720#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 224718#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 199054#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 224714#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 224712#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 224710#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 224708#L1009-3 assume !(1 == ~E_1~0); 224706#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 224704#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 224701#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 205220#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 224698#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 224696#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 224694#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 224693#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 224686#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 215616#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 215242#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 185976#L1334 assume !(0 == start_simulation_~tmp~3#1); 185978#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 223030#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 223021#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 223019#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 223018#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 223017#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223013#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 223011#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 186241#L1315-2 [2021-12-19 19:16:10,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:10,893 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2021-12-19 19:16:10,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:10,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334270636] [2021-12-19 19:16:10,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:10,893 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:10,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:10,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:10,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:10,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334270636] [2021-12-19 19:16:10,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334270636] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:10,941 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:10,942 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:10,942 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338539326] [2021-12-19 19:16:10,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:10,942 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:10,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:10,944 INFO L85 PathProgramCache]: Analyzing trace with hash -729031945, now seen corresponding path program 1 times [2021-12-19 19:16:10,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:10,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967018542] [2021-12-19 19:16:10,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:10,945 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:10,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:10,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:10,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:10,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967018542] [2021-12-19 19:16:10,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967018542] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:10,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:10,972 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:10,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088561062] [2021-12-19 19:16:10,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:10,973 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:10,973 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:10,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:10,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:10,974 INFO L87 Difference]: Start difference. First operand 43470 states and 62180 transitions. cyclomatic complexity: 18718 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:11,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:11,572 INFO L93 Difference]: Finished difference Result 100577 states and 143045 transitions. [2021-12-19 19:16:11,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:11,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100577 states and 143045 transitions. [2021-12-19 19:16:12,108 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 100140 [2021-12-19 19:16:12,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100577 states to 100577 states and 143045 transitions. [2021-12-19 19:16:12,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100577 [2021-12-19 19:16:12,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100577 [2021-12-19 19:16:12,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100577 states and 143045 transitions. [2021-12-19 19:16:12,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:12,722 INFO L681 BuchiCegarLoop]: Abstraction has 100577 states and 143045 transitions. [2021-12-19 19:16:12,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100577 states and 143045 transitions. [2021-12-19 19:16:13,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100577 to 81925. [2021-12-19 19:16:13,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81925 states, 81925 states have (on average 1.4259993896856882) internal successors, (116825), 81924 states have internal predecessors, (116825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:13,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81925 states to 81925 states and 116825 transitions. [2021-12-19 19:16:13,900 INFO L704 BuchiCegarLoop]: Abstraction has 81925 states and 116825 transitions. [2021-12-19 19:16:13,900 INFO L587 BuchiCegarLoop]: Abstraction has 81925 states and 116825 transitions. [2021-12-19 19:16:13,900 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:16:13,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81925 states and 116825 transitions. [2021-12-19 19:16:14,238 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 81712 [2021-12-19 19:16:14,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:14,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:14,242 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:14,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:14,243 INFO L791 eck$LassoCheckResult]: Stem: 330575#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 330576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 330487#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 330488#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 330321#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 330322#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 329891#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 329892#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 329971#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 330805#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 329863#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 329864#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 330288#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 330309#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 329977#L866 assume !(0 == ~M_E~0); 329978#L866-2 assume !(0 == ~T1_E~0); 330521#L871-1 assume !(0 == ~T2_E~0); 330522#L876-1 assume !(0 == ~T3_E~0); 330892#L881-1 assume !(0 == ~T4_E~0); 330535#L886-1 assume !(0 == ~T5_E~0); 330277#L891-1 assume !(0 == ~T6_E~0); 330278#L896-1 assume !(0 == ~T7_E~0); 330524#L901-1 assume !(0 == ~T8_E~0); 330549#L906-1 assume !(0 == ~E_M~0); 330550#L911-1 assume !(0 == ~E_1~0); 330319#L916-1 assume !(0 == ~E_2~0); 330320#L921-1 assume !(0 == ~E_3~0); 330669#L926-1 assume !(0 == ~E_4~0); 330822#L931-1 assume !(0 == ~E_5~0); 330907#L936-1 assume !(0 == ~E_6~0); 330928#L941-1 assume !(0 == ~E_7~0); 330326#L946-1 assume !(0 == ~E_8~0); 330327#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330857#L430 assume !(1 == ~m_pc~0); 330184#L430-2 is_master_triggered_~__retres1~0#1 := 0; 330773#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 330969#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330452#L1073 assume !(0 != activate_threads_~tmp~1#1); 330453#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 330647#L449 assume !(1 == ~t1_pc~0); 329980#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 329981#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 329758#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 329759#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 330563#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 330387#L468 assume !(1 == ~t2_pc~0); 329785#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 329784#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 330285#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330189#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 329803#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 329804#L487 assume !(1 == ~t3_pc~0); 329915#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 329895#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 329896#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 330633#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 330251#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 330252#L506 assume !(1 == ~t4_pc~0); 330380#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 330433#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 330836#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 330837#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 330377#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 330197#L525 assume !(1 == ~t5_pc~0); 329840#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 329841#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 330329#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 330330#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 330039#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 330040#L544 assume !(1 == ~t6_pc~0); 330198#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 330199#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 330583#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 329825#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 329826#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 330791#L563 assume !(1 == ~t7_pc~0); 330580#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 329851#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 329852#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 330284#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 329984#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 329985#L582 assume !(1 == ~t8_pc~0); 330586#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 330883#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 330884#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 330240#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 330131#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 330132#L964 assume !(1 == ~M_E~0); 330650#L964-2 assume !(1 == ~T1_E~0); 371119#L969-1 assume !(1 == ~T2_E~0); 371118#L974-1 assume !(1 == ~T3_E~0); 371117#L979-1 assume !(1 == ~T4_E~0); 371116#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 330204#L989-1 assume !(1 == ~T6_E~0); 330205#L994-1 assume !(1 == ~T7_E~0); 330087#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 330088#L1004-1 assume !(1 == ~E_M~0); 329827#L1009-1 assume !(1 == ~E_1~0); 329828#L1014-1 assume !(1 == ~E_2~0); 330636#L1019-1 assume !(1 == ~E_3~0); 330637#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 330001#L1029-1 assume !(1 == ~E_5~0); 330002#L1034-1 assume !(1 == ~E_6~0); 330962#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 330963#L1044-1 assume !(1 == ~E_8~0); 330296#L1049-1 assume { :end_inline_reset_delta_events } true; 330297#L1315-2 [2021-12-19 19:16:14,243 INFO L793 eck$LassoCheckResult]: Loop: 330297#L1315-2 assume !false; 401206#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 330101#L841 assume !false; 330102#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 330034#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 330035#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 329875#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 329796#L724 assume !(0 != eval_~tmp~0#1); 329798#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 330703#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 329807#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 329808#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 330106#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 330107#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 330121#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 330122#L886-3 assume !(0 == ~T5_E~0); 330354#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 330355#L896-3 assume !(0 == ~T7_E~0); 330219#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 330220#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 330357#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 330597#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 330153#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 330154#L926-3 assume !(0 == ~E_4~0); 330577#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 330226#L936-3 assume !(0 == ~E_6~0); 330227#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 330372#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 330108#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330109#L430-30 assume 1 == ~m_pc~0; 330136#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 330137#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 410910#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 410907#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 330617#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 330627#L449-30 assume !(1 == ~t1_pc~0); 330628#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 329821#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 329822#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 330203#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 329904#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329905#L468-30 assume 1 == ~t2_pc~0; 329996#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 329997#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 330684#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330345#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 330346#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 330856#L487-30 assume !(1 == ~t3_pc~0); 407348#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 407186#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 407184#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 407182#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 407180#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 407178#L506-30 assume !(1 == ~t4_pc~0); 407174#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 407170#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 407168#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 407166#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 407164#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406019#L525-30 assume !(1 == ~t5_pc~0); 406016#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 406014#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 406012#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 406010#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 406008#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 406006#L544-30 assume !(1 == ~t6_pc~0); 406004#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 406002#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406001#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 406000#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 405999#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 330758#L563-30 assume !(1 == ~t7_pc~0); 330083#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 329941#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 329942#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 330286#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 330287#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 330734#L582-30 assume !(1 == ~t8_pc~0); 330020#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 330021#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 330274#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 330789#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 330931#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 329832#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 329833#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 329965#L969-3 assume !(1 == ~T2_E~0); 329956#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 329957#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 330390#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 330391#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 330004#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 330005#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 330560#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 329878#L1009-3 assume !(1 == ~E_1~0); 329879#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 330368#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 330369#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 330349#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 330316#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 330317#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 330635#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 329994#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 329995#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 330130#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 330497#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 330030#L1334 assume !(0 == start_simulation_~tmp~3#1); 330032#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 401381#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 401371#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 401369#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 401367#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 401365#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 401363#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 401362#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 330297#L1315-2 [2021-12-19 19:16:14,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:14,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2021-12-19 19:16:14,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:14,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291577349] [2021-12-19 19:16:14,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:14,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:14,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:14,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:14,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:14,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291577349] [2021-12-19 19:16:14,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291577349] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:14,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:14,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:14,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115313646] [2021-12-19 19:16:14,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:14,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:14,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:14,272 INFO L85 PathProgramCache]: Analyzing trace with hash 396228024, now seen corresponding path program 1 times [2021-12-19 19:16:14,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:14,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769696467] [2021-12-19 19:16:14,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:14,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:14,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:14,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:14,293 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:14,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769696467] [2021-12-19 19:16:14,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769696467] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:14,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:14,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:14,294 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694744777] [2021-12-19 19:16:14,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:14,294 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:14,295 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:14,295 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:14,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:14,295 INFO L87 Difference]: Start difference. First operand 81925 states and 116825 transitions. cyclomatic complexity: 34908 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:14,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:14,688 INFO L93 Difference]: Finished difference Result 62646 states and 89131 transitions. [2021-12-19 19:16:14,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:14,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62646 states and 89131 transitions. [2021-12-19 19:16:14,919 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 62480 [2021-12-19 19:16:15,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62646 states to 62646 states and 89131 transitions. [2021-12-19 19:16:15,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62646 [2021-12-19 19:16:15,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62646 [2021-12-19 19:16:15,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62646 states and 89131 transitions. [2021-12-19 19:16:15,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:15,159 INFO L681 BuchiCegarLoop]: Abstraction has 62646 states and 89131 transitions. [2021-12-19 19:16:15,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62646 states and 89131 transitions. [2021-12-19 19:16:15,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62646 to 43393. [2021-12-19 19:16:15,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43393 states, 43393 states have (on average 1.422948401815961) internal successors, (61746), 43392 states have internal predecessors, (61746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:15,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43393 states to 43393 states and 61746 transitions. [2021-12-19 19:16:15,837 INFO L704 BuchiCegarLoop]: Abstraction has 43393 states and 61746 transitions. [2021-12-19 19:16:15,837 INFO L587 BuchiCegarLoop]: Abstraction has 43393 states and 61746 transitions. [2021-12-19 19:16:15,837 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:16:15,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43393 states and 61746 transitions. [2021-12-19 19:16:15,967 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:15,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:15,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:15,968 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:15,969 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:15,969 INFO L791 eck$LassoCheckResult]: Stem: 475150#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 475151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 475068#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 475069#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 474906#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 474907#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 474471#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 474472#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 474552#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 475379#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 474443#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 474444#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 474869#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 474895#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 474558#L866 assume !(0 == ~M_E~0); 474559#L866-2 assume !(0 == ~T1_E~0); 475100#L871-1 assume !(0 == ~T2_E~0); 475101#L876-1 assume !(0 == ~T3_E~0); 475463#L881-1 assume !(0 == ~T4_E~0); 475111#L886-1 assume !(0 == ~T5_E~0); 474860#L891-1 assume !(0 == ~T6_E~0); 474861#L896-1 assume !(0 == ~T7_E~0); 475103#L901-1 assume !(0 == ~T8_E~0); 475125#L906-1 assume !(0 == ~E_M~0); 475126#L911-1 assume !(0 == ~E_1~0); 474904#L916-1 assume !(0 == ~E_2~0); 474905#L921-1 assume !(0 == ~E_3~0); 475240#L926-1 assume !(0 == ~E_4~0); 475398#L931-1 assume !(0 == ~E_5~0); 475474#L936-1 assume !(0 == ~E_6~0); 475492#L941-1 assume !(0 == ~E_7~0); 474910#L946-1 assume !(0 == ~E_8~0); 474911#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475428#L430 assume !(1 == ~m_pc~0); 474760#L430-2 is_master_triggered_~__retres1~0#1 := 0; 474380#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 474381#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 475024#L1073 assume !(0 != activate_threads_~tmp~1#1); 475035#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475221#L449 assume !(1 == ~t1_pc~0); 474561#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 474562#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 474339#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 474340#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 475139#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 474973#L468 assume !(1 == ~t2_pc~0); 474364#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 474363#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 474868#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 474768#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 474382#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 474383#L487 assume !(1 == ~t3_pc~0); 474495#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 474475#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 474476#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475209#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 474832#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 474833#L506 assume !(1 == ~t4_pc~0); 474968#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 475020#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475412#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475413#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 474960#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474779#L525 assume !(1 == ~t5_pc~0); 474421#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 474422#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474914#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 474915#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 474623#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 474624#L544 assume !(1 == ~t6_pc~0); 474780#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 474781#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475159#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 474406#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 474407#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475362#L563 assume !(1 == ~t7_pc~0); 475155#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 474432#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 474433#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 474862#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 474563#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 474564#L582 assume !(1 == ~t8_pc~0); 475160#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 475450#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475451#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 474820#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 474711#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 474712#L964 assume !(1 == ~M_E~0); 475223#L964-2 assume !(1 == ~T1_E~0); 474625#L969-1 assume !(1 == ~T2_E~0); 474626#L974-1 assume !(1 == ~T3_E~0); 475256#L979-1 assume !(1 == ~T4_E~0); 475257#L984-1 assume !(1 == ~T5_E~0); 474786#L989-1 assume !(1 == ~T6_E~0); 474787#L994-1 assume !(1 == ~T7_E~0); 474664#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 474665#L1004-1 assume !(1 == ~E_M~0); 474408#L1009-1 assume !(1 == ~E_1~0); 474409#L1014-1 assume !(1 == ~E_2~0); 474653#L1019-1 assume !(1 == ~E_3~0); 475213#L1024-1 assume !(1 == ~E_4~0); 474582#L1029-1 assume !(1 == ~E_5~0); 474583#L1034-1 assume !(1 == ~E_6~0); 474680#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 475417#L1044-1 assume !(1 == ~E_8~0); 474877#L1049-1 assume { :end_inline_reset_delta_events } true; 474878#L1315-2 [2021-12-19 19:16:15,969 INFO L793 eck$LassoCheckResult]: Loop: 474878#L1315-2 assume !false; 508023#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 508021#L841 assume !false; 508019#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 508008#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 508002#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 508000#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 507998#L724 assume !(0 != eval_~tmp~0#1); 507999#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 514591#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 514587#L866-3 assume !(0 == ~M_E~0); 514572#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 514543#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 514521#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 514515#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 514510#L886-3 assume !(0 == ~T5_E~0); 514503#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 514498#L896-3 assume !(0 == ~T7_E~0); 514493#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 514487#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 514484#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 514480#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 514475#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 514469#L926-3 assume !(0 == ~E_4~0); 514460#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 514456#L936-3 assume !(0 == ~E_6~0); 514453#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 514450#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 514446#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514440#L430-30 assume !(1 == ~m_pc~0); 514434#L430-32 is_master_triggered_~__retres1~0#1 := 0; 514427#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514421#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 514415#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 514408#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 514403#L449-30 assume !(1 == ~t1_pc~0); 514398#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 514393#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514388#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 514384#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 514383#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 514382#L468-30 assume !(1 == ~t2_pc~0); 514340#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 514330#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 514322#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 514314#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 514306#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 474773#L487-30 assume !(1 == ~t3_pc~0); 474774#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 515304#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515298#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515292#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 515288#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 515283#L506-30 assume !(1 == ~t4_pc~0); 515278#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 515273#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 515269#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 515266#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 515263#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475524#L525-30 assume !(1 == ~t5_pc~0); 475457#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 475458#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474466#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 474467#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 474778#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 474532#L544-30 assume !(1 == ~t6_pc~0); 474349#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 474348#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475477#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475367#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 475368#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475330#L563-30 assume !(1 == ~t7_pc~0); 474666#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 474520#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 474521#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 474870#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 474871#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475308#L582-30 assume !(1 == ~t8_pc~0); 474604#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 474605#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 515333#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 515330#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 515326#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 474413#L964-3 assume !(1 == ~M_E~0); 474414#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 474746#L969-3 assume !(1 == ~T2_E~0); 474747#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475502#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 474978#L984-3 assume !(1 == ~T5_E~0); 474979#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 474585#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 474586#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 475137#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 474458#L1009-3 assume !(1 == ~E_1~0); 474459#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475210#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 475522#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 475523#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 515251#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 515246#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 515239#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 515236#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 475107#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 474710#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 475078#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 475079#L1334 assume !(0 == start_simulation_~tmp~3#1); 495176#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 508087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 508078#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 508076#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 508074#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 508073#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 508072#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 508071#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 474878#L1315-2 [2021-12-19 19:16:15,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:15,970 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2021-12-19 19:16:15,970 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:15,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657720171] [2021-12-19 19:16:15,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:15,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:15,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:15,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:15,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:15,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657720171] [2021-12-19 19:16:15,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657720171] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:15,998 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:15,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:15,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489220531] [2021-12-19 19:16:15,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:15,999 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:15,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:15,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1888842438, now seen corresponding path program 1 times [2021-12-19 19:16:15,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:15,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334178617] [2021-12-19 19:16:16,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:16,000 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:16,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:16,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:16,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:16,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334178617] [2021-12-19 19:16:16,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334178617] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:16,022 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:16,022 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:16,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304717995] [2021-12-19 19:16:16,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:16,023 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:16,023 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:16,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:16,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:16,024 INFO L87 Difference]: Start difference. First operand 43393 states and 61746 transitions. cyclomatic complexity: 18357 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:16,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:16,259 INFO L93 Difference]: Finished difference Result 69067 states and 98228 transitions. [2021-12-19 19:16:16,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:16,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69067 states and 98228 transitions. [2021-12-19 19:16:16,797 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 68816 [2021-12-19 19:16:16,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69067 states to 69067 states and 98228 transitions. [2021-12-19 19:16:16,958 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69067 [2021-12-19 19:16:17,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69067 [2021-12-19 19:16:17,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69067 states and 98228 transitions. [2021-12-19 19:16:17,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:17,042 INFO L681 BuchiCegarLoop]: Abstraction has 69067 states and 98228 transitions. [2021-12-19 19:16:17,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69067 states and 98228 transitions. [2021-12-19 19:16:17,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69067 to 48753. [2021-12-19 19:16:17,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48753 states, 48753 states have (on average 1.4243431173466248) internal successors, (69441), 48752 states have internal predecessors, (69441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:17,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48753 states to 48753 states and 69441 transitions. [2021-12-19 19:16:17,719 INFO L704 BuchiCegarLoop]: Abstraction has 48753 states and 69441 transitions. [2021-12-19 19:16:17,720 INFO L587 BuchiCegarLoop]: Abstraction has 48753 states and 69441 transitions. [2021-12-19 19:16:17,720 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:16:17,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48753 states and 69441 transitions. [2021-12-19 19:16:17,818 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48528 [2021-12-19 19:16:17,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:17,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:17,820 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:17,820 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:17,820 INFO L791 eck$LassoCheckResult]: Stem: 587643#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 587644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 587558#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 587559#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 587371#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 587372#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 586942#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 586943#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 587021#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 587871#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 586914#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 586915#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 587336#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 587360#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 587027#L866 assume !(0 == ~M_E~0); 587028#L866-2 assume !(0 == ~T1_E~0); 587589#L871-1 assume !(0 == ~T2_E~0); 587590#L876-1 assume !(0 == ~T3_E~0); 587960#L881-1 assume !(0 == ~T4_E~0); 587602#L886-1 assume !(0 == ~T5_E~0); 587323#L891-1 assume !(0 == ~T6_E~0); 587324#L896-1 assume !(0 == ~T7_E~0); 587592#L901-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 587732#L906-1 assume !(0 == ~E_M~0); 587969#L911-1 assume !(0 == ~E_1~0); 587970#L916-1 assume !(0 == ~E_2~0); 588077#L921-1 assume !(0 == ~E_3~0); 587885#L926-1 assume !(0 == ~E_4~0); 587886#L931-1 assume !(0 == ~E_5~0); 587995#L936-1 assume !(0 == ~E_6~0); 587996#L941-1 assume !(0 == ~E_7~0); 587376#L946-1 assume !(0 == ~E_8~0); 587377#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 588000#L430 assume !(1 == ~m_pc~0); 588001#L430-2 is_master_triggered_~__retres1~0#1 := 0; 588072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 588073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 587519#L1073 assume !(0 != activate_threads_~tmp~1#1); 587520#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 587713#L449 assume !(1 == ~t1_pc~0); 587714#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 587942#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 587943#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 588005#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 587630#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 587631#L468 assume !(1 == ~t2_pc~0); 586836#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 586835#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 587332#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 587333#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 588075#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 587998#L487 assume !(1 == ~t3_pc~0); 587999#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 586946#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 586947#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 587790#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 587297#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 587298#L506 assume !(1 == ~t4_pc~0); 587497#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 587498#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 587898#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 587899#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 587434#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 587435#L525 assume !(1 == ~t5_pc~0); 586891#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 586892#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 587379#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 587380#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 587088#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 587089#L544 assume !(1 == ~t6_pc~0); 587245#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 587246#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 587652#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 586876#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 586877#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 587857#L563 assume !(1 == ~t7_pc~0); 587648#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 587649#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 587484#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 587485#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 587034#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 587035#L582 assume !(1 == ~t8_pc~0); 587655#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 588063#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 588045#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 587287#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 587176#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 587177#L964 assume !(1 == ~M_E~0); 588060#L964-2 assume !(1 == ~T1_E~0); 588059#L969-1 assume !(1 == ~T2_E~0); 588058#L974-1 assume !(1 == ~T3_E~0); 588057#L979-1 assume !(1 == ~T4_E~0); 588056#L984-1 assume !(1 == ~T5_E~0); 588055#L989-1 assume !(1 == ~T6_E~0); 588054#L994-1 assume !(1 == ~T7_E~0); 588053#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 587134#L1004-1 assume !(1 == ~E_M~0); 586878#L1009-1 assume !(1 == ~E_1~0); 586879#L1014-1 assume !(1 == ~E_2~0); 587122#L1019-1 assume !(1 == ~E_3~0); 587704#L1024-1 assume !(1 == ~E_4~0); 587051#L1029-1 assume !(1 == ~E_5~0); 587052#L1034-1 assume !(1 == ~E_6~0); 587146#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 587905#L1044-1 assume !(1 == ~E_8~0); 587344#L1049-1 assume { :end_inline_reset_delta_events } true; 587345#L1315-2 [2021-12-19 19:16:17,821 INFO L793 eck$LassoCheckResult]: Loop: 587345#L1315-2 assume !false; 620760#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 620752#L841 assume !false; 620749#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 620724#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 620713#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 620706#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 620697#L724 assume !(0 != eval_~tmp~0#1); 620698#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 627042#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 627040#L866-3 assume !(0 == ~M_E~0); 627011#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 627003#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 626994#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 626985#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 626958#L886-3 assume !(0 == ~T5_E~0); 626949#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 626941#L896-3 assume !(0 == ~T7_E~0); 626933#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 626932#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 626930#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 626928#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 626926#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 626924#L926-3 assume !(0 == ~E_4~0); 626922#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 626920#L936-3 assume !(0 == ~E_6~0); 626918#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 626916#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 626914#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 626885#L430-30 assume !(1 == ~m_pc~0); 626887#L430-32 is_master_triggered_~__retres1~0#1 := 0; 626867#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 626868#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 626847#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 626846#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 626809#L449-30 assume !(1 == ~t1_pc~0); 626810#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 626793#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 626794#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 626752#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 626753#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 626732#L468-30 assume 1 == ~t2_pc~0; 626733#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 626727#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 626728#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 626723#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 626724#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 616433#L487-30 assume !(1 == ~t3_pc~0); 616434#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 616426#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 616427#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 616420#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 616421#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 616413#L506-30 assume 1 == ~t4_pc~0; 616415#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 616406#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 616407#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 616399#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 616400#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 616394#L525-30 assume !(1 == ~t5_pc~0); 613691#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 616387#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 616388#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 616381#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 616382#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 616374#L544-30 assume 1 == ~t6_pc~0; 616376#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 616367#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 616368#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 616363#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 616364#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 616356#L563-30 assume !(1 == ~t7_pc~0); 616355#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 616354#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 616353#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 616352#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 616351#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 616350#L582-30 assume !(1 == ~t8_pc~0); 611354#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 616349#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 616348#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 616347#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 616346#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 616345#L964-3 assume !(1 == ~M_E~0); 616344#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 616343#L969-3 assume !(1 == ~T2_E~0); 616342#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 616341#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 616340#L984-3 assume !(1 == ~T5_E~0); 616339#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 616338#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 616336#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 616333#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 616330#L1009-3 assume !(1 == ~E_1~0); 616328#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 616326#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 616324#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 616307#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 616298#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 616291#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 616250#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 616243#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 615920#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 615889#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 615876#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 615290#L1334 assume !(0 == start_simulation_~tmp~3#1); 615291#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 620847#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 620837#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 620835#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 620833#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 620804#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 620792#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 620783#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 587345#L1315-2 [2021-12-19 19:16:17,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:17,821 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2021-12-19 19:16:17,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:17,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949787320] [2021-12-19 19:16:17,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:17,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:17,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:17,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:17,843 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:17,843 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949787320] [2021-12-19 19:16:17,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949787320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:17,843 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:17,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:17,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888517831] [2021-12-19 19:16:17,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:17,844 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:17,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:17,844 INFO L85 PathProgramCache]: Analyzing trace with hash 2072368631, now seen corresponding path program 1 times [2021-12-19 19:16:17,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:17,845 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710967773] [2021-12-19 19:16:17,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:17,845 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:17,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:17,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:17,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:17,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710967773] [2021-12-19 19:16:17,866 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [710967773] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:17,866 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:17,866 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:17,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133847755] [2021-12-19 19:16:17,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:17,867 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:17,867 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:17,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:17,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:17,868 INFO L87 Difference]: Start difference. First operand 48753 states and 69441 transitions. cyclomatic complexity: 20692 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:18,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:18,022 INFO L93 Difference]: Finished difference Result 43393 states and 61584 transitions. [2021-12-19 19:16:18,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:18,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43393 states and 61584 transitions. [2021-12-19 19:16:18,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:18,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43393 states to 43393 states and 61584 transitions. [2021-12-19 19:16:18,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43393 [2021-12-19 19:16:18,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43393 [2021-12-19 19:16:18,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43393 states and 61584 transitions. [2021-12-19 19:16:18,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:18,304 INFO L681 BuchiCegarLoop]: Abstraction has 43393 states and 61584 transitions. [2021-12-19 19:16:18,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43393 states and 61584 transitions. [2021-12-19 19:16:18,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43393 to 43393. [2021-12-19 19:16:18,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43393 states, 43393 states have (on average 1.4192150807733965) internal successors, (61584), 43392 states have internal predecessors, (61584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:18,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43393 states to 43393 states and 61584 transitions. [2021-12-19 19:16:18,934 INFO L704 BuchiCegarLoop]: Abstraction has 43393 states and 61584 transitions. [2021-12-19 19:16:18,934 INFO L587 BuchiCegarLoop]: Abstraction has 43393 states and 61584 transitions. [2021-12-19 19:16:18,934 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:16:18,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43393 states and 61584 transitions. [2021-12-19 19:16:19,046 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:19,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:19,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:19,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:19,048 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:19,048 INFO L791 eck$LassoCheckResult]: Stem: 679782#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 679783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 679696#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 679697#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 679527#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 679528#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 679098#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 679099#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 679177#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 679990#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 679070#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 679071#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 679492#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 679516#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 679183#L866 assume !(0 == ~M_E~0); 679184#L866-2 assume !(0 == ~T1_E~0); 679725#L871-1 assume !(0 == ~T2_E~0); 679726#L876-1 assume !(0 == ~T3_E~0); 680070#L881-1 assume !(0 == ~T4_E~0); 679738#L886-1 assume !(0 == ~T5_E~0); 679481#L891-1 assume !(0 == ~T6_E~0); 679482#L896-1 assume !(0 == ~T7_E~0); 679731#L901-1 assume !(0 == ~T8_E~0); 679753#L906-1 assume !(0 == ~E_M~0); 679754#L911-1 assume !(0 == ~E_1~0); 679525#L916-1 assume !(0 == ~E_2~0); 679526#L921-1 assume !(0 == ~E_3~0); 679866#L926-1 assume !(0 == ~E_4~0); 680007#L931-1 assume !(0 == ~E_5~0); 680080#L936-1 assume !(0 == ~E_6~0); 680094#L941-1 assume !(0 == ~E_7~0); 679532#L946-1 assume !(0 == ~E_8~0); 679533#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 680038#L430 assume !(1 == ~m_pc~0); 679389#L430-2 is_master_triggered_~__retres1~0#1 := 0; 679960#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 680133#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 679659#L1073 assume !(0 != activate_threads_~tmp~1#1); 679660#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 679850#L449 assume !(1 == ~t1_pc~0); 679186#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 679187#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 678965#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 678966#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 679770#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 679592#L468 assume !(1 == ~t2_pc~0); 678992#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 678991#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679489#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 679394#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 679010#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 679011#L487 assume !(1 == ~t3_pc~0); 679122#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 679102#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 679103#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 679836#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 679456#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 679457#L506 assume !(1 == ~t4_pc~0); 679585#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 679639#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 680021#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 680022#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 679583#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 679403#L525 assume !(1 == ~t5_pc~0); 679047#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 679048#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 679535#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 679536#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 679248#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 679249#L544 assume !(1 == ~t6_pc~0); 679404#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 679405#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 679791#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 679032#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 679033#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 679977#L563 assume !(1 == ~t7_pc~0); 679787#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 679058#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 679059#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 679488#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 679190#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 679191#L582 assume !(1 == ~t8_pc~0); 679794#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 680061#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 680062#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 679444#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 679337#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 679338#L964 assume !(1 == ~M_E~0); 679853#L964-2 assume !(1 == ~T1_E~0); 679250#L969-1 assume !(1 == ~T2_E~0); 679251#L974-1 assume !(1 == ~T3_E~0); 679878#L979-1 assume !(1 == ~T4_E~0); 679879#L984-1 assume !(1 == ~T5_E~0); 679410#L989-1 assume !(1 == ~T6_E~0); 679411#L994-1 assume !(1 == ~T7_E~0); 679294#L999-1 assume !(1 == ~T8_E~0); 679295#L1004-1 assume !(1 == ~E_M~0); 679034#L1009-1 assume !(1 == ~E_1~0); 679035#L1014-1 assume !(1 == ~E_2~0); 679282#L1019-1 assume !(1 == ~E_3~0); 679842#L1024-1 assume !(1 == ~E_4~0); 679207#L1029-1 assume !(1 == ~E_5~0); 679208#L1034-1 assume !(1 == ~E_6~0); 679306#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 680027#L1044-1 assume !(1 == ~E_8~0); 679500#L1049-1 assume { :end_inline_reset_delta_events } true; 679501#L1315-2 [2021-12-19 19:16:19,048 INFO L793 eck$LassoCheckResult]: Loop: 679501#L1315-2 assume !false; 707483#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 707482#L841 assume !false; 707481#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 707476#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 707471#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 707470#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 707469#L724 assume !(0 != eval_~tmp~0#1); 679896#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 679897#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 679014#L866-3 assume !(0 == ~M_E~0); 679015#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 679311#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 679312#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 679326#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 679327#L886-3 assume !(0 == ~T5_E~0); 679561#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 679562#L896-3 assume !(0 == ~T7_E~0); 679423#L901-3 assume !(0 == ~T8_E~0); 679424#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 679563#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 679803#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 679359#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 679360#L926-3 assume !(0 == ~E_4~0); 679784#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 679431#L936-3 assume !(0 == ~E_6~0); 679432#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 679578#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 679313#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 679314#L430-30 assume 1 == ~m_pc~0; 679339#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 679340#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 721376#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 721374#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 679823#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 679830#L449-30 assume !(1 == ~t1_pc~0); 679831#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 679030#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 679031#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 679409#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 679111#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 679112#L468-30 assume !(1 == ~t2_pc~0); 719032#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 718934#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 718933#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 718931#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 718929#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 715514#L487-30 assume !(1 == ~t3_pc~0); 714997#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 715513#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 715512#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 715511#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 715510#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 715509#L506-30 assume 1 == ~t4_pc~0; 715506#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 715505#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 715504#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 715503#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 715499#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 715497#L525-30 assume !(1 == ~t5_pc~0); 707841#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 715494#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 715491#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 715489#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 715487#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 715485#L544-30 assume 1 == ~t6_pc~0; 715482#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 715480#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 715478#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 715476#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 715474#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 709032#L563-30 assume !(1 == ~t7_pc~0); 709022#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 708986#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 707767#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 707766#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 707765#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 707763#L582-30 assume !(1 == ~t8_pc~0); 705953#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 707760#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 707758#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 707756#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 707754#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707752#L964-3 assume !(1 == ~M_E~0); 707751#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 707749#L969-3 assume !(1 == ~T2_E~0); 707747#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 707745#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 707743#L984-3 assume !(1 == ~T5_E~0); 707741#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 707739#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 707737#L999-3 assume !(1 == ~T8_E~0); 707735#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 707733#L1009-3 assume !(1 == ~E_1~0); 707731#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 707729#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 707727#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 707725#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 707723#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 707721#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 707719#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 707717#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 707637#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 707633#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 707604#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 707574#L1334 assume !(0 == start_simulation_~tmp~3#1); 707559#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 707524#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 707515#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 707512#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 707511#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 707504#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 707500#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 707498#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 679501#L1315-2 [2021-12-19 19:16:19,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:19,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2021-12-19 19:16:19,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:19,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48793502] [2021-12-19 19:16:19,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:19,050 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:19,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:19,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:19,082 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:19,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48793502] [2021-12-19 19:16:19,083 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [48793502] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:19,083 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:19,083 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:19,083 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109771710] [2021-12-19 19:16:19,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:19,085 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:19,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:19,086 INFO L85 PathProgramCache]: Analyzing trace with hash -677755467, now seen corresponding path program 1 times [2021-12-19 19:16:19,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:19,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206388069] [2021-12-19 19:16:19,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:19,086 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:19,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:19,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:19,111 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:19,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206388069] [2021-12-19 19:16:19,111 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206388069] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:19,111 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:19,111 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:19,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013725399] [2021-12-19 19:16:19,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:19,112 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:19,112 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:19,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:19,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:19,113 INFO L87 Difference]: Start difference. First operand 43393 states and 61584 transitions. cyclomatic complexity: 18195 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:19,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:19,373 INFO L93 Difference]: Finished difference Result 67331 states and 95298 transitions. [2021-12-19 19:16:19,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:19,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67331 states and 95298 transitions. [2021-12-19 19:16:19,626 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 67056 [2021-12-19 19:16:20,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67331 states to 67331 states and 95298 transitions. [2021-12-19 19:16:20,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67331 [2021-12-19 19:16:20,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67331 [2021-12-19 19:16:20,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67331 states and 95298 transitions. [2021-12-19 19:16:20,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:20,199 INFO L681 BuchiCegarLoop]: Abstraction has 67331 states and 95298 transitions. [2021-12-19 19:16:20,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67331 states and 95298 transitions. [2021-12-19 19:16:20,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67331 to 48721. [2021-12-19 19:16:20,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48721 states, 48721 states have (on average 1.416370764146877) internal successors, (69007), 48720 states have internal predecessors, (69007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:20,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48721 states to 48721 states and 69007 transitions. [2021-12-19 19:16:20,613 INFO L704 BuchiCegarLoop]: Abstraction has 48721 states and 69007 transitions. [2021-12-19 19:16:20,613 INFO L587 BuchiCegarLoop]: Abstraction has 48721 states and 69007 transitions. [2021-12-19 19:16:20,613 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:16:20,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48721 states and 69007 transitions. [2021-12-19 19:16:20,729 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48496 [2021-12-19 19:16:20,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:20,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:20,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:20,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:20,731 INFO L791 eck$LassoCheckResult]: Stem: 790525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 790526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 790439#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 790440#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 790266#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 790267#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 789832#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 789833#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 789910#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 790744#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 789804#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 789805#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 790231#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 790255#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 789916#L866 assume !(0 == ~M_E~0); 789917#L866-2 assume !(0 == ~T1_E~0); 790471#L871-1 assume !(0 == ~T2_E~0); 790472#L876-1 assume !(0 == ~T3_E~0); 790837#L881-1 assume !(0 == ~T4_E~0); 790483#L886-1 assume !(0 == ~T5_E~0); 790218#L891-1 assume !(0 == ~T6_E~0); 790219#L896-1 assume !(0 == ~T7_E~0); 790474#L901-1 assume !(0 == ~T8_E~0); 790498#L906-1 assume !(0 == ~E_M~0); 790499#L911-1 assume !(0 == ~E_1~0); 790264#L916-1 assume !(0 == ~E_2~0); 790265#L921-1 assume !(0 == ~E_3~0); 790610#L926-1 assume !(0 == ~E_4~0); 790759#L931-1 assume !(0 == ~E_5~0); 790846#L936-1 assume !(0 == ~E_6~0); 790862#L941-1 assume 0 == ~E_7~0;~E_7~0 := 1; 790916#L946-1 assume !(0 == ~E_8~0); 790792#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 790793#L430 assume !(1 == ~m_pc~0); 790117#L430-2 is_master_triggered_~__retres1~0#1 := 0; 790711#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 790392#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 790393#L1073 assume !(0 != activate_threads_~tmp~1#1); 790826#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 790827#L449 assume !(1 == ~t1_pc~0); 789919#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 789920#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 789699#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 789700#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 790512#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790513#L468 assume !(1 == ~t2_pc~0); 789726#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 789725#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 790227#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 790228#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 789742#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 789743#L487 assume !(1 == ~t3_pc~0); 789855#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 789856#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 790577#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 790578#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 790938#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 790330#L506 assume !(1 == ~t4_pc~0); 790331#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 790937#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 790773#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 790774#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 790325#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 790326#L525 assume !(1 == ~t5_pc~0); 789781#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 789782#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 790274#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 790275#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 789980#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 789981#L544 assume !(1 == ~t6_pc~0); 790138#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 790139#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 790535#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 790923#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 790805#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 790806#L563 assume !(1 == ~t7_pc~0); 790934#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 789792#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 789793#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 790220#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 790221#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 790933#L582 assume !(1 == ~t8_pc~0); 790881#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 790882#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 790932#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 790931#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 790069#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 790070#L964 assume !(1 == ~M_E~0); 790824#L964-2 assume !(1 == ~T1_E~0); 790825#L969-1 assume !(1 == ~T2_E~0); 790766#L974-1 assume !(1 == ~T3_E~0); 790767#L979-1 assume !(1 == ~T4_E~0); 790903#L984-1 assume !(1 == ~T5_E~0); 790904#L989-1 assume !(1 == ~T6_E~0); 790477#L994-1 assume !(1 == ~T7_E~0); 790478#L999-1 assume !(1 == ~T8_E~0); 790599#L1004-1 assume !(1 == ~E_M~0); 789768#L1009-1 assume !(1 == ~E_1~0); 789769#L1014-1 assume !(1 == ~E_2~0); 790581#L1019-1 assume !(1 == ~E_3~0); 790582#L1024-1 assume !(1 == ~E_4~0); 789940#L1029-1 assume !(1 == ~E_5~0); 789941#L1034-1 assume !(1 == ~E_6~0); 790924#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 790779#L1044-1 assume !(1 == ~E_8~0); 790237#L1049-1 assume { :end_inline_reset_delta_events } true; 790238#L1315-2 [2021-12-19 19:16:20,731 INFO L793 eck$LassoCheckResult]: Loop: 790238#L1315-2 assume !false; 832030#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 832029#L841 assume !false; 832028#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 831966#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 831785#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 831781#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 831774#L724 assume !(0 != eval_~tmp~0#1); 831766#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 831757#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 831749#L866-3 assume !(0 == ~M_E~0); 831741#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831734#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 831728#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 831719#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 831712#L886-3 assume !(0 == ~T5_E~0); 831705#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 831698#L896-3 assume !(0 == ~T7_E~0); 831691#L901-3 assume !(0 == ~T8_E~0); 831684#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 831677#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 831670#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 831662#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 831655#L926-3 assume !(0 == ~E_4~0); 831648#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 831641#L936-3 assume !(0 == ~E_6~0); 831610#L941-3 assume !(0 == ~E_7~0); 831611#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 835740#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 835739#L430-30 assume !(1 == ~m_pc~0); 835736#L430-32 is_master_triggered_~__retres1~0#1 := 0; 835734#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 835733#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 835731#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 835727#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 835725#L449-30 assume !(1 == ~t1_pc~0); 835723#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 835721#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 835719#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 835717#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 835716#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 835711#L468-30 assume 1 == ~t2_pc~0; 835712#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 835705#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 835703#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 835701#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 835699#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 835697#L487-30 assume !(1 == ~t3_pc~0); 835694#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 835692#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 835690#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835688#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 835686#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 835684#L506-30 assume 1 == ~t4_pc~0; 835681#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 835680#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 835678#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 835676#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 835674#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 831404#L525-30 assume !(1 == ~t5_pc~0); 831398#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 831397#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 831396#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 831395#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 831394#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 831393#L544-30 assume !(1 == ~t6_pc~0); 831392#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 831390#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 831389#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 831388#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 831387#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 831386#L563-30 assume !(1 == ~t7_pc~0); 817389#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 831375#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 831373#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 831371#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 831369#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 807574#L582-30 assume !(1 == ~t8_pc~0); 807572#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 807569#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 807566#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 807562#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 807560#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 807558#L964-3 assume !(1 == ~M_E~0); 807556#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 807553#L969-3 assume !(1 == ~T2_E~0); 807551#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 807549#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 807547#L984-3 assume !(1 == ~T5_E~0); 807545#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 807543#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 807541#L999-3 assume !(1 == ~T8_E~0); 807539#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 807535#L1009-3 assume !(1 == ~E_1~0); 807531#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 807528#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 807525#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 807522#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 807519#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 807518#L1039-3 assume !(1 == ~E_7~0); 807515#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 807513#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 807414#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 807410#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 807408#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 807058#L1334 assume !(0 == start_simulation_~tmp~3#1); 807059#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 832420#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 832055#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 832051#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 832049#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 832047#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 832046#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 832041#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 790238#L1315-2 [2021-12-19 19:16:20,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:20,732 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2021-12-19 19:16:20,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:20,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462905259] [2021-12-19 19:16:20,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:20,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:20,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:20,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:20,756 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:20,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462905259] [2021-12-19 19:16:20,756 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462905259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:20,756 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:20,756 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:20,757 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476459696] [2021-12-19 19:16:20,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:20,757 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:20,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:20,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1596154952, now seen corresponding path program 1 times [2021-12-19 19:16:20,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:20,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561453920] [2021-12-19 19:16:20,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:20,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:20,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:20,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:20,782 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:20,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561453920] [2021-12-19 19:16:20,782 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561453920] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:20,783 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:20,783 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:20,783 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037796838] [2021-12-19 19:16:20,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:20,783 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:20,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:20,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:20,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:20,784 INFO L87 Difference]: Start difference. First operand 48721 states and 69007 transitions. cyclomatic complexity: 20290 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:21,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:21,285 INFO L93 Difference]: Finished difference Result 61633 states and 86974 transitions. [2021-12-19 19:16:21,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:21,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61633 states and 86974 transitions. [2021-12-19 19:16:21,505 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 61440 [2021-12-19 19:16:21,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61633 states to 61633 states and 86974 transitions. [2021-12-19 19:16:21,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61633 [2021-12-19 19:16:21,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61633 [2021-12-19 19:16:21,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61633 states and 86974 transitions. [2021-12-19 19:16:21,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:21,699 INFO L681 BuchiCegarLoop]: Abstraction has 61633 states and 86974 transitions. [2021-12-19 19:16:21,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61633 states and 86974 transitions. [2021-12-19 19:16:21,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61633 to 43393. [2021-12-19 19:16:22,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43393 states, 43393 states have (on average 1.4099509137418478) internal successors, (61182), 43392 states have internal predecessors, (61182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:22,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43393 states to 43393 states and 61182 transitions. [2021-12-19 19:16:22,057 INFO L704 BuchiCegarLoop]: Abstraction has 43393 states and 61182 transitions. [2021-12-19 19:16:22,058 INFO L587 BuchiCegarLoop]: Abstraction has 43393 states and 61182 transitions. [2021-12-19 19:16:22,058 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:16:22,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43393 states and 61182 transitions. [2021-12-19 19:16:22,152 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:22,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:22,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:22,153 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:22,153 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:22,154 INFO L791 eck$LassoCheckResult]: Stem: 900884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 900885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 900794#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 900795#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 900627#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 900628#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 900198#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 900199#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 900275#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 901119#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 900169#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 900170#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 900590#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 900616#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 900281#L866 assume !(0 == ~M_E~0); 900282#L866-2 assume !(0 == ~T1_E~0); 900829#L871-1 assume !(0 == ~T2_E~0); 900830#L876-1 assume !(0 == ~T3_E~0); 901218#L881-1 assume !(0 == ~T4_E~0); 900842#L886-1 assume !(0 == ~T5_E~0); 900581#L891-1 assume !(0 == ~T6_E~0); 900582#L896-1 assume !(0 == ~T7_E~0); 900832#L901-1 assume !(0 == ~T8_E~0); 900858#L906-1 assume !(0 == ~E_M~0); 900859#L911-1 assume !(0 == ~E_1~0); 900625#L916-1 assume !(0 == ~E_2~0); 900626#L921-1 assume !(0 == ~E_3~0); 900984#L926-1 assume !(0 == ~E_4~0); 901137#L931-1 assume !(0 == ~E_5~0); 901233#L936-1 assume !(0 == ~E_6~0); 901254#L941-1 assume !(0 == ~E_7~0); 900631#L946-1 assume !(0 == ~E_8~0); 900632#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 901178#L430 assume !(1 == ~m_pc~0); 900484#L430-2 is_master_triggered_~__retres1~0#1 := 0; 900104#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 900105#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 900746#L1073 assume !(0 != activate_threads_~tmp~1#1); 900760#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 900964#L449 assume !(1 == ~t1_pc~0); 900284#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 900285#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 900063#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 900064#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 900872#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 900694#L468 assume !(1 == ~t2_pc~0); 900088#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 900087#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 900589#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 900492#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 900106#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 900107#L487 assume !(1 == ~t3_pc~0); 900221#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 900202#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 900203#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 900949#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 900557#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 900558#L506 assume !(1 == ~t4_pc~0); 900690#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 900741#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 901154#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 901155#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 900682#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 900504#L525 assume !(1 == ~t5_pc~0); 900145#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 900146#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 900636#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 900637#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 900346#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 900347#L544 assume !(1 == ~t6_pc~0); 900505#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 900506#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 900895#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 900130#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 900131#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 901106#L563 assume !(1 == ~t7_pc~0); 900889#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 900156#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 900157#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 900583#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 900286#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 900287#L582 assume !(1 == ~t8_pc~0); 900896#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 901210#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 901211#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 900544#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 900434#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 900435#L964 assume !(1 == ~M_E~0); 900966#L964-2 assume !(1 == ~T1_E~0); 900348#L969-1 assume !(1 == ~T2_E~0); 900349#L974-1 assume !(1 == ~T3_E~0); 900998#L979-1 assume !(1 == ~T4_E~0); 900999#L984-1 assume !(1 == ~T5_E~0); 900511#L989-1 assume !(1 == ~T6_E~0); 900512#L994-1 assume !(1 == ~T7_E~0); 900389#L999-1 assume !(1 == ~T8_E~0); 900390#L1004-1 assume !(1 == ~E_M~0); 900132#L1009-1 assume !(1 == ~E_1~0); 900133#L1014-1 assume !(1 == ~E_2~0); 900378#L1019-1 assume !(1 == ~E_3~0); 900953#L1024-1 assume !(1 == ~E_4~0); 900305#L1029-1 assume !(1 == ~E_5~0); 900306#L1034-1 assume !(1 == ~E_6~0); 900403#L1039-1 assume !(1 == ~E_7~0); 901162#L1044-1 assume !(1 == ~E_8~0); 900598#L1049-1 assume { :end_inline_reset_delta_events } true; 900599#L1315-2 [2021-12-19 19:16:22,154 INFO L793 eck$LassoCheckResult]: Loop: 900599#L1315-2 assume !false; 940444#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 940442#L841 assume !false; 940440#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 940317#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 940307#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 940300#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 940298#L724 assume !(0 != eval_~tmp~0#1); 940299#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 943247#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 943246#L866-3 assume !(0 == ~M_E~0); 943245#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 943244#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 943243#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 943241#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 943239#L886-3 assume !(0 == ~T5_E~0); 943237#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 943235#L896-3 assume !(0 == ~T7_E~0); 943233#L901-3 assume !(0 == ~T8_E~0); 943231#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 943229#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 943227#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 943225#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 943223#L926-3 assume !(0 == ~E_4~0); 943221#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 943219#L936-3 assume !(0 == ~E_6~0); 943217#L941-3 assume !(0 == ~E_7~0); 943215#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 943213#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 943211#L430-30 assume 1 == ~m_pc~0; 943208#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 943206#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943204#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 943195#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 943193#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 943191#L449-30 assume !(1 == ~t1_pc~0); 943189#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 943187#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 943185#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 943183#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 943181#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 943179#L468-30 assume 1 == ~t2_pc~0; 943176#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 943174#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 943172#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 943170#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 943162#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 943157#L487-30 assume !(1 == ~t3_pc~0); 942965#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 943147#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 943143#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 943139#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 943136#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 943133#L506-30 assume !(1 == ~t4_pc~0); 943130#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 943126#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 943122#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 943109#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 942966#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 942651#L525-30 assume !(1 == ~t5_pc~0); 942019#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 942489#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 942488#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 942487#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 942486#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 942485#L544-30 assume !(1 == ~t6_pc~0); 942484#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 942481#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 942479#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 942477#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 942475#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 939085#L563-30 assume !(1 == ~t7_pc~0); 939078#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 939073#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 939067#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 939062#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 939056#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 921036#L582-30 assume !(1 == ~t8_pc~0); 921035#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 921034#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 921033#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 921032#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 921030#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 921028#L964-3 assume !(1 == ~M_E~0); 921026#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 921024#L969-3 assume !(1 == ~T2_E~0); 921022#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 921020#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 921018#L984-3 assume !(1 == ~T5_E~0); 921015#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 921013#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 921011#L999-3 assume !(1 == ~T8_E~0); 921009#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 921007#L1009-3 assume !(1 == ~E_1~0); 921004#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 921002#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 921000#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 920998#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 920996#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 920994#L1039-3 assume !(1 == ~E_7~0); 920992#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 920989#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 920973#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 920969#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 920967#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 920940#L1334 assume !(0 == start_simulation_~tmp~3#1); 901207#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 900358#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 900359#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 900679#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 900680#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 901266#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 940471#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 940468#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 900599#L1315-2 [2021-12-19 19:16:22,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:22,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2021-12-19 19:16:22,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:22,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494391233] [2021-12-19 19:16:22,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:22,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:22,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:22,163 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:22,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:22,223 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:22,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:22,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1707401910, now seen corresponding path program 1 times [2021-12-19 19:16:22,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:22,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77855185] [2021-12-19 19:16:22,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:22,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:22,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:22,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:22,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:22,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77855185] [2021-12-19 19:16:22,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77855185] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:22,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:22,256 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:22,256 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154955913] [2021-12-19 19:16:22,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:22,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:22,257 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:22,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:22,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:22,257 INFO L87 Difference]: Start difference. First operand 43393 states and 61182 transitions. cyclomatic complexity: 17793 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:22,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:22,571 INFO L93 Difference]: Finished difference Result 48753 states and 68747 transitions. [2021-12-19 19:16:22,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:22,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48753 states and 68747 transitions. [2021-12-19 19:16:22,724 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48528 [2021-12-19 19:16:22,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48753 states to 48753 states and 68747 transitions. [2021-12-19 19:16:22,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48753 [2021-12-19 19:16:22,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48753 [2021-12-19 19:16:22,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48753 states and 68747 transitions. [2021-12-19 19:16:22,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:22,868 INFO L681 BuchiCegarLoop]: Abstraction has 48753 states and 68747 transitions. [2021-12-19 19:16:22,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48753 states and 68747 transitions. [2021-12-19 19:16:23,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48753 to 48753. [2021-12-19 19:16:23,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48753 states, 48753 states have (on average 1.4101080959120464) internal successors, (68747), 48752 states have internal predecessors, (68747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:23,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48753 states to 48753 states and 68747 transitions. [2021-12-19 19:16:23,231 INFO L704 BuchiCegarLoop]: Abstraction has 48753 states and 68747 transitions. [2021-12-19 19:16:23,231 INFO L587 BuchiCegarLoop]: Abstraction has 48753 states and 68747 transitions. [2021-12-19 19:16:23,231 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:16:23,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48753 states and 68747 transitions. [2021-12-19 19:16:23,528 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48528 [2021-12-19 19:16:23,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:23,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:23,530 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:23,530 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:23,530 INFO L791 eck$LassoCheckResult]: Stem: 993048#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 993049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 992959#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 992960#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992781#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 992782#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 992347#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 992348#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 992425#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 993282#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 992319#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 992320#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 992746#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 992769#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 992431#L866 assume !(0 == ~M_E~0); 992432#L866-2 assume !(0 == ~T1_E~0); 992990#L871-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 992991#L876-1 assume !(0 == ~T3_E~0); 993383#L881-1 assume !(0 == ~T4_E~0); 993002#L886-1 assume !(0 == ~T5_E~0); 993003#L891-1 assume !(0 == ~T6_E~0); 992994#L896-1 assume !(0 == ~T7_E~0); 992995#L901-1 assume !(0 == ~T8_E~0); 993018#L906-1 assume !(0 == ~E_M~0); 993019#L911-1 assume !(0 == ~E_1~0); 992779#L916-1 assume !(0 == ~E_2~0); 992780#L921-1 assume !(0 == ~E_3~0); 993298#L926-1 assume !(0 == ~E_4~0); 993299#L931-1 assume !(0 == ~E_5~0); 993411#L936-1 assume !(0 == ~E_6~0); 993412#L941-1 assume !(0 == ~E_7~0); 992785#L946-1 assume !(0 == ~E_8~0); 992786#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 993416#L430 assume !(1 == ~m_pc~0); 993417#L430-2 is_master_triggered_~__retres1~0#1 := 0; 992258#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 992259#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 992925#L1073 assume !(0 != activate_threads_~tmp~1#1); 992926#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 993120#L449 assume !(1 == ~t1_pc~0); 993121#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 993357#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 992215#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 992216#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 993035#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 993036#L468 assume !(1 == ~t2_pc~0); 993491#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 992971#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 992972#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 992641#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 992642#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 993413#L487 assume !(1 == ~t3_pc~0); 993414#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 993489#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993106#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 993107#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 993486#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 992845#L506 assume !(1 == ~t4_pc~0); 992846#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 993456#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 993457#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 993363#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 993364#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 992652#L525 assume !(1 == ~t5_pc~0); 992653#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 993269#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 993270#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993448#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 993449#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992833#L544 assume !(1 == ~t6_pc~0); 992834#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 993483#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 993482#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 993481#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 993480#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 993264#L563 assume !(1 == ~t7_pc~0); 993054#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 993055#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992888#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 992889#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 992438#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 992439#L582 assume !(1 == ~t8_pc~0); 993059#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 993476#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993463#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 992696#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 992583#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 992584#L964 assume !(1 == ~M_E~0); 993124#L964-2 assume !(1 == ~T1_E~0); 992496#L969-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 992497#L974-1 assume !(1 == ~T3_E~0); 993156#L979-1 assume !(1 == ~T4_E~0); 993157#L984-1 assume !(1 == ~T5_E~0); 992660#L989-1 assume !(1 == ~T6_E~0); 992661#L994-1 assume !(1 == ~T7_E~0); 992540#L999-1 assume !(1 == ~T8_E~0); 992541#L1004-1 assume !(1 == ~E_M~0); 992284#L1009-1 assume !(1 == ~E_1~0); 992285#L1014-1 assume !(1 == ~E_2~0); 992527#L1019-1 assume !(1 == ~E_3~0); 993111#L1024-1 assume !(1 == ~E_4~0); 992455#L1029-1 assume !(1 == ~E_5~0); 992456#L1034-1 assume !(1 == ~E_6~0); 992552#L1039-1 assume !(1 == ~E_7~0); 993321#L1044-1 assume !(1 == ~E_8~0); 992754#L1049-1 assume { :end_inline_reset_delta_events } true; 992755#L1315-2 [2021-12-19 19:16:23,531 INFO L793 eck$LassoCheckResult]: Loop: 992755#L1315-2 assume !false; 1028854#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1028852#L841 assume !false; 1028850#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1028838#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1028832#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1028830#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1028827#L724 assume !(0 != eval_~tmp~0#1); 1028828#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1037473#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1037471#L866-3 assume !(0 == ~M_E~0); 1037469#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1037466#L871-3 assume !(0 == ~T2_E~0); 1037467#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1040042#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1040039#L886-3 assume !(0 == ~T5_E~0); 1039847#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1039846#L896-3 assume !(0 == ~T7_E~0); 1037717#L901-3 assume !(0 == ~T8_E~0); 1037714#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1037712#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1037710#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1037708#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1037706#L926-3 assume !(0 == ~E_4~0); 1037704#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1037703#L936-3 assume !(0 == ~E_6~0); 1037701#L941-3 assume !(0 == ~E_7~0); 1037699#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1037697#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1037695#L430-30 assume 1 == ~m_pc~0; 1037693#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1037694#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1037904#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1037683#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1037681#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1037679#L449-30 assume !(1 == ~t1_pc~0); 1037677#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1037676#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1037674#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1037672#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1037670#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1037668#L468-30 assume !(1 == ~t2_pc~0); 1037666#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1037662#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1037660#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1037658#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1037656#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1037654#L487-30 assume !(1 == ~t3_pc~0); 1034815#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1037652#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1037650#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1037648#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1037646#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1037644#L506-30 assume !(1 == ~t4_pc~0); 1037641#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1037638#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1037636#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1037634#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1037632#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1030855#L525-30 assume !(1 == ~t5_pc~0); 1030852#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1030850#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1030848#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1030846#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1030844#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1030842#L544-30 assume !(1 == ~t6_pc~0); 1030840#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1030829#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1030827#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030825#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1030823#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1030821#L563-30 assume !(1 == ~t7_pc~0); 1016233#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1030810#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030808#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1030806#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1030804#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1030802#L582-30 assume !(1 == ~t8_pc~0); 1012410#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1030799#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1030797#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1030795#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1030793#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1030790#L964-3 assume !(1 == ~M_E~0); 1030788#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1030709#L969-3 assume !(1 == ~T2_E~0); 1030706#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1030704#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1030702#L984-3 assume !(1 == ~T5_E~0); 1030700#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1030698#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1030696#L999-3 assume !(1 == ~T8_E~0); 1030695#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1030693#L1009-3 assume !(1 == ~E_1~0); 1030691#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1030689#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1030687#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1030685#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1030682#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1030680#L1039-3 assume !(1 == ~E_7~0); 1030678#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1030676#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1030660#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1030654#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1030630#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1030629#L1334 assume !(0 == start_simulation_~tmp~3#1); 1030627#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1030617#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1030608#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1030606#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1030604#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1030602#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1030601#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1030600#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 992755#L1315-2 [2021-12-19 19:16:23,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:23,532 INFO L85 PathProgramCache]: Analyzing trace with hash 743043657, now seen corresponding path program 1 times [2021-12-19 19:16:23,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:23,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903838553] [2021-12-19 19:16:23,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:23,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:23,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:23,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:23,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:23,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903838553] [2021-12-19 19:16:23,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903838553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:23,561 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:23,561 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:23,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053628164] [2021-12-19 19:16:23,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:23,562 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:23,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:23,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1972681269, now seen corresponding path program 1 times [2021-12-19 19:16:23,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:23,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346756553] [2021-12-19 19:16:23,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:23,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:23,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:23,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:23,586 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:23,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346756553] [2021-12-19 19:16:23,587 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346756553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:23,587 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:23,587 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:23,587 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173062905] [2021-12-19 19:16:23,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:23,588 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:23,588 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:23,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:23,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:23,589 INFO L87 Difference]: Start difference. First operand 48753 states and 68747 transitions. cyclomatic complexity: 19998 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:23,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:23,800 INFO L93 Difference]: Finished difference Result 63713 states and 89673 transitions. [2021-12-19 19:16:23,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:23,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63713 states and 89673 transitions. [2021-12-19 19:16:24,048 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 63536 [2021-12-19 19:16:24,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63713 states to 63713 states and 89673 transitions. [2021-12-19 19:16:24,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63713 [2021-12-19 19:16:24,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63713 [2021-12-19 19:16:24,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63713 states and 89673 transitions. [2021-12-19 19:16:24,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:24,271 INFO L681 BuchiCegarLoop]: Abstraction has 63713 states and 89673 transitions. [2021-12-19 19:16:24,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63713 states and 89673 transitions. [2021-12-19 19:16:24,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63713 to 43393. [2021-12-19 19:16:24,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43393 states, 43393 states have (on average 1.408452976286498) internal successors, (61117), 43392 states have internal predecessors, (61117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:24,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43393 states to 43393 states and 61117 transitions. [2021-12-19 19:16:24,751 INFO L704 BuchiCegarLoop]: Abstraction has 43393 states and 61117 transitions. [2021-12-19 19:16:24,751 INFO L587 BuchiCegarLoop]: Abstraction has 43393 states and 61117 transitions. [2021-12-19 19:16:24,751 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:16:24,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43393 states and 61117 transitions. [2021-12-19 19:16:24,981 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:24,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:24,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:24,982 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,982 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,983 INFO L791 eck$LassoCheckResult]: Stem: 1105491#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1105492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1105405#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1105406#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1105240#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1105241#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104823#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1104824#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1104900#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1105717#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1104795#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1104796#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1105206#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1105229#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1104906#L866 assume !(0 == ~M_E~0); 1104907#L866-2 assume !(0 == ~T1_E~0); 1105437#L871-1 assume !(0 == ~T2_E~0); 1105438#L876-1 assume !(0 == ~T3_E~0); 1105799#L881-1 assume !(0 == ~T4_E~0); 1105448#L886-1 assume !(0 == ~T5_E~0); 1105195#L891-1 assume !(0 == ~T6_E~0); 1105196#L896-1 assume !(0 == ~T7_E~0); 1105440#L901-1 assume !(0 == ~T8_E~0); 1105464#L906-1 assume !(0 == ~E_M~0); 1105465#L911-1 assume !(0 == ~E_1~0); 1105238#L916-1 assume !(0 == ~E_2~0); 1105239#L921-1 assume !(0 == ~E_3~0); 1105579#L926-1 assume !(0 == ~E_4~0); 1105732#L931-1 assume !(0 == ~E_5~0); 1105813#L936-1 assume !(0 == ~E_6~0); 1105827#L941-1 assume !(0 == ~E_7~0); 1105245#L946-1 assume !(0 == ~E_8~0); 1105246#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1105766#L430 assume !(1 == ~m_pc~0); 1105105#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1105688#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1105860#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1105370#L1073 assume !(0 != activate_threads_~tmp~1#1); 1105371#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1105560#L449 assume !(1 == ~t1_pc~0); 1104909#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1104910#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1104691#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1104692#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1105478#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1105308#L468 assume !(1 == ~t2_pc~0); 1104718#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1104717#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1105203#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1105110#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1104736#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1104737#L487 assume !(1 == ~t3_pc~0); 1104846#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1104827#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1104828#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1105545#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1105169#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1105170#L506 assume !(1 == ~t4_pc~0); 1105300#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1105354#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1105746#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1105747#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1105298#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1105119#L525 assume !(1 == ~t5_pc~0); 1104773#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1104774#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1105248#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1105249#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1104967#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1104968#L544 assume !(1 == ~t6_pc~0); 1105120#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1105121#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1105499#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1104758#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1104759#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1105702#L563 assume !(1 == ~t7_pc~0); 1105496#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1104784#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1104785#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1105202#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1104913#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1104914#L582 assume !(1 == ~t8_pc~0); 1105502#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1105791#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1105792#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1105160#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1105052#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1105053#L964 assume !(1 == ~M_E~0); 1105564#L964-2 assume !(1 == ~T1_E~0); 1104969#L969-1 assume !(1 == ~T2_E~0); 1104970#L974-1 assume !(1 == ~T3_E~0); 1105595#L979-1 assume !(1 == ~T4_E~0); 1105596#L984-1 assume !(1 == ~T5_E~0); 1105126#L989-1 assume !(1 == ~T6_E~0); 1105127#L994-1 assume !(1 == ~T7_E~0); 1105011#L999-1 assume !(1 == ~T8_E~0); 1105012#L1004-1 assume !(1 == ~E_M~0); 1104760#L1009-1 assume !(1 == ~E_1~0); 1104761#L1014-1 assume !(1 == ~E_2~0); 1105000#L1019-1 assume !(1 == ~E_3~0); 1105550#L1024-1 assume !(1 == ~E_4~0); 1104930#L1029-1 assume !(1 == ~E_5~0); 1104931#L1034-1 assume !(1 == ~E_6~0); 1105023#L1039-1 assume !(1 == ~E_7~0); 1105754#L1044-1 assume !(1 == ~E_8~0); 1105214#L1049-1 assume { :end_inline_reset_delta_events } true; 1105215#L1315-2 [2021-12-19 19:16:24,983 INFO L793 eck$LassoCheckResult]: Loop: 1105215#L1315-2 assume !false; 1132332#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1132330#L841 assume !false; 1132329#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1132317#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1132309#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1132305#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1132300#L724 assume !(0 != eval_~tmp~0#1); 1132301#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1146726#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1146725#L866-3 assume !(0 == ~M_E~0); 1146724#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1146723#L871-3 assume !(0 == ~T2_E~0); 1146722#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1146721#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1146720#L886-3 assume !(0 == ~T5_E~0); 1146719#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1146718#L896-3 assume !(0 == ~T7_E~0); 1146717#L901-3 assume !(0 == ~T8_E~0); 1140271#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1140269#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1140267#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1140265#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1140262#L926-3 assume !(0 == ~E_4~0); 1140263#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1140255#L936-3 assume !(0 == ~E_6~0); 1140256#L941-3 assume !(0 == ~E_7~0); 1140249#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1140250#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1140242#L430-30 assume 1 == ~m_pc~0; 1140240#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1140241#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1140303#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1140230#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1140228#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1140226#L449-30 assume !(1 == ~t1_pc~0); 1140223#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1140221#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1140219#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1140217#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1140205#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1135520#L468-30 assume 1 == ~t2_pc~0; 1135521#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1135513#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135511#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1135508#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1135509#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1137615#L487-30 assume !(1 == ~t3_pc~0); 1137614#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1137613#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1137612#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1137611#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1137610#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137609#L506-30 assume 1 == ~t4_pc~0; 1137607#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1137606#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1137605#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1137604#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1137603#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1137602#L525-30 assume !(1 == ~t5_pc~0); 1132493#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1137601#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1137600#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1137599#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1137598#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1137597#L544-30 assume 1 == ~t6_pc~0; 1137593#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1137591#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1137589#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1137587#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1137585#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1137583#L563-30 assume !(1 == ~t7_pc~0); 1129912#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1135585#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135583#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135581#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1135579#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1135577#L582-30 assume !(1 == ~t8_pc~0); 1129898#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1135574#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1135572#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1135569#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1135567#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1135565#L964-3 assume !(1 == ~M_E~0); 1135563#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1135560#L969-3 assume !(1 == ~T2_E~0); 1135558#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1135556#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1135554#L984-3 assume !(1 == ~T5_E~0); 1135552#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1135550#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1135548#L999-3 assume !(1 == ~T8_E~0); 1135546#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1135544#L1009-3 assume !(1 == ~E_1~0); 1135541#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1135539#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1135537#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1135535#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1135533#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1135532#L1039-3 assume !(1 == ~E_7~0); 1135531#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1104923#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1104924#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1130011#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1129002#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1129003#L1334 assume !(0 == start_simulation_~tmp~3#1); 1132365#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1132361#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1132352#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1132350#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1132346#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1132344#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1132342#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1132338#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1105215#L1315-2 [2021-12-19 19:16:24,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:24,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2021-12-19 19:16:24,984 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:24,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628644651] [2021-12-19 19:16:24,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:24,984 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:24,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:24,992 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:24,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:25,034 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:25,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1638925042, now seen corresponding path program 1 times [2021-12-19 19:16:25,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249006952] [2021-12-19 19:16:25,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,036 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249006952] [2021-12-19 19:16:25,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249006952] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,062 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542952250] [2021-12-19 19:16:25,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,063 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,064 INFO L87 Difference]: Start difference. First operand 43393 states and 61117 transitions. cyclomatic complexity: 17728 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,263 INFO L93 Difference]: Finished difference Result 65297 states and 91514 transitions. [2021-12-19 19:16:25,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65297 states and 91514 transitions. [2021-12-19 19:16:25,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65072 [2021-12-19 19:16:25,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65297 states to 65297 states and 91514 transitions. [2021-12-19 19:16:25,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65297 [2021-12-19 19:16:25,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65297 [2021-12-19 19:16:25,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65297 states and 91514 transitions. [2021-12-19 19:16:25,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,754 INFO L681 BuchiCegarLoop]: Abstraction has 65297 states and 91514 transitions. [2021-12-19 19:16:25,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65297 states and 91514 transitions. [2021-12-19 19:16:26,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65297 to 64977. [2021-12-19 19:16:26,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64977 states, 64977 states have (on average 1.4005263400895702) internal successors, (91002), 64976 states have internal predecessors, (91002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64977 states to 64977 states and 91002 transitions. [2021-12-19 19:16:26,669 INFO L704 BuchiCegarLoop]: Abstraction has 64977 states and 91002 transitions. [2021-12-19 19:16:26,669 INFO L587 BuchiCegarLoop]: Abstraction has 64977 states and 91002 transitions. [2021-12-19 19:16:26,669 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:16:26,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64977 states and 91002 transitions. [2021-12-19 19:16:26,842 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 64752 [2021-12-19 19:16:26,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,845 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,845 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,845 INFO L791 eck$LassoCheckResult]: Stem: 1214227#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1214228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1214133#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1214134#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1213951#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1213952#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1213521#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1213522#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1213599#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1214469#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1213493#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1213494#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1213917#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1213940#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1213605#L866 assume !(0 == ~M_E~0); 1213606#L866-2 assume !(0 == ~T1_E~0); 1214168#L871-1 assume !(0 == ~T2_E~0); 1214169#L876-1 assume !(0 == ~T3_E~0); 1214573#L881-1 assume !(0 == ~T4_E~0); 1214182#L886-1 assume !(0 == ~T5_E~0); 1213904#L891-1 assume !(0 == ~T6_E~0); 1213905#L896-1 assume !(0 == ~T7_E~0); 1214172#L901-1 assume !(0 == ~T8_E~0); 1214197#L906-1 assume !(0 == ~E_M~0); 1214198#L911-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1213949#L916-1 assume !(0 == ~E_2~0); 1213950#L921-1 assume !(0 == ~E_3~0); 1214488#L926-1 assume !(0 == ~E_4~0); 1214489#L931-1 assume !(0 == ~E_5~0); 1214615#L936-1 assume !(0 == ~E_6~0); 1214616#L941-1 assume !(0 == ~E_7~0); 1213956#L946-1 assume !(0 == ~E_8~0); 1213957#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1214619#L430 assume !(1 == ~m_pc~0); 1214620#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1214693#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1214694#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1214094#L1073 assume !(0 != activate_threads_~tmp~1#1); 1214095#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1214307#L449 assume !(1 == ~t1_pc~0); 1214308#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1214554#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1214555#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1214625#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1214626#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1214024#L468 assume !(1 == ~t2_pc~0); 1214025#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1214146#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1214147#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1213811#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1213812#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1214617#L487 assume !(1 == ~t3_pc~0); 1214618#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1213525#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1213526#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1214388#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1213878#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1213879#L506 assume !(1 == ~t4_pc~0); 1214075#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1214076#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1214662#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1214560#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1214561#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1213822#L525 assume !(1 == ~t5_pc~0); 1213469#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1213470#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1213959#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1213960#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1213667#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1213668#L544 assume !(1 == ~t6_pc~0); 1213823#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1213824#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1214239#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1213453#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1213454#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1214535#L563 assume !(1 == ~t7_pc~0); 1214688#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1213480#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1213481#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1213911#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1213912#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1214687#L582 assume !(1 == ~t8_pc~0); 1214686#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1214564#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1214565#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1214685#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1213755#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1213756#L964 assume !(1 == ~M_E~0); 1214556#L964-2 assume !(1 == ~T1_E~0); 1214557#L969-1 assume !(1 == ~T2_E~0); 1214499#L974-1 assume !(1 == ~T3_E~0); 1214500#L979-1 assume !(1 == ~T4_E~0); 1214654#L984-1 assume !(1 == ~T5_E~0); 1213830#L989-1 assume !(1 == ~T6_E~0); 1213831#L994-1 assume !(1 == ~T7_E~0); 1213712#L999-1 assume !(1 == ~T8_E~0); 1213713#L1004-1 assume !(1 == ~E_M~0); 1213455#L1009-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1213456#L1014-1 assume !(1 == ~E_2~0); 1213702#L1019-1 assume !(1 == ~E_3~0); 1214298#L1024-1 assume !(1 == ~E_4~0); 1213628#L1029-1 assume !(1 == ~E_5~0); 1213629#L1034-1 assume !(1 == ~E_6~0); 1213725#L1039-1 assume !(1 == ~E_7~0); 1214513#L1044-1 assume !(1 == ~E_8~0); 1213925#L1049-1 assume { :end_inline_reset_delta_events } true; 1213926#L1315-2 [2021-12-19 19:16:26,845 INFO L793 eck$LassoCheckResult]: Loop: 1213926#L1315-2 assume !false; 1227967#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1227965#L841 assume !false; 1227963#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1227951#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1227945#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1227943#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1227940#L724 assume !(0 != eval_~tmp~0#1); 1227941#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1233518#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1233514#L866-3 assume !(0 == ~M_E~0); 1233515#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1236467#L871-3 assume !(0 == ~T2_E~0); 1236465#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1233504#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1233505#L886-3 assume !(0 == ~T5_E~0); 1233500#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1233501#L896-3 assume !(0 == ~T7_E~0); 1233496#L901-3 assume !(0 == ~T8_E~0); 1233497#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1233491#L911-3 assume !(0 == ~E_1~0); 1233489#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1233490#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1233481#L926-3 assume !(0 == ~E_4~0); 1233482#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1233477#L936-3 assume !(0 == ~E_6~0); 1233478#L941-3 assume !(0 == ~E_7~0); 1233473#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1233474#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1233468#L430-30 assume !(1 == ~m_pc~0); 1233470#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1233462#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1233463#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1233452#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1233451#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1233444#L449-30 assume !(1 == ~t1_pc~0); 1233445#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1233436#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1233437#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1233430#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1233431#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1233422#L468-30 assume !(1 == ~t2_pc~0); 1233424#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1233415#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1233416#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1233409#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1233410#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1233404#L487-30 assume !(1 == ~t3_pc~0); 1227579#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1233398#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1233399#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1233392#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233393#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1233385#L506-30 assume !(1 == ~t4_pc~0); 1233386#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1233373#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1233374#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1233298#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1233299#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1232340#L525-30 assume !(1 == ~t5_pc~0); 1232274#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1232251#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1232244#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1232235#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1232227#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1232217#L544-30 assume 1 == ~t6_pc~0; 1232208#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1232197#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1232188#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1232180#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1232172#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1232165#L563-30 assume !(1 == ~t7_pc~0); 1227286#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1232164#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1232163#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1232162#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1232156#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1228314#L582-30 assume !(1 == ~t8_pc~0); 1228310#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1228308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1228306#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1228304#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1228301#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1228299#L964-3 assume !(1 == ~M_E~0); 1228297#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1228295#L969-3 assume !(1 == ~T2_E~0); 1228293#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1228291#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1228289#L984-3 assume !(1 == ~T5_E~0); 1228287#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1228285#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1228282#L999-3 assume !(1 == ~T8_E~0); 1228280#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1228242#L1009-3 assume !(1 == ~E_1~0); 1228240#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1228238#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1228236#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1228234#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1228231#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1228229#L1039-3 assume !(1 == ~E_7~0); 1228227#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1228225#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1228211#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1228208#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1228206#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1228203#L1334 assume !(0 == start_simulation_~tmp~3#1); 1228201#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1228195#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1228186#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1228184#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1228182#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1228180#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1228179#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1228177#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1213926#L1315-2 [2021-12-19 19:16:26,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,846 INFO L85 PathProgramCache]: Analyzing trace with hash -1215057335, now seen corresponding path program 1 times [2021-12-19 19:16:26,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511596984] [2021-12-19 19:16:26,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,877 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511596984] [2021-12-19 19:16:26,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511596984] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,877 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,877 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:26,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379439497] [2021-12-19 19:16:26,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,878 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,878 INFO L85 PathProgramCache]: Analyzing trace with hash 905445621, now seen corresponding path program 1 times [2021-12-19 19:16:26,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109179985] [2021-12-19 19:16:26,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,904 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109179985] [2021-12-19 19:16:26,904 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109179985] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,904 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,904 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:26,904 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043806533] [2021-12-19 19:16:26,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,905 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,905 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:26,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:26,906 INFO L87 Difference]: Start difference. First operand 64977 states and 91002 transitions. cyclomatic complexity: 26029 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:27,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:27,048 INFO L93 Difference]: Finished difference Result 43393 states and 60683 transitions. [2021-12-19 19:16:27,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:27,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43393 states and 60683 transitions. [2021-12-19 19:16:27,195 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:27,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43393 states to 43393 states and 60683 transitions. [2021-12-19 19:16:27,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43393 [2021-12-19 19:16:27,314 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43393 [2021-12-19 19:16:27,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43393 states and 60683 transitions. [2021-12-19 19:16:27,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:27,341 INFO L681 BuchiCegarLoop]: Abstraction has 43393 states and 60683 transitions. [2021-12-19 19:16:27,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43393 states and 60683 transitions. [2021-12-19 19:16:28,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43393 to 43393. [2021-12-19 19:16:28,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43393 states, 43393 states have (on average 1.3984513631230844) internal successors, (60683), 43392 states have internal predecessors, (60683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:28,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43393 states to 43393 states and 60683 transitions. [2021-12-19 19:16:28,172 INFO L704 BuchiCegarLoop]: Abstraction has 43393 states and 60683 transitions. [2021-12-19 19:16:28,172 INFO L587 BuchiCegarLoop]: Abstraction has 43393 states and 60683 transitions. [2021-12-19 19:16:28,173 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:16:28,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43393 states and 60683 transitions. [2021-12-19 19:16:28,279 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43248 [2021-12-19 19:16:28,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:28,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:28,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,281 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,282 INFO L791 eck$LassoCheckResult]: Stem: 1322571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1322572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1322483#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1322484#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1322318#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1322319#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1321899#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1321900#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1321977#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1322799#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1321871#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1321872#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1322285#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1322307#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1321983#L866 assume !(0 == ~M_E~0); 1321984#L866-2 assume !(0 == ~T1_E~0); 1322513#L871-1 assume !(0 == ~T2_E~0); 1322514#L876-1 assume !(0 == ~T3_E~0); 1322883#L881-1 assume !(0 == ~T4_E~0); 1322529#L886-1 assume !(0 == ~T5_E~0); 1322274#L891-1 assume !(0 == ~T6_E~0); 1322275#L896-1 assume !(0 == ~T7_E~0); 1322517#L901-1 assume !(0 == ~T8_E~0); 1322543#L906-1 assume !(0 == ~E_M~0); 1322544#L911-1 assume !(0 == ~E_1~0); 1322316#L916-1 assume !(0 == ~E_2~0); 1322317#L921-1 assume !(0 == ~E_3~0); 1322662#L926-1 assume !(0 == ~E_4~0); 1322816#L931-1 assume !(0 == ~E_5~0); 1322898#L936-1 assume !(0 == ~E_6~0); 1322924#L941-1 assume !(0 == ~E_7~0); 1322322#L946-1 assume !(0 == ~E_8~0); 1322323#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1322848#L430 assume !(1 == ~m_pc~0); 1322181#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1322768#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1322957#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1322445#L1073 assume !(0 != activate_threads_~tmp~1#1); 1322446#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1322644#L449 assume !(1 == ~t1_pc~0); 1321986#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1321987#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1321766#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1321767#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1322558#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1322385#L468 assume !(1 == ~t2_pc~0); 1321793#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1321792#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1322282#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1322186#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1321808#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1321809#L487 assume !(1 == ~t3_pc~0); 1321922#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1321903#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1321904#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1322627#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1322249#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1322250#L506 assume !(1 == ~t4_pc~0); 1322378#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1322428#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1322831#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1322832#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1322376#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1322195#L525 assume !(1 == ~t5_pc~0); 1321847#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1321848#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1322326#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1322327#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1322043#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1322044#L544 assume !(1 == ~t6_pc~0); 1322196#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1322197#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1322579#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1321832#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1321833#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1322784#L563 assume !(1 == ~t7_pc~0); 1322576#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1321858#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1321859#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1322281#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1321990#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1321991#L582 assume !(1 == ~t8_pc~0); 1322580#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1322876#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1322877#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1322239#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1322129#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1322130#L964 assume !(1 == ~M_E~0); 1322646#L964-2 assume !(1 == ~T1_E~0); 1322045#L969-1 assume !(1 == ~T2_E~0); 1322046#L974-1 assume !(1 == ~T3_E~0); 1322677#L979-1 assume !(1 == ~T4_E~0); 1322678#L984-1 assume !(1 == ~T5_E~0); 1322202#L989-1 assume !(1 == ~T6_E~0); 1322203#L994-1 assume !(1 == ~T7_E~0); 1322088#L999-1 assume !(1 == ~T8_E~0); 1322089#L1004-1 assume !(1 == ~E_M~0); 1321834#L1009-1 assume !(1 == ~E_1~0); 1321835#L1014-1 assume !(1 == ~E_2~0); 1322076#L1019-1 assume !(1 == ~E_3~0); 1322633#L1024-1 assume !(1 == ~E_4~0); 1322006#L1029-1 assume !(1 == ~E_5~0); 1322007#L1034-1 assume !(1 == ~E_6~0); 1322100#L1039-1 assume !(1 == ~E_7~0); 1322838#L1044-1 assume !(1 == ~E_8~0); 1322293#L1049-1 assume { :end_inline_reset_delta_events } true; 1322294#L1315-2 [2021-12-19 19:16:28,283 INFO L793 eck$LassoCheckResult]: Loop: 1322294#L1315-2 assume !false; 1332035#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1331792#L841 assume !false; 1332029#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1331969#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1331959#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1331952#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1331945#L724 assume !(0 != eval_~tmp~0#1); 1331946#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1356820#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1356818#L866-3 assume !(0 == ~M_E~0); 1356816#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1356431#L871-3 assume !(0 == ~T2_E~0); 1356421#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1356419#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1356417#L886-3 assume !(0 == ~T5_E~0); 1356414#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1356413#L896-3 assume !(0 == ~T7_E~0); 1356409#L901-3 assume !(0 == ~T8_E~0); 1356407#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1356405#L911-3 assume !(0 == ~E_1~0); 1356403#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1356400#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1356398#L926-3 assume !(0 == ~E_4~0); 1356396#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1356394#L936-3 assume !(0 == ~E_6~0); 1356392#L941-3 assume !(0 == ~E_7~0); 1356390#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1356388#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1356386#L430-30 assume !(1 == ~m_pc~0); 1356382#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1356379#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1356377#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1356375#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1356372#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1356370#L449-30 assume !(1 == ~t1_pc~0); 1356368#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1356366#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1356364#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1356362#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1356360#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1356358#L468-30 assume !(1 == ~t2_pc~0); 1356356#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1356352#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1356350#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1356348#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1356346#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1337558#L487-30 assume !(1 == ~t3_pc~0); 1337556#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1337552#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1337549#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1337547#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1337545#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1337542#L506-30 assume !(1 == ~t4_pc~0); 1337540#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1337537#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337534#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1337532#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1337530#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1337322#L525-30 assume !(1 == ~t5_pc~0); 1337321#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1337320#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337319#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1337318#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1337317#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1337316#L544-30 assume 1 == ~t6_pc~0; 1337314#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1337313#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1337312#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1337311#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1336770#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1332267#L563-30 assume !(1 == ~t7_pc~0); 1332266#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1332265#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1332261#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1332255#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1332252#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1332246#L582-30 assume !(1 == ~t8_pc~0); 1331608#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1332243#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1332241#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1332238#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1332236#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1332234#L964-3 assume !(1 == ~M_E~0); 1332229#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1332201#L969-3 assume !(1 == ~T2_E~0); 1332197#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1332196#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1332195#L984-3 assume !(1 == ~T5_E~0); 1332193#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1332191#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1332189#L999-3 assume !(1 == ~T8_E~0); 1332187#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1332185#L1009-3 assume !(1 == ~E_1~0); 1332183#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1332181#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1332180#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1332178#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1332176#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1332174#L1039-3 assume !(1 == ~E_7~0); 1332172#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1332165#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1332153#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1332149#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1332145#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1332141#L1334 assume !(0 == start_simulation_~tmp~3#1); 1332139#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1332087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1332073#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1332064#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1332059#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1332054#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1332050#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1332045#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1322294#L1315-2 [2021-12-19 19:16:28,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,283 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2021-12-19 19:16:28,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711001578] [2021-12-19 19:16:28,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,302 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:28,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:28,329 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:28,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,329 INFO L85 PathProgramCache]: Analyzing trace with hash 905445621, now seen corresponding path program 2 times [2021-12-19 19:16:28,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64961016] [2021-12-19 19:16:28,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:28,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:28,363 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:28,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64961016] [2021-12-19 19:16:28,363 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64961016] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:28,363 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:28,363 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:28,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004607464] [2021-12-19 19:16:28,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:28,364 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:28,364 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:28,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:28,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:28,365 INFO L87 Difference]: Start difference. First operand 43393 states and 60683 transitions. cyclomatic complexity: 17294 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:28,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:28,648 INFO L93 Difference]: Finished difference Result 79281 states and 109659 transitions. [2021-12-19 19:16:28,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:16:28,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79281 states and 109659 transitions. [2021-12-19 19:16:28,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 79104 [2021-12-19 19:16:29,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79281 states to 79281 states and 109659 transitions. [2021-12-19 19:16:29,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79281 [2021-12-19 19:16:29,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79281 [2021-12-19 19:16:29,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79281 states and 109659 transitions. [2021-12-19 19:16:29,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:29,346 INFO L681 BuchiCegarLoop]: Abstraction has 79281 states and 109659 transitions. [2021-12-19 19:16:29,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79281 states and 109659 transitions. [2021-12-19 19:16:30,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79281 to 43585. [2021-12-19 19:16:30,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43585 states, 43585 states have (on average 1.3966961110473788) internal successors, (60875), 43584 states have internal predecessors, (60875), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:30,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43585 states to 43585 states and 60875 transitions. [2021-12-19 19:16:30,262 INFO L704 BuchiCegarLoop]: Abstraction has 43585 states and 60875 transitions. [2021-12-19 19:16:30,262 INFO L587 BuchiCegarLoop]: Abstraction has 43585 states and 60875 transitions. [2021-12-19 19:16:30,262 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:16:30,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43585 states and 60875 transitions. [2021-12-19 19:16:30,375 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43440 [2021-12-19 19:16:30,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:30,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:30,377 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:30,377 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:30,377 INFO L791 eck$LassoCheckResult]: Stem: 1445249#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1445250#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1445169#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1445170#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1445009#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1445010#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1444587#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1444588#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1444664#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1445481#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1444559#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1444560#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1444975#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1444998#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1444670#L866 assume !(0 == ~M_E~0); 1444671#L866-2 assume !(0 == ~T1_E~0); 1445198#L871-1 assume !(0 == ~T2_E~0); 1445199#L876-1 assume !(0 == ~T3_E~0); 1445558#L881-1 assume !(0 == ~T4_E~0); 1445209#L886-1 assume !(0 == ~T5_E~0); 1444964#L891-1 assume !(0 == ~T6_E~0); 1444965#L896-1 assume !(0 == ~T7_E~0); 1445201#L901-1 assume !(0 == ~T8_E~0); 1445223#L906-1 assume !(0 == ~E_M~0); 1445224#L911-1 assume !(0 == ~E_1~0); 1445007#L916-1 assume !(0 == ~E_2~0); 1445008#L921-1 assume !(0 == ~E_3~0); 1445342#L926-1 assume !(0 == ~E_4~0); 1445496#L931-1 assume !(0 == ~E_5~0); 1445570#L936-1 assume !(0 == ~E_6~0); 1445585#L941-1 assume !(0 == ~E_7~0); 1445013#L946-1 assume !(0 == ~E_8~0); 1445014#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1445522#L430 assume !(1 == ~m_pc~0); 1444868#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1444495#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1444496#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1445120#L1073 assume !(0 != activate_threads_~tmp~1#1); 1445134#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1445325#L449 assume !(1 == ~t1_pc~0); 1444673#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1444674#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1444456#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1444457#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1445237#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1445073#L468 assume !(1 == ~t2_pc~0); 1444483#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1444482#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1444972#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1444877#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1444497#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1444498#L487 assume !(1 == ~t3_pc~0); 1444610#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1444591#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1444592#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1445308#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1444938#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1444939#L506 assume !(1 == ~t4_pc~0); 1445069#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1445116#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1445508#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1445509#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1445065#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1444885#L525 assume !(1 == ~t5_pc~0); 1444536#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1444537#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1445017#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1445018#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1444733#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1444734#L544 assume !(1 == ~t6_pc~0); 1444886#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1444887#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1445258#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1444521#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1444522#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1445467#L563 assume !(1 == ~t7_pc~0); 1445255#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1444547#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1444548#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1444966#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1444677#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1444678#L582 assume !(1 == ~t8_pc~0); 1445259#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1445547#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1445548#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1444925#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1444820#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1444821#L964 assume !(1 == ~M_E~0); 1445327#L964-2 assume !(1 == ~T1_E~0); 1444735#L969-1 assume !(1 == ~T2_E~0); 1444736#L974-1 assume !(1 == ~T3_E~0); 1445362#L979-1 assume !(1 == ~T4_E~0); 1445363#L984-1 assume !(1 == ~T5_E~0); 1444892#L989-1 assume !(1 == ~T6_E~0); 1444893#L994-1 assume !(1 == ~T7_E~0); 1444777#L999-1 assume !(1 == ~T8_E~0); 1444778#L1004-1 assume !(1 == ~E_M~0); 1444523#L1009-1 assume !(1 == ~E_1~0); 1444524#L1014-1 assume !(1 == ~E_2~0); 1444765#L1019-1 assume !(1 == ~E_3~0); 1445314#L1024-1 assume !(1 == ~E_4~0); 1444693#L1029-1 assume !(1 == ~E_5~0); 1444694#L1034-1 assume !(1 == ~E_6~0); 1444791#L1039-1 assume !(1 == ~E_7~0); 1445513#L1044-1 assume !(1 == ~E_8~0); 1444981#L1049-1 assume { :end_inline_reset_delta_events } true; 1444982#L1315-2 [2021-12-19 19:16:30,377 INFO L793 eck$LassoCheckResult]: Loop: 1444982#L1315-2 assume !false; 1483819#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1483816#L841 assume !false; 1482603#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1482564#L662 assume !(0 == ~m_st~0); 1482558#L666 assume !(0 == ~t1_st~0); 1482552#L670 assume !(0 == ~t2_st~0); 1482547#L674 assume !(0 == ~t3_st~0); 1482531#L678 assume !(0 == ~t4_st~0); 1482526#L682 assume !(0 == ~t5_st~0); 1482520#L686 assume !(0 == ~t6_st~0); 1482513#L690 assume !(0 == ~t7_st~0); 1482472#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1482455#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1482449#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1482447#L724 assume !(0 != eval_~tmp~0#1); 1482446#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1482444#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1482442#L866-3 assume !(0 == ~M_E~0); 1482440#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1482438#L871-3 assume !(0 == ~T2_E~0); 1482436#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1482434#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1482432#L886-3 assume !(0 == ~T5_E~0); 1482430#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1482428#L896-3 assume !(0 == ~T7_E~0); 1482426#L901-3 assume !(0 == ~T8_E~0); 1482424#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1482422#L911-3 assume !(0 == ~E_1~0); 1482420#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1482418#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1482416#L926-3 assume !(0 == ~E_4~0); 1482414#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1482412#L936-3 assume !(0 == ~E_6~0); 1482410#L941-3 assume !(0 == ~E_7~0); 1482408#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1482406#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1482404#L430-30 assume !(1 == ~m_pc~0); 1482402#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1482398#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1482394#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1482390#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1482386#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1482384#L449-30 assume !(1 == ~t1_pc~0); 1482382#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1482380#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1482378#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1482371#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1482372#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1482328#L468-30 assume !(1 == ~t2_pc~0); 1482330#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1482266#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1482267#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1482255#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1482256#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1481981#L487-30 assume !(1 == ~t3_pc~0); 1481980#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1481978#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1481976#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1481974#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1481972#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1481970#L506-30 assume 1 == ~t4_pc~0; 1481966#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1481964#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1481962#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1481960#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1481958#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1481956#L525-30 assume !(1 == ~t5_pc~0); 1481546#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1481954#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1481952#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1481950#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1481948#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1481946#L544-30 assume 1 == ~t6_pc~0; 1481942#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1481940#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1481938#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1481936#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1481934#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1481932#L563-30 assume !(1 == ~t7_pc~0); 1481641#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1481930#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1481928#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1481926#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1481924#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1481921#L582-30 assume !(1 == ~t8_pc~0); 1481920#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1481919#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1481918#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1481917#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1481916#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1481915#L964-3 assume !(1 == ~M_E~0); 1481914#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1481913#L969-3 assume !(1 == ~T2_E~0); 1481912#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1481911#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1481910#L984-3 assume !(1 == ~T5_E~0); 1481909#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1481908#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1481907#L999-3 assume !(1 == ~T8_E~0); 1481906#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1481905#L1009-3 assume !(1 == ~E_1~0); 1481904#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1481903#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1481902#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1481901#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1481900#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1481899#L1039-3 assume !(1 == ~E_7~0); 1481898#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1481897#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1481890#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1481886#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1481884#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1481881#L1334 assume !(0 == start_simulation_~tmp~3#1); 1481882#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1483887#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1483878#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1483876#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1483874#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1483872#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1483870#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1483869#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1444982#L1315-2 [2021-12-19 19:16:30,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:30,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2021-12-19 19:16:30,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:30,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829124888] [2021-12-19 19:16:30,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:30,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:30,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:30,387 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:30,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:30,419 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:30,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:30,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1991292894, now seen corresponding path program 1 times [2021-12-19 19:16:30,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:30,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488977747] [2021-12-19 19:16:30,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:30,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:30,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:30,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:30,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:30,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488977747] [2021-12-19 19:16:30,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488977747] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:30,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:30,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:30,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13751566] [2021-12-19 19:16:30,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:30,449 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:30,449 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:30,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:30,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:30,450 INFO L87 Difference]: Start difference. First operand 43585 states and 60875 transitions. cyclomatic complexity: 17294 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:30,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:30,689 INFO L93 Difference]: Finished difference Result 82065 states and 113179 transitions. [2021-12-19 19:16:30,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:30,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82065 states and 113179 transitions. [2021-12-19 19:16:31,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 81888 [2021-12-19 19:16:31,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82065 states to 82065 states and 113179 transitions. [2021-12-19 19:16:31,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82065 [2021-12-19 19:16:31,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82065 [2021-12-19 19:16:31,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82065 states and 113179 transitions. [2021-12-19 19:16:31,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:31,357 INFO L681 BuchiCegarLoop]: Abstraction has 82065 states and 113179 transitions. [2021-12-19 19:16:31,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82065 states and 113179 transitions. [2021-12-19 19:16:32,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82065 to 78513. [2021-12-19 19:16:32,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78513 states, 78513 states have (on average 1.3816183307223007) internal successors, (108475), 78512 states have internal predecessors, (108475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:32,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78513 states to 78513 states and 108475 transitions. [2021-12-19 19:16:32,565 INFO L704 BuchiCegarLoop]: Abstraction has 78513 states and 108475 transitions. [2021-12-19 19:16:32,565 INFO L587 BuchiCegarLoop]: Abstraction has 78513 states and 108475 transitions. [2021-12-19 19:16:32,565 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:16:32,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78513 states and 108475 transitions. [2021-12-19 19:16:32,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 78336 [2021-12-19 19:16:32,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:32,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:32,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:32,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:32,784 INFO L791 eck$LassoCheckResult]: Stem: 1570917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1570918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1570836#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1570837#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1570671#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1570672#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1570243#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1570244#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1570320#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1571150#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1570214#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1570215#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1570633#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1570659#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570326#L866 assume !(0 == ~M_E~0); 1570327#L866-2 assume !(0 == ~T1_E~0); 1570865#L871-1 assume !(0 == ~T2_E~0); 1570866#L876-1 assume !(0 == ~T3_E~0); 1571237#L881-1 assume !(0 == ~T4_E~0); 1570877#L886-1 assume !(0 == ~T5_E~0); 1570624#L891-1 assume !(0 == ~T6_E~0); 1570625#L896-1 assume !(0 == ~T7_E~0); 1570868#L901-1 assume !(0 == ~T8_E~0); 1570891#L906-1 assume !(0 == ~E_M~0); 1570892#L911-1 assume !(0 == ~E_1~0); 1570669#L916-1 assume !(0 == ~E_2~0); 1570670#L921-1 assume !(0 == ~E_3~0); 1571008#L926-1 assume !(0 == ~E_4~0); 1571165#L931-1 assume !(0 == ~E_5~0); 1571253#L936-1 assume !(0 == ~E_6~0); 1571272#L941-1 assume !(0 == ~E_7~0); 1570675#L946-1 assume !(0 == ~E_8~0); 1570676#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1571205#L430 assume !(1 == ~m_pc~0); 1570528#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1570151#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1570152#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1570791#L1073 assume !(0 != activate_threads_~tmp~1#1); 1570802#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1570991#L449 assume !(1 == ~t1_pc~0); 1570329#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1570330#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1570112#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1570113#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1570905#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1570738#L468 assume !(1 == ~t2_pc~0); 1570137#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1570136#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1570632#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1570535#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1570153#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1570154#L487 assume !(1 == ~t3_pc~0); 1570266#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1570247#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1570248#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1570976#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1570600#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1570601#L506 assume !(1 == ~t4_pc~0); 1570733#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1570787#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1571183#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1571184#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1570724#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1570545#L525 assume !(1 == ~t5_pc~0); 1570192#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1570193#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1570679#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1570680#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1570390#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1570391#L544 assume !(1 == ~t6_pc~0); 1570546#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1570547#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1570927#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1570177#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1570178#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1571136#L563 assume !(1 == ~t7_pc~0); 1570924#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1570203#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1570204#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1570626#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1570331#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1570332#L582 assume !(1 == ~t8_pc~0); 1570928#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1571230#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1571231#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1570588#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1570478#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1570479#L964 assume !(1 == ~M_E~0); 1570993#L964-2 assume !(1 == ~T1_E~0); 1570392#L969-1 assume !(1 == ~T2_E~0); 1570393#L974-1 assume !(1 == ~T3_E~0); 1571025#L979-1 assume !(1 == ~T4_E~0); 1571026#L984-1 assume !(1 == ~T5_E~0); 1570552#L989-1 assume !(1 == ~T6_E~0); 1570553#L994-1 assume !(1 == ~T7_E~0); 1570432#L999-1 assume !(1 == ~T8_E~0); 1570433#L1004-1 assume !(1 == ~E_M~0); 1570179#L1009-1 assume !(1 == ~E_1~0); 1570180#L1014-1 assume !(1 == ~E_2~0); 1570421#L1019-1 assume !(1 == ~E_3~0); 1570981#L1024-1 assume !(1 == ~E_4~0); 1570350#L1029-1 assume !(1 == ~E_5~0); 1570351#L1034-1 assume !(1 == ~E_6~0); 1570447#L1039-1 assume !(1 == ~E_7~0); 1571192#L1044-1 assume !(1 == ~E_8~0); 1570641#L1049-1 assume { :end_inline_reset_delta_events } true; 1570642#L1315-2 [2021-12-19 19:16:32,785 INFO L793 eck$LassoCheckResult]: Loop: 1570642#L1315-2 assume !false; 1604774#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1602011#L841 assume !false; 1604772#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1604768#L662 assume !(0 == ~m_st~0); 1604769#L666 assume !(0 == ~t1_st~0); 1605579#L670 assume !(0 == ~t2_st~0); 1605576#L674 assume !(0 == ~t3_st~0); 1605573#L678 assume !(0 == ~t4_st~0); 1605570#L682 assume !(0 == ~t5_st~0); 1605567#L686 assume !(0 == ~t6_st~0); 1605564#L690 assume !(0 == ~t7_st~0); 1605559#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1605556#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1605553#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1605549#L724 assume !(0 != eval_~tmp~0#1); 1605546#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1605543#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1605540#L866-3 assume !(0 == ~M_E~0); 1605537#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1605534#L871-3 assume !(0 == ~T2_E~0); 1605531#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1605529#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1605526#L886-3 assume !(0 == ~T5_E~0); 1605517#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1605514#L896-3 assume !(0 == ~T7_E~0); 1605511#L901-3 assume !(0 == ~T8_E~0); 1605508#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1605505#L911-3 assume !(0 == ~E_1~0); 1605502#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1605499#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1605496#L926-3 assume !(0 == ~E_4~0); 1605493#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1605491#L936-3 assume !(0 == ~E_6~0); 1605488#L941-3 assume !(0 == ~E_7~0); 1605485#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1605476#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1605474#L430-30 assume 1 == ~m_pc~0; 1605470#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1605467#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1605464#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1605460#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1605452#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1605443#L449-30 assume !(1 == ~t1_pc~0); 1605435#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1605427#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1605414#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1605404#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1605401#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1605394#L468-30 assume 1 == ~t2_pc~0; 1605395#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1605358#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1605359#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1605335#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1605336#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1605312#L487-30 assume !(1 == ~t3_pc~0); 1595782#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1605290#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1605291#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1605263#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1605264#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1605241#L506-30 assume !(1 == ~t4_pc~0); 1605242#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1605220#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1605221#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1605194#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1605195#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1605175#L525-30 assume !(1 == ~t5_pc~0); 1605174#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1605173#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1605170#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1605165#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1605161#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1605157#L544-30 assume 1 == ~t6_pc~0; 1605152#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1605150#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1605148#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1605145#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1605142#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1605138#L563-30 assume !(1 == ~t7_pc~0); 1604222#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1605028#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1605026#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1605021#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1605018#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1605015#L582-30 assume !(1 == ~t8_pc~0); 1596863#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1605010#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1605007#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1605005#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1605002#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1604999#L964-3 assume !(1 == ~M_E~0); 1604995#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1604992#L969-3 assume !(1 == ~T2_E~0); 1604988#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1604983#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1604979#L984-3 assume !(1 == ~T5_E~0); 1604975#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1604970#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1604966#L999-3 assume !(1 == ~T8_E~0); 1604962#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1604957#L1009-3 assume !(1 == ~E_1~0); 1604951#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1604945#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1604938#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1604932#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1604927#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1604922#L1039-3 assume !(1 == ~E_7~0); 1604917#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1604912#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1604907#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1604902#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1604896#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1604891#L1334 assume !(0 == start_simulation_~tmp~3#1); 1604885#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1604879#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1604873#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1604867#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1604859#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1604853#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1604847#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1604839#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1570642#L1315-2 [2021-12-19 19:16:32,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:32,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 5 times [2021-12-19 19:16:32,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:32,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850866148] [2021-12-19 19:16:32,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:32,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:32,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:32,793 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:32,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:32,822 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:32,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:32,824 INFO L85 PathProgramCache]: Analyzing trace with hash -1132105573, now seen corresponding path program 1 times [2021-12-19 19:16:32,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:32,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123122671] [2021-12-19 19:16:32,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:32,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:32,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:32,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:32,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:32,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123122671] [2021-12-19 19:16:32,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123122671] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:32,884 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:32,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:32,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464583621] [2021-12-19 19:16:32,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:32,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:32,885 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:32,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:32,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:32,885 INFO L87 Difference]: Start difference. First operand 78513 states and 108475 transitions. cyclomatic complexity: 29966 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:33,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:33,210 INFO L93 Difference]: Finished difference Result 90353 states and 124346 transitions. [2021-12-19 19:16:33,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:33,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90353 states and 124346 transitions. [2021-12-19 19:16:34,022 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 90176 [2021-12-19 19:16:34,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90353 states to 90353 states and 124346 transitions. [2021-12-19 19:16:34,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90353 [2021-12-19 19:16:34,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90353 [2021-12-19 19:16:34,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90353 states and 124346 transitions. [2021-12-19 19:16:34,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:34,317 INFO L681 BuchiCegarLoop]: Abstraction has 90353 states and 124346 transitions. [2021-12-19 19:16:34,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90353 states and 124346 transitions. [2021-12-19 19:16:34,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90353 to 78609. [2021-12-19 19:16:34,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78609 states, 78609 states have (on average 1.3693343001437495) internal successors, (107642), 78608 states have internal predecessors, (107642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:35,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78609 states to 78609 states and 107642 transitions. [2021-12-19 19:16:35,532 INFO L704 BuchiCegarLoop]: Abstraction has 78609 states and 107642 transitions. [2021-12-19 19:16:35,532 INFO L587 BuchiCegarLoop]: Abstraction has 78609 states and 107642 transitions. [2021-12-19 19:16:35,533 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:16:35,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78609 states and 107642 transitions. [2021-12-19 19:16:35,724 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 78432 [2021-12-19 19:16:35,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:35,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:35,725 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:35,725 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:35,725 INFO L791 eck$LassoCheckResult]: Stem: 1739834#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1739835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1739742#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1739743#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1739560#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1739561#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1739123#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1739124#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1739201#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1740100#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1739094#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1739095#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1739523#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1739547#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1739207#L866 assume !(0 == ~M_E~0); 1739208#L866-2 assume !(0 == ~T1_E~0); 1739774#L871-1 assume !(0 == ~T2_E~0); 1739775#L876-1 assume !(0 == ~T3_E~0); 1740219#L881-1 assume !(0 == ~T4_E~0); 1739788#L886-1 assume !(0 == ~T5_E~0); 1739512#L891-1 assume !(0 == ~T6_E~0); 1739513#L896-1 assume !(0 == ~T7_E~0); 1739778#L901-1 assume !(0 == ~T8_E~0); 1739803#L906-1 assume !(0 == ~E_M~0); 1739804#L911-1 assume !(0 == ~E_1~0); 1739558#L916-1 assume !(0 == ~E_2~0); 1739559#L921-1 assume !(0 == ~E_3~0); 1739942#L926-1 assume !(0 == ~E_4~0); 1740123#L931-1 assume !(0 == ~E_5~0); 1740257#L936-1 assume !(0 == ~E_6~0); 1740280#L941-1 assume !(0 == ~E_7~0); 1739564#L946-1 assume !(0 == ~E_8~0); 1739565#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1740168#L430 assume !(1 == ~m_pc~0); 1739416#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1740061#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1740352#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1739702#L1073 assume !(0 != activate_threads_~tmp~1#1); 1739703#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1739921#L449 assume !(1 == ~t1_pc~0); 1739210#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1739211#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738992#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1738993#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1739822#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1739629#L468 assume !(1 == ~t2_pc~0); 1739019#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1739018#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1739520#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1739421#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1739035#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1739036#L487 assume !(1 == ~t3_pc~0); 1739146#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1739127#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1739128#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1739906#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1739486#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1739487#L506 assume !(1 == ~t4_pc~0); 1739622#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1739679#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1740146#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1740147#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1739619#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1739429#L525 assume !(1 == ~t5_pc~0); 1739072#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1739073#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1739568#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1739569#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1739273#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1739274#L544 assume !(1 == ~t6_pc~0); 1739430#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1739431#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1739845#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1739057#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1739058#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1740081#L563 assume !(1 == ~t7_pc~0); 1739840#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1739083#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1739084#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1739519#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1739214#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1739215#L582 assume !(1 == ~t8_pc~0); 1739846#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1740213#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1740214#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1739473#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1739362#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1739363#L964 assume !(1 == ~M_E~0); 1739923#L964-2 assume !(1 == ~T1_E~0); 1739271#L969-1 assume !(1 == ~T2_E~0); 1739272#L974-1 assume !(1 == ~T3_E~0); 1739961#L979-1 assume !(1 == ~T4_E~0); 1739962#L984-1 assume !(1 == ~T5_E~0); 1739436#L989-1 assume !(1 == ~T6_E~0); 1739437#L994-1 assume !(1 == ~T7_E~0); 1739318#L999-1 assume !(1 == ~T8_E~0); 1739319#L1004-1 assume !(1 == ~E_M~0); 1739059#L1009-1 assume !(1 == ~E_1~0); 1739060#L1014-1 assume !(1 == ~E_2~0); 1739305#L1019-1 assume !(1 == ~E_3~0); 1739912#L1024-1 assume !(1 == ~E_4~0); 1739231#L1029-1 assume !(1 == ~E_5~0); 1739232#L1034-1 assume !(1 == ~E_6~0); 1739331#L1039-1 assume !(1 == ~E_7~0); 1740154#L1044-1 assume !(1 == ~E_8~0); 1739531#L1049-1 assume { :end_inline_reset_delta_events } true; 1739532#L1315-2 [2021-12-19 19:16:35,726 INFO L793 eck$LassoCheckResult]: Loop: 1739532#L1315-2 assume !false; 1743970#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1743969#L841 assume !false; 1743967#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1743963#L662 assume !(0 == ~m_st~0); 1743964#L666 assume !(0 == ~t1_st~0); 1760702#L670 assume !(0 == ~t2_st~0); 1760698#L674 assume !(0 == ~t3_st~0); 1760699#L678 assume !(0 == ~t4_st~0); 1760701#L682 assume !(0 == ~t5_st~0); 1760696#L686 assume !(0 == ~t6_st~0); 1760697#L690 assume !(0 == ~t7_st~0); 1760700#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1760703#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1760688#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1760689#L724 assume !(0 != eval_~tmp~0#1); 1776754#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1776753#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1776752#L866-3 assume !(0 == ~M_E~0); 1776751#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1776750#L871-3 assume !(0 == ~T2_E~0); 1776749#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1776748#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1776747#L886-3 assume !(0 == ~T5_E~0); 1776746#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1776745#L896-3 assume !(0 == ~T7_E~0); 1776744#L901-3 assume !(0 == ~T8_E~0); 1776743#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1776742#L911-3 assume !(0 == ~E_1~0); 1776741#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1776740#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1776739#L926-3 assume !(0 == ~E_4~0); 1776738#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1776737#L936-3 assume !(0 == ~E_6~0); 1776736#L941-3 assume !(0 == ~E_7~0); 1776735#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1776734#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1776733#L430-30 assume 1 == ~m_pc~0; 1776730#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1776731#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1776676#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1776677#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1776940#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1776939#L449-30 assume !(1 == ~t1_pc~0); 1776938#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1776937#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1776936#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1776935#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 1776934#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1776933#L468-30 assume 1 == ~t2_pc~0; 1776931#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1776928#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1776925#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1760694#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1760695#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1760687#L487-30 assume !(1 == ~t3_pc~0); 1760686#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1760685#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1760684#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1760683#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1760682#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1760681#L506-30 assume !(1 == ~t4_pc~0); 1760680#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1760676#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1760674#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1760672#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1760670#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1744050#L525-30 assume !(1 == ~t5_pc~0); 1744048#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1744046#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1744044#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1744042#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1744039#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1744037#L544-30 assume 1 == ~t6_pc~0; 1744034#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1744032#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1744030#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1744027#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1744024#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1744022#L563-30 assume !(1 == ~t7_pc~0); 1743560#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1744018#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1744016#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1744014#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1744013#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1744012#L582-30 assume !(1 == ~t8_pc~0); 1744011#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1744010#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1744009#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1744008#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1744007#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1744006#L964-3 assume !(1 == ~M_E~0); 1744005#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1744004#L969-3 assume !(1 == ~T2_E~0); 1744003#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1744002#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1744001#L984-3 assume !(1 == ~T5_E~0); 1744000#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1743999#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1743998#L999-3 assume !(1 == ~T8_E~0); 1743997#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1743996#L1009-3 assume !(1 == ~E_1~0); 1743995#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1743994#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1743993#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1743992#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1743991#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1743990#L1039-3 assume !(1 == ~E_7~0); 1743989#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1743988#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1743986#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1743985#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1743984#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1743982#L1334 assume !(0 == start_simulation_~tmp~3#1); 1743981#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1743979#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1743978#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1743977#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1743976#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1743975#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1743974#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1743973#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1739532#L1315-2 [2021-12-19 19:16:35,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:35,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 6 times [2021-12-19 19:16:35,726 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:35,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840951355] [2021-12-19 19:16:35,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:35,726 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:35,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:35,734 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:35,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:35,763 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:35,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:35,764 INFO L85 PathProgramCache]: Analyzing trace with hash 601998877, now seen corresponding path program 1 times [2021-12-19 19:16:35,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:35,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459343274] [2021-12-19 19:16:35,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:35,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:35,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:35,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:35,824 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:35,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459343274] [2021-12-19 19:16:35,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459343274] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:35,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:35,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:35,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637011100] [2021-12-19 19:16:35,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:35,825 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:35,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:35,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:35,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:35,826 INFO L87 Difference]: Start difference. First operand 78609 states and 107642 transitions. cyclomatic complexity: 29037 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:36,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:36,340 INFO L93 Difference]: Finished difference Result 145553 states and 199097 transitions. [2021-12-19 19:16:36,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:36,341 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145553 states and 199097 transitions. [2021-12-19 19:16:36,906 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 145312 [2021-12-19 19:16:37,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145553 states to 145553 states and 199097 transitions. [2021-12-19 19:16:37,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145553 [2021-12-19 19:16:37,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145553 [2021-12-19 19:16:37,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145553 states and 199097 transitions. [2021-12-19 19:16:37,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:37,992 INFO L681 BuchiCegarLoop]: Abstraction has 145553 states and 199097 transitions. [2021-12-19 19:16:38,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145553 states and 199097 transitions. [2021-12-19 19:16:38,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145553 to 80145. [2021-12-19 19:16:38,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80145 states, 80145 states have (on average 1.3566535654126894) internal successors, (108729), 80144 states have internal predecessors, (108729), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:39,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80145 states to 80145 states and 108729 transitions. [2021-12-19 19:16:39,025 INFO L704 BuchiCegarLoop]: Abstraction has 80145 states and 108729 transitions. [2021-12-19 19:16:39,025 INFO L587 BuchiCegarLoop]: Abstraction has 80145 states and 108729 transitions. [2021-12-19 19:16:39,025 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-19 19:16:39,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80145 states and 108729 transitions. [2021-12-19 19:16:39,740 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 79968 [2021-12-19 19:16:39,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:39,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:39,742 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:39,742 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:39,742 INFO L791 eck$LassoCheckResult]: Stem: 1963977#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1963978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1963894#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1963895#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1963722#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1963723#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1963300#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1963301#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1963377#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1964215#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1963271#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1963272#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1963689#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1963711#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1963383#L866 assume !(0 == ~M_E~0); 1963384#L866-2 assume !(0 == ~T1_E~0); 1963924#L871-1 assume !(0 == ~T2_E~0); 1963925#L876-1 assume !(0 == ~T3_E~0); 1964314#L881-1 assume !(0 == ~T4_E~0); 1963935#L886-1 assume !(0 == ~T5_E~0); 1963678#L891-1 assume !(0 == ~T6_E~0); 1963679#L896-1 assume !(0 == ~T7_E~0); 1963927#L901-1 assume !(0 == ~T8_E~0); 1963950#L906-1 assume !(0 == ~E_M~0); 1963951#L911-1 assume !(0 == ~E_1~0); 1963720#L916-1 assume !(0 == ~E_2~0); 1963721#L921-1 assume !(0 == ~E_3~0); 1964064#L926-1 assume !(0 == ~E_4~0); 1964233#L931-1 assume !(0 == ~E_5~0); 1964329#L936-1 assume !(0 == ~E_6~0); 1964348#L941-1 assume !(0 == ~E_7~0); 1963727#L946-1 assume !(0 == ~E_8~0); 1963728#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1964275#L430 assume !(1 == ~m_pc~0); 1963586#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1964178#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1964384#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1963854#L1073 assume !(0 != activate_threads_~tmp~1#1); 1963855#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1964046#L449 assume !(1 == ~t1_pc~0); 1963386#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1963387#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1963168#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1963169#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1963964#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1963788#L468 assume !(1 == ~t2_pc~0); 1963195#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1963194#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1963686#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1963591#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1963211#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1963212#L487 assume !(1 == ~t3_pc~0); 1963323#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1963304#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1963305#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1964033#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1963654#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1963655#L506 assume !(1 == ~t4_pc~0); 1963780#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1963835#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1964249#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1964250#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1963777#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1963600#L525 assume !(1 == ~t5_pc~0); 1963248#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1963249#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1963730#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1963731#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1963444#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1963445#L544 assume !(1 == ~t6_pc~0); 1963601#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1963602#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1963987#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1963233#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1963234#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1964200#L563 assume !(1 == ~t7_pc~0); 1963983#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1963259#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1963260#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1963685#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1963390#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1963391#L582 assume !(1 == ~t8_pc~0); 1963990#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1964306#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1964307#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1963644#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1963534#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1963535#L964 assume !(1 == ~M_E~0); 1964049#L964-2 assume !(1 == ~T1_E~0); 1963446#L969-1 assume !(1 == ~T2_E~0); 1963447#L974-1 assume !(1 == ~T3_E~0); 1964083#L979-1 assume !(1 == ~T4_E~0); 1964084#L984-1 assume !(1 == ~T5_E~0); 1963607#L989-1 assume !(1 == ~T6_E~0); 1963608#L994-1 assume !(1 == ~T7_E~0); 1963490#L999-1 assume !(1 == ~T8_E~0); 1963491#L1004-1 assume !(1 == ~E_M~0); 1963235#L1009-1 assume !(1 == ~E_1~0); 1963236#L1014-1 assume !(1 == ~E_2~0); 1963479#L1019-1 assume !(1 == ~E_3~0); 1964038#L1024-1 assume !(1 == ~E_4~0); 1963407#L1029-1 assume !(1 == ~E_5~0); 1963408#L1034-1 assume !(1 == ~E_6~0); 1963502#L1039-1 assume !(1 == ~E_7~0); 1964257#L1044-1 assume !(1 == ~E_8~0); 1963697#L1049-1 assume { :end_inline_reset_delta_events } true; 1963698#L1315-2 [2021-12-19 19:16:39,743 INFO L793 eck$LassoCheckResult]: Loop: 1963698#L1315-2 assume !false; 1985504#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1985396#L841 assume !false; 1985503#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1985502#L662 assume !(0 == ~m_st~0); 1982364#L666 assume !(0 == ~t1_st~0); 1987795#L670 assume !(0 == ~t2_st~0); 1987791#L674 assume !(0 == ~t3_st~0); 1987792#L678 assume !(0 == ~t4_st~0); 1987794#L682 assume !(0 == ~t5_st~0); 1987789#L686 assume !(0 == ~t6_st~0); 1987790#L690 assume !(0 == ~t7_st~0); 1987793#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1987796#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1987770#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1987771#L724 assume !(0 != eval_~tmp~0#1); 2031788#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2031787#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2031786#L866-3 assume !(0 == ~M_E~0); 2031785#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2031784#L871-3 assume !(0 == ~T2_E~0); 2031783#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2031782#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2031781#L886-3 assume !(0 == ~T5_E~0); 2031780#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2031779#L896-3 assume !(0 == ~T7_E~0); 2031778#L901-3 assume !(0 == ~T8_E~0); 2031777#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2031776#L911-3 assume !(0 == ~E_1~0); 2031775#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2031774#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2031773#L926-3 assume !(0 == ~E_4~0); 2031772#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2031771#L936-3 assume !(0 == ~E_6~0); 2031770#L941-3 assume !(0 == ~E_7~0); 2031769#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2031768#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2031767#L430-30 assume 1 == ~m_pc~0; 2031765#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2031764#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2031763#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2031761#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2031760#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2031759#L449-30 assume !(1 == ~t1_pc~0); 2031758#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2031757#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2031756#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2031755#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 2031754#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2031753#L468-30 assume !(1 == ~t2_pc~0); 2031752#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2031750#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2031749#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2031748#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2031747#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1980334#L487-30 assume !(1 == ~t3_pc~0); 1980332#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1980330#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1980328#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1980326#L1097-30 assume !(0 != activate_threads_~tmp___2~0#1); 1980324#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1980322#L506-30 assume 1 == ~t4_pc~0; 1980319#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1980316#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1980314#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1980312#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1980310#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1980308#L525-30 assume !(1 == ~t5_pc~0); 1977124#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1980306#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1980304#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1980302#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1980300#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1980298#L544-30 assume !(1 == ~t6_pc~0); 1980296#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1980292#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1980290#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1980288#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1980286#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1980284#L563-30 assume !(1 == ~t7_pc~0); 1968980#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1980282#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1980280#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1980278#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1980276#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1980274#L582-30 assume !(1 == ~t8_pc~0); 1976983#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1980272#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1980270#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1980268#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1980266#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1980263#L964-3 assume !(1 == ~M_E~0); 1980264#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1985533#L969-3 assume !(1 == ~T2_E~0); 1985532#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1985531#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1985530#L984-3 assume !(1 == ~T5_E~0); 1985529#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1985528#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1985527#L999-3 assume !(1 == ~T8_E~0); 1985526#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1985525#L1009-3 assume !(1 == ~E_1~0); 1985524#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1985523#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1985522#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1985521#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1985520#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1985519#L1039-3 assume !(1 == ~E_7~0); 1985518#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1985517#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1985516#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1985515#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1985514#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1985513#L1334 assume !(0 == start_simulation_~tmp~3#1); 1985512#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1985511#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1985510#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1985509#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1985508#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1985507#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1985506#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1985505#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1963698#L1315-2 [2021-12-19 19:16:39,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:39,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 7 times [2021-12-19 19:16:39,744 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:39,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903222109] [2021-12-19 19:16:39,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:39,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:39,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:39,751 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:39,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:39,771 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:39,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:39,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1538705824, now seen corresponding path program 1 times [2021-12-19 19:16:39,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:39,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476695867] [2021-12-19 19:16:39,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:39,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:39,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:39,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:39,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:39,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476695867] [2021-12-19 19:16:39,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476695867] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:39,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:39,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:39,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546163775] [2021-12-19 19:16:39,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:39,801 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:39,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:39,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:39,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:39,801 INFO L87 Difference]: Start difference. First operand 80145 states and 108729 transitions. cyclomatic complexity: 28588 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:40,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:40,292 INFO L93 Difference]: Finished difference Result 157345 states and 211612 transitions. [2021-12-19 19:16:40,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-19 19:16:40,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157345 states and 211612 transitions. [2021-12-19 19:16:40,869 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 157056 [2021-12-19 19:16:41,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157345 states to 157345 states and 211612 transitions. [2021-12-19 19:16:41,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 157345 [2021-12-19 19:16:41,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 157345 [2021-12-19 19:16:41,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157345 states and 211612 transitions. [2021-12-19 19:16:41,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:41,950 INFO L681 BuchiCegarLoop]: Abstraction has 157345 states and 211612 transitions. [2021-12-19 19:16:41,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157345 states and 211612 transitions. [2021-12-19 19:16:42,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157345 to 83028. [2021-12-19 19:16:42,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83028 states, 83028 states have (on average 1.3442694030929325) internal successors, (111612), 83027 states have internal predecessors, (111612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:42,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83028 states to 83028 states and 111612 transitions. [2021-12-19 19:16:42,816 INFO L704 BuchiCegarLoop]: Abstraction has 83028 states and 111612 transitions. [2021-12-19 19:16:42,816 INFO L587 BuchiCegarLoop]: Abstraction has 83028 states and 111612 transitions. [2021-12-19 19:16:42,816 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-19 19:16:42,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83028 states and 111612 transitions. [2021-12-19 19:16:43,032 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 82848 [2021-12-19 19:16:43,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:43,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:43,034 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:43,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:43,035 INFO L791 eck$LassoCheckResult]: Stem: 2201480#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2201481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2201390#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2201391#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2201227#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2201228#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2200804#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2200805#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2200882#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2201720#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2200775#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2200776#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2201195#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2201216#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2200888#L866 assume !(0 == ~M_E~0); 2200889#L866-2 assume !(0 == ~T1_E~0); 2201422#L871-1 assume !(0 == ~T2_E~0); 2201423#L876-1 assume !(0 == ~T3_E~0); 2201807#L881-1 assume !(0 == ~T4_E~0); 2201434#L886-1 assume !(0 == ~T5_E~0); 2201184#L891-1 assume !(0 == ~T6_E~0); 2201185#L896-1 assume !(0 == ~T7_E~0); 2201426#L901-1 assume !(0 == ~T8_E~0); 2201450#L906-1 assume !(0 == ~E_M~0); 2201451#L911-1 assume !(0 == ~E_1~0); 2201225#L916-1 assume !(0 == ~E_2~0); 2201226#L921-1 assume !(0 == ~E_3~0); 2201580#L926-1 assume !(0 == ~E_4~0); 2201735#L931-1 assume !(0 == ~E_5~0); 2201824#L936-1 assume !(0 == ~E_6~0); 2201848#L941-1 assume !(0 == ~E_7~0); 2201232#L946-1 assume !(0 == ~E_8~0); 2201233#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2201773#L430 assume !(1 == ~m_pc~0); 2201092#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2201688#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2201893#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2201353#L1073 assume !(0 != activate_threads_~tmp~1#1); 2201354#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2201559#L449 assume !(1 == ~t1_pc~0); 2200891#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2200892#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2200672#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2200673#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2201468#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2201292#L468 assume !(1 == ~t2_pc~0); 2200699#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2200698#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2201192#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2201097#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2200715#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2200716#L487 assume !(1 == ~t3_pc~0); 2200827#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2200808#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2200809#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2201541#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2201160#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2201161#L506 assume !(1 == ~t4_pc~0); 2201285#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2201817#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2201895#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2201894#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2201283#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2201105#L525 assume !(1 == ~t5_pc~0); 2200752#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2200753#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2201235#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2201236#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2200949#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2200950#L544 assume !(1 == ~t6_pc~0); 2201106#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2201107#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2201488#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2200737#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2200738#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2201705#L563 assume !(1 == ~t7_pc~0); 2201485#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2200763#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2200764#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2201191#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2200895#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2200896#L582 assume !(1 == ~t8_pc~0); 2201491#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2201797#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2201798#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2201149#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2201040#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2201041#L964 assume !(1 == ~M_E~0); 2201564#L964-2 assume !(1 == ~T1_E~0); 2200951#L969-1 assume !(1 == ~T2_E~0); 2200952#L974-1 assume !(1 == ~T3_E~0); 2201595#L979-1 assume !(1 == ~T4_E~0); 2201596#L984-1 assume !(1 == ~T5_E~0); 2201112#L989-1 assume !(1 == ~T6_E~0); 2201113#L994-1 assume !(1 == ~T7_E~0); 2200995#L999-1 assume !(1 == ~T8_E~0); 2200996#L1004-1 assume !(1 == ~E_M~0); 2200739#L1009-1 assume !(1 == ~E_1~0); 2200740#L1014-1 assume !(1 == ~E_2~0); 2200984#L1019-1 assume !(1 == ~E_3~0); 2201546#L1024-1 assume !(1 == ~E_4~0); 2200912#L1029-1 assume !(1 == ~E_5~0); 2200913#L1034-1 assume !(1 == ~E_6~0); 2201007#L1039-1 assume !(1 == ~E_7~0); 2201760#L1044-1 assume !(1 == ~E_8~0); 2201203#L1049-1 assume { :end_inline_reset_delta_events } true; 2201204#L1315-2 [2021-12-19 19:16:43,035 INFO L793 eck$LassoCheckResult]: Loop: 2201204#L1315-2 assume !false; 2248062#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2248060#L841 assume !false; 2248058#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2248056#L662 assume !(0 == ~m_st~0); 2200946#L666 assume !(0 == ~t1_st~0); 2201375#L670 assume !(0 == ~t2_st~0); 2201377#L674 assume !(0 == ~t3_st~0); 2201588#L678 assume !(0 == ~t4_st~0); 2201409#L682 assume !(0 == ~t5_st~0); 2201410#L686 assume !(0 == ~t6_st~0); 2201873#L690 assume !(0 == ~t7_st~0); 2201809#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 2201810#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2283698#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2283697#L724 assume !(0 != eval_~tmp~0#1); 2283696#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2283695#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2283694#L866-3 assume !(0 == ~M_E~0); 2201802#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2201014#L871-3 assume !(0 == ~T2_E~0); 2201015#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2201029#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2201030#L886-3 assume !(0 == ~T5_E~0); 2201260#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2201261#L896-3 assume !(0 == ~T7_E~0); 2201431#L901-3 assume !(0 == ~T8_E~0); 2283669#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2283667#L911-3 assume !(0 == ~E_1~0); 2201501#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2201061#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2201062#L926-3 assume !(0 == ~E_4~0); 2201482#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2201136#L936-3 assume !(0 == ~E_6~0); 2201137#L941-3 assume !(0 == ~E_7~0); 2201278#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2201016#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2201017#L430-30 assume 1 == ~m_pc~0; 2201042#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2201043#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2283678#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2283677#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2201861#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2201535#L449-30 assume !(1 == ~t1_pc~0); 2201536#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2200735#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2200736#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2201111#L1081-30 assume !(0 != activate_threads_~tmp___0~0#1); 2200817#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2200818#L468-30 assume 1 == ~t2_pc~0; 2200906#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2200907#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2201592#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2201850#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2283566#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2280422#L487-30 assume !(1 == ~t3_pc~0); 2280420#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2280417#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2280415#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2280396#L1097-30 assume !(0 != activate_threads_~tmp___2~0#1); 2278577#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2278576#L506-30 assume !(1 == ~t4_pc~0); 2278574#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2278572#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2278570#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2278568#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2278566#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2278563#L525-30 assume !(1 == ~t5_pc~0); 2258359#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2278560#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2278558#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2278556#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2278554#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2278553#L544-30 assume 1 == ~t6_pc~0; 2278550#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2278548#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2278546#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2278379#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2278377#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2255233#L563-30 assume !(1 == ~t7_pc~0); 2255220#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2255214#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2255192#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2255190#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2255188#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2248207#L582-30 assume !(1 == ~t8_pc~0); 2248205#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2248203#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2248198#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2248196#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2248194#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2248191#L964-3 assume !(1 == ~M_E~0); 2248189#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2248187#L969-3 assume !(1 == ~T2_E~0); 2248185#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2248183#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2248180#L984-3 assume !(1 == ~T5_E~0); 2248178#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2248176#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2248174#L999-3 assume !(1 == ~T8_E~0); 2248172#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2248170#L1009-3 assume !(1 == ~E_1~0); 2248168#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2248167#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2248166#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2248165#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2248164#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2248163#L1039-3 assume !(1 == ~E_7~0); 2248161#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2248159#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2248156#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2248154#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2248152#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2248150#L1334 assume !(0 == start_simulation_~tmp~3#1); 2248149#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2248148#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2248144#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2248142#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2248140#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2248139#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2248138#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2248136#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2201204#L1315-2 [2021-12-19 19:16:43,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:43,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 8 times [2021-12-19 19:16:43,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:43,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516466180] [2021-12-19 19:16:43,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:43,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:43,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:43,043 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:16:43,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:16:43,064 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:16:43,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:43,065 INFO L85 PathProgramCache]: Analyzing trace with hash 184602271, now seen corresponding path program 1 times [2021-12-19 19:16:43,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:43,065 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834223829] [2021-12-19 19:16:43,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:43,065 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:43,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:43,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:43,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:43,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834223829] [2021-12-19 19:16:43,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834223829] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:43,106 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:43,106 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:43,106 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531617076] [2021-12-19 19:16:43,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:43,106 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:43,106 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:43,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:43,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:43,107 INFO L87 Difference]: Start difference. First operand 83028 states and 111612 transitions. cyclomatic complexity: 28588 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:44,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:44,155 INFO L93 Difference]: Finished difference Result 145396 states and 195659 transitions. [2021-12-19 19:16:44,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:44,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145396 states and 195659 transitions. [2021-12-19 19:16:44,711 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 145152 [2021-12-19 19:16:45,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145396 states to 145396 states and 195659 transitions. [2021-12-19 19:16:45,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145396 [2021-12-19 19:16:45,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145396 [2021-12-19 19:16:45,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145396 states and 195659 transitions. [2021-12-19 19:16:45,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:45,242 INFO L681 BuchiCegarLoop]: Abstraction has 145396 states and 195659 transitions. [2021-12-19 19:16:45,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145396 states and 195659 transitions.