./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:16:21,659 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:16:21,670 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:16:21,704 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:16:21,704 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:16:21,705 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:16:21,706 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:16:21,708 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:16:21,709 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:16:21,709 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:16:21,710 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:16:21,711 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:16:21,711 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:16:21,712 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:16:21,713 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:16:21,714 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:16:21,717 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:16:21,720 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:16:21,721 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:16:21,732 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:16:21,733 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:16:21,734 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:16:21,735 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:16:21,736 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:16:21,738 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:16:21,738 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:16:21,738 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:16:21,739 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:16:21,740 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:16:21,740 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:16:21,741 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:16:21,741 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:16:21,742 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:16:21,743 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:16:21,743 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:16:21,744 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:16:21,744 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:16:21,745 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:16:21,745 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:16:21,746 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:16:21,746 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:16:21,747 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:16:21,767 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:16:21,767 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:16:21,768 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:16:21,768 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:16:21,769 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:16:21,769 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:16:21,769 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:16:21,769 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:16:21,770 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:16:21,770 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:16:21,770 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:16:21,770 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:16:21,770 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:16:21,771 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:16:21,771 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:16:21,771 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:16:21,772 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:16:21,772 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:16:21,773 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:16:21,774 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:16:21,774 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:16:21,774 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:16:21,775 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:16:21,775 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:16:21,775 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:16:21,775 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:16:21,776 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:16:21,776 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:16:21,776 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2021-12-19 19:16:21,959 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:16:21,978 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:16:21,980 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:16:21,982 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:16:21,983 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:16:21,984 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2021-12-19 19:16:22,039 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3cf48d433/a46afaaff3df418eaff8553936a895c6/FLAG09e58a340 [2021-12-19 19:16:22,442 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:16:22,444 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2021-12-19 19:16:22,458 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3cf48d433/a46afaaff3df418eaff8553936a895c6/FLAG09e58a340 [2021-12-19 19:16:22,831 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3cf48d433/a46afaaff3df418eaff8553936a895c6 [2021-12-19 19:16:22,833 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:16:22,834 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:16:22,835 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:22,835 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:16:22,840 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:16:22,840 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:22" (1/1) ... [2021-12-19 19:16:22,841 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52487ac0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:22, skipping insertion in model container [2021-12-19 19:16:22,841 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:22" (1/1) ... [2021-12-19 19:16:22,845 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:16:22,894 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:16:23,010 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2021-12-19 19:16:23,078 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:23,086 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:16:23,096 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2021-12-19 19:16:23,138 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:23,152 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:16:23,153 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23 WrapperNode [2021-12-19 19:16:23,153 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:23,154 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:23,154 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:16:23,154 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:16:23,160 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,174 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,238 INFO L137 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2769 [2021-12-19 19:16:23,239 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:23,239 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:16:23,240 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:16:23,240 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:16:23,246 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,246 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,253 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,254 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,278 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,296 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,299 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,306 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:16:23,313 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:16:23,313 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:16:23,313 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:16:23,314 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (1/1) ... [2021-12-19 19:16:23,319 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:23,327 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:23,337 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:23,340 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:16:23,370 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:16:23,371 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:16:23,371 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:16:23,371 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:16:23,464 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:16:23,465 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:16:24,528 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:16:24,537 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:16:24,538 INFO L301 CfgBuilder]: Removed 12 assume(true) statements. [2021-12-19 19:16:24,539 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:24 BoogieIcfgContainer [2021-12-19 19:16:24,540 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:16:24,540 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:16:24,541 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:16:24,542 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:16:24,556 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:24,556 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:16:22" (1/3) ... [2021-12-19 19:16:24,557 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@252a5489 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:24, skipping insertion in model container [2021-12-19 19:16:24,557 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:24,557 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:23" (2/3) ... [2021-12-19 19:16:24,558 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@252a5489 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:24, skipping insertion in model container [2021-12-19 19:16:24,558 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:24,558 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:24" (3/3) ... [2021-12-19 19:16:24,559 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2021-12-19 19:16:24,583 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:16:24,584 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:16:24,584 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:16:24,584 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:16:24,584 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:16:24,584 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:16:24,584 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:16:24,584 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:16:24,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:24,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2021-12-19 19:16:24,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:24,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:24,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,663 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:16:24,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:24,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2021-12-19 19:16:24,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:24,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:24,677 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,677 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:24,683 INFO L791 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1076#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1021#L1403true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 588#L663true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 494#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 301#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 814#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 898#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1012#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 876#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1164#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 378#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 370#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 511#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 254#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 755#L951true assume !(0 == ~M_E~0); 109#L951-2true assume !(0 == ~T1_E~0); 196#L956-1true assume !(0 == ~T2_E~0); 1133#L961-1true assume !(0 == ~T3_E~0); 509#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 637#L971-1true assume !(0 == ~T5_E~0); 1065#L976-1true assume !(0 == ~T6_E~0); 610#L981-1true assume !(0 == ~T7_E~0); 403#L986-1true assume !(0 == ~T8_E~0); 225#L991-1true assume !(0 == ~T9_E~0); 1106#L996-1true assume !(0 == ~E_M~0); 985#L1001-1true assume !(0 == ~E_1~0); 561#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 899#L1011-1true assume !(0 == ~E_3~0); 937#L1016-1true assume !(0 == ~E_4~0); 1078#L1021-1true assume !(0 == ~E_5~0); 22#L1026-1true assume !(0 == ~E_6~0); 1142#L1031-1true assume !(0 == ~E_7~0); 520#L1036-1true assume !(0 == ~E_8~0); 517#L1041-1true assume !(0 == ~E_9~0); 825#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1068#L472true assume 1 == ~m_pc~0; 1020#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 543#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1018#L484true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 553#L1179true assume !(0 != activate_threads_~tmp~1#1); 26#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 870#L491true assume 1 == ~t1_pc~0; 559#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 621#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514#L503true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 23#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 808#L510true assume !(1 == ~t2_pc~0); 7#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 979#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 828#L522true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1141#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407#L529true assume 1 == ~t3_pc~0; 347#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 747#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 958#L541true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1056#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 98#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1107#L548true assume !(1 == ~t4_pc~0); 308#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 201#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 894#L560true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 619#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47#L567true assume 1 == ~t5_pc~0; 866#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1082#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160#L579true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1010#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 805#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103#L586true assume !(1 == ~t6_pc~0); 139#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1006#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1168#L598true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1172#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 799#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1104#L605true assume 1 == ~t7_pc~0; 737#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 545#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512#L617true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1089#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1077#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488#L624true assume !(1 == ~t8_pc~0); 1042#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 597#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 537#L636true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 768#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1148#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33#L643true assume 1 == ~t9_pc~0; 833#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 692#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 612#L655true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 228#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1103#L1251-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124#L1059true assume !(1 == ~M_E~0); 1176#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 212#L1064-1true assume !(1 == ~T2_E~0); 700#L1069-1true assume !(1 == ~T3_E~0); 1064#L1074-1true assume !(1 == ~T4_E~0); 763#L1079-1true assume !(1 == ~T5_E~0); 736#L1084-1true assume !(1 == ~T6_E~0); 909#L1089-1true assume !(1 == ~T7_E~0); 790#L1094-1true assume !(1 == ~T8_E~0); 427#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 925#L1104-1true assume !(1 == ~E_M~0); 601#L1109-1true assume !(1 == ~E_1~0); 295#L1114-1true assume !(1 == ~E_2~0); 1112#L1119-1true assume !(1 == ~E_3~0); 331#L1124-1true assume !(1 == ~E_4~0); 31#L1129-1true assume !(1 == ~E_5~0); 497#L1134-1true assume !(1 == ~E_6~0); 194#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 306#L1144-1true assume !(1 == ~E_8~0); 1153#L1149-1true assume !(1 == ~E_9~0); 106#L1154-1true assume { :end_inline_reset_delta_events } true; 174#L1440-2true [2021-12-19 19:16:24,684 INFO L793 eck$LassoCheckResult]: Loop: 174#L1440-2true assume !false; 964#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 826#L926true assume false; 423#L941true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 765#L663-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245#L951-3true assume !(0 == ~M_E~0); 1143#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 651#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 491#L961-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 320#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 918#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 538#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 41#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 238#L986-3true assume !(0 == ~T8_E~0); 32#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 762#L1001-3true assume 0 == ~E_1~0;~E_1~0 := 1; 305#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 658#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 896#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 709#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 440#L1026-3true assume !(0 == ~E_6~0); 1059#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 627#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1118#L1041-3true assume 0 == ~E_9~0;~E_9~0 := 1; 695#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650#L472-33true assume 1 == ~m_pc~0; 771#L473-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 904#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11#L484-11true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 655#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 325#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1045#L491-33true assume 1 == ~t1_pc~0; 554#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 956#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1184#L503-11true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1001#L1187-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1063#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 605#L510-33true assume !(1 == ~t2_pc~0); 603#L510-35true is_transmit2_triggered_~__retres1~2#1 := 0; 987#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 510#L522-11true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 716#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152#L529-33true assume !(1 == ~t3_pc~0); 208#L529-35true is_transmit3_triggered_~__retres1~3#1 := 0; 143#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 947#L541-11true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1007#L1203-33true assume !(0 != activate_threads_~tmp___2~0#1); 61#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183#L548-33true assume !(1 == ~t4_pc~0); 1163#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 570#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278#L560-11true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L567-33true assume 1 == ~t5_pc~0; 414#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 353#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 957#L579-11true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1119#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508#L586-33true assume 1 == ~t6_pc~0; 478#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 546#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 436#L598-11true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1138#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 157#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261#L605-33true assume 1 == ~t7_pc~0; 1177#L606-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 120#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357#L617-11true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1108#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142#L624-33true assume !(1 == ~t8_pc~0); 146#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1039#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130#L636-11true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 270#L1243-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1154#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121#L643-33true assume 1 == ~t9_pc~0; 513#L644-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 459#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1099#L655-11true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 425#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 785#L1251-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62#L1059-3true assume 1 == ~M_E~0;~M_E~0 := 2; 339#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1170#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 376#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 611#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 859#L1079-3true assume !(1 == ~T5_E~0); 522#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 458#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 572#L1094-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 396#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 631#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 932#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 618#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1031#L1119-3true assume !(1 == ~E_3~0); 1167#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1061#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 216#L1134-3true assume 1 == ~E_6~0;~E_6~0 := 2; 472#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 317#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 428#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1159#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1095#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 729#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13#L781-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16#L1459true assume !(0 == start_simulation_~tmp~3#1); 712#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 891#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 527#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1134#L781-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 243#L1414true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 342#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 482#L1422true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 708#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 174#L1440-2true [2021-12-19 19:16:24,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:24,688 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2021-12-19 19:16:24,696 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:24,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760804339] [2021-12-19 19:16:24,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:24,697 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:24,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:24,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:24,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:24,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760804339] [2021-12-19 19:16:24,851 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760804339] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:24,851 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:24,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:24,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437933914] [2021-12-19 19:16:24,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:24,862 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:24,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:24,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1822815513, now seen corresponding path program 1 times [2021-12-19 19:16:24,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:24,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428908739] [2021-12-19 19:16:24,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:24,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:24,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:24,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:24,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:24,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428908739] [2021-12-19 19:16:24,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428908739] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:24,926 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:24,926 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:24,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578932701] [2021-12-19 19:16:24,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:24,927 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:24,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:24,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:24,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:24,973 INFO L87 Difference]: Start difference. First operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,018 INFO L93 Difference]: Finished difference Result 1181 states and 1757 transitions. [2021-12-19 19:16:25,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1757 transitions. [2021-12-19 19:16:25,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1175 states and 1751 transitions. [2021-12-19 19:16:25,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1751 transitions. [2021-12-19 19:16:25,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,066 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2021-12-19 19:16:25,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1751 transitions. [2021-12-19 19:16:25,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.490212765957447) internal successors, (1751), 1174 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1751 transitions. [2021-12-19 19:16:25,118 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2021-12-19 19:16:25,118 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2021-12-19 19:16:25,118 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:16:25,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1751 transitions. [2021-12-19 19:16:25,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,126 INFO L791 eck$LassoCheckResult]: Stem: 3275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3535#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3294#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2945#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2946#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3453#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3485#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3477#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3478#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3058#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3048#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3049#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2869#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2870#L951 assume !(0 == ~M_E~0); 2608#L951-2 assume !(0 == ~T1_E~0); 2609#L956-1 assume !(0 == ~T2_E~0); 2769#L961-1 assume !(0 == ~T3_E~0); 3210#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3211#L971-1 assume !(0 == ~T5_E~0); 3350#L976-1 assume !(0 == ~T6_E~0); 3321#L981-1 assume !(0 == ~T7_E~0); 3094#L986-1 assume !(0 == ~T8_E~0); 2822#L991-1 assume !(0 == ~T9_E~0); 2823#L996-1 assume !(0 == ~E_M~0); 3516#L1001-1 assume !(0 == ~E_1~0); 3273#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3274#L1011-1 assume !(0 == ~E_3~0); 3487#L1016-1 assume !(0 == ~E_4~0); 3499#L1021-1 assume !(0 == ~E_5~0); 2415#L1026-1 assume !(0 == ~E_6~0); 2416#L1031-1 assume !(0 == ~E_7~0); 3222#L1036-1 assume !(0 == ~E_8~0); 3218#L1041-1 assume !(0 == ~E_9~0); 3219#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3460#L472 assume 1 == ~m_pc~0; 3534#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3253#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3261#L1179 assume !(0 != activate_threads_~tmp~1#1); 2423#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2424#L491 assume 1 == ~t1_pc~0; 3270#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2920#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2395#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2396#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2419#L510 assume !(1 == ~t2_pc~0); 2382#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2383#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3463#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3464#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2664#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2665#L529 assume 1 == ~t3_pc~0; 3015#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3016#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3427#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3509#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2585#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L548 assume !(1 == ~t4_pc~0); 2483#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2482#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2527#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2528#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2470#L567 assume 1 == ~t5_pc~0; 2471#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2529#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2710#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2711#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3448#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2596#L586 assume !(1 == ~t6_pc~0); 2597#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2670#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3531#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3547#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3444#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3445#L605 assume 1 == ~t7_pc~0; 3424#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3075#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3214#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3215#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3543#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3190#L624 assume !(1 == ~t8_pc~0); 2658#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2657#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3246#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3247#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3432#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2438#L643 assume 1 == ~t9_pc~0; 2439#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3389#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3323#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2829#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2830#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2640#L1059 assume !(1 == ~M_E~0); 2641#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2797#L1064-1 assume !(1 == ~T2_E~0); 2798#L1069-1 assume !(1 == ~T3_E~0); 3396#L1074-1 assume !(1 == ~T4_E~0); 3430#L1079-1 assume !(1 == ~T5_E~0); 3422#L1084-1 assume !(1 == ~T6_E~0); 3423#L1089-1 assume !(1 == ~T7_E~0); 3440#L1094-1 assume !(1 == ~T8_E~0); 3123#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3124#L1104-1 assume !(1 == ~E_M~0); 3309#L1109-1 assume !(1 == ~E_1~0); 2938#L1114-1 assume !(1 == ~E_2~0); 2939#L1119-1 assume !(1 == ~E_3~0); 2991#L1124-1 assume !(1 == ~E_4~0); 2434#L1129-1 assume !(1 == ~E_5~0); 2435#L1134-1 assume !(1 == ~E_6~0); 2765#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2766#L1144-1 assume !(1 == ~E_8~0); 2953#L1149-1 assume !(1 == ~E_9~0); 2602#L1154-1 assume { :end_inline_reset_delta_events } true; 2603#L1440-2 [2021-12-19 19:16:25,127 INFO L793 eck$LassoCheckResult]: Loop: 2603#L1440-2 assume !false; 2732#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2374#L926 assume !false; 2993#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2994#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2692#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2693#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2698#L795 assume !(0 != eval_~tmp~0#1); 2699#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3118#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2854#L951-3 assume !(0 == ~M_E~0); 2855#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3358#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3194#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2977#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2978#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3248#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2456#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2457#L986-3 assume !(0 == ~T8_E~0); 2436#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2437#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3344#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3366#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3401#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3141#L1026-3 assume !(0 == ~E_6~0); 3142#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3338#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3339#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3394#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3356#L472-33 assume !(1 == ~m_pc~0); 2555#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2556#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2391#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2392#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2982#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2983#L491-33 assume !(1 == ~t1_pc~0); 2489#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2490#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3507#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3526#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3527#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3315#L510-33 assume 1 == ~t2_pc~0; 3316#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3311#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3212#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3213#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2375#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2376#L529-33 assume 1 == ~t3_pc~0; 2403#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2404#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2677#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3503#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2506#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2507#L548-33 assume 1 == ~t4_pc~0; 2750#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2871#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2911#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2912#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2687#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2688#L567-33 assume 1 == ~t5_pc~0; 3108#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2793#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3026#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3508#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3539#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3209#L586-33 assume !(1 == ~t6_pc~0); 2810#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2811#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3135#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3136#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2702#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2703#L605-33 assume !(1 == ~t7_pc~0); 2878#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2625#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2626#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3030#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2518#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2519#L624-33 assume 1 == ~t8_pc~0; 2673#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2681#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2652#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2653#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2894#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2627#L643-33 assume 1 == ~t9_pc~0; 2628#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2720#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3166#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3119#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3120#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2508#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3005#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3055#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3056#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3322#L1079-3 assume !(1 == ~T5_E~0); 3225#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3164#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3165#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3087#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3088#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3345#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3326#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3327#L1119-3 assume !(1 == ~E_3~0); 3538#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3542#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2805#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2806#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2964#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2965#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3125#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3545#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2511#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2393#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2394#L1459 assume !(0 == start_simulation_~tmp~3#1); 2402#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3402#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2690#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3233#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2852#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2853#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3006#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3186#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2603#L1440-2 [2021-12-19 19:16:25,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2021-12-19 19:16:25,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747198718] [2021-12-19 19:16:25,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,128 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747198718] [2021-12-19 19:16:25,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747198718] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,171 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818789291] [2021-12-19 19:16:25,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,171 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,172 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 1 times [2021-12-19 19:16:25,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914035200] [2021-12-19 19:16:25,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914035200] [2021-12-19 19:16:25,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914035200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,240 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,241 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369714971] [2021-12-19 19:16:25,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,241 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,241 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,242 INFO L87 Difference]: Start difference. First operand 1175 states and 1751 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,258 INFO L93 Difference]: Finished difference Result 1175 states and 1750 transitions. [2021-12-19 19:16:25,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1750 transitions. [2021-12-19 19:16:25,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1750 transitions. [2021-12-19 19:16:25,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1750 transitions. [2021-12-19 19:16:25,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,272 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2021-12-19 19:16:25,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1750 transitions. [2021-12-19 19:16:25,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4893617021276595) internal successors, (1750), 1174 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1750 transitions. [2021-12-19 19:16:25,289 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2021-12-19 19:16:25,289 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2021-12-19 19:16:25,290 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:16:25,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1750 transitions. [2021-12-19 19:16:25,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,307 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,309 INFO L791 eck$LassoCheckResult]: Stem: 5632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5892#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5651#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5552#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5302#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5303#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5810#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5842#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5834#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5835#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5415#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5405#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5406#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5227#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5228#L951 assume !(0 == ~M_E~0); 4967#L951-2 assume !(0 == ~T1_E~0); 4968#L956-1 assume !(0 == ~T2_E~0); 5126#L961-1 assume !(0 == ~T3_E~0); 5567#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5568#L971-1 assume !(0 == ~T5_E~0); 5707#L976-1 assume !(0 == ~T6_E~0); 5678#L981-1 assume !(0 == ~T7_E~0); 5454#L986-1 assume !(0 == ~T8_E~0); 5179#L991-1 assume !(0 == ~T9_E~0); 5180#L996-1 assume !(0 == ~E_M~0); 5874#L1001-1 assume !(0 == ~E_1~0); 5630#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5631#L1011-1 assume !(0 == ~E_3~0); 5844#L1016-1 assume !(0 == ~E_4~0); 5856#L1021-1 assume !(0 == ~E_5~0); 4772#L1026-1 assume !(0 == ~E_6~0); 4773#L1031-1 assume !(0 == ~E_7~0); 5581#L1036-1 assume !(0 == ~E_8~0); 5577#L1041-1 assume !(0 == ~E_9~0); 5578#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5817#L472 assume 1 == ~m_pc~0; 5891#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5610#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5611#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5618#L1179 assume !(0 != activate_threads_~tmp~1#1); 4780#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4781#L491 assume 1 == ~t1_pc~0; 5627#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5277#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5573#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4752#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4753#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4776#L510 assume !(1 == ~t2_pc~0); 4739#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4740#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5820#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5821#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5021#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5022#L529 assume 1 == ~t3_pc~0; 5372#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5373#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5784#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5866#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4942#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4943#L548 assume !(1 == ~t4_pc~0); 4840#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4839#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5136#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4884#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4885#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4829#L567 assume 1 == ~t5_pc~0; 4830#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4886#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5067#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5068#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5805#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4953#L586 assume !(1 == ~t6_pc~0); 4954#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5029#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5888#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5904#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5801#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5802#L605 assume 1 == ~t7_pc~0; 5781#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5436#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5571#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5572#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5900#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5547#L624 assume !(1 == ~t8_pc~0); 5015#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5014#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5603#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5604#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5789#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4795#L643 assume 1 == ~t9_pc~0; 4796#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5746#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5680#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5186#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5187#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4997#L1059 assume !(1 == ~M_E~0); 4998#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5154#L1064-1 assume !(1 == ~T2_E~0); 5155#L1069-1 assume !(1 == ~T3_E~0); 5753#L1074-1 assume !(1 == ~T4_E~0); 5788#L1079-1 assume !(1 == ~T5_E~0); 5779#L1084-1 assume !(1 == ~T6_E~0); 5780#L1089-1 assume !(1 == ~T7_E~0); 5797#L1094-1 assume !(1 == ~T8_E~0); 5480#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5481#L1104-1 assume !(1 == ~E_M~0); 5668#L1109-1 assume !(1 == ~E_1~0); 5295#L1114-1 assume !(1 == ~E_2~0); 5296#L1119-1 assume !(1 == ~E_3~0); 5348#L1124-1 assume !(1 == ~E_4~0); 4791#L1129-1 assume !(1 == ~E_5~0); 4792#L1134-1 assume !(1 == ~E_6~0); 5122#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5123#L1144-1 assume !(1 == ~E_8~0); 5310#L1149-1 assume !(1 == ~E_9~0); 4959#L1154-1 assume { :end_inline_reset_delta_events } true; 4960#L1440-2 [2021-12-19 19:16:25,309 INFO L793 eck$LassoCheckResult]: Loop: 4960#L1440-2 assume !false; 5091#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4731#L926 assume !false; 5350#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5351#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5049#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5050#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5055#L795 assume !(0 != eval_~tmp~0#1); 5056#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5475#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5211#L951-3 assume !(0 == ~M_E~0); 5212#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5715#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5551#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5335#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5336#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4813#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4814#L986-3 assume !(0 == ~T8_E~0); 4793#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4794#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5701#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5306#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5307#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5723#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5758#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5499#L1026-3 assume !(0 == ~E_6~0); 5500#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5695#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5696#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5751#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L472-33 assume !(1 == ~m_pc~0); 4912#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4913#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4748#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4749#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5339#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5340#L491-33 assume 1 == ~t1_pc~0; 5619#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4847#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5865#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5883#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5884#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5669#L510-33 assume !(1 == ~t2_pc~0); 5666#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5667#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5569#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5570#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4732#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4733#L529-33 assume 1 == ~t3_pc~0; 4760#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4761#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5034#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5860#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 4863#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4864#L548-33 assume 1 == ~t4_pc~0; 5104#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5226#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5266#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5267#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5044#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5045#L567-33 assume 1 == ~t5_pc~0; 5464#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5150#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5382#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5864#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5895#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5566#L586-33 assume !(1 == ~t6_pc~0); 5168#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5169#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5492#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5493#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5061#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5062#L605-33 assume !(1 == ~t7_pc~0); 5238#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4982#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4983#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5387#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4875#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4876#L624-33 assume 1 == ~t8_pc~0; 5032#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5041#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5009#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5010#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5251#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4984#L643-33 assume 1 == ~t9_pc~0; 4985#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5077#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5476#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5477#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4865#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4866#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5362#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5412#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5413#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5679#L1079-3 assume !(1 == ~T5_E~0); 5582#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5521#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5522#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5444#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5445#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5702#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5683#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5684#L1119-3 assume !(1 == ~E_3~0); 5896#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5899#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5162#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5163#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5324#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5325#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5482#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5902#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4868#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4750#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4751#L1459 assume !(0 == start_simulation_~tmp~3#1); 4759#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5759#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5047#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5590#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5209#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5210#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5364#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5543#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 4960#L1440-2 [2021-12-19 19:16:25,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2021-12-19 19:16:25,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601904971] [2021-12-19 19:16:25,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601904971] [2021-12-19 19:16:25,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601904971] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,354 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,354 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631248295] [2021-12-19 19:16:25,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,355 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,356 INFO L85 PathProgramCache]: Analyzing trace with hash -714854010, now seen corresponding path program 1 times [2021-12-19 19:16:25,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237987878] [2021-12-19 19:16:25,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237987878] [2021-12-19 19:16:25,403 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237987878] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,403 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217615033] [2021-12-19 19:16:25,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,404 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,404 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,405 INFO L87 Difference]: Start difference. First operand 1175 states and 1750 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,421 INFO L93 Difference]: Finished difference Result 1175 states and 1749 transitions. [2021-12-19 19:16:25,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1749 transitions. [2021-12-19 19:16:25,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1749 transitions. [2021-12-19 19:16:25,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1749 transitions. [2021-12-19 19:16:25,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,436 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2021-12-19 19:16:25,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1749 transitions. [2021-12-19 19:16:25,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4885106382978723) internal successors, (1749), 1174 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1749 transitions. [2021-12-19 19:16:25,453 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2021-12-19 19:16:25,453 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2021-12-19 19:16:25,453 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:16:25,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1749 transitions. [2021-12-19 19:16:25,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,459 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,460 INFO L791 eck$LassoCheckResult]: Stem: 7989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8250#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8010#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7909#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7661#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7662#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8167#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8199#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8191#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8192#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7772#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7762#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7763#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7584#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7585#L951 assume !(0 == ~M_E~0); 7326#L951-2 assume !(0 == ~T1_E~0); 7327#L956-1 assume !(0 == ~T2_E~0); 7483#L961-1 assume !(0 == ~T3_E~0); 7924#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7925#L971-1 assume !(0 == ~T5_E~0); 8064#L976-1 assume !(0 == ~T6_E~0); 8035#L981-1 assume !(0 == ~T7_E~0); 7811#L986-1 assume !(0 == ~T8_E~0); 7536#L991-1 assume !(0 == ~T9_E~0); 7537#L996-1 assume !(0 == ~E_M~0); 8231#L1001-1 assume !(0 == ~E_1~0); 7987#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7988#L1011-1 assume !(0 == ~E_3~0); 8202#L1016-1 assume !(0 == ~E_4~0); 8213#L1021-1 assume !(0 == ~E_5~0); 7129#L1026-1 assume !(0 == ~E_6~0); 7130#L1031-1 assume !(0 == ~E_7~0); 7938#L1036-1 assume !(0 == ~E_8~0); 7934#L1041-1 assume !(0 == ~E_9~0); 7935#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8174#L472 assume 1 == ~m_pc~0; 8248#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7967#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7968#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7975#L1179 assume !(0 != activate_threads_~tmp~1#1); 7137#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7138#L491 assume 1 == ~t1_pc~0; 7986#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7636#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7930#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7109#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7110#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7133#L510 assume !(1 == ~t2_pc~0); 7096#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7097#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8177#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8178#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7378#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7379#L529 assume 1 == ~t3_pc~0; 7729#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7730#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8141#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8223#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7299#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7300#L548 assume !(1 == ~t4_pc~0); 7197#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7196#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7493#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7241#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7242#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7189#L567 assume 1 == ~t5_pc~0; 7190#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7243#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7427#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7428#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8162#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7310#L586 assume !(1 == ~t6_pc~0); 7311#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7386#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8245#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8261#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8158#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8159#L605 assume 1 == ~t7_pc~0; 8139#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7796#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7928#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7929#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8257#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7904#L624 assume !(1 == ~t8_pc~0); 7372#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7371#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7960#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7961#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8146#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7154#L643 assume 1 == ~t9_pc~0; 7155#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8038#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7543#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7544#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7354#L1059 assume !(1 == ~M_E~0); 7355#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7511#L1064-1 assume !(1 == ~T2_E~0); 7512#L1069-1 assume !(1 == ~T3_E~0); 8110#L1074-1 assume !(1 == ~T4_E~0); 8145#L1079-1 assume !(1 == ~T5_E~0); 8136#L1084-1 assume !(1 == ~T6_E~0); 8137#L1089-1 assume !(1 == ~T7_E~0); 8154#L1094-1 assume !(1 == ~T8_E~0); 7837#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7838#L1104-1 assume !(1 == ~E_M~0); 8025#L1109-1 assume !(1 == ~E_1~0); 7652#L1114-1 assume !(1 == ~E_2~0); 7653#L1119-1 assume !(1 == ~E_3~0); 7706#L1124-1 assume !(1 == ~E_4~0); 7150#L1129-1 assume !(1 == ~E_5~0); 7151#L1134-1 assume !(1 == ~E_6~0); 7481#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7482#L1144-1 assume !(1 == ~E_8~0); 7667#L1149-1 assume !(1 == ~E_9~0); 7316#L1154-1 assume { :end_inline_reset_delta_events } true; 7317#L1440-2 [2021-12-19 19:16:25,460 INFO L793 eck$LassoCheckResult]: Loop: 7317#L1440-2 assume !false; 7448#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7088#L926 assume !false; 7707#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7708#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7406#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7407#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7412#L795 assume !(0 != eval_~tmp~0#1); 7413#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7832#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7570#L951-3 assume !(0 == ~M_E~0); 7571#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8073#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7908#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7692#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7693#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7962#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7176#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7177#L986-3 assume !(0 == ~T8_E~0); 7148#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7149#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8058#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7663#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7664#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8080#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8115#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7855#L1026-3 assume !(0 == ~E_6~0); 7856#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8052#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8053#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8108#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8069#L472-33 assume !(1 == ~m_pc~0); 7266#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7267#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7105#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7106#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7696#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7697#L491-33 assume !(1 == ~t1_pc~0); 7203#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7204#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8221#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8240#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8241#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8029#L510-33 assume !(1 == ~t2_pc~0); 8023#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8024#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7926#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7927#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7089#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7090#L529-33 assume 1 == ~t3_pc~0; 7117#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7118#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7391#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 7220#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7221#L548-33 assume 1 == ~t4_pc~0; 7462#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7583#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7623#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7624#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7401#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7402#L567-33 assume !(1 == ~t5_pc~0); 7506#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7739#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8222#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8252#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7923#L586-33 assume !(1 == ~t6_pc~0); 7525#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7526#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7849#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7850#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7418#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7419#L605-33 assume !(1 == ~t7_pc~0); 7595#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7346#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7347#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7744#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7232#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7233#L624-33 assume 1 == ~t8_pc~0; 7389#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7398#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7366#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7367#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7608#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7348#L643-33 assume 1 == ~t9_pc~0; 7349#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7434#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7880#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7833#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7834#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7222#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7223#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7719#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7769#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7770#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8036#L1079-3 assume !(1 == ~T5_E~0); 7939#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7878#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7879#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7801#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7802#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8059#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8041#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8042#L1119-3 assume !(1 == ~E_3~0); 8253#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8256#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7519#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7520#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7683#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7684#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7839#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8259#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7225#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7107#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7108#L1459 assume !(0 == start_simulation_~tmp~3#1); 7116#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8117#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7404#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7947#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7566#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7567#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7721#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7900#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7317#L1440-2 [2021-12-19 19:16:25,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2021-12-19 19:16:25,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722423575] [2021-12-19 19:16:25,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,462 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722423575] [2021-12-19 19:16:25,513 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722423575] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,513 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879423348] [2021-12-19 19:16:25,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,514 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 1 times [2021-12-19 19:16:25,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205258645] [2021-12-19 19:16:25,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205258645] [2021-12-19 19:16:25,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205258645] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,558 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089852007] [2021-12-19 19:16:25,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,558 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,558 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,559 INFO L87 Difference]: Start difference. First operand 1175 states and 1749 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,577 INFO L93 Difference]: Finished difference Result 1175 states and 1748 transitions. [2021-12-19 19:16:25,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1748 transitions. [2021-12-19 19:16:25,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1748 transitions. [2021-12-19 19:16:25,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1748 transitions. [2021-12-19 19:16:25,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,589 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2021-12-19 19:16:25,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1748 transitions. [2021-12-19 19:16:25,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4876595744680852) internal successors, (1748), 1174 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1748 transitions. [2021-12-19 19:16:25,628 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2021-12-19 19:16:25,628 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2021-12-19 19:16:25,628 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:16:25,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1748 transitions. [2021-12-19 19:16:25,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,635 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,635 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,636 INFO L791 eck$LassoCheckResult]: Stem: 10346#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10606#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10365#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10266#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10016#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10017#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10524#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10556#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10548#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10549#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10129#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10119#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10120#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9940#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9941#L951 assume !(0 == ~M_E~0); 9679#L951-2 assume !(0 == ~T1_E~0); 9680#L956-1 assume !(0 == ~T2_E~0); 9840#L961-1 assume !(0 == ~T3_E~0); 10281#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10282#L971-1 assume !(0 == ~T5_E~0); 10421#L976-1 assume !(0 == ~T6_E~0); 10392#L981-1 assume !(0 == ~T7_E~0); 10165#L986-1 assume !(0 == ~T8_E~0); 9893#L991-1 assume !(0 == ~T9_E~0); 9894#L996-1 assume !(0 == ~E_M~0); 10587#L1001-1 assume !(0 == ~E_1~0); 10344#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10345#L1011-1 assume !(0 == ~E_3~0); 10557#L1016-1 assume !(0 == ~E_4~0); 10570#L1021-1 assume !(0 == ~E_5~0); 9486#L1026-1 assume !(0 == ~E_6~0); 9487#L1031-1 assume !(0 == ~E_7~0); 10293#L1036-1 assume !(0 == ~E_8~0); 10289#L1041-1 assume !(0 == ~E_9~0); 10290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10531#L472 assume 1 == ~m_pc~0; 10605#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10325#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10332#L1179 assume !(0 != activate_threads_~tmp~1#1); 9494#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9495#L491 assume 1 == ~t1_pc~0; 10341#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9991#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10287#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9464#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9465#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9488#L510 assume !(1 == ~t2_pc~0); 9453#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9454#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10533#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10534#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9735#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9736#L529 assume 1 == ~t3_pc~0; 10086#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10087#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10498#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10580#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9656#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9657#L548 assume !(1 == ~t4_pc~0); 9554#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9553#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9848#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9596#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9597#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9541#L567 assume 1 == ~t5_pc~0; 9542#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9598#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9781#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9782#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10519#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9667#L586 assume !(1 == ~t6_pc~0); 9668#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9741#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10602#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10618#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10515#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10516#L605 assume 1 == ~t7_pc~0; 10495#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10145#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10285#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10286#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10614#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10261#L624 assume !(1 == ~t8_pc~0); 9729#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9728#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10317#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10318#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10503#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9509#L643 assume 1 == ~t9_pc~0; 9510#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10460#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10394#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9898#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9899#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9711#L1059 assume !(1 == ~M_E~0); 9712#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9868#L1064-1 assume !(1 == ~T2_E~0); 9869#L1069-1 assume !(1 == ~T3_E~0); 10467#L1074-1 assume !(1 == ~T4_E~0); 10501#L1079-1 assume !(1 == ~T5_E~0); 10493#L1084-1 assume !(1 == ~T6_E~0); 10494#L1089-1 assume !(1 == ~T7_E~0); 10511#L1094-1 assume !(1 == ~T8_E~0); 10194#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10195#L1104-1 assume !(1 == ~E_M~0); 10380#L1109-1 assume !(1 == ~E_1~0); 10009#L1114-1 assume !(1 == ~E_2~0); 10010#L1119-1 assume !(1 == ~E_3~0); 10062#L1124-1 assume !(1 == ~E_4~0); 9505#L1129-1 assume !(1 == ~E_5~0); 9506#L1134-1 assume !(1 == ~E_6~0); 9836#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9837#L1144-1 assume !(1 == ~E_8~0); 10022#L1149-1 assume !(1 == ~E_9~0); 9673#L1154-1 assume { :end_inline_reset_delta_events } true; 9674#L1440-2 [2021-12-19 19:16:25,636 INFO L793 eck$LassoCheckResult]: Loop: 9674#L1440-2 assume !false; 9803#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9445#L926 assume !false; 10064#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10065#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9760#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9761#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9768#L795 assume !(0 != eval_~tmp~0#1); 9769#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10189#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9925#L951-3 assume !(0 == ~M_E~0); 9926#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10429#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10265#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10045#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10319#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9525#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9526#L986-3 assume !(0 == ~T8_E~0); 9507#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9508#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10415#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10020#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10021#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10437#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10472#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10212#L1026-3 assume !(0 == ~E_6~0); 10213#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10409#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10410#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10465#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10427#L472-33 assume !(1 == ~m_pc~0); 9626#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9627#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9462#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9463#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10053#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10054#L491-33 assume !(1 == ~t1_pc~0); 9560#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9561#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10578#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10597#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10598#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L510-33 assume 1 == ~t2_pc~0; 10387#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10382#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10283#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10284#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9446#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9447#L529-33 assume 1 == ~t3_pc~0; 9474#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9475#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9748#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10574#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 9577#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9578#L548-33 assume 1 == ~t4_pc~0; 9819#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9942#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9980#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9981#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9758#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9759#L567-33 assume 1 == ~t5_pc~0; 10179#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9864#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10096#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10579#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10609#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10280#L586-33 assume !(1 == ~t6_pc~0); 9882#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9883#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10208#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10209#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9775#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9776#L605-33 assume !(1 == ~t7_pc~0); 9952#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9703#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9704#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9589#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9590#L624-33 assume 1 == ~t8_pc~0; 9746#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9755#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9723#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9724#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9965#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9705#L643-33 assume 1 == ~t9_pc~0; 9706#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9791#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10237#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10190#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10191#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9579#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9580#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10076#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10127#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10128#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10393#L1079-3 assume !(1 == ~T5_E~0); 10296#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10235#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10236#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10158#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10159#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10416#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10398#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10399#L1119-3 assume !(1 == ~E_3~0); 10610#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10613#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9876#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9877#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10040#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10041#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10196#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10616#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9584#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9466#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9467#L1459 assume !(0 == start_simulation_~tmp~3#1); 9473#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10474#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9763#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10304#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9923#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9924#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10080#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10257#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9674#L1440-2 [2021-12-19 19:16:25,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,637 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2021-12-19 19:16:25,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799285787] [2021-12-19 19:16:25,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799285787] [2021-12-19 19:16:25,671 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799285787] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,671 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,671 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527778887] [2021-12-19 19:16:25,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,672 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,672 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 2 times [2021-12-19 19:16:25,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29244043] [2021-12-19 19:16:25,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,674 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,720 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29244043] [2021-12-19 19:16:25,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29244043] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,722 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632479997] [2021-12-19 19:16:25,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,722 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,722 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,723 INFO L87 Difference]: Start difference. First operand 1175 states and 1748 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,739 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2021-12-19 19:16:25,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2021-12-19 19:16:25,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1747 transitions. [2021-12-19 19:16:25,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1747 transitions. [2021-12-19 19:16:25,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,753 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2021-12-19 19:16:25,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1747 transitions. [2021-12-19 19:16:25,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4868085106382978) internal successors, (1747), 1174 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1747 transitions. [2021-12-19 19:16:25,766 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2021-12-19 19:16:25,766 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2021-12-19 19:16:25,766 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:16:25,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1747 transitions. [2021-12-19 19:16:25,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,772 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,772 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,772 INFO L791 eck$LassoCheckResult]: Stem: 12703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12963#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12722#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12623#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12373#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12374#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12913#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12905#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12906#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12486#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12476#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12477#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12297#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12298#L951 assume !(0 == ~M_E~0); 12036#L951-2 assume !(0 == ~T1_E~0); 12037#L956-1 assume !(0 == ~T2_E~0); 12197#L961-1 assume !(0 == ~T3_E~0); 12638#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12639#L971-1 assume !(0 == ~T5_E~0); 12778#L976-1 assume !(0 == ~T6_E~0); 12749#L981-1 assume !(0 == ~T7_E~0); 12522#L986-1 assume !(0 == ~T8_E~0); 12250#L991-1 assume !(0 == ~T9_E~0); 12251#L996-1 assume !(0 == ~E_M~0); 12944#L1001-1 assume !(0 == ~E_1~0); 12701#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12702#L1011-1 assume !(0 == ~E_3~0); 12914#L1016-1 assume !(0 == ~E_4~0); 12927#L1021-1 assume !(0 == ~E_5~0); 11843#L1026-1 assume !(0 == ~E_6~0); 11844#L1031-1 assume !(0 == ~E_7~0); 12650#L1036-1 assume !(0 == ~E_8~0); 12646#L1041-1 assume !(0 == ~E_9~0); 12647#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12888#L472 assume 1 == ~m_pc~0; 12962#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12681#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12682#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12689#L1179 assume !(0 != activate_threads_~tmp~1#1); 11851#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11852#L491 assume 1 == ~t1_pc~0; 12698#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12348#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12644#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11821#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11822#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11845#L510 assume !(1 == ~t2_pc~0); 11810#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11811#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12890#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12891#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12092#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12093#L529 assume 1 == ~t3_pc~0; 12443#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12444#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12855#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12937#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12013#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12014#L548 assume !(1 == ~t4_pc~0); 11911#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11910#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12205#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11953#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 11954#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11898#L567 assume 1 == ~t5_pc~0; 11899#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11955#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12138#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12139#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12876#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L586 assume !(1 == ~t6_pc~0); 12025#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12098#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12959#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12975#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12872#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12873#L605 assume 1 == ~t7_pc~0; 12852#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12502#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12642#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12643#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 12971#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12618#L624 assume !(1 == ~t8_pc~0); 12086#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12085#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12674#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12675#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12860#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11866#L643 assume 1 == ~t9_pc~0; 11867#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12817#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12751#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12255#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12256#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12068#L1059 assume !(1 == ~M_E~0); 12069#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12225#L1064-1 assume !(1 == ~T2_E~0); 12226#L1069-1 assume !(1 == ~T3_E~0); 12824#L1074-1 assume !(1 == ~T4_E~0); 12858#L1079-1 assume !(1 == ~T5_E~0); 12850#L1084-1 assume !(1 == ~T6_E~0); 12851#L1089-1 assume !(1 == ~T7_E~0); 12868#L1094-1 assume !(1 == ~T8_E~0); 12551#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12552#L1104-1 assume !(1 == ~E_M~0); 12737#L1109-1 assume !(1 == ~E_1~0); 12366#L1114-1 assume !(1 == ~E_2~0); 12367#L1119-1 assume !(1 == ~E_3~0); 12419#L1124-1 assume !(1 == ~E_4~0); 11862#L1129-1 assume !(1 == ~E_5~0); 11863#L1134-1 assume !(1 == ~E_6~0); 12193#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12194#L1144-1 assume !(1 == ~E_8~0); 12379#L1149-1 assume !(1 == ~E_9~0); 12030#L1154-1 assume { :end_inline_reset_delta_events } true; 12031#L1440-2 [2021-12-19 19:16:25,773 INFO L793 eck$LassoCheckResult]: Loop: 12031#L1440-2 assume !false; 12160#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11802#L926 assume !false; 12421#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12422#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12117#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12118#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12125#L795 assume !(0 != eval_~tmp~0#1); 12126#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12546#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12282#L951-3 assume !(0 == ~M_E~0); 12283#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12786#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12622#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12402#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12403#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12676#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11882#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11883#L986-3 assume !(0 == ~T8_E~0); 11864#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11865#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12772#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12377#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12378#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12794#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12829#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12569#L1026-3 assume !(0 == ~E_6~0); 12570#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12766#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12767#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12822#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12784#L472-33 assume 1 == ~m_pc~0; 12785#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11984#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11819#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11820#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12410#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12411#L491-33 assume 1 == ~t1_pc~0; 12690#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11918#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12935#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12954#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12955#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12743#L510-33 assume !(1 == ~t2_pc~0); 12738#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12739#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12640#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12641#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11803#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11804#L529-33 assume 1 == ~t3_pc~0; 11831#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11832#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12105#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12931#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 11934#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11935#L548-33 assume 1 == ~t4_pc~0; 12176#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12299#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12337#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12338#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12115#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12116#L567-33 assume 1 == ~t5_pc~0; 12536#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12221#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12453#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12936#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12966#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12637#L586-33 assume 1 == ~t6_pc~0; 12610#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12240#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12565#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12566#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12132#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12133#L605-33 assume !(1 == ~t7_pc~0); 12309#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12060#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12061#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12458#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11946#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11947#L624-33 assume 1 == ~t8_pc~0; 12103#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12112#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12080#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12081#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12322#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12062#L643-33 assume !(1 == ~t9_pc~0); 12064#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 12148#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12594#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12547#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12548#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11936#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11937#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12433#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12484#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12485#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12750#L1079-3 assume !(1 == ~T5_E~0); 12653#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12592#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12593#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12515#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12516#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12773#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12755#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12756#L1119-3 assume !(1 == ~E_3~0); 12967#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12970#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12233#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12234#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12397#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12398#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12553#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12973#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11941#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11823#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11824#L1459 assume !(0 == start_simulation_~tmp~3#1); 11830#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12831#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12120#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12661#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 12280#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12281#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12437#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12614#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12031#L1440-2 [2021-12-19 19:16:25,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,774 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2021-12-19 19:16:25,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,774 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298334850] [2021-12-19 19:16:25,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,774 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,793 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298334850] [2021-12-19 19:16:25,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298334850] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907326466] [2021-12-19 19:16:25,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,795 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,797 INFO L85 PathProgramCache]: Analyzing trace with hash 1265732613, now seen corresponding path program 1 times [2021-12-19 19:16:25,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91864197] [2021-12-19 19:16:25,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91864197] [2021-12-19 19:16:25,835 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91864197] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,836 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,836 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,836 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506099726] [2021-12-19 19:16:25,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,836 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,837 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,838 INFO L87 Difference]: Start difference. First operand 1175 states and 1747 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,864 INFO L93 Difference]: Finished difference Result 1175 states and 1746 transitions. [2021-12-19 19:16:25,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1746 transitions. [2021-12-19 19:16:25,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1746 transitions. [2021-12-19 19:16:25,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1746 transitions. [2021-12-19 19:16:25,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,876 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2021-12-19 19:16:25,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1746 transitions. [2021-12-19 19:16:25,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:25,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4859574468085106) internal successors, (1746), 1174 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1746 transitions. [2021-12-19 19:16:25,891 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2021-12-19 19:16:25,891 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2021-12-19 19:16:25,891 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:16:25,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1746 transitions. [2021-12-19 19:16:25,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:25,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:25,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:25,896 INFO L791 eck$LassoCheckResult]: Stem: 15060#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 15061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15320#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15079#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14980#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14730#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14731#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15238#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15270#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15262#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15263#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14843#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14833#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14834#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14654#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14655#L951 assume !(0 == ~M_E~0); 14393#L951-2 assume !(0 == ~T1_E~0); 14394#L956-1 assume !(0 == ~T2_E~0); 14554#L961-1 assume !(0 == ~T3_E~0); 14995#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14996#L971-1 assume !(0 == ~T5_E~0); 15135#L976-1 assume !(0 == ~T6_E~0); 15106#L981-1 assume !(0 == ~T7_E~0); 14879#L986-1 assume !(0 == ~T8_E~0); 14607#L991-1 assume !(0 == ~T9_E~0); 14608#L996-1 assume !(0 == ~E_M~0); 15301#L1001-1 assume !(0 == ~E_1~0); 15058#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15059#L1011-1 assume !(0 == ~E_3~0); 15271#L1016-1 assume !(0 == ~E_4~0); 15284#L1021-1 assume !(0 == ~E_5~0); 14200#L1026-1 assume !(0 == ~E_6~0); 14201#L1031-1 assume !(0 == ~E_7~0); 15007#L1036-1 assume !(0 == ~E_8~0); 15003#L1041-1 assume !(0 == ~E_9~0); 15004#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15245#L472 assume 1 == ~m_pc~0; 15319#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15038#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15039#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15046#L1179 assume !(0 != activate_threads_~tmp~1#1); 14208#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14209#L491 assume 1 == ~t1_pc~0; 15055#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14705#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15001#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14178#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14179#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14202#L510 assume !(1 == ~t2_pc~0); 14167#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14168#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15247#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15248#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14449#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14450#L529 assume 1 == ~t3_pc~0; 14800#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14801#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15212#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15294#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14370#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14371#L548 assume !(1 == ~t4_pc~0); 14268#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14267#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14562#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14310#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14311#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14255#L567 assume 1 == ~t5_pc~0; 14256#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14312#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14495#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14496#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15233#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14381#L586 assume !(1 == ~t6_pc~0); 14382#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14455#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15316#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15332#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15229#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15230#L605 assume 1 == ~t7_pc~0; 15209#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14859#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14999#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15000#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15328#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14975#L624 assume !(1 == ~t8_pc~0); 14443#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14442#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15031#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15032#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15217#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14223#L643 assume 1 == ~t9_pc~0; 14224#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15174#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15108#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14612#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14613#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14425#L1059 assume !(1 == ~M_E~0); 14426#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14582#L1064-1 assume !(1 == ~T2_E~0); 14583#L1069-1 assume !(1 == ~T3_E~0); 15181#L1074-1 assume !(1 == ~T4_E~0); 15215#L1079-1 assume !(1 == ~T5_E~0); 15207#L1084-1 assume !(1 == ~T6_E~0); 15208#L1089-1 assume !(1 == ~T7_E~0); 15225#L1094-1 assume !(1 == ~T8_E~0); 14908#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14909#L1104-1 assume !(1 == ~E_M~0); 15094#L1109-1 assume !(1 == ~E_1~0); 14723#L1114-1 assume !(1 == ~E_2~0); 14724#L1119-1 assume !(1 == ~E_3~0); 14776#L1124-1 assume !(1 == ~E_4~0); 14219#L1129-1 assume !(1 == ~E_5~0); 14220#L1134-1 assume !(1 == ~E_6~0); 14550#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14551#L1144-1 assume !(1 == ~E_8~0); 14736#L1149-1 assume !(1 == ~E_9~0); 14387#L1154-1 assume { :end_inline_reset_delta_events } true; 14388#L1440-2 [2021-12-19 19:16:25,897 INFO L793 eck$LassoCheckResult]: Loop: 14388#L1440-2 assume !false; 14517#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14159#L926 assume !false; 14778#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14779#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14474#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14475#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14482#L795 assume !(0 != eval_~tmp~0#1); 14483#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14903#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14639#L951-3 assume !(0 == ~M_E~0); 14640#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15143#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14979#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14759#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14760#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15033#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14239#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14240#L986-3 assume !(0 == ~T8_E~0); 14221#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14222#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15129#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14734#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14735#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15151#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15186#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14926#L1026-3 assume !(0 == ~E_6~0); 14927#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15123#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15124#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15179#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L472-33 assume !(1 == ~m_pc~0); 14340#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14341#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14176#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14177#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14767#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14768#L491-33 assume !(1 == ~t1_pc~0); 14274#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14275#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15292#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15311#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15312#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15100#L510-33 assume !(1 == ~t2_pc~0); 15095#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15096#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14997#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14998#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14160#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14161#L529-33 assume 1 == ~t3_pc~0; 14188#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14189#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14462#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15288#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 14291#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14292#L548-33 assume 1 == ~t4_pc~0; 14533#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14656#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14694#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14695#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14472#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14473#L567-33 assume !(1 == ~t5_pc~0); 14577#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14578#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15293#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15323#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14994#L586-33 assume !(1 == ~t6_pc~0); 14596#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 14597#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14922#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14923#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14489#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14490#L605-33 assume !(1 == ~t7_pc~0); 14666#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14417#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14418#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14815#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14303#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14304#L624-33 assume 1 == ~t8_pc~0; 14460#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14469#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14437#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14438#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14679#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14419#L643-33 assume 1 == ~t9_pc~0; 14420#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14505#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14951#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14904#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14905#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14293#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14294#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14790#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14841#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15107#L1079-3 assume !(1 == ~T5_E~0); 15010#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14949#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14950#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14872#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14873#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15130#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15112#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15113#L1119-3 assume !(1 == ~E_3~0); 15324#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15327#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14590#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14591#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14754#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14755#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14910#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15330#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14298#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14180#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14181#L1459 assume !(0 == start_simulation_~tmp~3#1); 14187#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15188#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14477#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15018#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14637#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14638#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14794#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14971#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14388#L1440-2 [2021-12-19 19:16:25,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2021-12-19 19:16:25,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302349711] [2021-12-19 19:16:25,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,898 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302349711] [2021-12-19 19:16:25,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302349711] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,917 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922188088] [2021-12-19 19:16:25,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,918 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:25,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:25,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 2 times [2021-12-19 19:16:25,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:25,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963325411] [2021-12-19 19:16:25,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:25,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:25,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:25,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:25,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:25,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963325411] [2021-12-19 19:16:25,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963325411] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:25,947 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:25,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:25,948 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453362622] [2021-12-19 19:16:25,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:25,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:25,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:25,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:25,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:25,949 INFO L87 Difference]: Start difference. First operand 1175 states and 1746 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:25,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:25,963 INFO L93 Difference]: Finished difference Result 1175 states and 1745 transitions. [2021-12-19 19:16:25,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:25,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1745 transitions. [2021-12-19 19:16:25,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:25,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1745 transitions. [2021-12-19 19:16:25,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:25,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:25,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1745 transitions. [2021-12-19 19:16:25,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:25,990 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2021-12-19 19:16:25,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1745 transitions. [2021-12-19 19:16:26,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:26,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4851063829787234) internal successors, (1745), 1174 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1745 transitions. [2021-12-19 19:16:26,006 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2021-12-19 19:16:26,006 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2021-12-19 19:16:26,006 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:16:26,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1745 transitions. [2021-12-19 19:16:26,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:26,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,012 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,012 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,012 INFO L791 eck$LassoCheckResult]: Stem: 17417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17677#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17436#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17337#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17087#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17088#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17595#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17627#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17619#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17620#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17200#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17190#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17191#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17011#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17012#L951 assume !(0 == ~M_E~0); 16750#L951-2 assume !(0 == ~T1_E~0); 16751#L956-1 assume !(0 == ~T2_E~0); 16911#L961-1 assume !(0 == ~T3_E~0); 17352#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17353#L971-1 assume !(0 == ~T5_E~0); 17492#L976-1 assume !(0 == ~T6_E~0); 17463#L981-1 assume !(0 == ~T7_E~0); 17236#L986-1 assume !(0 == ~T8_E~0); 16964#L991-1 assume !(0 == ~T9_E~0); 16965#L996-1 assume !(0 == ~E_M~0); 17658#L1001-1 assume !(0 == ~E_1~0); 17415#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17416#L1011-1 assume !(0 == ~E_3~0); 17628#L1016-1 assume !(0 == ~E_4~0); 17641#L1021-1 assume !(0 == ~E_5~0); 16557#L1026-1 assume !(0 == ~E_6~0); 16558#L1031-1 assume !(0 == ~E_7~0); 17364#L1036-1 assume !(0 == ~E_8~0); 17360#L1041-1 assume !(0 == ~E_9~0); 17361#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17602#L472 assume 1 == ~m_pc~0; 17676#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17395#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17396#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17403#L1179 assume !(0 != activate_threads_~tmp~1#1); 16565#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16566#L491 assume 1 == ~t1_pc~0; 17412#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17062#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17358#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16537#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16538#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16559#L510 assume !(1 == ~t2_pc~0); 16524#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16525#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17605#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17606#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16806#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16807#L529 assume 1 == ~t3_pc~0; 17157#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17158#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17569#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17651#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16727#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16728#L548 assume !(1 == ~t4_pc~0); 16625#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16624#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16919#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16667#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16668#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16612#L567 assume 1 == ~t5_pc~0; 16613#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16669#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16852#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16853#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17590#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16738#L586 assume !(1 == ~t6_pc~0); 16739#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16812#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17673#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17689#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17586#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17587#L605 assume 1 == ~t7_pc~0; 17566#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17216#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17356#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17357#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17685#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17332#L624 assume !(1 == ~t8_pc~0); 16800#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16799#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17388#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17389#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17574#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16580#L643 assume 1 == ~t9_pc~0; 16581#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17531#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17465#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16971#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 16972#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1059 assume !(1 == ~M_E~0); 16783#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16939#L1064-1 assume !(1 == ~T2_E~0); 16940#L1069-1 assume !(1 == ~T3_E~0); 17538#L1074-1 assume !(1 == ~T4_E~0); 17572#L1079-1 assume !(1 == ~T5_E~0); 17564#L1084-1 assume !(1 == ~T6_E~0); 17565#L1089-1 assume !(1 == ~T7_E~0); 17582#L1094-1 assume !(1 == ~T8_E~0); 17265#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17266#L1104-1 assume !(1 == ~E_M~0); 17451#L1109-1 assume !(1 == ~E_1~0); 17080#L1114-1 assume !(1 == ~E_2~0); 17081#L1119-1 assume !(1 == ~E_3~0); 17133#L1124-1 assume !(1 == ~E_4~0); 16576#L1129-1 assume !(1 == ~E_5~0); 16577#L1134-1 assume !(1 == ~E_6~0); 16907#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16908#L1144-1 assume !(1 == ~E_8~0); 17095#L1149-1 assume !(1 == ~E_9~0); 16744#L1154-1 assume { :end_inline_reset_delta_events } true; 16745#L1440-2 [2021-12-19 19:16:26,013 INFO L793 eck$LassoCheckResult]: Loop: 16745#L1440-2 assume !false; 16874#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16516#L926 assume !false; 17135#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17136#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16834#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16835#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16840#L795 assume !(0 != eval_~tmp~0#1); 16841#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17260#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16996#L951-3 assume !(0 == ~M_E~0); 16997#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17500#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17336#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17117#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17118#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17390#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16598#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16599#L986-3 assume !(0 == ~T8_E~0); 16578#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16579#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17486#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17091#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17092#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17508#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17543#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17283#L1026-3 assume !(0 == ~E_6~0); 17284#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17480#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17481#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17536#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17498#L472-33 assume !(1 == ~m_pc~0); 16697#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16698#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16533#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16534#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17124#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17125#L491-33 assume !(1 == ~t1_pc~0); 16631#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16632#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17649#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17668#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17669#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17457#L510-33 assume 1 == ~t2_pc~0; 17458#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17453#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17354#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17355#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16517#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16518#L529-33 assume 1 == ~t3_pc~0; 16545#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16546#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16819#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17645#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 16648#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16649#L548-33 assume 1 == ~t4_pc~0; 16892#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17013#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17052#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16829#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16830#L567-33 assume 1 == ~t5_pc~0; 17250#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16935#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17168#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17650#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17681#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17351#L586-33 assume !(1 == ~t6_pc~0); 16953#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16954#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17279#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17280#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16846#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16847#L605-33 assume 1 == ~t7_pc~0; 17024#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16774#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16775#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17173#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16660#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16661#L624-33 assume 1 == ~t8_pc~0; 16817#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16826#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16794#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16795#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17036#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16776#L643-33 assume 1 == ~t9_pc~0; 16777#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16862#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17261#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17262#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16650#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16651#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17147#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17198#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17199#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17464#L1079-3 assume !(1 == ~T5_E~0); 17367#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17306#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17307#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17229#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17230#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17487#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17468#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17469#L1119-3 assume !(1 == ~E_3~0); 17680#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17684#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16947#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16948#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17106#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17107#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17267#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17687#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16653#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16535#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16536#L1459 assume !(0 == start_simulation_~tmp~3#1); 16544#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17544#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16832#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17375#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16994#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16995#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17148#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17327#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16745#L1440-2 [2021-12-19 19:16:26,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2021-12-19 19:16:26,013 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124068559] [2021-12-19 19:16:26,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,014 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,032 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124068559] [2021-12-19 19:16:26,033 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124068559] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,033 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,034 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630155789] [2021-12-19 19:16:26,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,034 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,035 INFO L85 PathProgramCache]: Analyzing trace with hash -1559246907, now seen corresponding path program 1 times [2021-12-19 19:16:26,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573152970] [2021-12-19 19:16:26,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,040 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,075 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573152970] [2021-12-19 19:16:26,076 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573152970] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,076 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,076 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860536420] [2021-12-19 19:16:26,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,078 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,078 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:26,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:26,078 INFO L87 Difference]: Start difference. First operand 1175 states and 1745 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:26,091 INFO L93 Difference]: Finished difference Result 1175 states and 1744 transitions. [2021-12-19 19:16:26,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:26,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1744 transitions. [2021-12-19 19:16:26,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:26,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1744 transitions. [2021-12-19 19:16:26,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2021-12-19 19:16:26,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2021-12-19 19:16:26,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1744 transitions. [2021-12-19 19:16:26,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:26,101 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2021-12-19 19:16:26,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1744 transitions. [2021-12-19 19:16:26,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2021-12-19 19:16:26,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4842553191489363) internal successors, (1744), 1174 states have internal predecessors, (1744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1744 transitions. [2021-12-19 19:16:26,113 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2021-12-19 19:16:26,113 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2021-12-19 19:16:26,113 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:16:26,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1744 transitions. [2021-12-19 19:16:26,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2021-12-19 19:16:26,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,117 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,117 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,117 INFO L791 eck$LassoCheckResult]: Stem: 19774#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20034#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19793#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19694#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19444#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19445#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19952#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19984#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19976#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19977#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19557#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19547#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19548#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19368#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19369#L951 assume !(0 == ~M_E~0); 19107#L951-2 assume !(0 == ~T1_E~0); 19108#L956-1 assume !(0 == ~T2_E~0); 19268#L961-1 assume !(0 == ~T3_E~0); 19709#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19710#L971-1 assume !(0 == ~T5_E~0); 19849#L976-1 assume !(0 == ~T6_E~0); 19820#L981-1 assume !(0 == ~T7_E~0); 19593#L986-1 assume !(0 == ~T8_E~0); 19321#L991-1 assume !(0 == ~T9_E~0); 19322#L996-1 assume !(0 == ~E_M~0); 20016#L1001-1 assume !(0 == ~E_1~0); 19772#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19773#L1011-1 assume !(0 == ~E_3~0); 19986#L1016-1 assume !(0 == ~E_4~0); 19998#L1021-1 assume !(0 == ~E_5~0); 18914#L1026-1 assume !(0 == ~E_6~0); 18915#L1031-1 assume !(0 == ~E_7~0); 19723#L1036-1 assume !(0 == ~E_8~0); 19717#L1041-1 assume !(0 == ~E_9~0); 19718#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19959#L472 assume 1 == ~m_pc~0; 20033#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19752#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19753#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19760#L1179 assume !(0 != activate_threads_~tmp~1#1); 18922#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18923#L491 assume 1 == ~t1_pc~0; 19769#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19419#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19715#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18894#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 18895#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18918#L510 assume !(1 == ~t2_pc~0); 18881#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18882#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19962#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19963#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19163#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19164#L529 assume 1 == ~t3_pc~0; 19514#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19515#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19926#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20008#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19084#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19085#L548 assume !(1 == ~t4_pc~0); 18982#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18981#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19276#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19026#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19027#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18969#L567 assume 1 == ~t5_pc~0; 18970#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19028#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19209#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19210#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 19947#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19095#L586 assume !(1 == ~t6_pc~0); 19096#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19169#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20030#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20046#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 19943#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19944#L605 assume 1 == ~t7_pc~0; 19923#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19577#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19713#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19714#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20042#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19689#L624 assume !(1 == ~t8_pc~0); 19157#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19156#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19745#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19746#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 19931#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18937#L643 assume 1 == ~t9_pc~0; 18938#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19888#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19822#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19328#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19329#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19139#L1059 assume !(1 == ~M_E~0); 19140#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19296#L1064-1 assume !(1 == ~T2_E~0); 19297#L1069-1 assume !(1 == ~T3_E~0); 19895#L1074-1 assume !(1 == ~T4_E~0); 19929#L1079-1 assume !(1 == ~T5_E~0); 19921#L1084-1 assume !(1 == ~T6_E~0); 19922#L1089-1 assume !(1 == ~T7_E~0); 19939#L1094-1 assume !(1 == ~T8_E~0); 19622#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19623#L1104-1 assume !(1 == ~E_M~0); 19808#L1109-1 assume !(1 == ~E_1~0); 19437#L1114-1 assume !(1 == ~E_2~0); 19438#L1119-1 assume !(1 == ~E_3~0); 19490#L1124-1 assume !(1 == ~E_4~0); 18933#L1129-1 assume !(1 == ~E_5~0); 18934#L1134-1 assume !(1 == ~E_6~0); 19264#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19265#L1144-1 assume !(1 == ~E_8~0); 19452#L1149-1 assume !(1 == ~E_9~0); 19101#L1154-1 assume { :end_inline_reset_delta_events } true; 19102#L1440-2 [2021-12-19 19:16:26,117 INFO L793 eck$LassoCheckResult]: Loop: 19102#L1440-2 assume !false; 19231#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18873#L926 assume !false; 19492#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19493#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19191#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19192#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19197#L795 assume !(0 != eval_~tmp~0#1); 19198#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19617#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19353#L951-3 assume !(0 == ~M_E~0); 19354#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19857#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19693#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19477#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19478#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19747#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18955#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18956#L986-3 assume !(0 == ~T8_E~0); 18935#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18936#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19843#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19448#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19449#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19865#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19900#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19641#L1026-3 assume !(0 == ~E_6~0); 19642#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19837#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19838#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19893#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19855#L472-33 assume 1 == ~m_pc~0; 19856#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19055#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18890#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18891#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19481#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19482#L491-33 assume 1 == ~t1_pc~0; 19761#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18989#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20007#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20025#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20026#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19814#L510-33 assume !(1 == ~t2_pc~0); 19809#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19810#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19711#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19712#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18874#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18875#L529-33 assume 1 == ~t3_pc~0; 18902#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18903#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19176#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20002#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 19005#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19006#L548-33 assume 1 == ~t4_pc~0; 19249#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19370#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19408#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19409#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19186#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19187#L567-33 assume 1 == ~t5_pc~0; 19606#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19289#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19524#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20006#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20037#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19708#L586-33 assume 1 == ~t6_pc~0; 19681#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19310#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19634#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19635#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19203#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19204#L605-33 assume !(1 == ~t7_pc~0); 19380#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19124#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19125#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19529#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19017#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19018#L624-33 assume 1 == ~t8_pc~0; 19174#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19183#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19151#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19152#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19393#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19126#L643-33 assume 1 == ~t9_pc~0; 19127#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19219#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19665#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19618#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19619#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19007#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19008#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19504#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19554#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19555#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19821#L1079-3 assume !(1 == ~T5_E~0); 19724#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19663#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19664#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19586#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19587#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19844#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19825#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19826#L1119-3 assume !(1 == ~E_3~0); 20038#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20041#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19304#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19305#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19463#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19464#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19624#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20044#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19010#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18892#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18893#L1459 assume !(0 == start_simulation_~tmp~3#1); 18901#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19901#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19189#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19732#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19351#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19352#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19505#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19685#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19102#L1440-2 [2021-12-19 19:16:26,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2021-12-19 19:16:26,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625365895] [2021-12-19 19:16:26,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,118 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625365895] [2021-12-19 19:16:26,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625365895] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,141 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152849327] [2021-12-19 19:16:26,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,142 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,142 INFO L85 PathProgramCache]: Analyzing trace with hash -2072306300, now seen corresponding path program 1 times [2021-12-19 19:16:26,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225679520] [2021-12-19 19:16:26,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225679520] [2021-12-19 19:16:26,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225679520] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664432083] [2021-12-19 19:16:26,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,165 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:26,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:26,166 INFO L87 Difference]: Start difference. First operand 1175 states and 1744 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:26,229 INFO L93 Difference]: Finished difference Result 2151 states and 3181 transitions. [2021-12-19 19:16:26,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:26,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 3181 transitions. [2021-12-19 19:16:26,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2021-12-19 19:16:26,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 2151 states and 3181 transitions. [2021-12-19 19:16:26,244 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2151 [2021-12-19 19:16:26,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2151 [2021-12-19 19:16:26,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2151 states and 3181 transitions. [2021-12-19 19:16:26,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:26,247 INFO L681 BuchiCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2021-12-19 19:16:26,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2151 states and 3181 transitions. [2021-12-19 19:16:26,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2151 to 2151. [2021-12-19 19:16:26,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2151 states, 2151 states have (on average 1.478847047884705) internal successors, (3181), 2150 states have internal predecessors, (3181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2151 states to 2151 states and 3181 transitions. [2021-12-19 19:16:26,278 INFO L704 BuchiCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2021-12-19 19:16:26,278 INFO L587 BuchiCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2021-12-19 19:16:26,278 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:16:26,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2151 states and 3181 transitions. [2021-12-19 19:16:26,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2021-12-19 19:16:26,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,297 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,297 INFO L791 eck$LassoCheckResult]: Stem: 23135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23423#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23156#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23052#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22792#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22793#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23332#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23368#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23359#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23360#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22907#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22896#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22897#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22714#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22715#L951 assume !(0 == ~M_E~0); 22450#L951-2 assume !(0 == ~T1_E~0); 22451#L956-1 assume !(0 == ~T2_E~0); 22612#L961-1 assume !(0 == ~T3_E~0); 23069#L966-1 assume !(0 == ~T4_E~0); 23070#L971-1 assume !(0 == ~T5_E~0); 23211#L976-1 assume !(0 == ~T6_E~0); 23181#L981-1 assume !(0 == ~T7_E~0); 22946#L986-1 assume !(0 == ~T8_E~0); 22665#L991-1 assume !(0 == ~T9_E~0); 22666#L996-1 assume !(0 == ~E_M~0); 23403#L1001-1 assume !(0 == ~E_1~0); 23132#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23133#L1011-1 assume !(0 == ~E_3~0); 23371#L1016-1 assume !(0 == ~E_4~0); 23383#L1021-1 assume !(0 == ~E_5~0); 22250#L1026-1 assume !(0 == ~E_6~0); 22251#L1031-1 assume !(0 == ~E_7~0); 23083#L1036-1 assume !(0 == ~E_8~0); 23079#L1041-1 assume !(0 == ~E_9~0); 23080#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23339#L472 assume 1 == ~m_pc~0; 23421#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23112#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23113#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23120#L1179 assume !(0 != activate_threads_~tmp~1#1); 22258#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22259#L491 assume 1 == ~t1_pc~0; 23131#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22767#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23075#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22230#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22231#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22254#L510 assume !(1 == ~t2_pc~0); 22217#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22218#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23344#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23345#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22503#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22504#L529 assume 1 == ~t3_pc~0; 22861#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22862#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23304#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23393#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22423#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22424#L548 assume !(1 == ~t4_pc~0); 22318#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22317#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22622#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22363#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22364#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22310#L567 assume 1 == ~t5_pc~0; 22311#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22365#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22553#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22554#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23327#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22434#L586 assume !(1 == ~t6_pc~0); 22435#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22511#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23418#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23442#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23323#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23324#L605 assume 1 == ~t7_pc~0; 23302#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22931#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23073#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23074#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23435#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23047#L624 assume !(1 == ~t8_pc~0); 22497#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22496#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23105#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23106#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23311#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22275#L643 assume 1 == ~t9_pc~0; 22276#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23259#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23185#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22672#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22673#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22478#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22479#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24028#L1064-1 assume !(1 == ~T2_E~0); 24027#L1069-1 assume !(1 == ~T3_E~0); 24026#L1074-1 assume !(1 == ~T4_E~0); 23434#L1079-1 assume !(1 == ~T5_E~0); 24025#L1084-1 assume !(1 == ~T6_E~0); 24024#L1089-1 assume !(1 == ~T7_E~0); 24023#L1094-1 assume !(1 == ~T8_E~0); 24022#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24021#L1104-1 assume !(1 == ~E_M~0); 24020#L1109-1 assume !(1 == ~E_1~0); 24019#L1114-1 assume !(1 == ~E_2~0); 24018#L1119-1 assume !(1 == ~E_3~0); 24017#L1124-1 assume !(1 == ~E_4~0); 24016#L1129-1 assume !(1 == ~E_5~0); 23057#L1134-1 assume !(1 == ~E_6~0); 23058#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22798#L1144-1 assume !(1 == ~E_8~0); 22799#L1149-1 assume !(1 == ~E_9~0); 22440#L1154-1 assume { :end_inline_reset_delta_events } true; 22441#L1440-2 [2021-12-19 19:16:26,297 INFO L793 eck$LassoCheckResult]: Loop: 22441#L1440-2 assume !false; 23397#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22209#L926 assume !false; 22839#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22840#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22532#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22533#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22538#L795 assume !(0 != eval_~tmp~0#1); 22539#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23309#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23310#L951-3 assume !(0 == ~M_E~0); 23443#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24226#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24225#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24224#L966-3 assume !(0 == ~T4_E~0); 24223#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24222#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24221#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24220#L986-3 assume !(0 == ~T8_E~0); 24219#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24218#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24217#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24216#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24215#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24214#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24213#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24212#L1026-3 assume !(0 == ~E_6~0); 24211#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24210#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24209#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24208#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24207#L472-33 assume !(1 == ~m_pc~0); 24205#L472-35 is_master_triggered_~__retres1~0#1 := 0; 24204#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24203#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24202#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24201#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24200#L491-33 assume 1 == ~t1_pc~0; 24198#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24197#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24196#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24195#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24194#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24193#L510-33 assume 1 == ~t2_pc~0; 24192#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24190#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24189#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24188#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24187#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24186#L529-33 assume 1 == ~t3_pc~0; 24184#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24183#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24182#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24181#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 24180#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24179#L548-33 assume 1 == ~t4_pc~0; 24177#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24176#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24175#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24174#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24173#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24172#L567-33 assume !(1 == ~t5_pc~0); 24170#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24169#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24168#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24167#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24163#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24161#L586-33 assume 1 == ~t6_pc~0; 24158#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24157#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24156#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24155#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24154#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22725#L605-33 assume !(1 == ~t7_pc~0); 22726#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 22470#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22471#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22878#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22354#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22355#L624-33 assume 1 == ~t8_pc~0; 22514#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24058#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24057#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24056#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24055#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24054#L643-33 assume !(1 == ~t9_pc~0); 24052#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 24051#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24050#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24049#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24048#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24047#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22344#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24046#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24045#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24044#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23182#L1079-3 assume !(1 == ~T5_E~0); 24043#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24042#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24041#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24040#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24039#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24038#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24037#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24036#L1119-3 assume !(1 == ~E_3~0); 24035#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24034#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24033#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24032#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24031#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24030#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24029#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23798#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23789#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23788#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23787#L1459 assume !(0 == start_simulation_~tmp~3#1); 23274#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23275#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23482#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23481#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23480#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23479#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23478#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23271#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 22441#L1440-2 [2021-12-19 19:16:26,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,298 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2021-12-19 19:16:26,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404498436] [2021-12-19 19:16:26,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,318 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404498436] [2021-12-19 19:16:26,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404498436] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,318 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628239176] [2021-12-19 19:16:26,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,319 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,319 INFO L85 PathProgramCache]: Analyzing trace with hash -631498428, now seen corresponding path program 1 times [2021-12-19 19:16:26,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997474632] [2021-12-19 19:16:26,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,340 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997474632] [2021-12-19 19:16:26,340 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997474632] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,340 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,340 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [110695250] [2021-12-19 19:16:26,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,341 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,341 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:26,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:26,341 INFO L87 Difference]: Start difference. First operand 2151 states and 3181 transitions. cyclomatic complexity: 1032 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:26,441 INFO L93 Difference]: Finished difference Result 3945 states and 5822 transitions. [2021-12-19 19:16:26,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:26,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3945 states and 5822 transitions. [2021-12-19 19:16:26,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2021-12-19 19:16:26,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3945 states to 3945 states and 5822 transitions. [2021-12-19 19:16:26,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3945 [2021-12-19 19:16:26,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3945 [2021-12-19 19:16:26,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3945 states and 5822 transitions. [2021-12-19 19:16:26,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:26,476 INFO L681 BuchiCegarLoop]: Abstraction has 3945 states and 5822 transitions. [2021-12-19 19:16:26,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3945 states and 5822 transitions. [2021-12-19 19:16:26,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3945 to 3943. [2021-12-19 19:16:26,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3943 states, 3943 states have (on average 1.476033477047933) internal successors, (5820), 3942 states have internal predecessors, (5820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3943 states to 3943 states and 5820 transitions. [2021-12-19 19:16:26,529 INFO L704 BuchiCegarLoop]: Abstraction has 3943 states and 5820 transitions. [2021-12-19 19:16:26,529 INFO L587 BuchiCegarLoop]: Abstraction has 3943 states and 5820 transitions. [2021-12-19 19:16:26,529 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:16:26,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3943 states and 5820 transitions. [2021-12-19 19:16:26,538 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2021-12-19 19:16:26,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,540 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,540 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,540 INFO L791 eck$LassoCheckResult]: Stem: 29240#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 29241#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 29547#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29263#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29155#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 28895#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28896#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29444#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29482#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29473#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29474#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29010#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28999#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29000#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28817#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28818#L951 assume !(0 == ~M_E~0); 28555#L951-2 assume !(0 == ~T1_E~0); 28556#L956-1 assume !(0 == ~T2_E~0); 28716#L961-1 assume !(0 == ~T3_E~0); 29173#L966-1 assume !(0 == ~T4_E~0); 29174#L971-1 assume !(0 == ~T5_E~0); 29321#L976-1 assume !(0 == ~T6_E~0); 29289#L981-1 assume !(0 == ~T7_E~0); 29051#L986-1 assume !(0 == ~T8_E~0); 28769#L991-1 assume !(0 == ~T9_E~0); 28770#L996-1 assume !(0 == ~E_M~0); 29525#L1001-1 assume !(0 == ~E_1~0); 29238#L1006-1 assume !(0 == ~E_2~0); 29239#L1011-1 assume !(0 == ~E_3~0); 29486#L1016-1 assume !(0 == ~E_4~0); 29501#L1021-1 assume !(0 == ~E_5~0); 28356#L1026-1 assume !(0 == ~E_6~0); 28357#L1031-1 assume !(0 == ~E_7~0); 29187#L1036-1 assume !(0 == ~E_8~0); 29183#L1041-1 assume !(0 == ~E_9~0); 29184#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29451#L472 assume 1 == ~m_pc~0; 29545#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29217#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29218#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29226#L1179 assume !(0 != activate_threads_~tmp~1#1); 28364#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28365#L491 assume 1 == ~t1_pc~0; 29237#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28869#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29179#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28336#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 28337#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28360#L510 assume !(1 == ~t2_pc~0); 28323#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28324#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29454#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29455#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28609#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28610#L529 assume 1 == ~t3_pc~0; 28965#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28966#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29408#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29513#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 28527#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28528#L548 assume !(1 == ~t4_pc~0); 28424#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28423#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28726#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28469#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 28470#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28416#L567 assume 1 == ~t5_pc~0; 28417#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28471#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28658#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28659#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 29439#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28538#L586 assume !(1 == ~t6_pc~0); 28539#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28617#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29541#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29574#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 29434#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29435#L605 assume 1 == ~t7_pc~0; 29406#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29034#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29177#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29178#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 29559#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29148#L624 assume !(1 == ~t8_pc~0); 28603#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28602#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29211#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29212#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 29417#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28381#L643 assume 1 == ~t9_pc~0; 28382#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29364#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29294#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28776#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 28777#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28584#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 28585#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28744#L1064-1 assume !(1 == ~T2_E~0); 28745#L1069-1 assume !(1 == ~T3_E~0); 29803#L1074-1 assume !(1 == ~T4_E~0); 29801#L1079-1 assume !(1 == ~T5_E~0); 29800#L1084-1 assume !(1 == ~T6_E~0); 29489#L1089-1 assume !(1 == ~T7_E~0); 29427#L1094-1 assume !(1 == ~T8_E~0); 29079#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29080#L1104-1 assume !(1 == ~E_M~0); 29278#L1109-1 assume !(1 == ~E_1~0); 29279#L1114-1 assume !(1 == ~E_2~0); 29682#L1119-1 assume !(1 == ~E_3~0); 29680#L1124-1 assume !(1 == ~E_4~0); 29664#L1129-1 assume !(1 == ~E_5~0); 29660#L1134-1 assume !(1 == ~E_6~0); 29658#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 29639#L1144-1 assume !(1 == ~E_8~0); 29623#L1149-1 assume !(1 == ~E_9~0); 29613#L1154-1 assume { :end_inline_reset_delta_events } true; 29605#L1440-2 [2021-12-19 19:16:26,540 INFO L793 eck$LassoCheckResult]: Loop: 29605#L1440-2 assume !false; 29599#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29595#L926 assume !false; 29594#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29592#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29583#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29582#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29580#L795 assume !(0 != eval_~tmp~0#1); 29579#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29578#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29576#L951-3 assume !(0 == ~M_E~0); 29577#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31191#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31189#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31187#L966-3 assume !(0 == ~T4_E~0); 31186#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31185#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31099#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31096#L986-3 assume !(0 == ~T8_E~0); 31094#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31092#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31090#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30993#L1006-3 assume !(0 == ~E_2~0); 30991#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30898#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30896#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30895#L1026-3 assume !(0 == ~E_6~0); 30893#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30891#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30889#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30887#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30885#L472-33 assume !(1 == ~m_pc~0); 30881#L472-35 is_master_triggered_~__retres1~0#1 := 0; 30879#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30877#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30875#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30873#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30871#L491-33 assume 1 == ~t1_pc~0; 30867#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30865#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30864#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30863#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30862#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30861#L510-33 assume !(1 == ~t2_pc~0); 30859#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 30858#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30857#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30856#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30855#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30854#L529-33 assume 1 == ~t3_pc~0; 30852#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30851#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30850#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30849#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 30848#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30847#L548-33 assume 1 == ~t4_pc~0; 30819#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30817#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30815#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30812#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30810#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30808#L567-33 assume !(1 == ~t5_pc~0); 30805#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 30803#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30600#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30597#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30595#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30404#L586-33 assume 1 == ~t6_pc~0; 30300#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30298#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30296#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30294#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30293#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30291#L605-33 assume !(1 == ~t7_pc~0); 30288#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 30286#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30284#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30282#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30215#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30161#L624-33 assume 1 == ~t8_pc~0; 30158#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30156#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30154#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30152#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30150#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30149#L643-33 assume !(1 == ~t9_pc~0); 30147#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 30146#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30143#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30141#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30089#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30053#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28450#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30050#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29008#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29009#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29291#L1079-3 assume !(1 == ~T5_E~0); 29919#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29917#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29915#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29896#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29894#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29892#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29891#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29867#L1119-3 assume !(1 == ~E_3~0); 29865#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29826#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29811#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29810#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29809#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29808#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29807#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29779#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29745#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29742#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 29740#L1459 assume !(0 == start_simulation_~tmp~3#1); 29457#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29691#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29681#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29665#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 29640#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29638#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29622#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 29612#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 29605#L1440-2 [2021-12-19 19:16:26,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2021-12-19 19:16:26,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055807550] [2021-12-19 19:16:26,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055807550] [2021-12-19 19:16:26,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055807550] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,562 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,562 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:26,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074041436] [2021-12-19 19:16:26,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,562 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,563 INFO L85 PathProgramCache]: Analyzing trace with hash -1038213181, now seen corresponding path program 1 times [2021-12-19 19:16:26,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619268136] [2021-12-19 19:16:26,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619268136] [2021-12-19 19:16:26,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619268136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,584 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,584 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,584 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686251624] [2021-12-19 19:16:26,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,585 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,585 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:26,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:26,585 INFO L87 Difference]: Start difference. First operand 3943 states and 5820 transitions. cyclomatic complexity: 1881 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:26,681 INFO L93 Difference]: Finished difference Result 7643 states and 11179 transitions. [2021-12-19 19:16:26,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:26,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7643 states and 11179 transitions. [2021-12-19 19:16:26,708 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7465 [2021-12-19 19:16:26,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7643 states to 7643 states and 11179 transitions. [2021-12-19 19:16:26,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7643 [2021-12-19 19:16:26,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7643 [2021-12-19 19:16:26,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7643 states and 11179 transitions. [2021-12-19 19:16:26,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:26,745 INFO L681 BuchiCegarLoop]: Abstraction has 7643 states and 11179 transitions. [2021-12-19 19:16:26,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7643 states and 11179 transitions. [2021-12-19 19:16:26,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7643 to 7367. [2021-12-19 19:16:26,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7367 states, 7367 states have (on average 1.4647753495316953) internal successors, (10791), 7366 states have internal predecessors, (10791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:26,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7367 states to 7367 states and 10791 transitions. [2021-12-19 19:16:26,846 INFO L704 BuchiCegarLoop]: Abstraction has 7367 states and 10791 transitions. [2021-12-19 19:16:26,846 INFO L587 BuchiCegarLoop]: Abstraction has 7367 states and 10791 transitions. [2021-12-19 19:16:26,846 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:16:26,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7367 states and 10791 transitions. [2021-12-19 19:16:26,865 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7189 [2021-12-19 19:16:26,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:26,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:26,866 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,866 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:26,867 INFO L791 eck$LassoCheckResult]: Stem: 40844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 40845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 41175#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40868#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40759#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 40496#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40497#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41057#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41108#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41094#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41095#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40613#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40601#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40602#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40416#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40417#L951 assume !(0 == ~M_E~0); 40148#L951-2 assume !(0 == ~T1_E~0); 40149#L956-1 assume !(0 == ~T2_E~0); 40310#L961-1 assume !(0 == ~T3_E~0); 40776#L966-1 assume !(0 == ~T4_E~0); 40777#L971-1 assume !(0 == ~T5_E~0); 40922#L976-1 assume !(0 == ~T6_E~0); 40893#L981-1 assume !(0 == ~T7_E~0); 40653#L986-1 assume !(0 == ~T8_E~0); 40363#L991-1 assume !(0 == ~T9_E~0); 40364#L996-1 assume !(0 == ~E_M~0); 41154#L1001-1 assume !(0 == ~E_1~0); 40842#L1006-1 assume !(0 == ~E_2~0); 40843#L1011-1 assume !(0 == ~E_3~0); 41111#L1016-1 assume !(0 == ~E_4~0); 41129#L1021-1 assume !(0 == ~E_5~0); 39949#L1026-1 assume !(0 == ~E_6~0); 39950#L1031-1 assume !(0 == ~E_7~0); 40790#L1036-1 assume !(0 == ~E_8~0); 40786#L1041-1 assume !(0 == ~E_9~0); 40787#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41066#L472 assume !(1 == ~m_pc~0); 41020#L472-2 is_master_triggered_~__retres1~0#1 := 0; 40821#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40822#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40830#L1179 assume !(0 != activate_threads_~tmp~1#1); 39957#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39958#L491 assume 1 == ~t1_pc~0; 40841#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40468#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40782#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39929#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 39930#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39953#L510 assume !(1 == ~t2_pc~0); 39916#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39917#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41069#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41070#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40200#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40201#L529 assume 1 == ~t3_pc~0; 40566#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40567#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41015#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41140#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 40121#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40122#L548 assume !(1 == ~t4_pc~0); 40016#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40015#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40320#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40061#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 40062#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40008#L567 assume 1 == ~t5_pc~0; 40009#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40063#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40249#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40250#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 41052#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40132#L586 assume !(1 == ~t6_pc~0); 40133#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40208#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41170#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41202#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 41048#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41049#L605 assume 1 == ~t7_pc~0; 41010#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40638#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40780#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40781#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 41190#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40754#L624 assume !(1 == ~t8_pc~0); 40194#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40193#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40814#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40815#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 41026#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39974#L643 assume 1 == ~t9_pc~0; 39975#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40969#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40896#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40371#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 40372#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40176#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 40177#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44838#L1064-1 assume !(1 == ~T2_E~0); 44836#L1069-1 assume !(1 == ~T3_E~0); 41189#L1074-1 assume !(1 == ~T4_E~0); 41022#L1079-1 assume !(1 == ~T5_E~0); 41023#L1084-1 assume !(1 == ~T6_E~0); 41116#L1089-1 assume !(1 == ~T7_E~0); 41043#L1094-1 assume !(1 == ~T8_E~0); 41044#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47148#L1104-1 assume !(1 == ~E_M~0); 40883#L1109-1 assume !(1 == ~E_1~0); 40485#L1114-1 assume !(1 == ~E_2~0); 40486#L1119-1 assume !(1 == ~E_3~0); 41196#L1124-1 assume !(1 == ~E_4~0); 39970#L1129-1 assume !(1 == ~E_5~0); 39971#L1134-1 assume !(1 == ~E_6~0); 40308#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 40309#L1144-1 assume !(1 == ~E_8~0); 40502#L1149-1 assume !(1 == ~E_9~0); 46468#L1154-1 assume { :end_inline_reset_delta_events } true; 41387#L1440-2 [2021-12-19 19:16:26,867 INFO L793 eck$LassoCheckResult]: Loop: 41387#L1440-2 assume !false; 41374#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41364#L926 assume !false; 41365#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41272#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41258#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41254#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41248#L795 assume !(0 != eval_~tmp~0#1); 41249#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41024#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41025#L951-3 assume !(0 == ~M_E~0); 46438#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47103#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47102#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47101#L966-3 assume !(0 == ~T4_E~0); 47100#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47099#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47098#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47097#L986-3 assume !(0 == ~T8_E~0); 47096#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47095#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47094#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47093#L1006-3 assume !(0 == ~E_2~0); 47092#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47091#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47090#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47089#L1026-3 assume !(0 == ~E_6~0); 47088#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47087#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47086#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47085#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47084#L472-33 assume !(1 == ~m_pc~0); 47083#L472-35 is_master_triggered_~__retres1~0#1 := 0; 47082#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47081#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47080#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47079#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47078#L491-33 assume 1 == ~t1_pc~0; 47076#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47075#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47074#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47073#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47072#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47071#L510-33 assume !(1 == ~t2_pc~0); 47069#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 47068#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47067#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47066#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47065#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47064#L529-33 assume 1 == ~t3_pc~0; 47062#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47061#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47060#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47059#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 47058#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47057#L548-33 assume !(1 == ~t4_pc~0); 47056#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 47054#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47053#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47052#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47051#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47050#L567-33 assume !(1 == ~t5_pc~0); 47048#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 47047#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47046#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47045#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47044#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47043#L586-33 assume 1 == ~t6_pc~0; 47041#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47040#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47039#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47038#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47037#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47036#L605-33 assume !(1 == ~t7_pc~0); 47034#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 47033#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47032#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47031#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47030#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47029#L624-33 assume 1 == ~t8_pc~0; 47027#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47026#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47025#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47024#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47023#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47022#L643-33 assume !(1 == ~t9_pc~0); 47020#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 47019#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47018#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47017#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47016#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47015#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40042#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47014#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47013#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47012#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45185#L1079-3 assume !(1 == ~T5_E~0); 47011#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47010#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47009#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47008#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47007#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47006#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47005#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40900#L1119-3 assume !(1 == ~E_3~0); 47004#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47003#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47002#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47001#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47000#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46999#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46998#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46996#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46987#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46986#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 46985#L1459 assume !(0 == start_simulation_~tmp~3#1); 41074#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46846#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46837#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46836#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 46835#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46834#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46833#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 46467#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 41387#L1440-2 [2021-12-19 19:16:26,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,867 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2021-12-19 19:16:26,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225715014] [2021-12-19 19:16:26,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,868 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,885 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225715014] [2021-12-19 19:16:26,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225715014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,885 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,885 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:26,885 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981074818] [2021-12-19 19:16:26,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,885 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:26,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:26,886 INFO L85 PathProgramCache]: Analyzing trace with hash 99415684, now seen corresponding path program 1 times [2021-12-19 19:16:26,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:26,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450930385] [2021-12-19 19:16:26,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:26,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:26,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:26,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:26,907 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:26,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450930385] [2021-12-19 19:16:26,907 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450930385] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:26,907 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:26,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:26,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838480784] [2021-12-19 19:16:26,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:26,907 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:26,907 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:26,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:26,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:26,908 INFO L87 Difference]: Start difference. First operand 7367 states and 10791 transitions. cyclomatic complexity: 3432 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:27,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:27,028 INFO L93 Difference]: Finished difference Result 14183 states and 20633 transitions. [2021-12-19 19:16:27,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:27,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14183 states and 20633 transitions. [2021-12-19 19:16:27,091 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13990 [2021-12-19 19:16:27,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14183 states to 14183 states and 20633 transitions. [2021-12-19 19:16:27,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14183 [2021-12-19 19:16:27,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14183 [2021-12-19 19:16:27,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14183 states and 20633 transitions. [2021-12-19 19:16:27,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:27,168 INFO L681 BuchiCegarLoop]: Abstraction has 14183 states and 20633 transitions. [2021-12-19 19:16:27,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14183 states and 20633 transitions. [2021-12-19 19:16:27,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14183 to 14167. [2021-12-19 19:16:27,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14167 states, 14167 states have (on average 1.4552834050963506) internal successors, (20617), 14166 states have internal predecessors, (20617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:27,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14167 states to 14167 states and 20617 transitions. [2021-12-19 19:16:27,452 INFO L704 BuchiCegarLoop]: Abstraction has 14167 states and 20617 transitions. [2021-12-19 19:16:27,453 INFO L587 BuchiCegarLoop]: Abstraction has 14167 states and 20617 transitions. [2021-12-19 19:16:27,453 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:16:27,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14167 states and 20617 transitions. [2021-12-19 19:16:27,493 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13974 [2021-12-19 19:16:27,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:27,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:27,495 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:27,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:27,495 INFO L791 eck$LassoCheckResult]: Stem: 62400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 62401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 62733#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62420#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62318#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 62055#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62056#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62616#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62665#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62646#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62647#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62174#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62164#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62165#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61973#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61974#L951 assume !(0 == ~M_E~0); 61702#L951-2 assume !(0 == ~T1_E~0); 61703#L956-1 assume !(0 == ~T2_E~0); 61871#L961-1 assume !(0 == ~T3_E~0); 62334#L966-1 assume !(0 == ~T4_E~0); 62335#L971-1 assume !(0 == ~T5_E~0); 62480#L976-1 assume !(0 == ~T6_E~0); 62449#L981-1 assume !(0 == ~T7_E~0); 62210#L986-1 assume !(0 == ~T8_E~0); 61926#L991-1 assume !(0 == ~T9_E~0); 61927#L996-1 assume !(0 == ~E_M~0); 62712#L1001-1 assume !(0 == ~E_1~0); 62398#L1006-1 assume !(0 == ~E_2~0); 62399#L1011-1 assume !(0 == ~E_3~0); 62666#L1016-1 assume !(0 == ~E_4~0); 62690#L1021-1 assume !(0 == ~E_5~0); 61507#L1026-1 assume !(0 == ~E_6~0); 61508#L1031-1 assume !(0 == ~E_7~0); 62346#L1036-1 assume !(0 == ~E_8~0); 62342#L1041-1 assume !(0 == ~E_9~0); 62343#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62623#L472 assume !(1 == ~m_pc~0); 62583#L472-2 is_master_triggered_~__retres1~0#1 := 0; 62378#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62379#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62387#L1179 assume !(0 != activate_threads_~tmp~1#1); 61515#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61516#L491 assume !(1 == ~t1_pc~0); 62024#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62025#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62340#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61484#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 61485#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61509#L510 assume !(1 == ~t2_pc~0); 61473#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61474#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62625#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62626#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61760#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61761#L529 assume 1 == ~t3_pc~0; 62128#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62129#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62580#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62702#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 61679#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61680#L548 assume !(1 == ~t4_pc~0); 61574#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61573#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61881#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61617#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 61618#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61561#L567 assume 1 == ~t5_pc~0; 61562#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61619#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61807#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61808#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 62611#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61690#L586 assume !(1 == ~t6_pc~0); 61691#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61766#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62730#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62763#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 62604#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62605#L605 assume 1 == ~t7_pc~0; 62576#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62190#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62338#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62339#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 62753#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62313#L624 assume !(1 == ~t8_pc~0); 61754#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61753#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62372#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62373#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 62588#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61530#L643 assume 1 == ~t9_pc~0; 61531#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62528#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62452#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61931#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 61932#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61734#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 61735#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61901#L1064-1 assume !(1 == ~T2_E~0); 61902#L1069-1 assume !(1 == ~T3_E~0); 62539#L1074-1 assume !(1 == ~T4_E~0); 69632#L1079-1 assume !(1 == ~T5_E~0); 69630#L1084-1 assume !(1 == ~T6_E~0); 69629#L1089-1 assume !(1 == ~T7_E~0); 69628#L1094-1 assume !(1 == ~T8_E~0); 69626#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62682#L1104-1 assume !(1 == ~E_M~0); 62436#L1109-1 assume !(1 == ~E_1~0); 62437#L1114-1 assume !(1 == ~E_2~0); 69620#L1119-1 assume !(1 == ~E_3~0); 69619#L1124-1 assume !(1 == ~E_4~0); 69618#L1129-1 assume !(1 == ~E_5~0); 69512#L1134-1 assume !(1 == ~E_6~0); 69440#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 69438#L1144-1 assume !(1 == ~E_8~0); 69418#L1149-1 assume !(1 == ~E_9~0); 69408#L1154-1 assume { :end_inline_reset_delta_events } true; 69399#L1440-2 [2021-12-19 19:16:27,496 INFO L793 eck$LassoCheckResult]: Loop: 69399#L1440-2 assume !false; 69391#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69386#L926 assume !false; 69382#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 69367#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 69355#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 69352#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69347#L795 assume !(0 != eval_~tmp~0#1); 69348#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72468#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72466#L951-3 assume !(0 == ~M_E~0); 72464#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72462#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72460#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72458#L966-3 assume !(0 == ~T4_E~0); 72457#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62374#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61546#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61547#L986-3 assume !(0 == ~T8_E~0); 61528#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61529#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62584#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62585#L1006-3 assume !(0 == ~E_2~0); 62498#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62499#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62545#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62258#L1026-3 assume !(0 == ~E_6~0); 62259#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62746#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72441#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72440#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72439#L472-33 assume !(1 == ~m_pc~0); 72438#L472-35 is_master_triggered_~__retres1~0#1 := 0; 72437#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72436#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72435#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72434#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72433#L491-33 assume !(1 == ~t1_pc~0); 72432#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 72431#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72430#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72429#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72428#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72427#L510-33 assume !(1 == ~t2_pc~0); 64509#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 64507#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64505#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64502#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64499#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64500#L529-33 assume 1 == ~t3_pc~0; 72421#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72420#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72419#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72418#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 72417#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64483#L548-33 assume 1 == ~t4_pc~0; 64480#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64478#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64476#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64474#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64471#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64469#L567-33 assume !(1 == ~t5_pc~0); 64466#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64464#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64462#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64460#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64458#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64456#L586-33 assume 1 == ~t6_pc~0; 64453#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64451#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64449#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64446#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64447#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72243#L605-33 assume 1 == ~t7_pc~0; 72239#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72236#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72233#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72231#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 72229#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64423#L624-33 assume 1 == ~t8_pc~0; 64420#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64417#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64418#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70113#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70111#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70103#L643-33 assume 1 == ~t9_pc~0; 70097#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70091#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70090#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70088#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70083#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70041#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64390#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70023#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70015#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70008#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69999#L1079-3 assume !(1 == ~T5_E~0); 69984#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69982#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69971#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69964#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69957#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69951#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69933#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69927#L1119-3 assume !(1 == ~E_3~0); 69922#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69916#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69910#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69904#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69900#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69750#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69748#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 69532#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 69521#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 69519#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 69517#L1459 assume !(0 == start_simulation_~tmp~3#1); 69515#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 69452#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 69442#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 69441#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 69439#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69437#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69417#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 69407#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 69399#L1440-2 [2021-12-19 19:16:27,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:27,496 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2021-12-19 19:16:27,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:27,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483568014] [2021-12-19 19:16:27,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:27,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:27,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:27,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:27,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:27,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483568014] [2021-12-19 19:16:27,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483568014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:27,527 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:27,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:16:27,528 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994703342] [2021-12-19 19:16:27,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:27,528 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:27,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:27,528 INFO L85 PathProgramCache]: Analyzing trace with hash 534316226, now seen corresponding path program 1 times [2021-12-19 19:16:27,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:27,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103453520] [2021-12-19 19:16:27,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:27,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:27,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:27,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:27,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:27,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103453520] [2021-12-19 19:16:27,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103453520] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:27,551 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:27,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:27,551 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041990611] [2021-12-19 19:16:27,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:27,552 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:27,552 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:27,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:16:27,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:16:27,553 INFO L87 Difference]: Start difference. First operand 14167 states and 20617 transitions. cyclomatic complexity: 6466 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:27,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:27,915 INFO L93 Difference]: Finished difference Result 38862 states and 56552 transitions. [2021-12-19 19:16:27,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:16:27,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38862 states and 56552 transitions. [2021-12-19 19:16:28,125 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38388 [2021-12-19 19:16:28,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38862 states to 38862 states and 56552 transitions. [2021-12-19 19:16:28,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38862 [2021-12-19 19:16:28,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38862 [2021-12-19 19:16:28,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38862 states and 56552 transitions. [2021-12-19 19:16:28,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:28,301 INFO L681 BuchiCegarLoop]: Abstraction has 38862 states and 56552 transitions. [2021-12-19 19:16:28,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38862 states and 56552 transitions. [2021-12-19 19:16:28,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38862 to 14650. [2021-12-19 19:16:28,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14650 states, 14650 states have (on average 1.4402730375426622) internal successors, (21100), 14649 states have internal predecessors, (21100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:28,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14650 states to 14650 states and 21100 transitions. [2021-12-19 19:16:28,708 INFO L704 BuchiCegarLoop]: Abstraction has 14650 states and 21100 transitions. [2021-12-19 19:16:28,708 INFO L587 BuchiCegarLoop]: Abstraction has 14650 states and 21100 transitions. [2021-12-19 19:16:28,709 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:16:28,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14650 states and 21100 transitions. [2021-12-19 19:16:28,756 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14454 [2021-12-19 19:16:28,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:28,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:28,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:28,758 INFO L791 eck$LassoCheckResult]: Stem: 115489#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 115490#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 115935#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115517#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115396#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 115105#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115106#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115765#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115831#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115810#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115811#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115230#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 115218#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115219#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115022#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115023#L951 assume !(0 == ~M_E~0); 114744#L951-2 assume !(0 == ~T1_E~0); 114745#L956-1 assume !(0 == ~T2_E~0); 114918#L961-1 assume !(0 == ~T3_E~0); 115415#L966-1 assume !(0 == ~T4_E~0); 115416#L971-1 assume !(0 == ~T5_E~0); 115587#L976-1 assume !(0 == ~T6_E~0); 115550#L981-1 assume !(0 == ~T7_E~0); 115271#L986-1 assume !(0 == ~T8_E~0); 114973#L991-1 assume !(0 == ~T9_E~0); 114974#L996-1 assume !(0 == ~E_M~0); 115907#L1001-1 assume !(0 == ~E_1~0); 115487#L1006-1 assume !(0 == ~E_2~0); 115488#L1011-1 assume !(0 == ~E_3~0); 115832#L1016-1 assume !(0 == ~E_4~0); 115864#L1021-1 assume !(0 == ~E_5~0); 114548#L1026-1 assume !(0 == ~E_6~0); 114549#L1031-1 assume !(0 == ~E_7~0); 115428#L1036-1 assume !(0 == ~E_8~0); 115424#L1041-1 assume !(0 == ~E_9~0); 115425#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115774#L472 assume !(1 == ~m_pc~0); 115718#L472-2 is_master_triggered_~__retres1~0#1 := 0; 115461#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115462#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115473#L1179 assume !(0 != activate_threads_~tmp~1#1); 114556#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114557#L491 assume !(1 == ~t1_pc~0); 115074#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115075#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115422#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 114526#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 114527#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114550#L510 assume !(1 == ~t2_pc~0); 114515#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114516#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115902#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116003#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 114803#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114804#L529 assume 1 == ~t3_pc~0; 115181#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 115182#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115711#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115883#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 114720#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114721#L548 assume !(1 == ~t4_pc~0); 114616#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 114615#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114926#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114658#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 114659#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114603#L567 assume 1 == ~t5_pc~0; 114604#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 114660#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114851#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114852#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 115757#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114731#L586 assume !(1 == ~t6_pc~0); 114732#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 114809#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115929#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116014#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 115749#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115750#L605 assume 1 == ~t7_pc~0; 115705#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115247#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115419#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115420#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 115968#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 115389#L624 assume !(1 == ~t8_pc~0); 114796#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 114795#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115454#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 115455#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 115724#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114571#L643 assume 1 == ~t9_pc~0; 114572#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 115653#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 115554#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114978#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 114979#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114777#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 114778#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114947#L1064-1 assume !(1 == ~T2_E~0); 114948#L1069-1 assume !(1 == ~T3_E~0); 115964#L1074-1 assume !(1 == ~T4_E~0); 115965#L1079-1 assume !(1 == ~T5_E~0); 119392#L1084-1 assume !(1 == ~T6_E~0); 119367#L1089-1 assume !(1 == ~T7_E~0); 119364#L1094-1 assume !(1 == ~T8_E~0); 119362#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 119360#L1104-1 assume !(1 == ~E_M~0); 119272#L1109-1 assume !(1 == ~E_1~0); 119270#L1114-1 assume !(1 == ~E_2~0); 119267#L1119-1 assume !(1 == ~E_3~0); 119080#L1124-1 assume !(1 == ~E_4~0); 119071#L1129-1 assume !(1 == ~E_5~0); 118825#L1134-1 assume !(1 == ~E_6~0); 118823#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 118650#L1144-1 assume !(1 == ~E_8~0); 118583#L1149-1 assume !(1 == ~E_9~0); 118566#L1154-1 assume { :end_inline_reset_delta_events } true; 118557#L1440-2 [2021-12-19 19:16:28,758 INFO L793 eck$LassoCheckResult]: Loop: 118557#L1440-2 assume !false; 118550#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118545#L926 assume !false; 118543#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118539#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118529#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118527#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 118524#L795 assume !(0 != eval_~tmp~0#1); 118525#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119755#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119753#L951-3 assume !(0 == ~M_E~0); 119751#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119749#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 119747#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119745#L966-3 assume !(0 == ~T4_E~0); 119743#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119741#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119739#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119737#L986-3 assume !(0 == ~T8_E~0); 119735#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 119733#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119731#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119729#L1006-3 assume !(0 == ~E_2~0); 119695#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119693#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119691#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119688#L1026-3 assume !(0 == ~E_6~0); 119677#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 119670#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119662#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 119653#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119652#L472-33 assume !(1 == ~m_pc~0); 119651#L472-35 is_master_triggered_~__retres1~0#1 := 0; 119650#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119649#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119648#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119647#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119646#L491-33 assume !(1 == ~t1_pc~0); 119645#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 119644#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119643#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119642#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119641#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119640#L510-33 assume !(1 == ~t2_pc~0); 119639#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 119637#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119635#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119633#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 119624#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119594#L529-33 assume 1 == ~t3_pc~0; 119591#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 119588#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119586#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119584#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 119582#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119580#L548-33 assume 1 == ~t4_pc~0; 119577#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 119574#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119572#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119570#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119568#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119566#L567-33 assume 1 == ~t5_pc~0; 119563#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 119560#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119558#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119556#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119553#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119551#L586-33 assume !(1 == ~t6_pc~0); 119549#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 119546#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119544#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 119542#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119541#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119538#L605-33 assume 1 == ~t7_pc~0; 119536#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119533#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119531#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 119529#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 119527#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 119524#L624-33 assume 1 == ~t8_pc~0; 119521#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 119519#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 119517#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119515#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 119513#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 119510#L643-33 assume !(1 == ~t9_pc~0); 119429#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 119420#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119413#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119408#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 119403#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119342#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 119301#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119337#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119335#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119333#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119328#L1079-3 assume !(1 == ~T5_E~0); 119326#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 119324#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 119322#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 119320#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 119318#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119317#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119078#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119069#L1119-3 assume !(1 == ~E_3~0); 119064#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119060#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119034#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119029#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 119025#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 119020#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 119015#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118753#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118744#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118743#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 118741#L1459 assume !(0 == start_simulation_~tmp~3#1); 115782#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118647#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118637#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118635#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 118633#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118631#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118582#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 118565#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 118557#L1440-2 [2021-12-19 19:16:28,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2021-12-19 19:16:28,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129007108] [2021-12-19 19:16:28,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:28,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:28,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:28,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129007108] [2021-12-19 19:16:28,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2129007108] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:28,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:28,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:28,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926363577] [2021-12-19 19:16:28,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:28,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:28,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:28,789 INFO L85 PathProgramCache]: Analyzing trace with hash -732207867, now seen corresponding path program 1 times [2021-12-19 19:16:28,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:28,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412505778] [2021-12-19 19:16:28,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:28,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:28,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:28,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:28,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:28,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412505778] [2021-12-19 19:16:28,810 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412505778] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:28,810 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:28,810 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:28,810 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335468273] [2021-12-19 19:16:28,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:28,810 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:28,810 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:28,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:28,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:28,811 INFO L87 Difference]: Start difference. First operand 14650 states and 21100 transitions. cyclomatic complexity: 6466 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:29,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:29,088 INFO L93 Difference]: Finished difference Result 34936 states and 49944 transitions. [2021-12-19 19:16:29,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:29,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34936 states and 49944 transitions. [2021-12-19 19:16:29,231 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34653 [2021-12-19 19:16:29,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34936 states to 34936 states and 49944 transitions. [2021-12-19 19:16:29,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34936 [2021-12-19 19:16:29,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34936 [2021-12-19 19:16:29,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34936 states and 49944 transitions. [2021-12-19 19:16:29,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:29,499 INFO L681 BuchiCegarLoop]: Abstraction has 34936 states and 49944 transitions. [2021-12-19 19:16:29,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34936 states and 49944 transitions. [2021-12-19 19:16:29,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34936 to 27751. [2021-12-19 19:16:29,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27751 states, 27751 states have (on average 1.4338582393427264) internal successors, (39791), 27750 states have internal predecessors, (39791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:30,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27751 states to 27751 states and 39791 transitions. [2021-12-19 19:16:30,100 INFO L704 BuchiCegarLoop]: Abstraction has 27751 states and 39791 transitions. [2021-12-19 19:16:30,100 INFO L587 BuchiCegarLoop]: Abstraction has 27751 states and 39791 transitions. [2021-12-19 19:16:30,100 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:16:30,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27751 states and 39791 transitions. [2021-12-19 19:16:30,236 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27532 [2021-12-19 19:16:30,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:30,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:30,237 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:30,238 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:30,238 INFO L791 eck$LassoCheckResult]: Stem: 165043#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 165044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 165388#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165070#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164961#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 164688#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164689#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 165266#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 165321#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 165308#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 165309#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164806#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164794#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164795#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164605#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164606#L951 assume !(0 == ~M_E~0); 164343#L951-2 assume !(0 == ~T1_E~0); 164344#L956-1 assume !(0 == ~T2_E~0); 164505#L961-1 assume !(0 == ~T3_E~0); 164978#L966-1 assume !(0 == ~T4_E~0); 164979#L971-1 assume !(0 == ~T5_E~0); 165126#L976-1 assume !(0 == ~T6_E~0); 165097#L981-1 assume !(0 == ~T7_E~0); 164848#L986-1 assume !(0 == ~T8_E~0); 164558#L991-1 assume !(0 == ~T9_E~0); 164559#L996-1 assume !(0 == ~E_M~0); 165369#L1001-1 assume !(0 == ~E_1~0); 165041#L1006-1 assume !(0 == ~E_2~0); 165042#L1011-1 assume !(0 == ~E_3~0); 165325#L1016-1 assume !(0 == ~E_4~0); 165347#L1021-1 assume !(0 == ~E_5~0); 164144#L1026-1 assume !(0 == ~E_6~0); 164145#L1031-1 assume !(0 == ~E_7~0); 164992#L1036-1 assume !(0 == ~E_8~0); 164988#L1041-1 assume !(0 == ~E_9~0); 164989#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165276#L472 assume !(1 == ~m_pc~0); 165232#L472-2 is_master_triggered_~__retres1~0#1 := 0; 165020#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165021#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 165030#L1179 assume !(0 != activate_threads_~tmp~1#1); 164152#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164153#L491 assume !(1 == ~t1_pc~0); 164659#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164660#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164984#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164124#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 164125#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164148#L510 assume !(1 == ~t2_pc~0); 164111#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164112#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 165430#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 165422#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 164397#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164398#L529 assume !(1 == ~t3_pc~0); 164851#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165153#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165228#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 165358#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 164315#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164316#L548 assume !(1 == ~t4_pc~0); 164212#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 164211#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164515#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 164255#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 164256#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164204#L567 assume 1 == ~t5_pc~0; 164205#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164257#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164446#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 164447#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 165261#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 164326#L586 assume !(1 == ~t6_pc~0); 164327#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 164405#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 165384#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 165428#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 165252#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 165253#L605 assume 1 == ~t7_pc~0; 165226#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 164830#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164982#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164983#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 165412#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164952#L624 assume !(1 == ~t8_pc~0); 164391#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 164390#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 165015#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 165016#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 165236#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 164169#L643 assume 1 == ~t9_pc~0; 164170#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 165181#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 165100#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164565#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 164566#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164372#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 164373#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164533#L1064-1 assume !(1 == ~T2_E~0); 164534#L1069-1 assume !(1 == ~T3_E~0); 165408#L1074-1 assume !(1 == ~T4_E~0); 165234#L1079-1 assume !(1 == ~T5_E~0); 165235#L1084-1 assume !(1 == ~T6_E~0); 165332#L1089-1 assume !(1 == ~T7_E~0); 165333#L1094-1 assume !(1 == ~T8_E~0); 164877#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 164878#L1104-1 assume !(1 == ~E_M~0); 165086#L1109-1 assume !(1 == ~E_1~0); 165087#L1114-1 assume !(1 == ~E_2~0); 164678#L1119-1 assume !(1 == ~E_3~0); 165418#L1124-1 assume !(1 == ~E_4~0); 164165#L1129-1 assume !(1 == ~E_5~0); 164166#L1134-1 assume !(1 == ~E_6~0); 164503#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 164504#L1144-1 assume !(1 == ~E_8~0); 165424#L1149-1 assume !(1 == ~E_9~0); 165425#L1154-1 assume { :end_inline_reset_delta_events } true; 187036#L1440-2 [2021-12-19 19:16:30,238 INFO L793 eck$LassoCheckResult]: Loop: 187036#L1440-2 assume !false; 187033#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 187029#L926 assume !false; 187028#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 187026#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 183397#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 183392#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 183388#L795 assume !(0 != eval_~tmp~0#1); 183389#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 187991#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 187990#L951-3 assume !(0 == ~M_E~0); 187985#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187984#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 187983#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 187982#L966-3 assume !(0 == ~T4_E~0); 187981#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187980#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 187979#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 187978#L986-3 assume !(0 == ~T8_E~0); 187977#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 187976#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 187975#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187974#L1006-3 assume !(0 == ~E_2~0); 187972#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 187971#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 187970#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 187969#L1026-3 assume !(0 == ~E_6~0); 187968#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 187966#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 187963#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 187961#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 187959#L472-33 assume !(1 == ~m_pc~0); 187957#L472-35 is_master_triggered_~__retres1~0#1 := 0; 187955#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187953#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 187951#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187949#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187947#L491-33 assume !(1 == ~t1_pc~0); 187945#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 187943#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187939#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 187937#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187935#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187933#L510-33 assume !(1 == ~t2_pc~0); 187930#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 187915#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187912#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 187910#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 187907#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187905#L529-33 assume !(1 == ~t3_pc~0); 181171#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 187902#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187899#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 187897#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 187895#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187893#L548-33 assume !(1 == ~t4_pc~0); 187890#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 187886#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187884#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 187882#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187880#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187878#L567-33 assume !(1 == ~t5_pc~0); 187875#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 187874#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187873#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187871#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 187869#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187552#L586-33 assume 1 == ~t6_pc~0; 187527#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 187356#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187353#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187351#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 187349#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187347#L605-33 assume !(1 == ~t7_pc~0); 187344#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 187342#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 187339#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 187337#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 187335#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 187333#L624-33 assume 1 == ~t8_pc~0; 187330#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 187329#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 187328#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187326#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 187324#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 187322#L643-33 assume !(1 == ~t9_pc~0); 187319#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 187317#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 187315#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 187313#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 187312#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 187309#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 186005#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 187304#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 187302#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 187300#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 186888#L1079-3 assume !(1 == ~T5_E~0); 187296#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 187294#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 187292#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 187290#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 187288#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 187286#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 187283#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 187280#L1119-3 assume !(1 == ~E_3~0); 187278#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187276#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187274#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187272#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 187269#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 187267#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 187265#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 187214#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 187204#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 187202#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 187164#L1459 assume !(0 == start_simulation_~tmp~3#1); 187161#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 187061#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 187052#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 187048#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 187046#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 187044#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 187039#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 187038#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 187036#L1440-2 [2021-12-19 19:16:30,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:30,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2021-12-19 19:16:30,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:30,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344951670] [2021-12-19 19:16:30,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:30,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:30,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:30,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:30,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:30,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344951670] [2021-12-19 19:16:30,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344951670] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:30,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:30,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:30,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922597824] [2021-12-19 19:16:30,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:30,265 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:30,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:30,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1217659384, now seen corresponding path program 1 times [2021-12-19 19:16:30,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:30,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803781623] [2021-12-19 19:16:30,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:30,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:30,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:30,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:30,288 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:30,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803781623] [2021-12-19 19:16:30,289 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803781623] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:30,289 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:30,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:30,289 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949909559] [2021-12-19 19:16:30,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:30,289 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:30,290 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:30,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:30,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:30,290 INFO L87 Difference]: Start difference. First operand 27751 states and 39791 transitions. cyclomatic complexity: 12056 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:30,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:30,704 INFO L93 Difference]: Finished difference Result 65866 states and 93812 transitions. [2021-12-19 19:16:30,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:30,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65866 states and 93812 transitions. [2021-12-19 19:16:31,054 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 65472 [2021-12-19 19:16:31,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65866 states to 65866 states and 93812 transitions. [2021-12-19 19:16:31,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65866 [2021-12-19 19:16:31,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65866 [2021-12-19 19:16:31,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65866 states and 93812 transitions. [2021-12-19 19:16:31,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:31,308 INFO L681 BuchiCegarLoop]: Abstraction has 65866 states and 93812 transitions. [2021-12-19 19:16:31,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65866 states and 93812 transitions. [2021-12-19 19:16:31,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65866 to 52610. [2021-12-19 19:16:31,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52610 states, 52610 states have (on average 1.428321611860863) internal successors, (75144), 52609 states have internal predecessors, (75144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:32,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52610 states to 52610 states and 75144 transitions. [2021-12-19 19:16:32,068 INFO L704 BuchiCegarLoop]: Abstraction has 52610 states and 75144 transitions. [2021-12-19 19:16:32,068 INFO L587 BuchiCegarLoop]: Abstraction has 52610 states and 75144 transitions. [2021-12-19 19:16:32,068 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:16:32,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52610 states and 75144 transitions. [2021-12-19 19:16:32,226 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 52344 [2021-12-19 19:16:32,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:32,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:32,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:32,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:32,228 INFO L791 eck$LassoCheckResult]: Stem: 258675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 258676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 259044#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 258696#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 258594#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 258316#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 258317#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 258920#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 258972#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 258957#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 258958#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 258439#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 258427#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 258428#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 258235#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 258236#L951 assume !(0 == ~M_E~0); 257965#L951-2 assume !(0 == ~T1_E~0); 257966#L956-1 assume !(0 == ~T2_E~0); 258133#L961-1 assume !(0 == ~T3_E~0); 258610#L966-1 assume !(0 == ~T4_E~0); 258611#L971-1 assume !(0 == ~T5_E~0); 258757#L976-1 assume !(0 == ~T6_E~0); 258725#L981-1 assume !(0 == ~T7_E~0); 258476#L986-1 assume !(0 == ~T8_E~0); 258186#L991-1 assume !(0 == ~T9_E~0); 258187#L996-1 assume !(0 == ~E_M~0); 259021#L1001-1 assume !(0 == ~E_1~0); 258673#L1006-1 assume !(0 == ~E_2~0); 258674#L1011-1 assume !(0 == ~E_3~0); 258973#L1016-1 assume !(0 == ~E_4~0); 258998#L1021-1 assume !(0 == ~E_5~0); 257772#L1026-1 assume !(0 == ~E_6~0); 257773#L1031-1 assume !(0 == ~E_7~0); 258622#L1036-1 assume !(0 == ~E_8~0); 258618#L1041-1 assume !(0 == ~E_9~0); 258619#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 258934#L472 assume !(1 == ~m_pc~0); 258873#L472-2 is_master_triggered_~__retres1~0#1 := 0; 258652#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 258653#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 258660#L1179 assume !(0 != activate_threads_~tmp~1#1); 257780#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 257781#L491 assume !(1 == ~t1_pc~0); 258286#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 258287#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258616#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 257749#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 257750#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 257774#L510 assume !(1 == ~t2_pc~0); 257738#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 257739#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259094#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 259088#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 258022#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258023#L529 assume !(1 == ~t3_pc~0); 258481#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 258783#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 258867#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 259010#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 257942#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 257943#L548 assume !(1 == ~t4_pc~0); 257837#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 257836#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258141#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 257879#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 257880#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 257825#L567 assume !(1 == ~t5_pc~0); 257826#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 257878#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258070#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 258071#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 258915#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 257953#L586 assume !(1 == ~t6_pc~0); 257954#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 258028#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259039#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 259092#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 258907#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 258908#L605 assume 1 == ~t7_pc~0; 258861#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 258454#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 258614#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 258615#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 259072#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258588#L624 assume !(1 == ~t8_pc~0); 258015#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 258014#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 258646#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 258647#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 258882#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 257794#L643 assume 1 == ~t9_pc~0; 257795#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 258815#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 258727#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 258192#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 258193#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 257997#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 257998#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 258161#L1064-1 assume !(1 == ~T2_E~0); 258162#L1069-1 assume !(1 == ~T3_E~0); 258826#L1074-1 assume !(1 == ~T4_E~0); 295368#L1079-1 assume !(1 == ~T5_E~0); 300065#L1084-1 assume !(1 == ~T6_E~0); 300064#L1089-1 assume !(1 == ~T7_E~0); 300063#L1094-1 assume !(1 == ~T8_E~0); 300062#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 300061#L1104-1 assume !(1 == ~E_M~0); 300060#L1109-1 assume !(1 == ~E_1~0); 300059#L1114-1 assume !(1 == ~E_2~0); 258306#L1119-1 assume !(1 == ~E_3~0); 258366#L1124-1 assume !(1 == ~E_4~0); 258367#L1129-1 assume !(1 == ~E_5~0); 300057#L1134-1 assume !(1 == ~E_6~0); 300056#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 300055#L1144-1 assume !(1 == ~E_8~0); 300053#L1149-1 assume !(1 == ~E_9~0); 300051#L1154-1 assume { :end_inline_reset_delta_events } true; 300048#L1440-2 [2021-12-19 19:16:32,228 INFO L793 eck$LassoCheckResult]: Loop: 300048#L1440-2 assume !false; 299934#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 299929#L926 assume !false; 299927#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 299919#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 299909#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 299907#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 299904#L795 assume !(0 != eval_~tmp~0#1); 299905#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 301943#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 301941#L951-3 assume !(0 == ~M_E~0); 301939#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 301936#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 301934#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 301932#L966-3 assume !(0 == ~T4_E~0); 301930#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 301928#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 301926#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 301923#L986-3 assume !(0 == ~T8_E~0); 301921#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 301919#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 301917#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 301915#L1006-3 assume !(0 == ~E_2~0); 301913#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 301911#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 301909#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 301907#L1026-3 assume !(0 == ~E_6~0); 301905#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 301904#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 301902#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 301900#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 301898#L472-33 assume !(1 == ~m_pc~0); 301874#L472-35 is_master_triggered_~__retres1~0#1 := 0; 301862#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 301851#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 301841#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 301834#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 301828#L491-33 assume !(1 == ~t1_pc~0); 301824#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 301819#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 301815#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 301809#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 301805#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 301766#L510-33 assume 1 == ~t2_pc~0; 301760#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 301755#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301750#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 301745#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 301741#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300257#L529-33 assume !(1 == ~t3_pc~0); 300253#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 300251#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 300249#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 300246#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 300245#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300243#L548-33 assume 1 == ~t4_pc~0; 300240#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 300238#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300236#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 300234#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 300232#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 300230#L567-33 assume !(1 == ~t5_pc~0); 281940#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 300227#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 300225#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 300223#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 300221#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300217#L586-33 assume 1 == ~t6_pc~0; 300214#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 300212#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 300210#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 300207#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 300205#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 300202#L605-33 assume !(1 == ~t7_pc~0); 300198#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 300196#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 300194#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 300192#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 300190#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 300188#L624-33 assume 1 == ~t8_pc~0; 300184#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 300182#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 300180#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 300178#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 300176#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 300174#L643-33 assume !(1 == ~t9_pc~0); 300172#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 300170#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 300168#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 300166#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 300164#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300162#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 296279#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 300156#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 300154#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 300152#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 299130#L1079-3 assume !(1 == ~T5_E~0); 300149#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 300146#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 300144#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 300142#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 300140#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 300138#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 300136#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 300131#L1119-3 assume !(1 == ~E_3~0); 300129#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 300127#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 300125#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 300123#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 300121#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 300118#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 300116#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 300110#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 300100#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 300098#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 300096#L1459 assume !(0 == start_simulation_~tmp~3#1); 300093#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 300087#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 300077#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 300075#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 300073#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 300071#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 300069#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 300050#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 300048#L1440-2 [2021-12-19 19:16:32,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:32,229 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2021-12-19 19:16:32,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:32,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734957209] [2021-12-19 19:16:32,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:32,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:32,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:32,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:32,259 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:32,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734957209] [2021-12-19 19:16:32,259 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734957209] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:32,259 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:32,259 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:32,260 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047454800] [2021-12-19 19:16:32,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:32,260 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:32,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:32,260 INFO L85 PathProgramCache]: Analyzing trace with hash 452619524, now seen corresponding path program 1 times [2021-12-19 19:16:32,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:32,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496371001] [2021-12-19 19:16:32,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:32,261 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:32,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:32,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:32,281 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:32,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496371001] [2021-12-19 19:16:32,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496371001] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:32,282 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:32,282 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:32,282 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575509712] [2021-12-19 19:16:32,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:32,283 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:32,283 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:32,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:32,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:32,283 INFO L87 Difference]: Start difference. First operand 52610 states and 75144 transitions. cyclomatic complexity: 22550 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:32,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:32,850 INFO L93 Difference]: Finished difference Result 123973 states and 175993 transitions. [2021-12-19 19:16:32,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:32,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123973 states and 175993 transitions. [2021-12-19 19:16:33,559 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 123356 [2021-12-19 19:16:33,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123973 states to 123973 states and 175993 transitions. [2021-12-19 19:16:33,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123973 [2021-12-19 19:16:33,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123973 [2021-12-19 19:16:33,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123973 states and 175993 transitions. [2021-12-19 19:16:34,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:34,017 INFO L681 BuchiCegarLoop]: Abstraction has 123973 states and 175993 transitions. [2021-12-19 19:16:34,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123973 states and 175993 transitions. [2021-12-19 19:16:34,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123973 to 99673. [2021-12-19 19:16:34,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99673 states, 99673 states have (on average 1.423504860895127) internal successors, (141885), 99672 states have internal predecessors, (141885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:35,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99673 states to 99673 states and 141885 transitions. [2021-12-19 19:16:35,477 INFO L704 BuchiCegarLoop]: Abstraction has 99673 states and 141885 transitions. [2021-12-19 19:16:35,477 INFO L587 BuchiCegarLoop]: Abstraction has 99673 states and 141885 transitions. [2021-12-19 19:16:35,477 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:16:35,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99673 states and 141885 transitions. [2021-12-19 19:16:35,717 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 99312 [2021-12-19 19:16:35,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:35,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:35,733 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:35,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:35,739 INFO L791 eck$LassoCheckResult]: Stem: 435283#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 435284#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 435658#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 435306#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 435192#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 434908#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434909#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 435517#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 435584#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 435566#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 435567#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 435029#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 435018#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 435019#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 434827#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 434828#L951 assume !(0 == ~M_E~0); 434555#L951-2 assume !(0 == ~T1_E~0); 434556#L956-1 assume !(0 == ~T2_E~0); 434724#L961-1 assume !(0 == ~T3_E~0); 435213#L966-1 assume !(0 == ~T4_E~0); 435214#L971-1 assume !(0 == ~T5_E~0); 435365#L976-1 assume !(0 == ~T6_E~0); 435336#L981-1 assume !(0 == ~T7_E~0); 435069#L986-1 assume !(0 == ~T8_E~0); 434779#L991-1 assume !(0 == ~T9_E~0); 434780#L996-1 assume !(0 == ~E_M~0); 435635#L1001-1 assume !(0 == ~E_1~0); 435281#L1006-1 assume !(0 == ~E_2~0); 435282#L1011-1 assume !(0 == ~E_3~0); 435585#L1016-1 assume !(0 == ~E_4~0); 435611#L1021-1 assume !(0 == ~E_5~0); 434365#L1026-1 assume !(0 == ~E_6~0); 434366#L1031-1 assume !(0 == ~E_7~0); 435225#L1036-1 assume !(0 == ~E_8~0); 435221#L1041-1 assume !(0 == ~E_9~0); 435222#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435531#L472 assume !(1 == ~m_pc~0); 435478#L472-2 is_master_triggered_~__retres1~0#1 := 0; 435259#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 435260#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 435268#L1179 assume !(0 != activate_threads_~tmp~1#1); 434373#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 434374#L491 assume !(1 == ~t1_pc~0); 434880#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 434881#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435219#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 434342#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 434343#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 434367#L510 assume !(1 == ~t2_pc~0); 434331#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 434332#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 435715#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 435701#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 434614#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434615#L529 assume !(1 == ~t3_pc~0); 435074#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 435394#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 435470#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 435625#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 434532#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434533#L548 assume !(1 == ~t4_pc~0); 434430#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 434429#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434732#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 434471#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 434472#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 434418#L567 assume !(1 == ~t5_pc~0); 434419#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 434470#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434662#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 434663#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 435510#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 434543#L586 assume !(1 == ~t6_pc~0); 434544#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 434620#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 435653#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 435707#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 435505#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 435506#L605 assume !(1 == ~t7_pc~0); 435043#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 435044#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 435217#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 435218#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 435681#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 435186#L624 assume !(1 == ~t8_pc~0); 434607#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 434606#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 435252#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 435253#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 435483#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 434387#L643 assume 1 == ~t9_pc~0; 434388#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 435422#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 435338#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 434784#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 434785#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434588#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 434589#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 434753#L1064-1 assume !(1 == ~T2_E~0); 434754#L1069-1 assume !(1 == ~T3_E~0); 435677#L1074-1 assume !(1 == ~T4_E~0); 435479#L1079-1 assume !(1 == ~T5_E~0); 435480#L1084-1 assume !(1 == ~T6_E~0); 435593#L1089-1 assume !(1 == ~T7_E~0); 435594#L1094-1 assume !(1 == ~T8_E~0); 435103#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 435104#L1104-1 assume !(1 == ~E_M~0); 435322#L1109-1 assume !(1 == ~E_1~0); 435323#L1114-1 assume !(1 == ~E_2~0); 434900#L1119-1 assume !(1 == ~E_3~0); 467395#L1124-1 assume !(1 == ~E_4~0); 467394#L1129-1 assume !(1 == ~E_5~0); 467393#L1134-1 assume !(1 == ~E_6~0); 467392#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 467391#L1144-1 assume !(1 == ~E_8~0); 467390#L1149-1 assume !(1 == ~E_9~0); 467389#L1154-1 assume { :end_inline_reset_delta_events } true; 467386#L1440-2 [2021-12-19 19:16:35,740 INFO L793 eck$LassoCheckResult]: Loop: 467386#L1440-2 assume !false; 467383#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 467379#L926 assume !false; 467378#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 467375#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 467365#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 467363#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 467360#L795 assume !(0 != eval_~tmp~0#1); 467361#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 477367#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 477341#L951-3 assume !(0 == ~M_E~0); 477333#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 477330#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 477328#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 477326#L966-3 assume !(0 == ~T4_E~0); 477324#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 477322#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 477316#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 477312#L986-3 assume !(0 == ~T8_E~0); 477310#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 477308#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 477303#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 477302#L1006-3 assume !(0 == ~E_2~0); 477301#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 477300#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 477294#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 477275#L1026-3 assume !(0 == ~E_6~0); 477242#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 477192#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 477146#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 475801#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475798#L472-33 assume !(1 == ~m_pc~0); 475796#L472-35 is_master_triggered_~__retres1~0#1 := 0; 475794#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475792#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475790#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475788#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475785#L491-33 assume !(1 == ~t1_pc~0); 475783#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 475781#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475779#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475777#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475774#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475772#L510-33 assume 1 == ~t2_pc~0; 475770#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 475771#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475953#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475761#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 475758#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475756#L529-33 assume !(1 == ~t3_pc~0); 470916#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 475753#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475751#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475750#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 475749#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475745#L548-33 assume !(1 == ~t4_pc~0); 475743#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 475740#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475739#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475738#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 475737#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475736#L567-33 assume !(1 == ~t5_pc~0); 463388#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 474157#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474156#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 474155#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 474153#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 474152#L586-33 assume !(1 == ~t6_pc~0); 474147#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 474144#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 474142#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 474140#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 474138#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 474136#L605-33 assume !(1 == ~t7_pc~0); 459503#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 474133#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 474131#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 474126#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 474120#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 474113#L624-33 assume !(1 == ~t8_pc~0); 474108#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 474102#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474097#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 474091#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 474084#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 474078#L643-33 assume !(1 == ~t9_pc~0); 474071#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 474065#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 473721#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 473718#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 473716#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473714#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 462653#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 473711#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 473709#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 473708#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 462704#L1079-3 assume !(1 == ~T5_E~0); 473705#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 473703#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 473701#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 473699#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 473696#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 473694#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 473692#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 470098#L1119-3 assume !(1 == ~E_3~0); 468622#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 468611#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 468609#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 468607#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 468605#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 468603#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 468601#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 467442#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 467432#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 467430#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 467428#L1459 assume !(0 == start_simulation_~tmp~3#1); 467424#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 467418#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 467409#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 467405#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 467403#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 467401#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 467396#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 467388#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 467386#L1440-2 [2021-12-19 19:16:35,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:35,741 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2021-12-19 19:16:35,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:35,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620323509] [2021-12-19 19:16:35,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:35,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:35,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:35,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:35,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:35,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1620323509] [2021-12-19 19:16:35,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1620323509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:35,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:35,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:35,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979907773] [2021-12-19 19:16:35,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:35,766 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:35,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:35,767 INFO L85 PathProgramCache]: Analyzing trace with hash 957038023, now seen corresponding path program 1 times [2021-12-19 19:16:35,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:35,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011827347] [2021-12-19 19:16:35,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:35,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:35,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:35,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:35,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:35,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011827347] [2021-12-19 19:16:35,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011827347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:35,789 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:35,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:35,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145178192] [2021-12-19 19:16:35,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:35,790 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:35,790 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:35,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:35,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:35,790 INFO L87 Difference]: Start difference. First operand 99673 states and 141885 transitions. cyclomatic complexity: 42228 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:36,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:36,807 INFO L93 Difference]: Finished difference Result 232760 states and 329482 transitions. [2021-12-19 19:16:36,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:36,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232760 states and 329482 transitions. [2021-12-19 19:16:37,979 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 231696 [2021-12-19 19:16:38,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232760 states to 232760 states and 329482 transitions. [2021-12-19 19:16:38,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232760 [2021-12-19 19:16:38,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232760 [2021-12-19 19:16:38,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232760 states and 329482 transitions. [2021-12-19 19:16:38,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:38,903 INFO L681 BuchiCegarLoop]: Abstraction has 232760 states and 329482 transitions. [2021-12-19 19:16:39,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232760 states and 329482 transitions. [2021-12-19 19:16:40,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232760 to 188552. [2021-12-19 19:16:41,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188552 states, 188552 states have (on average 1.4193750265178837) internal successors, (267626), 188551 states have internal predecessors, (267626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:41,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188552 states to 188552 states and 267626 transitions. [2021-12-19 19:16:41,452 INFO L704 BuchiCegarLoop]: Abstraction has 188552 states and 267626 transitions. [2021-12-19 19:16:41,452 INFO L587 BuchiCegarLoop]: Abstraction has 188552 states and 267626 transitions. [2021-12-19 19:16:41,453 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:16:41,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188552 states and 267626 transitions. [2021-12-19 19:16:41,929 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 188000 [2021-12-19 19:16:41,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:41,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:41,933 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:41,933 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:41,933 INFO L791 eck$LassoCheckResult]: Stem: 767731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 767732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 768141#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 767759#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 767642#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 767346#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 767347#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 767993#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 768060#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 768041#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 768042#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 767469#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 767455#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 767456#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 767267#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 767268#L951 assume !(0 == ~M_E~0); 766997#L951-2 assume !(0 == ~T1_E~0); 766998#L956-1 assume !(0 == ~T2_E~0); 767164#L961-1 assume !(0 == ~T3_E~0); 767658#L966-1 assume !(0 == ~T4_E~0); 767659#L971-1 assume !(0 == ~T5_E~0); 767820#L976-1 assume !(0 == ~T6_E~0); 767788#L981-1 assume !(0 == ~T7_E~0); 767509#L986-1 assume !(0 == ~T8_E~0); 767217#L991-1 assume !(0 == ~T9_E~0); 767218#L996-1 assume !(0 == ~E_M~0); 768116#L1001-1 assume !(0 == ~E_1~0); 767729#L1006-1 assume !(0 == ~E_2~0); 767730#L1011-1 assume !(0 == ~E_3~0); 768061#L1016-1 assume !(0 == ~E_4~0); 768088#L1021-1 assume !(0 == ~E_5~0); 766807#L1026-1 assume !(0 == ~E_6~0); 766808#L1031-1 assume !(0 == ~E_7~0); 767673#L1036-1 assume !(0 == ~E_8~0); 767669#L1041-1 assume !(0 == ~E_9~0); 767670#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 768006#L472 assume !(1 == ~m_pc~0); 767945#L472-2 is_master_triggered_~__retres1~0#1 := 0; 767707#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767708#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 767716#L1179 assume !(0 != activate_threads_~tmp~1#1); 766815#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 766816#L491 assume !(1 == ~t1_pc~0); 767318#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 767319#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 767667#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 766785#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 766786#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 766809#L510 assume !(1 == ~t2_pc~0); 766774#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 766775#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 768216#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768201#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 767053#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 767054#L529 assume !(1 == ~t3_pc~0); 767514#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 767850#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 767938#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 768101#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 766974#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766975#L548 assume !(1 == ~t4_pc~0); 766871#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 766870#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 767173#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 766911#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 766912#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 766859#L567 assume !(1 == ~t5_pc~0); 766860#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 766913#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 767102#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 767103#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 767988#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 766985#L586 assume !(1 == ~t6_pc~0); 766986#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 767059#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 768132#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 768211#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 767978#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 767979#L605 assume !(1 == ~t7_pc~0); 767483#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 767484#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 767662#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 767663#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 768169#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 767634#L624 assume !(1 == ~t8_pc~0); 767047#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 767046#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 767701#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 767702#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 767949#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 766829#L643 assume !(1 == ~t9_pc~0); 766830#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 767883#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 767790#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 767222#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 767223#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 767029#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 767030#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 888960#L1064-1 assume !(1 == ~T2_E~0); 888959#L1069-1 assume !(1 == ~T3_E~0); 888958#L1074-1 assume !(1 == ~T4_E~0); 888957#L1079-1 assume !(1 == ~T5_E~0); 888955#L1084-1 assume !(1 == ~T6_E~0); 888953#L1089-1 assume !(1 == ~T7_E~0); 888951#L1094-1 assume !(1 == ~T8_E~0); 888949#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 888947#L1104-1 assume !(1 == ~E_M~0); 888946#L1109-1 assume !(1 == ~E_1~0); 888939#L1114-1 assume !(1 == ~E_2~0); 888935#L1119-1 assume !(1 == ~E_3~0); 888930#L1124-1 assume !(1 == ~E_4~0); 888925#L1129-1 assume !(1 == ~E_5~0); 886864#L1134-1 assume !(1 == ~E_6~0); 886862#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 886860#L1144-1 assume !(1 == ~E_8~0); 886858#L1149-1 assume !(1 == ~E_9~0); 824704#L1154-1 assume { :end_inline_reset_delta_events } true; 824701#L1440-2 [2021-12-19 19:16:41,933 INFO L793 eck$LassoCheckResult]: Loop: 824701#L1440-2 assume !false; 824699#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 824693#L926 assume !false; 824691#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 824589#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 824579#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 824577#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 824574#L795 assume !(0 != eval_~tmp~0#1); 824575#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 952649#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 952645#L951-3 assume !(0 == ~M_E~0); 952641#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 952637#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 952633#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 952628#L966-3 assume !(0 == ~T4_E~0); 952623#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 952619#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 952615#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 952611#L986-3 assume !(0 == ~T8_E~0); 952607#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 952588#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 952584#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 952580#L1006-3 assume !(0 == ~E_2~0); 952552#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 952550#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 952549#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 767566#L1026-3 assume !(0 == ~E_6~0); 767567#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 952162#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 952160#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 767889#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767832#L472-33 assume !(1 == ~m_pc~0); 766937#L472-35 is_master_triggered_~__retres1~0#1 := 0; 766938#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766780#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 766781#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 767386#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 767387#L491-33 assume !(1 == ~t1_pc~0); 766874#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 766875#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768099#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 768127#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 768128#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 767779#L510-33 assume !(1 == ~t2_pc~0); 767776#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 767777#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 767660#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 767661#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 766767#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766768#L529-33 assume !(1 == ~t3_pc~0); 930093#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 930091#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 930089#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 930087#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 930085#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 930084#L548-33 assume !(1 == ~t4_pc~0); 930082#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 930079#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 930077#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 930055#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 930047#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 930040#L567-33 assume !(1 == ~t5_pc~0); 908096#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 929968#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 929959#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 929952#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 929945#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 929937#L586-33 assume !(1 == ~t6_pc~0); 929934#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 929930#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 929929#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 929927#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 929924#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 929921#L605-33 assume !(1 == ~t7_pc~0); 853973#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 929916#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 929900#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 929895#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 929889#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 929882#L624-33 assume !(1 == ~t8_pc~0); 929874#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 929867#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 929859#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 929854#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 929779#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 824833#L643-33 assume !(1 == ~t9_pc~0); 824831#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 824829#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 824827#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 824825#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 824823#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 824821#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 824817#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 824813#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 824811#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 824809#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 824805#L1079-3 assume !(1 == ~T5_E~0); 824803#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 824801#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 824799#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 824797#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 824796#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 824795#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 824793#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 824789#L1119-3 assume !(1 == ~E_3~0); 824787#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 824785#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 824783#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 824781#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 824779#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 824776#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 824774#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 824752#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 824741#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 824739#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 824736#L1459 assume !(0 == start_simulation_~tmp~3#1); 824733#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 824725#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 824715#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 824713#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 824711#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 824710#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 824708#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 824703#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 824701#L1440-2 [2021-12-19 19:16:41,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:41,938 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2021-12-19 19:16:41,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:41,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751247351] [2021-12-19 19:16:41,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:41,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:41,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:41,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:41,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:41,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751247351] [2021-12-19 19:16:41,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751247351] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:41,957 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:41,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:41,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810752285] [2021-12-19 19:16:41,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:41,958 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:41,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:41,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1850869750, now seen corresponding path program 1 times [2021-12-19 19:16:41,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:41,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395463637] [2021-12-19 19:16:41,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:41,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:41,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:41,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:41,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:41,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395463637] [2021-12-19 19:16:41,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395463637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:41,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:41,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:41,978 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840123097] [2021-12-19 19:16:41,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:41,978 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:41,978 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:41,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:41,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:41,979 INFO L87 Difference]: Start difference. First operand 188552 states and 267626 transitions. cyclomatic complexity: 79090 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:43,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:43,022 INFO L93 Difference]: Finished difference Result 236604 states and 336049 transitions. [2021-12-19 19:16:43,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:43,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236604 states and 336049 transitions. [2021-12-19 19:16:44,386 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 235968 [2021-12-19 19:16:44,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236604 states to 236604 states and 336049 transitions. [2021-12-19 19:16:44,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 236604 [2021-12-19 19:16:45,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 236604 [2021-12-19 19:16:45,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236604 states and 336049 transitions. [2021-12-19 19:16:45,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:45,125 INFO L681 BuchiCegarLoop]: Abstraction has 236604 states and 336049 transitions. [2021-12-19 19:16:45,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236604 states and 336049 transitions. [2021-12-19 19:16:46,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236604 to 100860. [2021-12-19 19:16:46,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100860 states, 100860 states have (on average 1.425698988697204) internal successors, (143796), 100859 states have internal predecessors, (143796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:46,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100860 states to 100860 states and 143796 transitions. [2021-12-19 19:16:46,869 INFO L704 BuchiCegarLoop]: Abstraction has 100860 states and 143796 transitions. [2021-12-19 19:16:46,869 INFO L587 BuchiCegarLoop]: Abstraction has 100860 states and 143796 transitions. [2021-12-19 19:16:46,869 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:16:46,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100860 states and 143796 transitions. [2021-12-19 19:16:47,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 100544 [2021-12-19 19:16:47,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:47,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:47,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:47,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:47,171 INFO L791 eck$LassoCheckResult]: Stem: 1192894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1192895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1193291#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1192923#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1192806#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1192522#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1192523#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1193141#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1193205#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1193188#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1193189#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1192641#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1192630#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1192631#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1192436#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1192437#L951 assume !(0 == ~M_E~0); 1192165#L951-2 assume !(0 == ~T1_E~0); 1192166#L956-1 assume !(0 == ~T2_E~0); 1192331#L961-1 assume !(0 == ~T3_E~0); 1192824#L966-1 assume !(0 == ~T4_E~0); 1192825#L971-1 assume !(0 == ~T5_E~0); 1192978#L976-1 assume !(0 == ~T6_E~0); 1192949#L981-1 assume !(0 == ~T7_E~0); 1192681#L986-1 assume !(0 == ~T8_E~0); 1192384#L991-1 assume !(0 == ~T9_E~0); 1192385#L996-1 assume !(0 == ~E_M~0); 1193264#L1001-1 assume !(0 == ~E_1~0); 1192892#L1006-1 assume !(0 == ~E_2~0); 1192893#L1011-1 assume !(0 == ~E_3~0); 1193209#L1016-1 assume !(0 == ~E_4~0); 1193234#L1021-1 assume !(0 == ~E_5~0); 1191970#L1026-1 assume !(0 == ~E_6~0); 1191971#L1031-1 assume !(0 == ~E_7~0); 1192839#L1036-1 assume !(0 == ~E_8~0); 1192835#L1041-1 assume !(0 == ~E_9~0); 1192836#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1193150#L472 assume !(1 == ~m_pc~0); 1193101#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1192871#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1192872#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1192881#L1179 assume !(0 != activate_threads_~tmp~1#1); 1191978#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191979#L491 assume !(1 == ~t1_pc~0); 1192491#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1192492#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1192831#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1191950#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1191951#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1191974#L510 assume !(1 == ~t2_pc~0); 1191937#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1191938#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1193355#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1193342#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1192217#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1192218#L529 assume !(1 == ~t3_pc~0); 1192684#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1193006#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1193096#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1193250#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1192137#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1192138#L548 assume !(1 == ~t4_pc~0); 1192034#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1192033#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1192341#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1192077#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1192078#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1192027#L567 assume !(1 == ~t5_pc~0); 1192028#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1192076#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1192268#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1192269#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1193135#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1192148#L586 assume !(1 == ~t6_pc~0); 1192149#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1192225#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1193281#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1193351#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1193131#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1193132#L605 assume !(1 == ~t7_pc~0); 1192663#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1192664#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1192828#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1192829#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1193319#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1192799#L624 assume !(1 == ~t8_pc~0); 1192211#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1192210#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1192865#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1192866#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1193107#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1191994#L643 assume !(1 == ~t9_pc~0); 1191995#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1193041#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1192952#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1192391#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1192392#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1192193#L1059 assume !(1 == ~M_E~0); 1192194#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1192360#L1064-1 assume !(1 == ~T2_E~0); 1192361#L1069-1 assume !(1 == ~T3_E~0); 1193051#L1074-1 assume !(1 == ~T4_E~0); 1193103#L1079-1 assume !(1 == ~T5_E~0); 1193089#L1084-1 assume !(1 == ~T6_E~0); 1193090#L1089-1 assume !(1 == ~T7_E~0); 1193118#L1094-1 assume !(1 == ~T8_E~0); 1192711#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1192712#L1104-1 assume !(1 == ~E_M~0); 1192939#L1109-1 assume !(1 == ~E_1~0); 1192511#L1114-1 assume !(1 == ~E_2~0); 1192512#L1119-1 assume !(1 == ~E_3~0); 1192573#L1124-1 assume !(1 == ~E_4~0); 1191990#L1129-1 assume !(1 == ~E_5~0); 1191991#L1134-1 assume !(1 == ~E_6~0); 1192329#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1192330#L1144-1 assume !(1 == ~E_8~0); 1192531#L1149-1 assume !(1 == ~E_9~0); 1192155#L1154-1 assume { :end_inline_reset_delta_events } true; 1192156#L1440-2 [2021-12-19 19:16:47,172 INFO L793 eck$LassoCheckResult]: Loop: 1192156#L1440-2 assume !false; 1257471#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1257467#L926 assume !false; 1257466#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1257384#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1257371#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1257367#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1257346#L795 assume !(0 != eval_~tmp~0#1); 1257347#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1288945#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1288943#L951-3 assume !(0 == ~M_E~0); 1288941#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1288939#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1288937#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1288935#L966-3 assume !(0 == ~T4_E~0); 1288933#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1288931#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1288929#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1288927#L986-3 assume !(0 == ~T8_E~0); 1288925#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1288923#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1288921#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1288919#L1006-3 assume !(0 == ~E_2~0); 1288917#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1288915#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1288913#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1288911#L1026-3 assume !(0 == ~E_6~0); 1288909#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1288907#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1288905#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1288903#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1288901#L472-33 assume !(1 == ~m_pc~0); 1288899#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1288897#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1288895#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1288893#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1288891#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1288889#L491-33 assume !(1 == ~t1_pc~0); 1288887#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1288885#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1288883#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1288881#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1288879#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1288877#L510-33 assume !(1 == ~t2_pc~0); 1288871#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1288869#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1288867#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1288865#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1288861#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1288859#L529-33 assume !(1 == ~t3_pc~0); 1288290#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1288857#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1288855#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1288853#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1288851#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1288849#L548-33 assume !(1 == ~t4_pc~0); 1288847#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1288843#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1288841#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1288839#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1288837#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1288835#L567-33 assume !(1 == ~t5_pc~0); 1288830#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1288827#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1288825#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1288823#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1288821#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1288819#L586-33 assume !(1 == ~t6_pc~0); 1288817#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1288813#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1288811#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1288809#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1288807#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1266274#L605-33 assume !(1 == ~t7_pc~0); 1266272#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1266270#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1266265#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1266264#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1266263#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1266262#L624-33 assume !(1 == ~t8_pc~0); 1266261#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1266259#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1266258#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1266257#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1266237#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1266236#L643-33 assume !(1 == ~t9_pc~0); 1246365#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1266235#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1266234#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1266223#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1266221#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1266219#L1059-3 assume !(1 == ~M_E~0); 1231527#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1266216#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1266214#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1266212#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1266210#L1079-3 assume !(1 == ~T5_E~0); 1266209#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1266208#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1266207#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1266206#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1266205#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1266204#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1266203#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1266201#L1119-3 assume !(1 == ~E_3~0); 1266199#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1266197#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1266195#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1266193#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1266191#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1266189#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1266188#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1266182#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1266172#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1260406#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1231841#L1459 assume !(0 == start_simulation_~tmp~3#1); 1231842#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1257544#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1257531#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1257530#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1257529#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1257528#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1257525#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1257506#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1192156#L1440-2 [2021-12-19 19:16:47,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:47,172 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2021-12-19 19:16:47,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:47,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373412321] [2021-12-19 19:16:47,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:47,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:47,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:47,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:47,195 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:47,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373412321] [2021-12-19 19:16:47,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373412321] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:47,195 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:47,195 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:47,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331392766] [2021-12-19 19:16:47,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:47,196 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:47,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:47,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1923256308, now seen corresponding path program 1 times [2021-12-19 19:16:47,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:47,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556894790] [2021-12-19 19:16:47,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:47,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:47,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:47,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:47,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:47,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556894790] [2021-12-19 19:16:47,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556894790] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:47,215 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:47,215 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:47,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201700392] [2021-12-19 19:16:47,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:47,215 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:47,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:47,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:47,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:47,216 INFO L87 Difference]: Start difference. First operand 100860 states and 143796 transitions. cyclomatic complexity: 42940 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:48,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:48,022 INFO L93 Difference]: Finished difference Result 159399 states and 226739 transitions. [2021-12-19 19:16:48,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:48,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 159399 states and 226739 transitions. [2021-12-19 19:16:48,605 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 158880 [2021-12-19 19:16:48,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 159399 states to 159399 states and 226739 transitions. [2021-12-19 19:16:48,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159399 [2021-12-19 19:16:49,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159399 [2021-12-19 19:16:49,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 159399 states and 226739 transitions. [2021-12-19 19:16:49,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:49,599 INFO L681 BuchiCegarLoop]: Abstraction has 159399 states and 226739 transitions. [2021-12-19 19:16:49,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159399 states and 226739 transitions. [2021-12-19 19:16:50,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159399 to 112596. [2021-12-19 19:16:50,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112596 states, 112596 states have (on average 1.4265338022665104) internal successors, (160622), 112595 states have internal predecessors, (160622), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:51,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112596 states to 112596 states and 160622 transitions. [2021-12-19 19:16:51,252 INFO L704 BuchiCegarLoop]: Abstraction has 112596 states and 160622 transitions. [2021-12-19 19:16:51,252 INFO L587 BuchiCegarLoop]: Abstraction has 112596 states and 160622 transitions. [2021-12-19 19:16:51,252 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:16:51,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112596 states and 160622 transitions. [2021-12-19 19:16:51,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 112192 [2021-12-19 19:16:51,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:51,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:51,551 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:51,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:51,552 INFO L791 eck$LassoCheckResult]: Stem: 1453153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1453154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1453562#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1453184#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1453060#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1452782#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1452783#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1453410#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1453475#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1453464#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1453465#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1452903#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1452893#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1452894#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1452702#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1452703#L951 assume !(0 == ~M_E~0); 1452435#L951-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1452436#L956-1 assume !(0 == ~T2_E~0); 1452599#L961-1 assume !(0 == ~T3_E~0); 1453687#L966-1 assume !(0 == ~T4_E~0); 1453249#L971-1 assume !(0 == ~T5_E~0); 1453250#L976-1 assume !(0 == ~T6_E~0); 1453216#L981-1 assume !(0 == ~T7_E~0); 1453217#L986-1 assume !(0 == ~T8_E~0); 1453686#L991-1 assume !(0 == ~T9_E~0); 1453619#L996-1 assume !(0 == ~E_M~0); 1453533#L1001-1 assume !(0 == ~E_1~0); 1453534#L1006-1 assume !(0 == ~E_2~0); 1453684#L1011-1 assume !(0 == ~E_3~0); 1453683#L1016-1 assume !(0 == ~E_4~0); 1453599#L1021-1 assume !(0 == ~E_5~0); 1453600#L1026-1 assume !(0 == ~E_6~0); 1453641#L1031-1 assume !(0 == ~E_7~0); 1453642#L1036-1 assume !(0 == ~E_8~0); 1453091#L1041-1 assume !(0 == ~E_9~0); 1453092#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453594#L472 assume !(1 == ~m_pc~0); 1453595#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1453129#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1453130#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1453560#L1179 assume !(0 != activate_threads_~tmp~1#1); 1452248#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1452249#L491 assume !(1 == ~t1_pc~0); 1453459#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1453228#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1453086#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1453087#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1452243#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1452244#L510 assume !(1 == ~t2_pc~0); 1453394#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1453666#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1453667#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453636#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1453637#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1452945#L529 assume !(1 == ~t3_pc~0); 1452946#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1453358#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1453359#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1453515#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1452408#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1452409#L548 assume !(1 == ~t4_pc~0); 1453677#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1452610#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1452611#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1453473#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1453226#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1453227#L567 assume !(1 == ~t5_pc~0); 1452348#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1452349#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1452539#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1452540#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1453555#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1452419#L586 assume !(1 == ~t6_pc~0); 1452420#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1453673#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1453652#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1453653#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1453396#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1453397#L605 assume !(1 == ~t7_pc~0); 1452924#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1452925#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1453672#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1453607#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1453608#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1453671#L624 assume !(1 == ~t8_pc~0); 1452481#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1452480#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1453121#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1453122#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1453643#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1453644#L643 assume !(1 == ~t9_pc~0); 1453670#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1453307#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1453308#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1453669#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1453615#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1452464#L1059 assume !(1 == ~M_E~0); 1452465#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1452630#L1064-1 assume !(1 == ~T2_E~0); 1452631#L1069-1 assume !(1 == ~T3_E~0); 1453316#L1074-1 assume !(1 == ~T4_E~0); 1453367#L1079-1 assume !(1 == ~T5_E~0); 1453350#L1084-1 assume !(1 == ~T6_E~0); 1453351#L1089-1 assume !(1 == ~T7_E~0); 1453385#L1094-1 assume !(1 == ~T8_E~0); 1452970#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1452971#L1104-1 assume !(1 == ~E_M~0); 1453205#L1109-1 assume !(1 == ~E_1~0); 1452772#L1114-1 assume !(1 == ~E_2~0); 1452773#L1119-1 assume !(1 == ~E_3~0); 1452833#L1124-1 assume !(1 == ~E_4~0); 1452260#L1129-1 assume !(1 == ~E_5~0); 1452261#L1134-1 assume !(1 == ~E_6~0); 1452597#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1452598#L1144-1 assume !(1 == ~E_8~0); 1452791#L1149-1 assume !(1 == ~E_9~0); 1452425#L1154-1 assume { :end_inline_reset_delta_events } true; 1452426#L1440-2 [2021-12-19 19:16:51,552 INFO L793 eck$LassoCheckResult]: Loop: 1452426#L1440-2 assume !false; 1550742#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1550736#L926 assume !false; 1550733#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1550701#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1550691#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1550690#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1550688#L795 assume !(0 != eval_~tmp~0#1); 1550689#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1555888#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1555881#L951-3 assume !(0 == ~M_E~0); 1555872#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1555871#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1555870#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1555869#L966-3 assume !(0 == ~T4_E~0); 1555868#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1555867#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1555866#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1555865#L986-3 assume !(0 == ~T8_E~0); 1555864#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1555863#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1555862#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1555861#L1006-3 assume !(0 == ~E_2~0); 1555860#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1555859#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1555858#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1555857#L1026-3 assume !(0 == ~E_6~0); 1555856#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1555855#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1555854#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1555853#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1555852#L472-33 assume !(1 == ~m_pc~0); 1555851#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1555850#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1555849#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1555848#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1555847#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1555846#L491-33 assume !(1 == ~t1_pc~0); 1555845#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1555844#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1555843#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1555842#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1555841#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1555840#L510-33 assume !(1 == ~t2_pc~0); 1555839#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1555837#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1555835#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1555833#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1555831#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1555830#L529-33 assume !(1 == ~t3_pc~0); 1520256#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1555829#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1555828#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1555827#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1555826#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1555825#L548-33 assume !(1 == ~t4_pc~0); 1555824#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1555822#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1555821#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1555820#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1555819#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1555818#L567-33 assume !(1 == ~t5_pc~0); 1511526#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1555817#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1555816#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1555815#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1555814#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1555813#L586-33 assume !(1 == ~t6_pc~0); 1555812#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1555810#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1555809#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1555808#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1555807#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1497338#L605-33 assume !(1 == ~t7_pc~0); 1497336#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1497334#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1497332#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1497330#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1497328#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1497326#L624-33 assume !(1 == ~t8_pc~0); 1497324#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1497321#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1497319#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1497317#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1497315#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1497313#L643-33 assume !(1 == ~t9_pc~0); 1497311#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1497309#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1497307#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1497305#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1497303#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1497301#L1059-3 assume !(1 == ~M_E~0); 1497295#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1497293#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1497289#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1497286#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1497283#L1079-3 assume !(1 == ~T5_E~0); 1497280#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1497277#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1497274#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1497271#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1497268#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1497265#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1497262#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1497259#L1119-3 assume !(1 == ~E_3~0); 1497256#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1497253#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1497250#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1497247#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1497244#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1497241#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1497238#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1497228#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1497217#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1497214#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1497210#L1459 assume !(0 == start_simulation_~tmp~3#1); 1497211#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1550811#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1550795#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1550787#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1550778#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1550770#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1550761#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1550754#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1452426#L1440-2 [2021-12-19 19:16:51,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:51,553 INFO L85 PathProgramCache]: Analyzing trace with hash -532012407, now seen corresponding path program 1 times [2021-12-19 19:16:51,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:51,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502192309] [2021-12-19 19:16:51,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:51,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:51,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:51,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:51,581 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:51,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1502192309] [2021-12-19 19:16:51,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1502192309] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:51,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:51,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:51,582 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994498710] [2021-12-19 19:16:51,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:51,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:51,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:51,584 INFO L85 PathProgramCache]: Analyzing trace with hash -1923256308, now seen corresponding path program 2 times [2021-12-19 19:16:51,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:51,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350054871] [2021-12-19 19:16:51,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:51,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:51,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:51,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:51,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:51,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350054871] [2021-12-19 19:16:51,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350054871] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:51,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:51,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:51,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666270309] [2021-12-19 19:16:51,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:51,605 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:51,605 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:51,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:51,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:51,606 INFO L87 Difference]: Start difference. First operand 112596 states and 160622 transitions. cyclomatic complexity: 48030 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:52,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:52,026 INFO L93 Difference]: Finished difference Result 147644 states and 209426 transitions. [2021-12-19 19:16:52,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:52,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147644 states and 209426 transitions. [2021-12-19 19:16:52,650 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 147232 [2021-12-19 19:16:53,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147644 states to 147644 states and 209426 transitions. [2021-12-19 19:16:53,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147644 [2021-12-19 19:16:53,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147644 [2021-12-19 19:16:53,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147644 states and 209426 transitions. [2021-12-19 19:16:53,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:53,454 INFO L681 BuchiCegarLoop]: Abstraction has 147644 states and 209426 transitions. [2021-12-19 19:16:53,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147644 states and 209426 transitions. [2021-12-19 19:16:54,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147644 to 100860. [2021-12-19 19:16:54,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100860 states, 100860 states have (on average 1.4218719016458456) internal successors, (143410), 100859 states have internal predecessors, (143410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:54,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100860 states to 100860 states and 143410 transitions. [2021-12-19 19:16:54,973 INFO L704 BuchiCegarLoop]: Abstraction has 100860 states and 143410 transitions. [2021-12-19 19:16:54,973 INFO L587 BuchiCegarLoop]: Abstraction has 100860 states and 143410 transitions. [2021-12-19 19:16:54,973 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:16:54,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100860 states and 143410 transitions. [2021-12-19 19:16:55,263 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 100544 [2021-12-19 19:16:55,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,268 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,268 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,268 INFO L791 eck$LassoCheckResult]: Stem: 1713412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1713413#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1713801#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1713443#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1713323#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1713033#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1713034#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1713653#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1713716#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1713701#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1713702#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1713157#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1713146#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1713147#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1712954#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1712955#L951 assume !(0 == ~M_E~0); 1712684#L951-2 assume !(0 == ~T1_E~0); 1712685#L956-1 assume !(0 == ~T2_E~0); 1712851#L961-1 assume !(0 == ~T3_E~0); 1713339#L966-1 assume !(0 == ~T4_E~0); 1713340#L971-1 assume !(0 == ~T5_E~0); 1713502#L976-1 assume !(0 == ~T6_E~0); 1713469#L981-1 assume !(0 == ~T7_E~0); 1713200#L986-1 assume !(0 == ~T8_E~0); 1712904#L991-1 assume !(0 == ~T9_E~0); 1712905#L996-1 assume !(0 == ~E_M~0); 1713772#L1001-1 assume !(0 == ~E_1~0); 1713410#L1006-1 assume !(0 == ~E_2~0); 1713411#L1011-1 assume !(0 == ~E_3~0); 1713719#L1016-1 assume !(0 == ~E_4~0); 1713741#L1021-1 assume !(0 == ~E_5~0); 1712491#L1026-1 assume !(0 == ~E_6~0); 1712492#L1031-1 assume !(0 == ~E_7~0); 1713358#L1036-1 assume !(0 == ~E_8~0); 1713354#L1041-1 assume !(0 == ~E_9~0); 1713355#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1713672#L472 assume !(1 == ~m_pc~0); 1713608#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1713388#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1713389#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1713397#L1179 assume !(0 != activate_threads_~tmp~1#1); 1712499#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1712500#L491 assume !(1 == ~t1_pc~0); 1713004#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1713005#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1713348#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1712469#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1712470#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1712495#L510 assume !(1 == ~t2_pc~0); 1712456#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1712457#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1713850#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1713838#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1712737#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1712738#L529 assume !(1 == ~t3_pc~0); 1713203#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1713524#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1713605#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1713756#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1712657#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1712658#L548 assume !(1 == ~t4_pc~0); 1712554#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1712553#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1712861#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1712597#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1712598#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1712547#L567 assume !(1 == ~t5_pc~0); 1712548#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1712596#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1712790#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1712791#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1713647#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1712668#L586 assume !(1 == ~t6_pc~0); 1712669#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1712745#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1713792#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1713845#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1713639#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1713640#L605 assume !(1 == ~t7_pc~0); 1713179#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1713180#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1713343#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1713344#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1713820#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1713316#L624 assume !(1 == ~t8_pc~0); 1712730#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1712729#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1713383#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1713384#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1713611#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1712515#L643 assume !(1 == ~t9_pc~0); 1712516#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1713555#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1713472#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1712911#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1712912#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1712712#L1059 assume !(1 == ~M_E~0); 1712713#L1059-2 assume !(1 == ~T1_E~0); 1712880#L1064-1 assume !(1 == ~T2_E~0); 1712881#L1069-1 assume !(1 == ~T3_E~0); 1713563#L1074-1 assume !(1 == ~T4_E~0); 1713610#L1079-1 assume !(1 == ~T5_E~0); 1713598#L1084-1 assume !(1 == ~T6_E~0); 1713599#L1089-1 assume !(1 == ~T7_E~0); 1713629#L1094-1 assume !(1 == ~T8_E~0); 1713229#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1713230#L1104-1 assume !(1 == ~E_M~0); 1713459#L1109-1 assume !(1 == ~E_1~0); 1713024#L1114-1 assume !(1 == ~E_2~0); 1713025#L1119-1 assume !(1 == ~E_3~0); 1713084#L1124-1 assume !(1 == ~E_4~0); 1712511#L1129-1 assume !(1 == ~E_5~0); 1712512#L1134-1 assume !(1 == ~E_6~0); 1712849#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1712850#L1144-1 assume !(1 == ~E_8~0); 1713042#L1149-1 assume !(1 == ~E_9~0); 1712674#L1154-1 assume { :end_inline_reset_delta_events } true; 1712675#L1440-2 [2021-12-19 19:16:55,269 INFO L793 eck$LassoCheckResult]: Loop: 1712675#L1440-2 assume !false; 1787394#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1787391#L926 assume !false; 1787390#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1787388#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1787379#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1787378#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1787371#L795 assume !(0 != eval_~tmp~0#1); 1787372#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1813163#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1813161#L951-3 assume !(0 == ~M_E~0); 1813159#L951-5 assume !(0 == ~T1_E~0); 1813157#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1813154#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1813152#L966-3 assume !(0 == ~T4_E~0); 1813150#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1813149#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1813146#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1813144#L986-3 assume !(0 == ~T8_E~0); 1813142#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1813140#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1813139#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1813138#L1006-3 assume !(0 == ~E_2~0); 1813137#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1813136#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1813135#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1813134#L1026-3 assume !(0 == ~E_6~0); 1813133#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1813132#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1813131#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1813130#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1713509#L472-33 assume !(1 == ~m_pc~0); 1712619#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1712620#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1712460#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1712461#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1713072#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1713073#L491-33 assume !(1 == ~t1_pc~0); 1712557#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1712558#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1713754#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1713785#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1713786#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1713463#L510-33 assume 1 == ~t2_pc~0; 1713464#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1713520#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1813086#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1813083#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1712449#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1712450#L529-33 assume !(1 == ~t3_pc~0); 1805790#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1805785#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1805778#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1805771#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1805765#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1805759#L548-33 assume !(1 == ~t4_pc~0); 1805673#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1805670#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1805668#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1805666#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1805664#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1805576#L567-33 assume !(1 == ~t5_pc~0); 1805572#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1805565#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1805560#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1805555#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1805550#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1805545#L586-33 assume !(1 == ~t6_pc~0); 1805541#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1805538#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1805535#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1805532#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1805506#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1805504#L605-33 assume !(1 == ~t7_pc~0); 1802764#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1805499#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1805496#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1805493#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1805490#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1805487#L624-33 assume !(1 == ~t8_pc~0); 1805379#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1805376#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1805374#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1805372#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1805370#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1805368#L643-33 assume !(1 == ~t9_pc~0); 1763304#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1805366#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1805364#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1805362#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1805360#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1805358#L1059-3 assume !(1 == ~M_E~0); 1758929#L1059-5 assume !(1 == ~T1_E~0); 1805355#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1805353#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1805351#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1805349#L1079-3 assume !(1 == ~T5_E~0); 1805347#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1805345#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1805343#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1805341#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1805339#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1805334#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1805324#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1805323#L1119-3 assume !(1 == ~E_3~0); 1805322#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1805299#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1805265#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1805160#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1805157#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1805155#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1805153#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1805147#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1805136#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1805065#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1759112#L1459 assume !(0 == start_simulation_~tmp~3#1); 1759113#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1787420#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1787410#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1787408#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1787407#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1787403#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1787401#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1787399#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1712675#L1440-2 [2021-12-19 19:16:55,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2021-12-19 19:16:55,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391416373] [2021-12-19 19:16:55,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391416373] [2021-12-19 19:16:55,312 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391416373] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,312 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429910154] [2021-12-19 19:16:55,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,313 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,313 INFO L85 PathProgramCache]: Analyzing trace with hash -1408411255, now seen corresponding path program 1 times [2021-12-19 19:16:55,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484501341] [2021-12-19 19:16:55,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484501341] [2021-12-19 19:16:55,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1484501341] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,335 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606509525] [2021-12-19 19:16:55,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:55,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:55,336 INFO L87 Difference]: Start difference. First operand 100860 states and 143410 transitions. cyclomatic complexity: 42554 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,751 INFO L93 Difference]: Finished difference Result 159391 states and 226209 transitions. [2021-12-19 19:16:55,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:55,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 159391 states and 226209 transitions. [2021-12-19 19:16:56,851 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 158880 [2021-12-19 19:16:57,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 159391 states to 159391 states and 226209 transitions. [2021-12-19 19:16:57,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159391 [2021-12-19 19:16:57,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159391 [2021-12-19 19:16:57,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 159391 states and 226209 transitions. [2021-12-19 19:16:57,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,272 INFO L681 BuchiCegarLoop]: Abstraction has 159391 states and 226209 transitions. [2021-12-19 19:16:57,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159391 states and 226209 transitions. [2021-12-19 19:16:58,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159391 to 112596. [2021-12-19 19:16:58,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112596 states, 112596 states have (on average 1.423105616540552) internal successors, (160236), 112595 states have internal predecessors, (160236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112596 states to 112596 states and 160236 transitions. [2021-12-19 19:16:58,858 INFO L704 BuchiCegarLoop]: Abstraction has 112596 states and 160236 transitions. [2021-12-19 19:16:58,858 INFO L587 BuchiCegarLoop]: Abstraction has 112596 states and 160236 transitions. [2021-12-19 19:16:58,858 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:16:58,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112596 states and 160236 transitions. [2021-12-19 19:16:59,232 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 112192 [2021-12-19 19:16:59,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,238 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,238 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,239 INFO L791 eck$LassoCheckResult]: Stem: 1973678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1973679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1974101#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1973706#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1973586#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1973295#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1973296#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1973941#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1974015#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1973999#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1974000#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1973417#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1973405#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1973406#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1973217#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1973218#L951 assume !(0 == ~M_E~0); 1972949#L951-2 assume !(0 == ~T1_E~0); 1972950#L956-1 assume !(0 == ~T2_E~0); 1973112#L961-1 assume !(0 == ~T3_E~0); 1973601#L966-1 assume !(0 == ~T4_E~0); 1973602#L971-1 assume !(0 == ~T5_E~0); 1973768#L976-1 assume !(0 == ~T6_E~0); 1973735#L981-1 assume !(0 == ~T7_E~0); 1973459#L986-1 assume !(0 == ~T8_E~0); 1973166#L991-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1973167#L996-1 assume !(0 == ~E_M~0); 1974070#L1001-1 assume !(0 == ~E_1~0); 1974071#L1006-1 assume !(0 == ~E_2~0); 1974019#L1011-1 assume !(0 == ~E_3~0); 1974020#L1016-1 assume !(0 == ~E_4~0); 1974125#L1021-1 assume !(0 == ~E_5~0); 1974126#L1026-1 assume !(0 == ~E_6~0); 1974165#L1031-1 assume !(0 == ~E_7~0); 1974166#L1036-1 assume !(0 == ~E_8~0); 1973613#L1041-1 assume !(0 == ~E_9~0); 1973614#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1974122#L472 assume !(1 == ~m_pc~0); 1974123#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1973651#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1973652#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1974099#L1179 assume !(0 != activate_threads_~tmp~1#1); 1972760#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1972761#L491 assume !(1 == ~t1_pc~0); 1973268#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1973269#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1974204#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1972730#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1972731#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1973936#L510 assume !(1 == ~t2_pc~0); 1972717#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1972718#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1974192#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1974193#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1973001#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1973002#L529 assume !(1 == ~t3_pc~0); 1973793#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1973794#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1974202#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1974114#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1974115#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1974143#L548 assume !(1 == ~t4_pc~0); 1974144#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1973122#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1973123#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1972861#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1972862#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1972810#L567 assume !(1 == ~t5_pc~0); 1972811#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1974132#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1974133#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1974201#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1973933#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1973934#L586 assume !(1 == ~t6_pc~0); 1973009#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1973010#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1974091#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1974181#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1974182#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1974141#L605 assume !(1 == ~t7_pc~0); 1974142#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1973654#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1973605#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1973606#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1974124#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1973579#L624 assume !(1 == ~t8_pc~0); 1973580#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1973717#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1973718#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1973900#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1973901#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1972777#L643 assume !(1 == ~t9_pc~0); 1972778#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1974088#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1973738#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1973739#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1974140#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1972977#L1059 assume !(1 == ~M_E~0); 1972978#L1059-2 assume !(1 == ~T1_E~0); 1973142#L1064-1 assume !(1 == ~T2_E~0); 1973143#L1069-1 assume !(1 == ~T3_E~0); 1974118#L1074-1 assume !(1 == ~T4_E~0); 1974119#L1079-1 assume !(1 == ~T5_E~0); 1973877#L1084-1 assume !(1 == ~T6_E~0); 1973878#L1089-1 assume !(1 == ~T7_E~0); 1973915#L1094-1 assume !(1 == ~T8_E~0); 1973916#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1973493#L1104-1 assume !(1 == ~E_M~0); 1973724#L1109-1 assume !(1 == ~E_1~0); 1973286#L1114-1 assume !(1 == ~E_2~0); 1973287#L1119-1 assume !(1 == ~E_3~0); 1973345#L1124-1 assume !(1 == ~E_4~0); 1972773#L1129-1 assume !(1 == ~E_5~0); 1972774#L1134-1 assume !(1 == ~E_6~0); 1973110#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1973111#L1144-1 assume !(1 == ~E_8~0); 1973303#L1149-1 assume !(1 == ~E_9~0); 1972939#L1154-1 assume { :end_inline_reset_delta_events } true; 1972940#L1440-2 [2021-12-19 19:16:59,239 INFO L793 eck$LassoCheckResult]: Loop: 1972940#L1440-2 assume !false; 2072292#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2072288#L926 assume !false; 2072287#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2072285#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2072276#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2072275#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2072273#L795 assume !(0 != eval_~tmp~0#1); 2072271#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2072269#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2072267#L951-3 assume !(0 == ~M_E~0); 2072265#L951-5 assume !(0 == ~T1_E~0); 2072263#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2072261#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2072259#L966-3 assume !(0 == ~T4_E~0); 2072256#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2072254#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2072252#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2072250#L986-3 assume !(0 == ~T8_E~0); 2072247#L991-3 assume !(0 == ~T9_E~0); 2072248#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2084752#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2084751#L1006-3 assume !(0 == ~E_2~0); 2084750#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2084749#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2084748#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2084747#L1026-3 assume !(0 == ~E_6~0); 2084746#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2084745#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2084744#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2084743#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2084742#L472-33 assume !(1 == ~m_pc~0); 2084741#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2084740#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084739#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2084738#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2084737#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2084736#L491-33 assume !(1 == ~t1_pc~0); 2084735#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2084734#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2084733#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2084732#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2084731#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2084730#L510-33 assume !(1 == ~t2_pc~0); 2084729#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2078273#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2078274#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2078263#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 2077478#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2073503#L529-33 assume !(1 == ~t3_pc~0); 2073500#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2073497#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2073494#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2073490#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2073486#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2073483#L548-33 assume !(1 == ~t4_pc~0); 2073480#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2073476#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2073473#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2073470#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2073436#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2073426#L567-33 assume !(1 == ~t5_pc~0); 2044106#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2073422#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2073420#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2073418#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2073416#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2073414#L586-33 assume !(1 == ~t6_pc~0); 2073411#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2073408#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2073406#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2073404#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2073402#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2073400#L605-33 assume !(1 == ~t7_pc~0); 2049965#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2073397#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2073352#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2073349#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2073347#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2073345#L624-33 assume !(1 == ~t8_pc~0); 2073337#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2073334#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2073323#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2073308#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2073305#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2073303#L643-33 assume !(1 == ~t9_pc~0); 2064510#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2073300#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2073298#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2073296#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2073293#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2073291#L1059-3 assume !(1 == ~M_E~0); 2010144#L1059-5 assume !(1 == ~T1_E~0); 2073288#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2073286#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2073284#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2073283#L1079-3 assume !(1 == ~T5_E~0); 2073280#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2073278#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2054161#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2031800#L1099-3 assume !(1 == ~T9_E~0); 2031796#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2031794#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2031792#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2031790#L1119-3 assume !(1 == ~E_3~0); 2031788#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2031786#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2031784#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2031782#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2031780#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2031778#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2031776#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2029711#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2029702#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2029701#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1972736#L1459 assume !(0 == start_simulation_~tmp~3#1); 1972738#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2072318#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2072308#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2072306#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2072305#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2072301#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2072299#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2072297#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1972940#L1440-2 [2021-12-19 19:16:59,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,240 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2021-12-19 19:16:59,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351995060] [2021-12-19 19:16:59,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,265 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351995060] [2021-12-19 19:16:59,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351995060] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,266 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356426899] [2021-12-19 19:16:59,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,266 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,266 INFO L85 PathProgramCache]: Analyzing trace with hash 63076236, now seen corresponding path program 1 times [2021-12-19 19:16:59,267 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144418] [2021-12-19 19:16:59,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,267 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144418] [2021-12-19 19:16:59,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144418] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,287 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327655343] [2021-12-19 19:16:59,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,288 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,288 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:59,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:59,288 INFO L87 Difference]: Start difference. First operand 112596 states and 160236 transitions. cyclomatic complexity: 47644 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,704 INFO L93 Difference]: Finished difference Result 147644 states and 208912 transitions. [2021-12-19 19:16:59,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:59,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147644 states and 208912 transitions. [2021-12-19 19:17:00,787 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 147232 [2021-12-19 19:17:01,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147644 states to 147644 states and 208912 transitions. [2021-12-19 19:17:01,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147644 [2021-12-19 19:17:01,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147644 [2021-12-19 19:17:01,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147644 states and 208912 transitions. [2021-12-19 19:17:01,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,158 INFO L681 BuchiCegarLoop]: Abstraction has 147644 states and 208912 transitions. [2021-12-19 19:17:01,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147644 states and 208912 transitions. [2021-12-19 19:17:02,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147644 to 100860. [2021-12-19 19:17:02,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100860 states, 100860 states have (on average 1.4180448145944875) internal successors, (143024), 100859 states have internal predecessors, (143024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100860 states to 100860 states and 143024 transitions. [2021-12-19 19:17:02,611 INFO L704 BuchiCegarLoop]: Abstraction has 100860 states and 143024 transitions. [2021-12-19 19:17:02,611 INFO L587 BuchiCegarLoop]: Abstraction has 100860 states and 143024 transitions. [2021-12-19 19:17:02,611 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:02,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100860 states and 143024 transitions. [2021-12-19 19:17:02,924 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 100544 [2021-12-19 19:17:02,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,928 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,929 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,929 INFO L791 eck$LassoCheckResult]: Stem: 2233915#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2233916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2234298#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2233941#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2233827#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2233540#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2233541#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2234155#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2234221#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2234208#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2234209#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2233659#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2233648#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2233649#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2233459#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2233460#L951 assume !(0 == ~M_E~0); 2233193#L951-2 assume !(0 == ~T1_E~0); 2233194#L956-1 assume !(0 == ~T2_E~0); 2233355#L961-1 assume !(0 == ~T3_E~0); 2233844#L966-1 assume !(0 == ~T4_E~0); 2233845#L971-1 assume !(0 == ~T5_E~0); 2233997#L976-1 assume !(0 == ~T6_E~0); 2233967#L981-1 assume !(0 == ~T7_E~0); 2233702#L986-1 assume !(0 == ~T8_E~0); 2233409#L991-1 assume !(0 == ~T9_E~0); 2233410#L996-1 assume !(0 == ~E_M~0); 2234274#L1001-1 assume !(0 == ~E_1~0); 2233913#L1006-1 assume !(0 == ~E_2~0); 2233914#L1011-1 assume !(0 == ~E_3~0); 2234224#L1016-1 assume !(0 == ~E_4~0); 2234244#L1021-1 assume !(0 == ~E_5~0); 2233001#L1026-1 assume !(0 == ~E_6~0); 2233002#L1031-1 assume !(0 == ~E_7~0); 2233861#L1036-1 assume !(0 == ~E_8~0); 2233857#L1041-1 assume !(0 == ~E_9~0); 2233858#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2234169#L472 assume !(1 == ~m_pc~0); 2234113#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2233892#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2233893#L484 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2233902#L1179 assume !(0 != activate_threads_~tmp~1#1); 2233009#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2233010#L491 assume !(1 == ~t1_pc~0); 2233510#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2233511#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2233853#L503 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232980#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2232981#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2233005#L510 assume !(1 == ~t2_pc~0); 2232967#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2232968#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2234358#L522 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2234348#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2233245#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2233246#L529 assume !(1 == ~t3_pc~0); 2233706#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2234023#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2234108#L541 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2234259#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2233166#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2233167#L548 assume !(1 == ~t4_pc~0); 2233064#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2233063#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2233365#L560 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2233107#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2233108#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2233057#L567 assume !(1 == ~t5_pc~0); 2233058#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2233106#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2233296#L579 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2233297#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2234149#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2233177#L586 assume !(1 == ~t6_pc~0); 2233178#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2233253#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2234289#L598 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2234355#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2234140#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2234141#L605 assume !(1 == ~t7_pc~0); 2233680#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2233681#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2233848#L617 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2233849#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2234325#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2233821#L624 assume !(1 == ~t8_pc~0); 2233238#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2233237#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2233887#L636 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2233888#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2234117#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2233025#L643 assume !(1 == ~t9_pc~0); 2233026#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2234055#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2233971#L655 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2233416#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2233417#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2233221#L1059 assume !(1 == ~M_E~0); 2233222#L1059-2 assume !(1 == ~T1_E~0); 2233385#L1064-1 assume !(1 == ~T2_E~0); 2233386#L1069-1 assume !(1 == ~T3_E~0); 2234063#L1074-1 assume !(1 == ~T4_E~0); 2234115#L1079-1 assume !(1 == ~T5_E~0); 2234100#L1084-1 assume !(1 == ~T6_E~0); 2234101#L1089-1 assume !(1 == ~T7_E~0); 2234132#L1094-1 assume !(1 == ~T8_E~0); 2233735#L1099-1 assume !(1 == ~T9_E~0); 2233736#L1104-1 assume !(1 == ~E_M~0); 2233957#L1109-1 assume !(1 == ~E_1~0); 2233530#L1114-1 assume !(1 == ~E_2~0); 2233531#L1119-1 assume !(1 == ~E_3~0); 2233589#L1124-1 assume !(1 == ~E_4~0); 2233021#L1129-1 assume !(1 == ~E_5~0); 2233022#L1134-1 assume !(1 == ~E_6~0); 2233353#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2233354#L1144-1 assume !(1 == ~E_8~0); 2233548#L1149-1 assume !(1 == ~E_9~0); 2233183#L1154-1 assume { :end_inline_reset_delta_events } true; 2233184#L1440-2 [2021-12-19 19:17:02,929 INFO L793 eck$LassoCheckResult]: Loop: 2233184#L1440-2 assume !false; 2315910#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2315144#L926 assume !false; 2315389#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2315354#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2315341#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2315335#L781 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2315328#L795 assume !(0 != eval_~tmp~0#1); 2315329#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2333642#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2333641#L951-3 assume !(0 == ~M_E~0); 2333640#L951-5 assume !(0 == ~T1_E~0); 2333639#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2333638#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2333637#L966-3 assume !(0 == ~T4_E~0); 2333636#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2333635#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2333634#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2333633#L986-3 assume !(0 == ~T8_E~0); 2333632#L991-3 assume !(0 == ~T9_E~0); 2333631#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2333630#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2333629#L1006-3 assume !(0 == ~E_2~0); 2333628#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2333627#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2333626#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2333625#L1026-3 assume !(0 == ~E_6~0); 2333624#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2333623#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2333622#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2333621#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2333620#L472-33 assume !(1 == ~m_pc~0); 2333619#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2333618#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2333617#L484-11 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2333616#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2333615#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2333614#L491-33 assume !(1 == ~t1_pc~0); 2333613#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2333612#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2333611#L503-11 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2333610#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2333609#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2331106#L510-33 assume 1 == ~t2_pc~0; 2331105#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2331103#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2331101#L522-11 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2331098#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2331097#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2302329#L529-33 assume !(1 == ~t3_pc~0); 2302327#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2302325#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2302323#L541-11 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2302321#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2302319#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2302317#L548-33 assume !(1 == ~t4_pc~0); 2302315#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2302312#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2302310#L560-11 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2302308#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2302305#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2302303#L567-33 assume !(1 == ~t5_pc~0); 2296506#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2302300#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2302298#L579-11 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2302296#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2302294#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2302292#L586-33 assume !(1 == ~t6_pc~0); 2302290#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2302287#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2302285#L598-11 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2302283#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2302280#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2302277#L605-33 assume !(1 == ~t7_pc~0); 2299924#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2302272#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2302270#L617-11 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2302268#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2302267#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2302265#L624-33 assume !(1 == ~t8_pc~0); 2302263#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2302260#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2302258#L636-11 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2302256#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2302253#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2302251#L643-33 assume !(1 == ~t9_pc~0); 2300370#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2302248#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2302246#L655-11 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2302244#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2302241#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2302239#L1059-3 assume !(1 == ~M_E~0); 2281524#L1059-5 assume !(1 == ~T1_E~0); 2302236#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2302234#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2302232#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2302229#L1079-3 assume !(1 == ~T5_E~0); 2302227#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2302225#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2302223#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2302221#L1099-3 assume !(1 == ~T9_E~0); 2302219#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2302218#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2302216#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2302214#L1119-3 assume !(1 == ~E_3~0); 2302212#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2302210#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2302208#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2302205#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2302203#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2302201#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2302199#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2302196#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2302186#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2302185#L781-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2232986#L1459 assume !(0 == start_simulation_~tmp~3#1); 2232988#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2315941#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2315931#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2315929#L781-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2315927#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2315925#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2315923#L1422 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2315921#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2233184#L1440-2 [2021-12-19 19:17:02,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2021-12-19 19:17:02,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019205006] [2021-12-19 19:17:02,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019205006] [2021-12-19 19:17:02,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019205006] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,950 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385183049] [2021-12-19 19:17:02,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,951 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1423983287, now seen corresponding path program 1 times [2021-12-19 19:17:02,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061794023] [2021-12-19 19:17:02,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,952 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061794023] [2021-12-19 19:17:02,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061794023] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,970 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647124332] [2021-12-19 19:17:02,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,970 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,970 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:02,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:02,971 INFO L87 Difference]: Start difference. First operand 100860 states and 143024 transitions. cyclomatic complexity: 42168 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:03,437 INFO L93 Difference]: Finished difference Result 155959 states and 220351 transitions. [2021-12-19 19:17:03,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:03,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155959 states and 220351 transitions.