./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:16:50,458 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:16:50,461 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:16:50,513 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:16:50,514 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:16:50,516 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:16:50,518 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:16:50,520 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:16:50,522 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:16:50,526 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:16:50,527 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:16:50,528 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:16:50,529 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:16:50,531 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:16:50,533 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:16:50,536 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:16:50,537 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:16:50,537 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:16:50,538 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:16:50,540 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:16:50,541 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:16:50,542 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:16:50,543 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:16:50,543 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:16:50,545 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:16:50,545 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:16:50,546 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:16:50,546 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:16:50,547 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:16:50,547 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:16:50,547 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:16:50,548 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:16:50,549 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:16:50,549 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:16:50,550 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:16:50,550 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:16:50,550 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:16:50,551 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:16:50,551 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:16:50,551 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:16:50,552 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:16:50,553 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:16:50,571 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:16:50,574 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:16:50,574 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:16:50,576 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:16:50,576 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:16:50,577 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:16:50,577 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:16:50,578 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:16:50,578 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:16:50,578 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:16:50,578 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:16:50,578 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:16:50,579 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:16:50,580 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:16:50,580 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:16:50,580 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:16:50,580 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:16:50,580 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:16:50,581 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:16:50,581 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:16:50,581 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:16:50,581 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:16:50,582 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:16:50,582 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2021-12-19 19:16:50,842 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:16:50,867 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:16:50,869 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:16:50,870 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:16:50,871 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:16:50,872 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2021-12-19 19:16:50,940 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4c94855f7/ec236e486bfe44aaa438d79622c76076/FLAG0650f76cf [2021-12-19 19:16:51,384 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:16:51,385 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2021-12-19 19:16:51,397 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4c94855f7/ec236e486bfe44aaa438d79622c76076/FLAG0650f76cf [2021-12-19 19:16:51,759 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4c94855f7/ec236e486bfe44aaa438d79622c76076 [2021-12-19 19:16:51,761 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:16:51,762 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:16:51,765 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:51,765 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:16:51,770 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:16:51,770 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:51" (1/1) ... [2021-12-19 19:16:51,771 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1421c3d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:51, skipping insertion in model container [2021-12-19 19:16:51,771 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:51" (1/1) ... [2021-12-19 19:16:51,777 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:16:51,815 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:16:51,974 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2021-12-19 19:16:52,083 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:52,092 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:16:52,101 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2021-12-19 19:16:52,157 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:52,175 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:16:52,176 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52 WrapperNode [2021-12-19 19:16:52,176 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:52,177 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:52,177 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:16:52,178 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:16:52,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,205 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,309 INFO L137 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 302, statements flattened = 4653 [2021-12-19 19:16:52,310 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:52,310 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:16:52,311 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:16:52,311 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:16:52,318 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,318 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,332 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,333 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,381 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,419 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,429 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,446 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:16:52,467 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:16:52,467 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:16:52,468 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:16:52,476 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,484 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:52,493 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:52,509 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:52,524 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:16:52,574 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:16:52,574 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:16:52,575 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:16:52,575 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:16:52,710 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:16:52,719 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:16:54,559 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:16:54,576 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:16:54,576 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-19 19:16:54,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:54 BoogieIcfgContainer [2021-12-19 19:16:54,580 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:16:54,581 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:16:54,581 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:16:54,584 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:16:54,585 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,585 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:16:51" (1/3) ... [2021-12-19 19:16:54,586 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e63756d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:54, skipping insertion in model container [2021-12-19 19:16:54,586 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,586 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (2/3) ... [2021-12-19 19:16:54,586 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e63756d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:54, skipping insertion in model container [2021-12-19 19:16:54,586 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,586 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:54" (3/3) ... [2021-12-19 19:16:54,587 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2021-12-19 19:16:54,633 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:16:54,633 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:16:54,633 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:16:54,633 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:16:54,634 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:16:54,634 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:16:54,634 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:16:54,634 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:16:54,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:54,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2021-12-19 19:16:54,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:54,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:54,785 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,788 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:16:54,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:54,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2021-12-19 19:16:54,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:54,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:54,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,847 INFO L791 eck$LassoCheckResult]: Stem: 473#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1943#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1566#L1891true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 827#L895true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1866#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 461#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 504#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1550#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 822#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 985#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 483#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 375#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1475#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 658#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1539#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 574#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 902#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 357#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1961#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1551#L1279-2true assume !(0 == ~T1_E~0); 160#L1284-1true assume !(0 == ~T2_E~0); 1773#L1289-1true assume !(0 == ~T3_E~0); 571#L1294-1true assume !(0 == ~T4_E~0); 578#L1299-1true assume !(0 == ~T5_E~0); 1857#L1304-1true assume !(0 == ~T6_E~0); 1902#L1309-1true assume !(0 == ~T7_E~0); 1875#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 124#L1319-1true assume !(0 == ~T9_E~0); 1109#L1324-1true assume !(0 == ~T10_E~0); 214#L1329-1true assume !(0 == ~T11_E~0); 1365#L1334-1true assume !(0 == ~T12_E~0); 1804#L1339-1true assume !(0 == ~T13_E~0); 1527#L1344-1true assume !(0 == ~E_M~0); 1959#L1349-1true assume !(0 == ~E_1~0); 708#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1114#L1359-1true assume !(0 == ~E_3~0); 1778#L1364-1true assume !(0 == ~E_4~0); 282#L1369-1true assume !(0 == ~E_5~0); 1090#L1374-1true assume !(0 == ~E_6~0); 712#L1379-1true assume !(0 == ~E_7~0); 771#L1384-1true assume !(0 == ~E_8~0); 2001#L1389-1true assume !(0 == ~E_9~0); 1402#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1873#L1399-1true assume !(0 == ~E_11~0); 1642#L1404-1true assume !(0 == ~E_12~0); 329#L1409-1true assume !(0 == ~E_13~0); 1616#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1955#L628true assume !(1 == ~m_pc~0); 1413#L628-2true is_master_triggered_~__retres1~0#1 := 0; 935#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 770#L640true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1660#L1591true assume !(0 != activate_threads_~tmp~1#1); 1890#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606#L647true assume 1 == ~t1_pc~0; 239#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 647#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 383#L659true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1639#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1503#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1913#L666true assume 1 == ~t2_pc~0; 159#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1620#L678true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1532#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 864#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1858#L685true assume !(1 == ~t3_pc~0); 1026#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1686#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 650#L697true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 747#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1065#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402#L704true assume 1 == ~t4_pc~0; 1246#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 758#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1578#L716true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1774#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 645#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743#L723true assume !(1 == ~t5_pc~0); 947#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1108#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1533#L735true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 849#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 868#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273#L742true assume 1 == ~t6_pc~0; 959#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 349#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 897#L754true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 109#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1357#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313#L761true assume !(1 == ~t7_pc~0); 318#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 244#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1948#L773true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 749#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1560#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121#L780true assume 1 == ~t8_pc~0; 579#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 266#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 907#L792true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 719#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 811#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1395#L799true assume 1 == ~t9_pc~0; 911#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 820#L811true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1001#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1920#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 836#L818true assume !(1 == ~t10_pc~0); 24#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 904#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1744#L830true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 840#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1096#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 873#L837true assume 1 == ~t11_pc~0; 1797#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1577#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1136#L849true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 806#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1861#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 613#L856true assume !(1 == ~t12_pc~0); 1443#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1253#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1795#L868true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1221#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1788#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1557#L875true assume 1 == ~t13_pc~0; 577#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 351#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1635#L887true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 321#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 901#L1695-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1898#L1427true assume !(1 == ~M_E~0); 884#L1427-2true assume !(1 == ~T1_E~0); 306#L1432-1true assume !(1 == ~T2_E~0); 1561#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1124#L1442-1true assume !(1 == ~T4_E~0); 1485#L1447-1true assume !(1 == ~T5_E~0); 955#L1452-1true assume !(1 == ~T6_E~0); 84#L1457-1true assume !(1 == ~T7_E~0); 1160#L1462-1true assume !(1 == ~T8_E~0); 1844#L1467-1true assume !(1 == ~T9_E~0); 1185#L1472-1true assume !(1 == ~T10_E~0); 1371#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 900#L1482-1true assume !(1 == ~T12_E~0); 1299#L1487-1true assume !(1 == ~T13_E~0); 252#L1492-1true assume !(1 == ~E_M~0); 656#L1497-1true assume !(1 == ~E_1~0); 449#L1502-1true assume !(1 == ~E_2~0); 1297#L1507-1true assume !(1 == ~E_3~0); 189#L1512-1true assume !(1 == ~E_4~0); 1279#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1390#L1522-1true assume !(1 == ~E_6~0); 604#L1527-1true assume !(1 == ~E_7~0); 1755#L1532-1true assume !(1 == ~E_8~0); 2014#L1537-1true assume !(1 == ~E_9~0); 762#L1542-1true assume !(1 == ~E_10~0); 630#L1547-1true assume !(1 == ~E_11~0); 1782#L1552-1true assume !(1 == ~E_12~0); 42#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 344#L1562-1true assume { :end_inline_reset_delta_events } true; 742#L1928-2true [2021-12-19 19:16:54,851 INFO L793 eck$LassoCheckResult]: Loop: 742#L1928-2true assume !false; 653#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 489#L1254true assume false; 442#L1269true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 212#L895-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1605#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 463#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 451#L1284-3true assume !(0 == ~T2_E~0); 1669#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 441#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1894#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 706#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1145#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 381#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1971#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1210#L1324-3true assume !(0 == ~T10_E~0); 187#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1823#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 636#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 928#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 870#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 369#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 881#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1856#L1364-3true assume !(0 == ~E_4~0); 1743#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1437#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 254#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1304#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 368#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 544#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1946#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1465#L1404-3true assume !(0 == ~E_12~0); 1389#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1549#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 782#L628-45true assume 1 == ~m_pc~0; 543#L629-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1737#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#L640-15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 389#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1671#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 910#L647-45true assume !(1 == ~t1_pc~0); 1396#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 718#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 966#L659-15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 217#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1548#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327#L666-45true assume 1 == ~t2_pc~0; 1919#L667-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1692#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1144#L678-15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1016#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1011#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92#L685-45true assume !(1 == ~t3_pc~0); 1416#L685-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1531#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1582#L697-15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1274#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1553#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1638#L704-45true assume 1 == ~t4_pc~0; 1311#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 481#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 721#L716-15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2017#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1980#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 808#L723-45true assume !(1 == ~t5_pc~0); 1404#L723-47true is_transmit5_triggered_~__retres1~5#1 := 0; 1703#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510#L735-15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 376#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1929#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1236#L742-45true assume !(1 == ~t6_pc~0); 526#L742-47true is_transmit6_triggered_~__retres1~6#1 := 0; 879#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1088#L754-15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 915#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1278#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 990#L761-45true assume !(1 == ~t7_pc~0); 1167#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 521#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1042#L773-15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 191#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1954#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1393#L780-45true assume !(1 == ~t8_pc~0); 1179#L780-47true is_transmit8_triggered_~__retres1~8#1 := 0; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1956#L792-15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1754#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 179#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 634#L799-45true assume !(1 == ~t9_pc~0); 297#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2007#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1502#L811-15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 956#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1817#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 149#L818-45true assume 1 == ~t10_pc~0; 1058#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 934#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1829#L830-15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 480#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1048#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1523#L837-45true assume 1 == ~t11_pc~0; 1764#L838-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 522#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1070#L849-15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1848#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 221#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2026#L856-45true assume 1 == ~t12_pc~0; 1545#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1273#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 192#L868-15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1800#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 717#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1281#L875-45true assume !(1 == ~t13_pc~0); 701#L875-47true is_transmit13_triggered_~__retres1~13#1 := 0; 741#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1851#L887-15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1484#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1766#L1695-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363#L1427-3true assume !(1 == ~M_E~0); 567#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1562#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 997#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 707#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1017#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 50#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1979#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259#L1462-3true assume !(1 == ~T8_E~0); 1681#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1068#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1709#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 170#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 243#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1809#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 332#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1020#L1502-3true assume !(1 == ~E_2~0); 1208#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1918#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 353#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1682#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 174#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 882#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1574#L1542-3true assume !(1 == ~E_10~0); 1004#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 697#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1398#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 286#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1970#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1414#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 384#L1053-1true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 799#L1947true assume !(0 == start_simulation_~tmp~3#1); 978#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1129#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1628#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1645#L1053-2true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1451#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1173#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 894#L1910true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1715#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 742#L1928-2true [2021-12-19 19:16:54,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:54,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2021-12-19 19:16:54,868 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:54,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298302719] [2021-12-19 19:16:54,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:54,870 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:54,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,083 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,083 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298302719] [2021-12-19 19:16:55,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298302719] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,084 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,086 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676721626] [2021-12-19 19:16:55,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,091 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1066176643, now seen corresponding path program 1 times [2021-12-19 19:16:55,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24626694] [2021-12-19 19:16:55,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24626694] [2021-12-19 19:16:55,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24626694] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:55,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584315681] [2021-12-19 19:16:55,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,192 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,193 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-19 19:16:55,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-19 19:16:55,237 INFO L87 Difference]: Start difference. First operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,369 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2021-12-19 19:16:55,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-19 19:16:55,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2021-12-19 19:16:55,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:55,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2018 states and 2987 transitions. [2021-12-19 19:16:55,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:55,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:55,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2987 transitions. [2021-12-19 19:16:55,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:55,423 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2021-12-19 19:16:55,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2987 transitions. [2021-12-19 19:16:55,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:55,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2987 transitions. [2021-12-19 19:16:55,510 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2021-12-19 19:16:55,510 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2021-12-19 19:16:55,511 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:16:55,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2987 transitions. [2021-12-19 19:16:55,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:55,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,527 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,529 INFO L791 eck$LassoCheckResult]: Stem: 4971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 6008#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5463#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5464#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4953#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4954#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5020#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5021#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5459#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5460#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4986#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4805#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4806#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5250#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5251#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5126#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5127#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4776#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4777#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6000#L1279-2 assume !(0 == ~T1_E~0); 4399#L1284-1 assume !(0 == ~T2_E~0); 4400#L1289-1 assume !(0 == ~T3_E~0); 5123#L1294-1 assume !(0 == ~T4_E~0); 5124#L1299-1 assume !(0 == ~T5_E~0); 5135#L1304-1 assume !(0 == ~T6_E~0); 6066#L1309-1 assume !(0 == ~T7_E~0); 6067#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4329#L1319-1 assume !(0 == ~T9_E~0); 4330#L1324-1 assume !(0 == ~T10_E~0); 4502#L1329-1 assume !(0 == ~T11_E~0); 4503#L1334-1 assume !(0 == ~T12_E~0); 5907#L1339-1 assume !(0 == ~T13_E~0); 5988#L1344-1 assume !(0 == ~E_M~0); 5989#L1349-1 assume !(0 == ~E_1~0); 5310#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5311#L1359-1 assume !(0 == ~E_3~0); 5740#L1364-1 assume !(0 == ~E_4~0); 4631#L1369-1 assume !(0 == ~E_5~0); 4632#L1374-1 assume !(0 == ~E_6~0); 5315#L1379-1 assume !(0 == ~E_7~0); 5316#L1384-1 assume !(0 == ~E_8~0); 5393#L1389-1 assume !(0 == ~E_9~0); 5926#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5927#L1399-1 assume !(0 == ~E_11~0); 6030#L1404-1 assume !(0 == ~E_12~0); 4724#L1409-1 assume !(0 == ~E_13~0); 4725#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6022#L628 assume !(1 == ~m_pc~0); 4628#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4627#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5391#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5392#L1591 assume !(0 != activate_threads_~tmp~1#1); 6035#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5179#L647 assume 1 == ~t1_pc~0; 4548#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4549#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4820#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4821#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 5975#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5976#L666 assume 1 == ~t2_pc~0; 4396#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4397#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4563#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5992#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5511#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5512#L685 assume !(1 == ~t3_pc~0); 5617#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5616#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5239#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5240#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4847#L704 assume 1 == ~t4_pc~0; 4848#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5372#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5373#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6013#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5232#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5233#L723 assume !(1 == ~t5_pc~0); 5355#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5591#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5735#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5490#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5491#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4613#L742 assume 1 == ~t6_pc~0; 4614#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4762#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4763#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4298#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4299#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4690#L761 assume !(1 == ~t7_pc~0); 4691#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4559#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4560#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5362#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5363#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4323#L780 assume 1 == ~t8_pc~0; 4324#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4599#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4600#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5323#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5324#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5443#L799 assume 1 == ~t9_pc~0; 5555#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4326#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4327#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5455#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5662#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5473#L818 assume !(1 == ~t10_pc~0); 4107#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4108#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5548#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5477#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5478#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5518#L837 assume 1 == ~t11_pc~0; 5519#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5353#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5756#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5436#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5437#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5188#L856 assume !(1 == ~t12_pc~0); 5189#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5842#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5843#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5823#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5824#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6003#L875 assume 1 == ~t13_pc~0; 5133#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4765#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4766#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4705#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4706#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5545#L1427 assume !(1 == ~M_E~0); 5529#L1427-2 assume !(1 == ~T1_E~0); 4677#L1432-1 assume !(1 == ~T2_E~0); 4678#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5746#L1442-1 assume !(1 == ~T4_E~0); 5747#L1447-1 assume !(1 == ~T5_E~0); 5602#L1452-1 assume !(1 == ~T6_E~0); 4242#L1457-1 assume !(1 == ~T7_E~0); 4243#L1462-1 assume !(1 == ~T8_E~0); 5773#L1467-1 assume !(1 == ~T9_E~0); 5791#L1472-1 assume !(1 == ~T10_E~0); 5792#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5543#L1482-1 assume !(1 == ~T12_E~0); 5544#L1487-1 assume !(1 == ~T13_E~0); 4573#L1492-1 assume !(1 == ~E_M~0); 4574#L1497-1 assume !(1 == ~E_1~0); 4935#L1502-1 assume !(1 == ~E_2~0); 4936#L1507-1 assume !(1 == ~E_3~0); 4451#L1512-1 assume !(1 == ~E_4~0); 4452#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5862#L1522-1 assume !(1 == ~E_6~0); 5176#L1527-1 assume !(1 == ~E_7~0); 5177#L1532-1 assume !(1 == ~E_8~0); 6050#L1537-1 assume !(1 == ~E_9~0); 5379#L1542-1 assume !(1 == ~E_10~0); 5210#L1547-1 assume !(1 == ~E_11~0); 5211#L1552-1 assume !(1 == ~E_12~0); 4146#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4147#L1562-1 assume { :end_inline_reset_delta_events } true; 4753#L1928-2 [2021-12-19 19:16:55,529 INFO L793 eck$LassoCheckResult]: Loop: 4753#L1928-2 assume !false; 5244#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4407#L1254 assume !false; 4994#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4481#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4482#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4679#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5850#L1067 assume !(0 != eval_~tmp~0#1); 4920#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4497#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4498#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4957#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4939#L1284-3 assume !(0 == ~T2_E~0); 4940#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4918#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4919#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5306#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5307#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4816#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4817#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5813#L1324-3 assume !(0 == ~T10_E~0); 4448#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4449#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5216#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5217#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5515#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4797#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4798#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5526#L1364-3 assume !(0 == ~E_4~0); 6048#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5944#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4577#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4578#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4795#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4796#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5086#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5954#L1404-3 assume !(0 == ~E_12~0); 5918#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5919#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5405#L628-45 assume 1 == ~m_pc~0; 5083#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5085#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4442#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4443#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4831#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5554#L647-45 assume 1 == ~t1_pc~0; 4393#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4394#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5322#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4507#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4508#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4719#L666-45 assume !(1 == ~t2_pc~0); 4720#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5201#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5678#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5672#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4257#L685-45 assume 1 == ~t3_pc~0; 4258#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5317#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5991#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5860#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5861#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6001#L704-45 assume 1 == ~t4_pc~0; 5880#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4124#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4983#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5326#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6073#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5438#L723-45 assume 1 == ~t5_pc~0; 5440#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5928#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5030#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4807#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4808#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5832#L742-45 assume 1 == ~t6_pc~0; 5833#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5055#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5524#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5560#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5561#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5649#L761-45 assume !(1 == ~t7_pc~0); 5650#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5048#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5049#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4455#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4456#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5922#L780-45 assume 1 == ~t8_pc~0; 4833#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4467#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4468#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6049#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4437#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4438#L799-45 assume !(1 == ~t9_pc~0); 4658#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4659#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5974#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5603#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5604#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4375#L818-45 assume 1 == ~t10_pc~0; 4376#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4494#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5577#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4981#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4982#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5697#L837-45 assume !(1 == ~t11_pc~0); 4912#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4913#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5050#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5715#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4513#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4514#L856-45 assume !(1 == ~t12_pc~0); 4515#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4516#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4457#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4458#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5320#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5321#L875-45 assume 1 == ~t13_pc~0; 5291#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5292#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5354#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5966#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5967#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5906#L1427-3 assume !(1 == ~M_E~0); 5117#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5118#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5656#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5308#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5309#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4165#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4166#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5848#L1462-3 assume !(1 == ~T8_E~0); 5849#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5712#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5713#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4416#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4417#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4558#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4731#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4732#L1502-3 assume !(1 == ~E_2~0); 5680#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5811#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4769#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4461#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4462#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4426#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4427#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5527#L1542-3 assume !(1 == ~E_10~0); 5665#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5294#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5295#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4637#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4638#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4057#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4822#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4823#L1947 assume !(0 == start_simulation_~tmp~3#1); 5428#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5633#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4694#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 6026#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 5950#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5780#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5539#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5540#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4753#L1928-2 [2021-12-19 19:16:55,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,530 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2021-12-19 19:16:55,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569798998] [2021-12-19 19:16:55,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,531 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,605 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569798998] [2021-12-19 19:16:55,605 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569798998] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,606 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,606 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770770188] [2021-12-19 19:16:55,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,607 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1579703507, now seen corresponding path program 1 times [2021-12-19 19:16:55,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242685164] [2021-12-19 19:16:55,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,608 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242685164] [2021-12-19 19:16:55,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242685164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,724 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,724 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752847433] [2021-12-19 19:16:55,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,725 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,725 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:55,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:55,726 INFO L87 Difference]: Start difference. First operand 2018 states and 2987 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,776 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2021-12-19 19:16:55,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:55,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2986 transitions. [2021-12-19 19:16:55,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:55,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2986 transitions. [2021-12-19 19:16:55,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:55,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:55,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2986 transitions. [2021-12-19 19:16:55,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:55,832 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2021-12-19 19:16:55,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2986 transitions. [2021-12-19 19:16:55,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:55,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2986 transitions. [2021-12-19 19:16:55,868 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2021-12-19 19:16:55,868 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2021-12-19 19:16:55,868 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:16:55,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2986 transitions. [2021-12-19 19:16:55,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:55,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,879 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,880 INFO L791 eck$LassoCheckResult]: Stem: 9014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10051#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9506#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9507#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 8996#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8997#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9063#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9064#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9502#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9503#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9029#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8848#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8849#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9293#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9294#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9169#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9170#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8819#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8820#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10043#L1279-2 assume !(0 == ~T1_E~0); 8442#L1284-1 assume !(0 == ~T2_E~0); 8443#L1289-1 assume !(0 == ~T3_E~0); 9166#L1294-1 assume !(0 == ~T4_E~0); 9167#L1299-1 assume !(0 == ~T5_E~0); 9178#L1304-1 assume !(0 == ~T6_E~0); 10109#L1309-1 assume !(0 == ~T7_E~0); 10110#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8372#L1319-1 assume !(0 == ~T9_E~0); 8373#L1324-1 assume !(0 == ~T10_E~0); 8545#L1329-1 assume !(0 == ~T11_E~0); 8546#L1334-1 assume !(0 == ~T12_E~0); 9950#L1339-1 assume !(0 == ~T13_E~0); 10031#L1344-1 assume !(0 == ~E_M~0); 10032#L1349-1 assume !(0 == ~E_1~0); 9353#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9354#L1359-1 assume !(0 == ~E_3~0); 9783#L1364-1 assume !(0 == ~E_4~0); 8674#L1369-1 assume !(0 == ~E_5~0); 8675#L1374-1 assume !(0 == ~E_6~0); 9358#L1379-1 assume !(0 == ~E_7~0); 9359#L1384-1 assume !(0 == ~E_8~0); 9436#L1389-1 assume !(0 == ~E_9~0); 9969#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9970#L1399-1 assume !(0 == ~E_11~0); 10073#L1404-1 assume !(0 == ~E_12~0); 8767#L1409-1 assume !(0 == ~E_13~0); 8768#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10065#L628 assume !(1 == ~m_pc~0); 8671#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8670#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9434#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9435#L1591 assume !(0 != activate_threads_~tmp~1#1); 10078#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9222#L647 assume 1 == ~t1_pc~0; 8591#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8592#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8863#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8864#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10018#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10019#L666 assume 1 == ~t2_pc~0; 8439#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8440#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8606#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10035#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9554#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9555#L685 assume !(1 == ~t3_pc~0); 9660#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9659#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9282#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9283#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9404#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8890#L704 assume 1 == ~t4_pc~0; 8891#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9415#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9416#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10056#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9275#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9276#L723 assume !(1 == ~t5_pc~0); 9398#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9634#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9778#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9533#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9534#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8656#L742 assume 1 == ~t6_pc~0; 8657#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8805#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8806#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8341#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8342#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8733#L761 assume !(1 == ~t7_pc~0); 8734#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8602#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8603#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9405#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9406#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8366#L780 assume 1 == ~t8_pc~0; 8367#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8642#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8643#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9366#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9367#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9486#L799 assume 1 == ~t9_pc~0; 9598#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8369#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8370#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9498#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9705#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9516#L818 assume !(1 == ~t10_pc~0); 8150#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8151#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9591#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9520#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9521#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9561#L837 assume 1 == ~t11_pc~0; 9562#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9396#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9799#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9479#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9480#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9231#L856 assume !(1 == ~t12_pc~0); 9232#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9885#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9886#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9866#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9867#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10046#L875 assume 1 == ~t13_pc~0; 9176#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8808#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8809#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8748#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8749#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9588#L1427 assume !(1 == ~M_E~0); 9572#L1427-2 assume !(1 == ~T1_E~0); 8720#L1432-1 assume !(1 == ~T2_E~0); 8721#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9789#L1442-1 assume !(1 == ~T4_E~0); 9790#L1447-1 assume !(1 == ~T5_E~0); 9645#L1452-1 assume !(1 == ~T6_E~0); 8285#L1457-1 assume !(1 == ~T7_E~0); 8286#L1462-1 assume !(1 == ~T8_E~0); 9816#L1467-1 assume !(1 == ~T9_E~0); 9834#L1472-1 assume !(1 == ~T10_E~0); 9835#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9586#L1482-1 assume !(1 == ~T12_E~0); 9587#L1487-1 assume !(1 == ~T13_E~0); 8616#L1492-1 assume !(1 == ~E_M~0); 8617#L1497-1 assume !(1 == ~E_1~0); 8978#L1502-1 assume !(1 == ~E_2~0); 8979#L1507-1 assume !(1 == ~E_3~0); 8494#L1512-1 assume !(1 == ~E_4~0); 8495#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9905#L1522-1 assume !(1 == ~E_6~0); 9219#L1527-1 assume !(1 == ~E_7~0); 9220#L1532-1 assume !(1 == ~E_8~0); 10093#L1537-1 assume !(1 == ~E_9~0); 9422#L1542-1 assume !(1 == ~E_10~0); 9253#L1547-1 assume !(1 == ~E_11~0); 9254#L1552-1 assume !(1 == ~E_12~0); 8189#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8190#L1562-1 assume { :end_inline_reset_delta_events } true; 8796#L1928-2 [2021-12-19 19:16:55,880 INFO L793 eck$LassoCheckResult]: Loop: 8796#L1928-2 assume !false; 9287#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8450#L1254 assume !false; 9037#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8524#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8525#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8722#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9893#L1067 assume !(0 != eval_~tmp~0#1); 8963#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8540#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8541#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9000#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8982#L1284-3 assume !(0 == ~T2_E~0); 8983#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8961#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8962#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9349#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9350#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8859#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8860#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9856#L1324-3 assume !(0 == ~T10_E~0); 8491#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8492#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9259#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9260#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9558#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8840#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8841#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9569#L1364-3 assume !(0 == ~E_4~0); 10091#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9987#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8620#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8621#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8838#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8839#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9129#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9997#L1404-3 assume !(0 == ~E_12~0); 9961#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9962#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9448#L628-45 assume 1 == ~m_pc~0; 9126#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9128#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8485#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8486#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8874#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9597#L647-45 assume 1 == ~t1_pc~0; 8436#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8437#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9365#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8550#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8551#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8762#L666-45 assume !(1 == ~t2_pc~0); 8763#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9244#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9806#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9721#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9715#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8300#L685-45 assume 1 == ~t3_pc~0; 8301#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9360#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10034#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9903#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9904#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10044#L704-45 assume 1 == ~t4_pc~0; 9923#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8167#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9026#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9369#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9481#L723-45 assume !(1 == ~t5_pc~0); 9482#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 9971#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9073#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8850#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8851#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9875#L742-45 assume 1 == ~t6_pc~0; 9876#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9098#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9567#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9603#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9604#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9692#L761-45 assume !(1 == ~t7_pc~0); 9693#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9091#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9092#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8498#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8499#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9965#L780-45 assume 1 == ~t8_pc~0; 8876#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8510#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8511#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10092#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8480#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8481#L799-45 assume 1 == ~t9_pc~0; 9257#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8702#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10017#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9646#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9647#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8418#L818-45 assume 1 == ~t10_pc~0; 8419#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8537#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9620#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9024#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9025#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9740#L837-45 assume !(1 == ~t11_pc~0); 8955#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8956#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9093#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9758#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8556#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8557#L856-45 assume 1 == ~t12_pc~0; 10042#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8559#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8500#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8501#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9363#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9364#L875-45 assume 1 == ~t13_pc~0; 9334#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9335#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9397#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10009#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10010#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9949#L1427-3 assume !(1 == ~M_E~0); 9160#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9161#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9699#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9352#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8208#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8209#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9891#L1462-3 assume !(1 == ~T8_E~0); 9892#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9755#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9756#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8459#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8460#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8601#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8774#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8775#L1502-3 assume !(1 == ~E_2~0); 9723#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9854#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8812#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8504#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8505#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8469#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8470#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9570#L1542-3 assume !(1 == ~E_10~0); 9708#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9337#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9338#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8680#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8681#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8100#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8865#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8866#L1947 assume !(0 == start_simulation_~tmp~3#1); 9471#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9676#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8737#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 10069#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 9993#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9823#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9583#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8796#L1928-2 [2021-12-19 19:16:55,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2021-12-19 19:16:55,884 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677375333] [2021-12-19 19:16:55,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,884 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677375333] [2021-12-19 19:16:55,934 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [677375333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,934 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,934 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,934 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25280190] [2021-12-19 19:16:55,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,935 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,935 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 1 times [2021-12-19 19:16:55,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083907307] [2021-12-19 19:16:55,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,062 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083907307] [2021-12-19 19:16:56,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083907307] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,062 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590355579] [2021-12-19 19:16:56,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,063 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,064 INFO L87 Difference]: Start difference. First operand 2018 states and 2986 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,101 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2021-12-19 19:16:56,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2985 transitions. [2021-12-19 19:16:56,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2985 transitions. [2021-12-19 19:16:56,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:56,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:56,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2985 transitions. [2021-12-19 19:16:56,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,132 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2021-12-19 19:16:56,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2985 transitions. [2021-12-19 19:16:56,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:56,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2985 transitions. [2021-12-19 19:16:56,205 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2021-12-19 19:16:56,205 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2021-12-19 19:16:56,205 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:16:56,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2985 transitions. [2021-12-19 19:16:56,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,216 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,216 INFO L791 eck$LassoCheckResult]: Stem: 13057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14094#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13549#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13550#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13039#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13040#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13106#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13107#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13545#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13546#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13072#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12891#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12892#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13336#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13337#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13212#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13213#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12862#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12863#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14086#L1279-2 assume !(0 == ~T1_E~0); 12485#L1284-1 assume !(0 == ~T2_E~0); 12486#L1289-1 assume !(0 == ~T3_E~0); 13209#L1294-1 assume !(0 == ~T4_E~0); 13210#L1299-1 assume !(0 == ~T5_E~0); 13221#L1304-1 assume !(0 == ~T6_E~0); 14152#L1309-1 assume !(0 == ~T7_E~0); 14153#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12415#L1319-1 assume !(0 == ~T9_E~0); 12416#L1324-1 assume !(0 == ~T10_E~0); 12588#L1329-1 assume !(0 == ~T11_E~0); 12589#L1334-1 assume !(0 == ~T12_E~0); 13993#L1339-1 assume !(0 == ~T13_E~0); 14074#L1344-1 assume !(0 == ~E_M~0); 14075#L1349-1 assume !(0 == ~E_1~0); 13396#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13397#L1359-1 assume !(0 == ~E_3~0); 13826#L1364-1 assume !(0 == ~E_4~0); 12717#L1369-1 assume !(0 == ~E_5~0); 12718#L1374-1 assume !(0 == ~E_6~0); 13401#L1379-1 assume !(0 == ~E_7~0); 13402#L1384-1 assume !(0 == ~E_8~0); 13479#L1389-1 assume !(0 == ~E_9~0); 14012#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14013#L1399-1 assume !(0 == ~E_11~0); 14116#L1404-1 assume !(0 == ~E_12~0); 12810#L1409-1 assume !(0 == ~E_13~0); 12811#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14108#L628 assume !(1 == ~m_pc~0); 12714#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12713#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13477#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13478#L1591 assume !(0 != activate_threads_~tmp~1#1); 14121#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13265#L647 assume 1 == ~t1_pc~0; 12634#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12635#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12906#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12907#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14061#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14062#L666 assume 1 == ~t2_pc~0; 12482#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12483#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12649#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14078#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13597#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13598#L685 assume !(1 == ~t3_pc~0); 13703#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13702#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13325#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13326#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13447#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12933#L704 assume 1 == ~t4_pc~0; 12934#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13458#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13459#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14099#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13318#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13319#L723 assume !(1 == ~t5_pc~0); 13441#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13677#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13821#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13576#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13577#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12699#L742 assume 1 == ~t6_pc~0; 12700#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12848#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12849#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12384#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12385#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12776#L761 assume !(1 == ~t7_pc~0); 12777#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12645#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12646#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13448#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13449#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12409#L780 assume 1 == ~t8_pc~0; 12410#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12685#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12686#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13409#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13410#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13529#L799 assume 1 == ~t9_pc~0; 13641#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12412#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12413#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13541#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13748#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13559#L818 assume !(1 == ~t10_pc~0); 12193#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12194#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13634#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13563#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13564#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13604#L837 assume 1 == ~t11_pc~0; 13605#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13439#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13842#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13522#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13523#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13274#L856 assume !(1 == ~t12_pc~0); 13275#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13928#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13929#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13909#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13910#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14089#L875 assume 1 == ~t13_pc~0; 13219#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12851#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12852#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12791#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12792#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13631#L1427 assume !(1 == ~M_E~0); 13615#L1427-2 assume !(1 == ~T1_E~0); 12763#L1432-1 assume !(1 == ~T2_E~0); 12764#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13832#L1442-1 assume !(1 == ~T4_E~0); 13833#L1447-1 assume !(1 == ~T5_E~0); 13688#L1452-1 assume !(1 == ~T6_E~0); 12328#L1457-1 assume !(1 == ~T7_E~0); 12329#L1462-1 assume !(1 == ~T8_E~0); 13859#L1467-1 assume !(1 == ~T9_E~0); 13877#L1472-1 assume !(1 == ~T10_E~0); 13878#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13629#L1482-1 assume !(1 == ~T12_E~0); 13630#L1487-1 assume !(1 == ~T13_E~0); 12659#L1492-1 assume !(1 == ~E_M~0); 12660#L1497-1 assume !(1 == ~E_1~0); 13021#L1502-1 assume !(1 == ~E_2~0); 13022#L1507-1 assume !(1 == ~E_3~0); 12537#L1512-1 assume !(1 == ~E_4~0); 12538#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 13948#L1522-1 assume !(1 == ~E_6~0); 13262#L1527-1 assume !(1 == ~E_7~0); 13263#L1532-1 assume !(1 == ~E_8~0); 14136#L1537-1 assume !(1 == ~E_9~0); 13465#L1542-1 assume !(1 == ~E_10~0); 13296#L1547-1 assume !(1 == ~E_11~0); 13297#L1552-1 assume !(1 == ~E_12~0); 12232#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12233#L1562-1 assume { :end_inline_reset_delta_events } true; 12839#L1928-2 [2021-12-19 19:16:56,217 INFO L793 eck$LassoCheckResult]: Loop: 12839#L1928-2 assume !false; 13330#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12493#L1254 assume !false; 13080#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12567#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12568#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12765#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13936#L1067 assume !(0 != eval_~tmp~0#1); 13006#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12583#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12584#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13043#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13025#L1284-3 assume !(0 == ~T2_E~0); 13026#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13004#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13005#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13392#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13393#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12902#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12903#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13899#L1324-3 assume !(0 == ~T10_E~0); 12534#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12535#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13302#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13303#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13601#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12883#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12884#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13612#L1364-3 assume !(0 == ~E_4~0); 14134#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14030#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12663#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12664#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12881#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12882#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13172#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14040#L1404-3 assume !(0 == ~E_12~0); 14004#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14005#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13491#L628-45 assume 1 == ~m_pc~0; 13169#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13171#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12528#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12529#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12917#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13640#L647-45 assume !(1 == ~t1_pc~0); 12481#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 12480#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13408#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12594#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12805#L666-45 assume !(1 == ~t2_pc~0); 12806#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13287#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13849#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13764#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13758#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12343#L685-45 assume 1 == ~t3_pc~0; 12344#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13403#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14077#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13946#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13947#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14087#L704-45 assume !(1 == ~t4_pc~0); 12209#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 12210#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13069#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13412#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14159#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13524#L723-45 assume !(1 == ~t5_pc~0); 13525#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 14014#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13116#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12893#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12894#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13918#L742-45 assume !(1 == ~t6_pc~0); 13140#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13141#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13610#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13646#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13647#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13735#L761-45 assume !(1 == ~t7_pc~0); 13736#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13134#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13135#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12541#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12542#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14008#L780-45 assume 1 == ~t8_pc~0; 12919#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12553#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12554#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14135#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12523#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12524#L799-45 assume 1 == ~t9_pc~0; 13300#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12745#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14060#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13689#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13690#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12461#L818-45 assume 1 == ~t10_pc~0; 12462#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12580#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13663#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13067#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13068#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13783#L837-45 assume !(1 == ~t11_pc~0); 12998#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12999#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13136#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13801#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12599#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12600#L856-45 assume 1 == ~t12_pc~0; 14085#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12602#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12543#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12544#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13406#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13407#L875-45 assume 1 == ~t13_pc~0; 13377#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13378#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13440#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14052#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14053#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13992#L1427-3 assume !(1 == ~M_E~0); 13203#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13204#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13742#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13394#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13395#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12251#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12252#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13934#L1462-3 assume !(1 == ~T8_E~0); 13935#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13798#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13799#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12502#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12503#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12644#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12817#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12818#L1502-3 assume !(1 == ~E_2~0); 13766#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13897#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12855#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12547#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12548#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12512#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12513#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13613#L1542-3 assume !(1 == ~E_10~0); 13751#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13380#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13381#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12723#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12724#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12143#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12908#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12909#L1947 assume !(0 == start_simulation_~tmp~3#1); 13514#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13719#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12780#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14112#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 14036#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13866#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13625#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13626#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12839#L1928-2 [2021-12-19 19:16:56,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,218 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2021-12-19 19:16:56,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995414377] [2021-12-19 19:16:56,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,281 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995414377] [2021-12-19 19:16:56,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995414377] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,283 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740676424] [2021-12-19 19:16:56,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,286 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,288 INFO L85 PathProgramCache]: Analyzing trace with hash 975518447, now seen corresponding path program 1 times [2021-12-19 19:16:56,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408452225] [2021-12-19 19:16:56,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,360 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,361 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408452225] [2021-12-19 19:16:56,361 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408452225] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,361 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,361 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,361 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838862169] [2021-12-19 19:16:56,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,362 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,362 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,364 INFO L87 Difference]: Start difference. First operand 2018 states and 2985 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,399 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2021-12-19 19:16:56,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2984 transitions. [2021-12-19 19:16:56,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2984 transitions. [2021-12-19 19:16:56,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:56,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:56,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2984 transitions. [2021-12-19 19:16:56,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,428 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2021-12-19 19:16:56,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2984 transitions. [2021-12-19 19:16:56,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:56,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2984 transitions. [2021-12-19 19:16:56,494 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2021-12-19 19:16:56,494 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2021-12-19 19:16:56,494 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:16:56,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2984 transitions. [2021-12-19 19:16:56,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,507 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,507 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,508 INFO L791 eck$LassoCheckResult]: Stem: 17100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 18137#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17592#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17593#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17082#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17083#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17149#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17150#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17588#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17589#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17115#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16934#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16935#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17379#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17380#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17255#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17256#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16905#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16906#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18129#L1279-2 assume !(0 == ~T1_E~0); 16528#L1284-1 assume !(0 == ~T2_E~0); 16529#L1289-1 assume !(0 == ~T3_E~0); 17252#L1294-1 assume !(0 == ~T4_E~0); 17253#L1299-1 assume !(0 == ~T5_E~0); 17264#L1304-1 assume !(0 == ~T6_E~0); 18195#L1309-1 assume !(0 == ~T7_E~0); 18196#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16458#L1319-1 assume !(0 == ~T9_E~0); 16459#L1324-1 assume !(0 == ~T10_E~0); 16631#L1329-1 assume !(0 == ~T11_E~0); 16632#L1334-1 assume !(0 == ~T12_E~0); 18036#L1339-1 assume !(0 == ~T13_E~0); 18117#L1344-1 assume !(0 == ~E_M~0); 18118#L1349-1 assume !(0 == ~E_1~0); 17439#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17440#L1359-1 assume !(0 == ~E_3~0); 17869#L1364-1 assume !(0 == ~E_4~0); 16760#L1369-1 assume !(0 == ~E_5~0); 16761#L1374-1 assume !(0 == ~E_6~0); 17444#L1379-1 assume !(0 == ~E_7~0); 17445#L1384-1 assume !(0 == ~E_8~0); 17522#L1389-1 assume !(0 == ~E_9~0); 18055#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18056#L1399-1 assume !(0 == ~E_11~0); 18159#L1404-1 assume !(0 == ~E_12~0); 16853#L1409-1 assume !(0 == ~E_13~0); 16854#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18151#L628 assume !(1 == ~m_pc~0); 16757#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16756#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17520#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17521#L1591 assume !(0 != activate_threads_~tmp~1#1); 18164#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17308#L647 assume 1 == ~t1_pc~0; 16677#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16678#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16949#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16950#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18104#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18105#L666 assume 1 == ~t2_pc~0; 16525#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16526#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16692#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18121#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17640#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17641#L685 assume !(1 == ~t3_pc~0); 17746#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17745#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17368#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17369#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17490#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16976#L704 assume 1 == ~t4_pc~0; 16977#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17501#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17502#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18142#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17361#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17362#L723 assume !(1 == ~t5_pc~0); 17484#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17720#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17864#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17619#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17620#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16742#L742 assume 1 == ~t6_pc~0; 16743#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16891#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16892#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16427#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16428#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16819#L761 assume !(1 == ~t7_pc~0); 16820#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16688#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16689#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17491#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17492#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16452#L780 assume 1 == ~t8_pc~0; 16453#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16728#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16729#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17452#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17453#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17572#L799 assume 1 == ~t9_pc~0; 17684#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16455#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16456#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17584#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17791#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17602#L818 assume !(1 == ~t10_pc~0); 16236#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16237#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17677#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17606#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17607#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17647#L837 assume 1 == ~t11_pc~0; 17648#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17482#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17885#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17565#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17566#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17317#L856 assume !(1 == ~t12_pc~0); 17318#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17971#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17972#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 17953#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18132#L875 assume 1 == ~t13_pc~0; 17262#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16894#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16895#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16834#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16835#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17674#L1427 assume !(1 == ~M_E~0); 17658#L1427-2 assume !(1 == ~T1_E~0); 16806#L1432-1 assume !(1 == ~T2_E~0); 16807#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17875#L1442-1 assume !(1 == ~T4_E~0); 17876#L1447-1 assume !(1 == ~T5_E~0); 17731#L1452-1 assume !(1 == ~T6_E~0); 16371#L1457-1 assume !(1 == ~T7_E~0); 16372#L1462-1 assume !(1 == ~T8_E~0); 17902#L1467-1 assume !(1 == ~T9_E~0); 17920#L1472-1 assume !(1 == ~T10_E~0); 17921#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17672#L1482-1 assume !(1 == ~T12_E~0); 17673#L1487-1 assume !(1 == ~T13_E~0); 16702#L1492-1 assume !(1 == ~E_M~0); 16703#L1497-1 assume !(1 == ~E_1~0); 17064#L1502-1 assume !(1 == ~E_2~0); 17065#L1507-1 assume !(1 == ~E_3~0); 16580#L1512-1 assume !(1 == ~E_4~0); 16581#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 17991#L1522-1 assume !(1 == ~E_6~0); 17305#L1527-1 assume !(1 == ~E_7~0); 17306#L1532-1 assume !(1 == ~E_8~0); 18179#L1537-1 assume !(1 == ~E_9~0); 17508#L1542-1 assume !(1 == ~E_10~0); 17339#L1547-1 assume !(1 == ~E_11~0); 17340#L1552-1 assume !(1 == ~E_12~0); 16275#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16276#L1562-1 assume { :end_inline_reset_delta_events } true; 16882#L1928-2 [2021-12-19 19:16:56,508 INFO L793 eck$LassoCheckResult]: Loop: 16882#L1928-2 assume !false; 17373#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16536#L1254 assume !false; 17123#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16610#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16611#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16808#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17979#L1067 assume !(0 != eval_~tmp~0#1); 17049#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16626#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16627#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17086#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17068#L1284-3 assume !(0 == ~T2_E~0); 17069#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17047#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17048#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17435#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17436#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16945#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16946#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17942#L1324-3 assume !(0 == ~T10_E~0); 16577#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16578#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17345#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17346#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17644#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16927#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17655#L1364-3 assume !(0 == ~E_4~0); 18177#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18073#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16706#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16707#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16924#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16925#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17215#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18083#L1404-3 assume !(0 == ~E_12~0); 18047#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18048#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17534#L628-45 assume 1 == ~m_pc~0; 17212#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17214#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16571#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16572#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16960#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17683#L647-45 assume 1 == ~t1_pc~0; 16522#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16523#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17451#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16636#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16637#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16848#L666-45 assume !(1 == ~t2_pc~0); 16849#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17330#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17892#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17807#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17801#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16386#L685-45 assume 1 == ~t3_pc~0; 16387#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17446#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18120#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17989#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17990#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18130#L704-45 assume 1 == ~t4_pc~0; 18009#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16253#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17112#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17455#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18202#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17567#L723-45 assume !(1 == ~t5_pc~0); 17568#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18057#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17159#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16936#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 16937#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17961#L742-45 assume 1 == ~t6_pc~0; 17962#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17184#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17653#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17689#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17690#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17778#L761-45 assume !(1 == ~t7_pc~0); 17779#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17177#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17178#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16584#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16585#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18051#L780-45 assume 1 == ~t8_pc~0; 16962#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16596#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16597#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18178#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16566#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16567#L799-45 assume !(1 == ~t9_pc~0); 16787#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16788#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18103#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17732#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17733#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16504#L818-45 assume 1 == ~t10_pc~0; 16505#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16623#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17706#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17110#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17111#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17826#L837-45 assume !(1 == ~t11_pc~0); 17041#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17042#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17179#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17844#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16642#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16643#L856-45 assume 1 == ~t12_pc~0; 18128#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16645#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16586#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16587#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17449#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17450#L875-45 assume 1 == ~t13_pc~0; 17420#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17421#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17483#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18095#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18096#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18035#L1427-3 assume !(1 == ~M_E~0); 17246#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17247#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17785#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17437#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17438#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16294#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16295#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17977#L1462-3 assume !(1 == ~T8_E~0); 17978#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17841#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17842#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16545#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16546#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16687#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16860#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16861#L1502-3 assume !(1 == ~E_2~0); 17809#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17940#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16898#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16590#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16591#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16555#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16556#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17656#L1542-3 assume !(1 == ~E_10~0); 17794#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17423#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17424#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16766#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16767#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16186#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16951#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16952#L1947 assume !(0 == start_simulation_~tmp~3#1); 17557#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17762#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16823#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 18155#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 18079#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17909#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17668#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17669#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1928-2 [2021-12-19 19:16:56,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,509 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2021-12-19 19:16:56,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53942028] [2021-12-19 19:16:56,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53942028] [2021-12-19 19:16:56,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53942028] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,547 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951722102] [2021-12-19 19:16:56,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,548 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1433001491, now seen corresponding path program 1 times [2021-12-19 19:16:56,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139326074] [2021-12-19 19:16:56,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139326074] [2021-12-19 19:16:56,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139326074] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,601 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149386785] [2021-12-19 19:16:56,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,602 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,602 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,603 INFO L87 Difference]: Start difference. First operand 2018 states and 2984 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,642 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2021-12-19 19:16:56,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2983 transitions. [2021-12-19 19:16:56,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2983 transitions. [2021-12-19 19:16:56,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:56,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:56,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2983 transitions. [2021-12-19 19:16:56,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,668 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2021-12-19 19:16:56,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2983 transitions. [2021-12-19 19:16:56,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:56,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2983 transitions. [2021-12-19 19:16:56,703 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2021-12-19 19:16:56,703 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2021-12-19 19:16:56,703 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:16:56,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2983 transitions. [2021-12-19 19:16:56,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,712 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,713 INFO L791 eck$LassoCheckResult]: Stem: 21143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22180#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21635#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21636#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21125#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21126#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21192#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21193#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21631#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21632#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21158#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20978#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21422#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21423#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21298#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21299#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20948#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20949#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22172#L1279-2 assume !(0 == ~T1_E~0); 20571#L1284-1 assume !(0 == ~T2_E~0); 20572#L1289-1 assume !(0 == ~T3_E~0); 21295#L1294-1 assume !(0 == ~T4_E~0); 21296#L1299-1 assume !(0 == ~T5_E~0); 21307#L1304-1 assume !(0 == ~T6_E~0); 22238#L1309-1 assume !(0 == ~T7_E~0); 22239#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20501#L1319-1 assume !(0 == ~T9_E~0); 20502#L1324-1 assume !(0 == ~T10_E~0); 20674#L1329-1 assume !(0 == ~T11_E~0); 20675#L1334-1 assume !(0 == ~T12_E~0); 22079#L1339-1 assume !(0 == ~T13_E~0); 22160#L1344-1 assume !(0 == ~E_M~0); 22161#L1349-1 assume !(0 == ~E_1~0); 21482#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21483#L1359-1 assume !(0 == ~E_3~0); 21912#L1364-1 assume !(0 == ~E_4~0); 20803#L1369-1 assume !(0 == ~E_5~0); 20804#L1374-1 assume !(0 == ~E_6~0); 21487#L1379-1 assume !(0 == ~E_7~0); 21488#L1384-1 assume !(0 == ~E_8~0); 21565#L1389-1 assume !(0 == ~E_9~0); 22098#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22099#L1399-1 assume !(0 == ~E_11~0); 22202#L1404-1 assume !(0 == ~E_12~0); 20896#L1409-1 assume !(0 == ~E_13~0); 20897#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22194#L628 assume !(1 == ~m_pc~0); 20800#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20799#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21563#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21564#L1591 assume !(0 != activate_threads_~tmp~1#1); 22207#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21351#L647 assume 1 == ~t1_pc~0; 20720#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20721#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20992#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20993#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22147#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22148#L666 assume 1 == ~t2_pc~0; 20568#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20569#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20735#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22164#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21683#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21684#L685 assume !(1 == ~t3_pc~0); 21789#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21788#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21411#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21412#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21533#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21019#L704 assume 1 == ~t4_pc~0; 21020#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21544#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21545#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22185#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21404#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21405#L723 assume !(1 == ~t5_pc~0); 21527#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21763#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21907#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21662#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21663#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20785#L742 assume 1 == ~t6_pc~0; 20786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20934#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20935#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20470#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20471#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20862#L761 assume !(1 == ~t7_pc~0); 20863#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20731#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20732#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21534#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21535#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20495#L780 assume 1 == ~t8_pc~0; 20496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20771#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20772#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21495#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21496#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21615#L799 assume 1 == ~t9_pc~0; 21727#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20499#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21627#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21834#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21645#L818 assume !(1 == ~t10_pc~0); 20279#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20280#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21720#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21649#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21650#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21690#L837 assume 1 == ~t11_pc~0; 21691#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21525#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21928#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21608#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21609#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21360#L856 assume !(1 == ~t12_pc~0); 21361#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22014#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22015#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21995#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 21996#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22175#L875 assume 1 == ~t13_pc~0; 21305#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20937#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20938#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20877#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 20878#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21717#L1427 assume !(1 == ~M_E~0); 21701#L1427-2 assume !(1 == ~T1_E~0); 20849#L1432-1 assume !(1 == ~T2_E~0); 20850#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21918#L1442-1 assume !(1 == ~T4_E~0); 21919#L1447-1 assume !(1 == ~T5_E~0); 21774#L1452-1 assume !(1 == ~T6_E~0); 20414#L1457-1 assume !(1 == ~T7_E~0); 20415#L1462-1 assume !(1 == ~T8_E~0); 21945#L1467-1 assume !(1 == ~T9_E~0); 21963#L1472-1 assume !(1 == ~T10_E~0); 21964#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21715#L1482-1 assume !(1 == ~T12_E~0); 21716#L1487-1 assume !(1 == ~T13_E~0); 20745#L1492-1 assume !(1 == ~E_M~0); 20746#L1497-1 assume !(1 == ~E_1~0); 21107#L1502-1 assume !(1 == ~E_2~0); 21108#L1507-1 assume !(1 == ~E_3~0); 20623#L1512-1 assume !(1 == ~E_4~0); 20624#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22034#L1522-1 assume !(1 == ~E_6~0); 21348#L1527-1 assume !(1 == ~E_7~0); 21349#L1532-1 assume !(1 == ~E_8~0); 22222#L1537-1 assume !(1 == ~E_9~0); 21551#L1542-1 assume !(1 == ~E_10~0); 21382#L1547-1 assume !(1 == ~E_11~0); 21383#L1552-1 assume !(1 == ~E_12~0); 20318#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20319#L1562-1 assume { :end_inline_reset_delta_events } true; 20925#L1928-2 [2021-12-19 19:16:56,713 INFO L793 eck$LassoCheckResult]: Loop: 20925#L1928-2 assume !false; 21416#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20579#L1254 assume !false; 21166#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20653#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20654#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20851#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22022#L1067 assume !(0 != eval_~tmp~0#1); 21092#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20669#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20670#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21129#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21111#L1284-3 assume !(0 == ~T2_E~0); 21112#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21090#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21091#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21478#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21479#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20988#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20989#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21985#L1324-3 assume !(0 == ~T10_E~0); 20620#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20621#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21388#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21389#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21687#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20969#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20970#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21698#L1364-3 assume !(0 == ~E_4~0); 22220#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22116#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20749#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20750#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20967#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20968#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21258#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22126#L1404-3 assume !(0 == ~E_12~0); 22090#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22091#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21577#L628-45 assume 1 == ~m_pc~0; 21255#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21257#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20614#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20615#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21003#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21726#L647-45 assume 1 == ~t1_pc~0; 20565#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20566#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21494#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20679#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20680#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20891#L666-45 assume !(1 == ~t2_pc~0); 20892#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21373#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21935#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21850#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21844#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20429#L685-45 assume 1 == ~t3_pc~0; 20430#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21489#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22163#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22032#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22033#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22173#L704-45 assume 1 == ~t4_pc~0; 22052#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20296#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21155#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21498#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22245#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21610#L723-45 assume !(1 == ~t5_pc~0); 21611#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22100#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21202#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20979#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 20980#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22004#L742-45 assume 1 == ~t6_pc~0; 22005#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21227#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21696#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21732#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21733#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21821#L761-45 assume !(1 == ~t7_pc~0); 21822#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21220#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21221#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20627#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20628#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22094#L780-45 assume 1 == ~t8_pc~0; 21005#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20639#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20640#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22221#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20609#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20610#L799-45 assume 1 == ~t9_pc~0; 21386#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20831#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22146#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21775#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21776#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20547#L818-45 assume 1 == ~t10_pc~0; 20548#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20666#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21749#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21153#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21154#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21869#L837-45 assume !(1 == ~t11_pc~0); 21084#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21085#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21222#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21887#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20685#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20686#L856-45 assume 1 == ~t12_pc~0; 22171#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20688#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20629#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20630#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21492#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21493#L875-45 assume 1 == ~t13_pc~0; 21463#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21464#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21526#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22138#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22139#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22078#L1427-3 assume !(1 == ~M_E~0); 21289#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21290#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21828#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21480#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21481#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20337#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20338#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22020#L1462-3 assume !(1 == ~T8_E~0); 22021#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21884#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21885#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20588#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20589#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20730#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20903#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20904#L1502-3 assume !(1 == ~E_2~0); 21852#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21983#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20941#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20633#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20634#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20598#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20599#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21699#L1542-3 assume !(1 == ~E_10~0); 21837#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21466#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21467#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20809#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20810#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20229#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20994#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20995#L1947 assume !(0 == start_simulation_~tmp~3#1); 21600#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21805#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20866#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22198#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 22122#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21952#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21711#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21712#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 20925#L1928-2 [2021-12-19 19:16:56,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2021-12-19 19:16:56,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,718 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774466053] [2021-12-19 19:16:56,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,718 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,757 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774466053] [2021-12-19 19:16:56,757 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774466053] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,757 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,758 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,758 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091582218] [2021-12-19 19:16:56,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,760 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,762 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 2 times [2021-12-19 19:16:56,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192054803] [2021-12-19 19:16:56,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,766 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192054803] [2021-12-19 19:16:56,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192054803] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139917525] [2021-12-19 19:16:56,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,837 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,838 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,838 INFO L87 Difference]: Start difference. First operand 2018 states and 2983 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,871 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2021-12-19 19:16:56,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2982 transitions. [2021-12-19 19:16:56,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2982 transitions. [2021-12-19 19:16:56,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:56,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:56,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2982 transitions. [2021-12-19 19:16:56,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,892 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2021-12-19 19:16:56,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2982 transitions. [2021-12-19 19:16:56,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:56,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2982 transitions. [2021-12-19 19:16:56,922 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2021-12-19 19:16:56,922 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2021-12-19 19:16:56,922 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:16:56,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2982 transitions. [2021-12-19 19:16:56,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:56,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,930 INFO L791 eck$LassoCheckResult]: Stem: 25186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 26223#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25678#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25679#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25168#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25169#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25235#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25236#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25674#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25675#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25201#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25020#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25021#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25465#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25466#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25341#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25342#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 24991#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24992#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26215#L1279-2 assume !(0 == ~T1_E~0); 24614#L1284-1 assume !(0 == ~T2_E~0); 24615#L1289-1 assume !(0 == ~T3_E~0); 25338#L1294-1 assume !(0 == ~T4_E~0); 25339#L1299-1 assume !(0 == ~T5_E~0); 25350#L1304-1 assume !(0 == ~T6_E~0); 26281#L1309-1 assume !(0 == ~T7_E~0); 26282#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24544#L1319-1 assume !(0 == ~T9_E~0); 24545#L1324-1 assume !(0 == ~T10_E~0); 24717#L1329-1 assume !(0 == ~T11_E~0); 24718#L1334-1 assume !(0 == ~T12_E~0); 26122#L1339-1 assume !(0 == ~T13_E~0); 26203#L1344-1 assume !(0 == ~E_M~0); 26204#L1349-1 assume !(0 == ~E_1~0); 25525#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25526#L1359-1 assume !(0 == ~E_3~0); 25955#L1364-1 assume !(0 == ~E_4~0); 24846#L1369-1 assume !(0 == ~E_5~0); 24847#L1374-1 assume !(0 == ~E_6~0); 25530#L1379-1 assume !(0 == ~E_7~0); 25531#L1384-1 assume !(0 == ~E_8~0); 25608#L1389-1 assume !(0 == ~E_9~0); 26141#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26142#L1399-1 assume !(0 == ~E_11~0); 26245#L1404-1 assume !(0 == ~E_12~0); 24939#L1409-1 assume !(0 == ~E_13~0); 24940#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26237#L628 assume !(1 == ~m_pc~0); 24843#L628-2 is_master_triggered_~__retres1~0#1 := 0; 24842#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25606#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25607#L1591 assume !(0 != activate_threads_~tmp~1#1); 26250#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25394#L647 assume 1 == ~t1_pc~0; 24763#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24764#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25035#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25036#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26190#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26191#L666 assume 1 == ~t2_pc~0; 24611#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24612#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24778#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26207#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25726#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25727#L685 assume !(1 == ~t3_pc~0); 25832#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25831#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25454#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25455#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25576#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25062#L704 assume 1 == ~t4_pc~0; 25063#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25587#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25588#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26228#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25447#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25448#L723 assume !(1 == ~t5_pc~0); 25570#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25806#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25950#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25705#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25706#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24828#L742 assume 1 == ~t6_pc~0; 24829#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24977#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24978#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24513#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24514#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24905#L761 assume !(1 == ~t7_pc~0); 24906#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24774#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24775#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25577#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25578#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24538#L780 assume 1 == ~t8_pc~0; 24539#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24814#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24815#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25538#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25539#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25658#L799 assume 1 == ~t9_pc~0; 25770#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24541#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24542#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25670#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 25877#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25688#L818 assume !(1 == ~t10_pc~0); 24322#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24323#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25763#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25692#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25693#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25733#L837 assume 1 == ~t11_pc~0; 25734#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25568#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25971#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25651#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25652#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25403#L856 assume !(1 == ~t12_pc~0); 25404#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26057#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26058#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26038#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26039#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26218#L875 assume 1 == ~t13_pc~0; 25348#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 24980#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24981#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24920#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 24921#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25760#L1427 assume !(1 == ~M_E~0); 25744#L1427-2 assume !(1 == ~T1_E~0); 24892#L1432-1 assume !(1 == ~T2_E~0); 24893#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25961#L1442-1 assume !(1 == ~T4_E~0); 25962#L1447-1 assume !(1 == ~T5_E~0); 25817#L1452-1 assume !(1 == ~T6_E~0); 24457#L1457-1 assume !(1 == ~T7_E~0); 24458#L1462-1 assume !(1 == ~T8_E~0); 25988#L1467-1 assume !(1 == ~T9_E~0); 26006#L1472-1 assume !(1 == ~T10_E~0); 26007#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25758#L1482-1 assume !(1 == ~T12_E~0); 25759#L1487-1 assume !(1 == ~T13_E~0); 24788#L1492-1 assume !(1 == ~E_M~0); 24789#L1497-1 assume !(1 == ~E_1~0); 25150#L1502-1 assume !(1 == ~E_2~0); 25151#L1507-1 assume !(1 == ~E_3~0); 24666#L1512-1 assume !(1 == ~E_4~0); 24667#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26077#L1522-1 assume !(1 == ~E_6~0); 25391#L1527-1 assume !(1 == ~E_7~0); 25392#L1532-1 assume !(1 == ~E_8~0); 26265#L1537-1 assume !(1 == ~E_9~0); 25594#L1542-1 assume !(1 == ~E_10~0); 25425#L1547-1 assume !(1 == ~E_11~0); 25426#L1552-1 assume !(1 == ~E_12~0); 24361#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24362#L1562-1 assume { :end_inline_reset_delta_events } true; 24968#L1928-2 [2021-12-19 19:16:56,931 INFO L793 eck$LassoCheckResult]: Loop: 24968#L1928-2 assume !false; 25459#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24622#L1254 assume !false; 25209#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24696#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24697#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24894#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26065#L1067 assume !(0 != eval_~tmp~0#1); 25135#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24712#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24713#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25172#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25154#L1284-3 assume !(0 == ~T2_E~0); 25155#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25133#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25134#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25521#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25522#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25031#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25032#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26028#L1324-3 assume !(0 == ~T10_E~0); 24663#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24664#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25431#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25432#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25730#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25012#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25013#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25741#L1364-3 assume !(0 == ~E_4~0); 26263#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26159#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24792#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24793#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25010#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25011#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25301#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26169#L1404-3 assume !(0 == ~E_12~0); 26133#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26134#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25620#L628-45 assume 1 == ~m_pc~0; 25298#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25300#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24657#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24658#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25046#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25769#L647-45 assume 1 == ~t1_pc~0; 24608#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24609#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25537#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24722#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24723#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24934#L666-45 assume !(1 == ~t2_pc~0); 24935#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25416#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25978#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25893#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25887#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24472#L685-45 assume 1 == ~t3_pc~0; 24473#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25532#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26206#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26075#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26076#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26216#L704-45 assume !(1 == ~t4_pc~0); 24338#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24339#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25198#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25541#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26288#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25653#L723-45 assume !(1 == ~t5_pc~0); 25654#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 26143#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25245#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25022#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25023#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26047#L742-45 assume 1 == ~t6_pc~0; 26048#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25270#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25739#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25775#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25776#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25864#L761-45 assume !(1 == ~t7_pc~0); 25865#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25263#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25264#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24670#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24671#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26137#L780-45 assume 1 == ~t8_pc~0; 25048#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24682#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24683#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26264#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24652#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24653#L799-45 assume 1 == ~t9_pc~0; 25429#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24874#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26189#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25818#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25819#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24590#L818-45 assume !(1 == ~t10_pc~0); 24592#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24709#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25792#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25196#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25197#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25912#L837-45 assume !(1 == ~t11_pc~0); 25127#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25128#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25265#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25930#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24728#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24729#L856-45 assume 1 == ~t12_pc~0; 26214#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24731#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24672#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24673#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25535#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25536#L875-45 assume 1 == ~t13_pc~0; 25506#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25507#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25569#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26181#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26182#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26121#L1427-3 assume !(1 == ~M_E~0); 25332#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25333#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25871#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25523#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25524#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24380#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24381#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26063#L1462-3 assume !(1 == ~T8_E~0); 26064#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25927#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25928#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24631#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24632#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24773#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24946#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24947#L1502-3 assume !(1 == ~E_2~0); 25895#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26026#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24984#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24676#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24677#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24641#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24642#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25742#L1542-3 assume !(1 == ~E_10~0); 25880#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25509#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25510#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24852#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24853#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24272#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25037#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25038#L1947 assume !(0 == start_simulation_~tmp~3#1); 25643#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25848#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24909#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26241#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 26165#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25995#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25754#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25755#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 24968#L1928-2 [2021-12-19 19:16:56,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,931 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2021-12-19 19:16:56,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621173834] [2021-12-19 19:16:56,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621173834] [2021-12-19 19:16:56,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621173834] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157152841] [2021-12-19 19:16:56,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,962 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,963 INFO L85 PathProgramCache]: Analyzing trace with hash -130029202, now seen corresponding path program 1 times [2021-12-19 19:16:56,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32027558] [2021-12-19 19:16:56,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,004 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32027558] [2021-12-19 19:16:57,004 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32027558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,004 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048532844] [2021-12-19 19:16:57,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,005 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,005 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,006 INFO L87 Difference]: Start difference. First operand 2018 states and 2982 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,037 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2021-12-19 19:16:57,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2981 transitions. [2021-12-19 19:16:57,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2981 transitions. [2021-12-19 19:16:57,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:57,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:57,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2981 transitions. [2021-12-19 19:16:57,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,061 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2021-12-19 19:16:57,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2981 transitions. [2021-12-19 19:16:57,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:57,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2981 transitions. [2021-12-19 19:16:57,098 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2021-12-19 19:16:57,098 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2021-12-19 19:16:57,098 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:16:57,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2981 transitions. [2021-12-19 19:16:57,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,107 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,107 INFO L791 eck$LassoCheckResult]: Stem: 29229#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30266#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29721#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29722#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29211#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29212#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29278#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29279#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29717#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29718#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29244#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29063#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29064#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29508#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29509#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29384#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29385#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29034#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29035#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30258#L1279-2 assume !(0 == ~T1_E~0); 28657#L1284-1 assume !(0 == ~T2_E~0); 28658#L1289-1 assume !(0 == ~T3_E~0); 29381#L1294-1 assume !(0 == ~T4_E~0); 29382#L1299-1 assume !(0 == ~T5_E~0); 29393#L1304-1 assume !(0 == ~T6_E~0); 30324#L1309-1 assume !(0 == ~T7_E~0); 30325#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28587#L1319-1 assume !(0 == ~T9_E~0); 28588#L1324-1 assume !(0 == ~T10_E~0); 28760#L1329-1 assume !(0 == ~T11_E~0); 28761#L1334-1 assume !(0 == ~T12_E~0); 30165#L1339-1 assume !(0 == ~T13_E~0); 30246#L1344-1 assume !(0 == ~E_M~0); 30247#L1349-1 assume !(0 == ~E_1~0); 29568#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29569#L1359-1 assume !(0 == ~E_3~0); 29998#L1364-1 assume !(0 == ~E_4~0); 28889#L1369-1 assume !(0 == ~E_5~0); 28890#L1374-1 assume !(0 == ~E_6~0); 29573#L1379-1 assume !(0 == ~E_7~0); 29574#L1384-1 assume !(0 == ~E_8~0); 29651#L1389-1 assume !(0 == ~E_9~0); 30184#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30185#L1399-1 assume !(0 == ~E_11~0); 30288#L1404-1 assume !(0 == ~E_12~0); 28982#L1409-1 assume !(0 == ~E_13~0); 28983#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30280#L628 assume !(1 == ~m_pc~0); 28886#L628-2 is_master_triggered_~__retres1~0#1 := 0; 28885#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29649#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29650#L1591 assume !(0 != activate_threads_~tmp~1#1); 30293#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29437#L647 assume 1 == ~t1_pc~0; 28806#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28807#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29078#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29079#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30233#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30234#L666 assume 1 == ~t2_pc~0; 28654#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28655#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28821#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30250#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29769#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29770#L685 assume !(1 == ~t3_pc~0); 29875#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29874#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29497#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29498#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29619#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29105#L704 assume 1 == ~t4_pc~0; 29106#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29630#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29631#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30271#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29490#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29491#L723 assume !(1 == ~t5_pc~0); 29613#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29849#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29993#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29748#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29749#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28871#L742 assume 1 == ~t6_pc~0; 28872#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29020#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29021#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28556#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28557#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28948#L761 assume !(1 == ~t7_pc~0); 28949#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28817#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28818#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29620#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29621#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28581#L780 assume 1 == ~t8_pc~0; 28582#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28857#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28858#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29581#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29582#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29701#L799 assume 1 == ~t9_pc~0; 29813#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28584#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28585#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29713#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 29920#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29731#L818 assume !(1 == ~t10_pc~0); 28365#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28366#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29806#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29735#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29736#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29776#L837 assume 1 == ~t11_pc~0; 29777#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29611#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30014#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29694#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29695#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29446#L856 assume !(1 == ~t12_pc~0); 29447#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30100#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30101#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30081#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30082#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30261#L875 assume 1 == ~t13_pc~0; 29391#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29023#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29024#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28963#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 28964#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29803#L1427 assume !(1 == ~M_E~0); 29787#L1427-2 assume !(1 == ~T1_E~0); 28935#L1432-1 assume !(1 == ~T2_E~0); 28936#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30004#L1442-1 assume !(1 == ~T4_E~0); 30005#L1447-1 assume !(1 == ~T5_E~0); 29860#L1452-1 assume !(1 == ~T6_E~0); 28500#L1457-1 assume !(1 == ~T7_E~0); 28501#L1462-1 assume !(1 == ~T8_E~0); 30031#L1467-1 assume !(1 == ~T9_E~0); 30049#L1472-1 assume !(1 == ~T10_E~0); 30050#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29801#L1482-1 assume !(1 == ~T12_E~0); 29802#L1487-1 assume !(1 == ~T13_E~0); 28831#L1492-1 assume !(1 == ~E_M~0); 28832#L1497-1 assume !(1 == ~E_1~0); 29193#L1502-1 assume !(1 == ~E_2~0); 29194#L1507-1 assume !(1 == ~E_3~0); 28709#L1512-1 assume !(1 == ~E_4~0); 28710#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30120#L1522-1 assume !(1 == ~E_6~0); 29434#L1527-1 assume !(1 == ~E_7~0); 29435#L1532-1 assume !(1 == ~E_8~0); 30308#L1537-1 assume !(1 == ~E_9~0); 29637#L1542-1 assume !(1 == ~E_10~0); 29468#L1547-1 assume !(1 == ~E_11~0); 29469#L1552-1 assume !(1 == ~E_12~0); 28404#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28405#L1562-1 assume { :end_inline_reset_delta_events } true; 29011#L1928-2 [2021-12-19 19:16:57,108 INFO L793 eck$LassoCheckResult]: Loop: 29011#L1928-2 assume !false; 29502#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28665#L1254 assume !false; 29252#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28739#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28740#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28937#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30108#L1067 assume !(0 != eval_~tmp~0#1); 29178#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28755#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28756#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29215#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29197#L1284-3 assume !(0 == ~T2_E~0); 29198#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29176#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29177#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29564#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29565#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29074#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29075#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30071#L1324-3 assume !(0 == ~T10_E~0); 28706#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28707#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29474#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29475#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29773#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29055#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29056#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29784#L1364-3 assume !(0 == ~E_4~0); 30306#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30202#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28835#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28836#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29053#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29054#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29344#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30212#L1404-3 assume !(0 == ~E_12~0); 30176#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30177#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29663#L628-45 assume 1 == ~m_pc~0; 29341#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29343#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28700#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28701#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29089#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29812#L647-45 assume 1 == ~t1_pc~0; 28651#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28652#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29580#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28765#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28766#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28977#L666-45 assume !(1 == ~t2_pc~0); 28978#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29459#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30021#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29936#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29930#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28515#L685-45 assume 1 == ~t3_pc~0; 28516#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29575#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30249#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30118#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30119#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30259#L704-45 assume 1 == ~t4_pc~0; 30138#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28382#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29241#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29584#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30331#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29696#L723-45 assume !(1 == ~t5_pc~0); 29697#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30186#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29288#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29065#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29066#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30090#L742-45 assume !(1 == ~t6_pc~0); 29312#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29313#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29782#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29818#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29819#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29907#L761-45 assume !(1 == ~t7_pc~0); 29908#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29306#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29307#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28713#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28714#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30180#L780-45 assume 1 == ~t8_pc~0; 29091#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28725#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28726#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30307#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28695#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28696#L799-45 assume 1 == ~t9_pc~0; 29472#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28917#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30232#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29861#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29862#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28633#L818-45 assume 1 == ~t10_pc~0; 28634#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28752#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29835#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29239#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29240#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29955#L837-45 assume !(1 == ~t11_pc~0); 29170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29171#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29308#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29973#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28771#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28772#L856-45 assume 1 == ~t12_pc~0; 30257#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28774#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28715#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28716#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29578#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29579#L875-45 assume 1 == ~t13_pc~0; 29549#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29550#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29612#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30224#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30225#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30164#L1427-3 assume !(1 == ~M_E~0); 29375#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29376#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29914#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29566#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29567#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28423#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28424#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30106#L1462-3 assume !(1 == ~T8_E~0); 30107#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29970#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29971#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28674#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28675#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 28816#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28989#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28990#L1502-3 assume !(1 == ~E_2~0); 29938#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30069#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29027#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28719#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28720#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28684#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28685#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29785#L1542-3 assume !(1 == ~E_10~0); 29923#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29552#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29553#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28895#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28896#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28315#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29080#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29081#L1947 assume !(0 == start_simulation_~tmp~3#1); 29686#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29891#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28952#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30284#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 30208#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30038#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29797#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29798#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29011#L1928-2 [2021-12-19 19:16:57,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2021-12-19 19:16:57,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432689219] [2021-12-19 19:16:57,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,154 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432689219] [2021-12-19 19:16:57,154 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432689219] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,155 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,155 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016634304] [2021-12-19 19:16:57,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,156 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,156 INFO L85 PathProgramCache]: Analyzing trace with hash -864361555, now seen corresponding path program 1 times [2021-12-19 19:16:57,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111362594] [2021-12-19 19:16:57,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111362594] [2021-12-19 19:16:57,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111362594] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,205 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,206 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090488135] [2021-12-19 19:16:57,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,206 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,206 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,207 INFO L87 Difference]: Start difference. First operand 2018 states and 2981 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,240 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2021-12-19 19:16:57,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2980 transitions. [2021-12-19 19:16:57,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2980 transitions. [2021-12-19 19:16:57,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:57,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:57,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2980 transitions. [2021-12-19 19:16:57,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,262 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2021-12-19 19:16:57,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2980 transitions. [2021-12-19 19:16:57,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:57,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2980 transitions. [2021-12-19 19:16:57,299 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2021-12-19 19:16:57,299 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2021-12-19 19:16:57,299 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:16:57,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2980 transitions. [2021-12-19 19:16:57,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,306 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,307 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,307 INFO L791 eck$LassoCheckResult]: Stem: 33272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 34309#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33764#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33765#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33254#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33255#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33321#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33322#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33760#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33761#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33287#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33106#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33107#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33551#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33552#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33427#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33428#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33077#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33078#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34301#L1279-2 assume !(0 == ~T1_E~0); 32700#L1284-1 assume !(0 == ~T2_E~0); 32701#L1289-1 assume !(0 == ~T3_E~0); 33424#L1294-1 assume !(0 == ~T4_E~0); 33425#L1299-1 assume !(0 == ~T5_E~0); 33436#L1304-1 assume !(0 == ~T6_E~0); 34367#L1309-1 assume !(0 == ~T7_E~0); 34368#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32630#L1319-1 assume !(0 == ~T9_E~0); 32631#L1324-1 assume !(0 == ~T10_E~0); 32803#L1329-1 assume !(0 == ~T11_E~0); 32804#L1334-1 assume !(0 == ~T12_E~0); 34208#L1339-1 assume !(0 == ~T13_E~0); 34289#L1344-1 assume !(0 == ~E_M~0); 34290#L1349-1 assume !(0 == ~E_1~0); 33611#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33612#L1359-1 assume !(0 == ~E_3~0); 34041#L1364-1 assume !(0 == ~E_4~0); 32932#L1369-1 assume !(0 == ~E_5~0); 32933#L1374-1 assume !(0 == ~E_6~0); 33616#L1379-1 assume !(0 == ~E_7~0); 33617#L1384-1 assume !(0 == ~E_8~0); 33694#L1389-1 assume !(0 == ~E_9~0); 34227#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34228#L1399-1 assume !(0 == ~E_11~0); 34331#L1404-1 assume !(0 == ~E_12~0); 33025#L1409-1 assume !(0 == ~E_13~0); 33026#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34323#L628 assume !(1 == ~m_pc~0); 32929#L628-2 is_master_triggered_~__retres1~0#1 := 0; 32928#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33692#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33693#L1591 assume !(0 != activate_threads_~tmp~1#1); 34336#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33480#L647 assume 1 == ~t1_pc~0; 32849#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32850#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33121#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33122#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34276#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34277#L666 assume 1 == ~t2_pc~0; 32697#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32698#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32864#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34293#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 33812#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33813#L685 assume !(1 == ~t3_pc~0); 33918#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33917#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33540#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33541#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33662#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33148#L704 assume 1 == ~t4_pc~0; 33149#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33673#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33674#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34314#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33533#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33534#L723 assume !(1 == ~t5_pc~0); 33656#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33892#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34036#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33791#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 33792#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32914#L742 assume 1 == ~t6_pc~0; 32915#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33063#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33064#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32599#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32600#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32991#L761 assume !(1 == ~t7_pc~0); 32992#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32860#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32861#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33663#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33664#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32624#L780 assume 1 == ~t8_pc~0; 32625#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32900#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32901#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33624#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33625#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33744#L799 assume 1 == ~t9_pc~0; 33856#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32627#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32628#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33756#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 33963#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33774#L818 assume !(1 == ~t10_pc~0); 32408#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32409#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33849#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33778#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33779#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33819#L837 assume 1 == ~t11_pc~0; 33820#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33654#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34057#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33737#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33738#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33489#L856 assume !(1 == ~t12_pc~0); 33490#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34143#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34144#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34124#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34125#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34304#L875 assume 1 == ~t13_pc~0; 33434#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33066#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33067#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33006#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33007#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33846#L1427 assume !(1 == ~M_E~0); 33830#L1427-2 assume !(1 == ~T1_E~0); 32978#L1432-1 assume !(1 == ~T2_E~0); 32979#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34047#L1442-1 assume !(1 == ~T4_E~0); 34048#L1447-1 assume !(1 == ~T5_E~0); 33903#L1452-1 assume !(1 == ~T6_E~0); 32543#L1457-1 assume !(1 == ~T7_E~0); 32544#L1462-1 assume !(1 == ~T8_E~0); 34074#L1467-1 assume !(1 == ~T9_E~0); 34092#L1472-1 assume !(1 == ~T10_E~0); 34093#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33844#L1482-1 assume !(1 == ~T12_E~0); 33845#L1487-1 assume !(1 == ~T13_E~0); 32874#L1492-1 assume !(1 == ~E_M~0); 32875#L1497-1 assume !(1 == ~E_1~0); 33236#L1502-1 assume !(1 == ~E_2~0); 33237#L1507-1 assume !(1 == ~E_3~0); 32752#L1512-1 assume !(1 == ~E_4~0); 32753#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34163#L1522-1 assume !(1 == ~E_6~0); 33477#L1527-1 assume !(1 == ~E_7~0); 33478#L1532-1 assume !(1 == ~E_8~0); 34351#L1537-1 assume !(1 == ~E_9~0); 33680#L1542-1 assume !(1 == ~E_10~0); 33511#L1547-1 assume !(1 == ~E_11~0); 33512#L1552-1 assume !(1 == ~E_12~0); 32447#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32448#L1562-1 assume { :end_inline_reset_delta_events } true; 33054#L1928-2 [2021-12-19 19:16:57,307 INFO L793 eck$LassoCheckResult]: Loop: 33054#L1928-2 assume !false; 33545#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32708#L1254 assume !false; 33295#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32782#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32783#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32980#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34151#L1067 assume !(0 != eval_~tmp~0#1); 33221#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32798#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32799#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33258#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33240#L1284-3 assume !(0 == ~T2_E~0); 33241#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33219#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33220#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33607#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33608#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33117#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33118#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34114#L1324-3 assume !(0 == ~T10_E~0); 32749#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32750#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33517#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33518#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33816#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33098#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33099#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33827#L1364-3 assume !(0 == ~E_4~0); 34349#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34245#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32878#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32879#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33096#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33097#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33387#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34255#L1404-3 assume !(0 == ~E_12~0); 34219#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34220#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33706#L628-45 assume 1 == ~m_pc~0; 33384#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33386#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32743#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32744#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33132#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33855#L647-45 assume 1 == ~t1_pc~0; 32694#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32695#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33623#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32808#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32809#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33020#L666-45 assume !(1 == ~t2_pc~0); 33021#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33502#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34064#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33979#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33973#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32558#L685-45 assume !(1 == ~t3_pc~0); 32560#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 33618#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34292#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34161#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34162#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34302#L704-45 assume 1 == ~t4_pc~0; 34181#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32425#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33627#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34374#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33739#L723-45 assume !(1 == ~t5_pc~0); 33740#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34229#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33331#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33108#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33109#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34133#L742-45 assume 1 == ~t6_pc~0; 34134#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33356#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33825#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33861#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33862#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33950#L761-45 assume 1 == ~t7_pc~0; 33952#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33349#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33350#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32756#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32757#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34223#L780-45 assume 1 == ~t8_pc~0; 33134#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32768#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32769#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34350#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32738#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32739#L799-45 assume 1 == ~t9_pc~0; 33515#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32960#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34275#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33904#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33905#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32676#L818-45 assume 1 == ~t10_pc~0; 32677#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32795#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33878#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33282#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33283#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33998#L837-45 assume !(1 == ~t11_pc~0); 33213#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33214#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33351#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34016#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32814#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32815#L856-45 assume !(1 == ~t12_pc~0); 32816#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 32817#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32758#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32759#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33621#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33622#L875-45 assume 1 == ~t13_pc~0; 33592#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33593#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33655#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34267#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34268#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34207#L1427-3 assume !(1 == ~M_E~0); 33418#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33419#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33957#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33609#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33610#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32466#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32467#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34149#L1462-3 assume !(1 == ~T8_E~0); 34150#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34013#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34014#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32717#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32718#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 32859#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33032#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33033#L1502-3 assume !(1 == ~E_2~0); 33981#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34112#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33070#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32762#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32763#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32727#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32728#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33828#L1542-3 assume !(1 == ~E_10~0); 33966#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33595#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33596#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32938#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32939#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32358#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33123#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33124#L1947 assume !(0 == start_simulation_~tmp~3#1); 33729#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33934#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32995#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34327#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 34251#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34081#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33840#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33841#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33054#L1928-2 [2021-12-19 19:16:57,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2021-12-19 19:16:57,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804986622] [2021-12-19 19:16:57,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,340 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804986622] [2021-12-19 19:16:57,341 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804986622] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,341 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,341 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468552983] [2021-12-19 19:16:57,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,342 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1275216595, now seen corresponding path program 1 times [2021-12-19 19:16:57,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998485847] [2021-12-19 19:16:57,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,381 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998485847] [2021-12-19 19:16:57,381 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998485847] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,381 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,382 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,382 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699254439] [2021-12-19 19:16:57,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,382 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,382 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,383 INFO L87 Difference]: Start difference. First operand 2018 states and 2980 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,410 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2021-12-19 19:16:57,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2979 transitions. [2021-12-19 19:16:57,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2979 transitions. [2021-12-19 19:16:57,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:57,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:57,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2979 transitions. [2021-12-19 19:16:57,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,436 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2021-12-19 19:16:57,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2979 transitions. [2021-12-19 19:16:57,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:57,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2979 transitions. [2021-12-19 19:16:57,487 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2021-12-19 19:16:57,487 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2021-12-19 19:16:57,487 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:16:57,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2979 transitions. [2021-12-19 19:16:57,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,495 INFO L791 eck$LassoCheckResult]: Stem: 37315#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38352#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37807#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37808#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37297#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37298#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37364#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37365#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37803#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37804#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37330#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37149#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37150#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37594#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37595#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37470#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37471#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37120#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37121#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38344#L1279-2 assume !(0 == ~T1_E~0); 36743#L1284-1 assume !(0 == ~T2_E~0); 36744#L1289-1 assume !(0 == ~T3_E~0); 37467#L1294-1 assume !(0 == ~T4_E~0); 37468#L1299-1 assume !(0 == ~T5_E~0); 37479#L1304-1 assume !(0 == ~T6_E~0); 38410#L1309-1 assume !(0 == ~T7_E~0); 38411#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36673#L1319-1 assume !(0 == ~T9_E~0); 36674#L1324-1 assume !(0 == ~T10_E~0); 36846#L1329-1 assume !(0 == ~T11_E~0); 36847#L1334-1 assume !(0 == ~T12_E~0); 38251#L1339-1 assume !(0 == ~T13_E~0); 38332#L1344-1 assume !(0 == ~E_M~0); 38333#L1349-1 assume !(0 == ~E_1~0); 37654#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37655#L1359-1 assume !(0 == ~E_3~0); 38084#L1364-1 assume !(0 == ~E_4~0); 36975#L1369-1 assume !(0 == ~E_5~0); 36976#L1374-1 assume !(0 == ~E_6~0); 37659#L1379-1 assume !(0 == ~E_7~0); 37660#L1384-1 assume !(0 == ~E_8~0); 37737#L1389-1 assume !(0 == ~E_9~0); 38270#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38271#L1399-1 assume !(0 == ~E_11~0); 38374#L1404-1 assume !(0 == ~E_12~0); 37068#L1409-1 assume !(0 == ~E_13~0); 37069#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38366#L628 assume !(1 == ~m_pc~0); 36972#L628-2 is_master_triggered_~__retres1~0#1 := 0; 36971#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37735#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37736#L1591 assume !(0 != activate_threads_~tmp~1#1); 38379#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37523#L647 assume 1 == ~t1_pc~0; 36892#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36893#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37164#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37165#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38319#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38320#L666 assume 1 == ~t2_pc~0; 36740#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36741#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36907#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38336#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 37855#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37856#L685 assume !(1 == ~t3_pc~0); 37961#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37960#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37583#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37584#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37705#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37191#L704 assume 1 == ~t4_pc~0; 37192#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37716#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37717#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38357#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37576#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37577#L723 assume !(1 == ~t5_pc~0); 37699#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37935#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38079#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37834#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 37835#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36957#L742 assume 1 == ~t6_pc~0; 36958#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37106#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37107#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36642#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36643#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37034#L761 assume !(1 == ~t7_pc~0); 37035#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36903#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36904#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37706#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37707#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36667#L780 assume 1 == ~t8_pc~0; 36668#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36943#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36944#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37667#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37668#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37787#L799 assume 1 == ~t9_pc~0; 37899#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36670#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36671#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37799#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 38006#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37817#L818 assume !(1 == ~t10_pc~0); 36451#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36452#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37892#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37821#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37822#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37862#L837 assume 1 == ~t11_pc~0; 37863#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37697#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38100#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37780#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 37781#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37532#L856 assume !(1 == ~t12_pc~0); 37533#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38186#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38187#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38167#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38168#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38347#L875 assume 1 == ~t13_pc~0; 37477#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37109#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37110#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37049#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37050#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37889#L1427 assume !(1 == ~M_E~0); 37873#L1427-2 assume !(1 == ~T1_E~0); 37021#L1432-1 assume !(1 == ~T2_E~0); 37022#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38090#L1442-1 assume !(1 == ~T4_E~0); 38091#L1447-1 assume !(1 == ~T5_E~0); 37946#L1452-1 assume !(1 == ~T6_E~0); 36586#L1457-1 assume !(1 == ~T7_E~0); 36587#L1462-1 assume !(1 == ~T8_E~0); 38117#L1467-1 assume !(1 == ~T9_E~0); 38135#L1472-1 assume !(1 == ~T10_E~0); 38136#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37887#L1482-1 assume !(1 == ~T12_E~0); 37888#L1487-1 assume !(1 == ~T13_E~0); 36917#L1492-1 assume !(1 == ~E_M~0); 36918#L1497-1 assume !(1 == ~E_1~0); 37279#L1502-1 assume !(1 == ~E_2~0); 37280#L1507-1 assume !(1 == ~E_3~0); 36795#L1512-1 assume !(1 == ~E_4~0); 36796#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38206#L1522-1 assume !(1 == ~E_6~0); 37520#L1527-1 assume !(1 == ~E_7~0); 37521#L1532-1 assume !(1 == ~E_8~0); 38394#L1537-1 assume !(1 == ~E_9~0); 37723#L1542-1 assume !(1 == ~E_10~0); 37554#L1547-1 assume !(1 == ~E_11~0); 37555#L1552-1 assume !(1 == ~E_12~0); 36490#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36491#L1562-1 assume { :end_inline_reset_delta_events } true; 37097#L1928-2 [2021-12-19 19:16:57,495 INFO L793 eck$LassoCheckResult]: Loop: 37097#L1928-2 assume !false; 37588#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36751#L1254 assume !false; 37338#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36825#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36826#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37023#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38194#L1067 assume !(0 != eval_~tmp~0#1); 37264#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36841#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36842#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37301#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37283#L1284-3 assume !(0 == ~T2_E~0); 37284#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37262#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37263#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37650#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37651#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37160#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37161#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38157#L1324-3 assume !(0 == ~T10_E~0); 36792#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36793#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37560#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37561#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37859#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37141#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37142#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37870#L1364-3 assume !(0 == ~E_4~0); 38392#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38288#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36921#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36922#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37139#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37140#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37430#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38298#L1404-3 assume !(0 == ~E_12~0); 38262#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38263#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37749#L628-45 assume 1 == ~m_pc~0; 37427#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37429#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36786#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36787#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37175#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37898#L647-45 assume 1 == ~t1_pc~0; 36737#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36738#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37666#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36851#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36852#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37063#L666-45 assume !(1 == ~t2_pc~0); 37064#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37545#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38107#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38022#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38016#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36601#L685-45 assume 1 == ~t3_pc~0; 36602#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37661#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38335#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38204#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38205#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38345#L704-45 assume 1 == ~t4_pc~0; 38224#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36468#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37327#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37670#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38417#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37782#L723-45 assume !(1 == ~t5_pc~0); 37783#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38272#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37374#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37151#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37152#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38176#L742-45 assume 1 == ~t6_pc~0; 38177#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37399#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37868#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37904#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37905#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37993#L761-45 assume !(1 == ~t7_pc~0); 37994#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37392#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37393#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36799#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36800#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38266#L780-45 assume 1 == ~t8_pc~0; 37177#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36811#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36812#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38393#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36781#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36782#L799-45 assume 1 == ~t9_pc~0; 37558#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37003#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38318#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37947#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37948#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36719#L818-45 assume 1 == ~t10_pc~0; 36720#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36838#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37921#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37325#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37326#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38041#L837-45 assume !(1 == ~t11_pc~0); 37256#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37257#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37394#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38059#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36857#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36858#L856-45 assume 1 == ~t12_pc~0; 38343#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36860#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36801#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36802#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37664#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37665#L875-45 assume 1 == ~t13_pc~0; 37635#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37636#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37698#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38310#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38311#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38250#L1427-3 assume !(1 == ~M_E~0); 37461#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37462#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38000#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37652#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37653#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36509#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36510#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38192#L1462-3 assume !(1 == ~T8_E~0); 38193#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38056#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38057#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36760#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36761#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 36902#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37075#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37076#L1502-3 assume !(1 == ~E_2~0); 38024#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38155#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37113#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36805#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36806#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36770#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36771#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37871#L1542-3 assume !(1 == ~E_10~0); 38009#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37638#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37639#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 36981#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36982#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36401#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37166#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37167#L1947 assume !(0 == start_simulation_~tmp~3#1); 37772#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37977#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37038#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38370#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 38294#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38124#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37883#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37884#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37097#L1928-2 [2021-12-19 19:16:57,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2021-12-19 19:16:57,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449862472] [2021-12-19 19:16:57,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,552 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,552 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449862472] [2021-12-19 19:16:57,552 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449862472] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,552 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55668153] [2021-12-19 19:16:57,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,554 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,554 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 3 times [2021-12-19 19:16:57,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064427415] [2021-12-19 19:16:57,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,555 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,602 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064427415] [2021-12-19 19:16:57,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064427415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,602 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,602 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939572653] [2021-12-19 19:16:57,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,603 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,603 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,604 INFO L87 Difference]: Start difference. First operand 2018 states and 2979 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,631 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2021-12-19 19:16:57,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2978 transitions. [2021-12-19 19:16:57,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2978 transitions. [2021-12-19 19:16:57,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:57,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:57,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2978 transitions. [2021-12-19 19:16:57,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,649 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2021-12-19 19:16:57,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2978 transitions. [2021-12-19 19:16:57,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:57,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2978 transitions. [2021-12-19 19:16:57,682 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2021-12-19 19:16:57,682 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2021-12-19 19:16:57,682 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:16:57,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2978 transitions. [2021-12-19 19:16:57,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,689 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,689 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,689 INFO L791 eck$LassoCheckResult]: Stem: 41358#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42395#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41850#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41851#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41340#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41341#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41407#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41408#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41846#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41847#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41373#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41192#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41637#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41638#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41513#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41514#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41163#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41164#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42387#L1279-2 assume !(0 == ~T1_E~0); 40786#L1284-1 assume !(0 == ~T2_E~0); 40787#L1289-1 assume !(0 == ~T3_E~0); 41510#L1294-1 assume !(0 == ~T4_E~0); 41511#L1299-1 assume !(0 == ~T5_E~0); 41522#L1304-1 assume !(0 == ~T6_E~0); 42453#L1309-1 assume !(0 == ~T7_E~0); 42454#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40716#L1319-1 assume !(0 == ~T9_E~0); 40717#L1324-1 assume !(0 == ~T10_E~0); 40889#L1329-1 assume !(0 == ~T11_E~0); 40890#L1334-1 assume !(0 == ~T12_E~0); 42294#L1339-1 assume !(0 == ~T13_E~0); 42375#L1344-1 assume !(0 == ~E_M~0); 42376#L1349-1 assume !(0 == ~E_1~0); 41697#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41698#L1359-1 assume !(0 == ~E_3~0); 42127#L1364-1 assume !(0 == ~E_4~0); 41018#L1369-1 assume !(0 == ~E_5~0); 41019#L1374-1 assume !(0 == ~E_6~0); 41702#L1379-1 assume !(0 == ~E_7~0); 41703#L1384-1 assume !(0 == ~E_8~0); 41780#L1389-1 assume !(0 == ~E_9~0); 42313#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42314#L1399-1 assume !(0 == ~E_11~0); 42417#L1404-1 assume !(0 == ~E_12~0); 41111#L1409-1 assume !(0 == ~E_13~0); 41112#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42409#L628 assume !(1 == ~m_pc~0); 41015#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41014#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41778#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41779#L1591 assume !(0 != activate_threads_~tmp~1#1); 42422#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41566#L647 assume 1 == ~t1_pc~0; 40935#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40936#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41207#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41208#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42362#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42363#L666 assume 1 == ~t2_pc~0; 40783#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40784#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40950#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42379#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 41898#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41899#L685 assume !(1 == ~t3_pc~0); 42004#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42003#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41626#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41627#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41748#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41234#L704 assume 1 == ~t4_pc~0; 41235#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41759#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41760#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42400#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41619#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41620#L723 assume !(1 == ~t5_pc~0); 41742#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41978#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42122#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41877#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 41878#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41000#L742 assume 1 == ~t6_pc~0; 41001#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41149#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41150#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40685#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40686#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41077#L761 assume !(1 == ~t7_pc~0); 41078#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40946#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40947#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41749#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 41750#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40710#L780 assume 1 == ~t8_pc~0; 40711#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40986#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40987#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41710#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 41711#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41830#L799 assume 1 == ~t9_pc~0; 41942#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40713#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40714#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41842#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42049#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41860#L818 assume !(1 == ~t10_pc~0); 40494#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40495#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41935#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41864#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41865#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41905#L837 assume 1 == ~t11_pc~0; 41906#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41740#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42143#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41823#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 41824#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41575#L856 assume !(1 == ~t12_pc~0); 41576#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42229#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42230#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42210#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42211#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42390#L875 assume 1 == ~t13_pc~0; 41520#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41152#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41153#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41092#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41093#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41932#L1427 assume !(1 == ~M_E~0); 41916#L1427-2 assume !(1 == ~T1_E~0); 41064#L1432-1 assume !(1 == ~T2_E~0); 41065#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42133#L1442-1 assume !(1 == ~T4_E~0); 42134#L1447-1 assume !(1 == ~T5_E~0); 41989#L1452-1 assume !(1 == ~T6_E~0); 40629#L1457-1 assume !(1 == ~T7_E~0); 40630#L1462-1 assume !(1 == ~T8_E~0); 42160#L1467-1 assume !(1 == ~T9_E~0); 42178#L1472-1 assume !(1 == ~T10_E~0); 42179#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41930#L1482-1 assume !(1 == ~T12_E~0); 41931#L1487-1 assume !(1 == ~T13_E~0); 40960#L1492-1 assume !(1 == ~E_M~0); 40961#L1497-1 assume !(1 == ~E_1~0); 41322#L1502-1 assume !(1 == ~E_2~0); 41323#L1507-1 assume !(1 == ~E_3~0); 40838#L1512-1 assume !(1 == ~E_4~0); 40839#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42249#L1522-1 assume !(1 == ~E_6~0); 41563#L1527-1 assume !(1 == ~E_7~0); 41564#L1532-1 assume !(1 == ~E_8~0); 42437#L1537-1 assume !(1 == ~E_9~0); 41766#L1542-1 assume !(1 == ~E_10~0); 41597#L1547-1 assume !(1 == ~E_11~0); 41598#L1552-1 assume !(1 == ~E_12~0); 40533#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40534#L1562-1 assume { :end_inline_reset_delta_events } true; 41140#L1928-2 [2021-12-19 19:16:57,689 INFO L793 eck$LassoCheckResult]: Loop: 41140#L1928-2 assume !false; 41631#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40794#L1254 assume !false; 41381#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40868#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40869#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41066#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42237#L1067 assume !(0 != eval_~tmp~0#1); 41307#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40884#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40885#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41344#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41326#L1284-3 assume !(0 == ~T2_E~0); 41327#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41305#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41306#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41693#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41694#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41203#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41204#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42200#L1324-3 assume !(0 == ~T10_E~0); 40835#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40836#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41603#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41604#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41902#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41913#L1364-3 assume !(0 == ~E_4~0); 42435#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42331#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40964#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40965#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41473#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42341#L1404-3 assume !(0 == ~E_12~0); 42305#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42306#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41792#L628-45 assume 1 == ~m_pc~0; 41470#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41472#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40829#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40830#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41218#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41941#L647-45 assume 1 == ~t1_pc~0; 40780#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40781#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41709#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40894#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40895#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41106#L666-45 assume !(1 == ~t2_pc~0); 41107#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41588#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42150#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42065#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42059#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40644#L685-45 assume 1 == ~t3_pc~0; 40645#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41704#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42378#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42247#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42248#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42388#L704-45 assume 1 == ~t4_pc~0; 42267#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40511#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41370#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41713#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42460#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41825#L723-45 assume !(1 == ~t5_pc~0); 41826#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42315#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41417#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41194#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41195#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42219#L742-45 assume !(1 == ~t6_pc~0); 41441#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 41442#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41911#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41947#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41948#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42036#L761-45 assume !(1 == ~t7_pc~0); 42037#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 41435#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41436#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40842#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40843#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42309#L780-45 assume 1 == ~t8_pc~0; 41220#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40854#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40855#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42436#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40824#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40825#L799-45 assume 1 == ~t9_pc~0; 41601#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41046#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42361#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41990#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41991#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40762#L818-45 assume 1 == ~t10_pc~0; 40763#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40881#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41964#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41368#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41369#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42084#L837-45 assume !(1 == ~t11_pc~0); 41299#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41300#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41437#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42102#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40900#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40901#L856-45 assume 1 == ~t12_pc~0; 42386#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40903#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40844#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40845#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41707#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41708#L875-45 assume !(1 == ~t13_pc~0); 41680#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 41679#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41741#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42353#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42354#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42293#L1427-3 assume !(1 == ~M_E~0); 41504#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41505#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42043#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41695#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41696#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40552#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40553#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42235#L1462-3 assume !(1 == ~T8_E~0); 42236#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42099#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42100#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40803#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40804#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 40945#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41118#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41119#L1502-3 assume !(1 == ~E_2~0); 42067#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42198#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41156#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40848#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40849#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40813#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40814#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41914#L1542-3 assume !(1 == ~E_10~0); 42052#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41681#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41682#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41024#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41025#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40444#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41209#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41210#L1947 assume !(0 == start_simulation_~tmp~3#1); 41815#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42020#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41081#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42413#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 42337#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42167#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41926#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41927#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41140#L1928-2 [2021-12-19 19:16:57,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,690 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2021-12-19 19:16:57,690 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400841985] [2021-12-19 19:16:57,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,690 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400841985] [2021-12-19 19:16:57,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400841985] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,728 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135753465] [2021-12-19 19:16:57,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,729 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1537163566, now seen corresponding path program 1 times [2021-12-19 19:16:57,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116670259] [2021-12-19 19:16:57,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,775 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116670259] [2021-12-19 19:16:57,775 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116670259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,775 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,775 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,775 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792513492] [2021-12-19 19:16:57,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,776 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,776 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,777 INFO L87 Difference]: Start difference. First operand 2018 states and 2978 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,804 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2021-12-19 19:16:57,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2977 transitions. [2021-12-19 19:16:57,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2977 transitions. [2021-12-19 19:16:57,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:57,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:57,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2977 transitions. [2021-12-19 19:16:57,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,822 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2021-12-19 19:16:57,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2977 transitions. [2021-12-19 19:16:57,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:57,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2977 transitions. [2021-12-19 19:16:57,855 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2021-12-19 19:16:57,855 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2021-12-19 19:16:57,855 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:16:57,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2977 transitions. [2021-12-19 19:16:57,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:57,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,863 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,864 INFO L791 eck$LassoCheckResult]: Stem: 45401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46438#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45893#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45894#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45383#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45384#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45450#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45451#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45889#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45890#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45416#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45235#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45236#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45680#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45681#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45556#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45557#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45206#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45207#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46430#L1279-2 assume !(0 == ~T1_E~0); 44829#L1284-1 assume !(0 == ~T2_E~0); 44830#L1289-1 assume !(0 == ~T3_E~0); 45553#L1294-1 assume !(0 == ~T4_E~0); 45554#L1299-1 assume !(0 == ~T5_E~0); 45565#L1304-1 assume !(0 == ~T6_E~0); 46496#L1309-1 assume !(0 == ~T7_E~0); 46497#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44759#L1319-1 assume !(0 == ~T9_E~0); 44760#L1324-1 assume !(0 == ~T10_E~0); 44932#L1329-1 assume !(0 == ~T11_E~0); 44933#L1334-1 assume !(0 == ~T12_E~0); 46337#L1339-1 assume !(0 == ~T13_E~0); 46418#L1344-1 assume !(0 == ~E_M~0); 46419#L1349-1 assume !(0 == ~E_1~0); 45740#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45741#L1359-1 assume !(0 == ~E_3~0); 46170#L1364-1 assume !(0 == ~E_4~0); 45061#L1369-1 assume !(0 == ~E_5~0); 45062#L1374-1 assume !(0 == ~E_6~0); 45745#L1379-1 assume !(0 == ~E_7~0); 45746#L1384-1 assume !(0 == ~E_8~0); 45823#L1389-1 assume !(0 == ~E_9~0); 46356#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46357#L1399-1 assume !(0 == ~E_11~0); 46460#L1404-1 assume !(0 == ~E_12~0); 45154#L1409-1 assume !(0 == ~E_13~0); 45155#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46452#L628 assume !(1 == ~m_pc~0); 45058#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45057#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45821#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45822#L1591 assume !(0 != activate_threads_~tmp~1#1); 46465#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45609#L647 assume 1 == ~t1_pc~0; 44978#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44979#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45250#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45251#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46405#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46406#L666 assume 1 == ~t2_pc~0; 44826#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44827#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44993#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46422#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 45941#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45942#L685 assume !(1 == ~t3_pc~0); 46047#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46046#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45669#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45670#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45791#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45277#L704 assume 1 == ~t4_pc~0; 45278#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45802#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45803#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46443#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45662#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45663#L723 assume !(1 == ~t5_pc~0); 45785#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46021#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46165#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45920#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 45921#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45043#L742 assume 1 == ~t6_pc~0; 45044#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45192#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45193#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44728#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 44729#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45120#L761 assume !(1 == ~t7_pc~0); 45121#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44989#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44990#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45792#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 45793#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44753#L780 assume 1 == ~t8_pc~0; 44754#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45029#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45030#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45753#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 45754#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45873#L799 assume 1 == ~t9_pc~0; 45985#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44756#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44757#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45885#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46092#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45903#L818 assume !(1 == ~t10_pc~0); 44537#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44538#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45978#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45907#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45908#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45948#L837 assume 1 == ~t11_pc~0; 45949#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45783#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46186#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45866#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 45867#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45618#L856 assume !(1 == ~t12_pc~0); 45619#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46272#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46273#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46253#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46254#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46433#L875 assume 1 == ~t13_pc~0; 45563#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45195#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45196#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45135#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45136#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45975#L1427 assume !(1 == ~M_E~0); 45959#L1427-2 assume !(1 == ~T1_E~0); 45107#L1432-1 assume !(1 == ~T2_E~0); 45108#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46176#L1442-1 assume !(1 == ~T4_E~0); 46177#L1447-1 assume !(1 == ~T5_E~0); 46032#L1452-1 assume !(1 == ~T6_E~0); 44672#L1457-1 assume !(1 == ~T7_E~0); 44673#L1462-1 assume !(1 == ~T8_E~0); 46203#L1467-1 assume !(1 == ~T9_E~0); 46221#L1472-1 assume !(1 == ~T10_E~0); 46222#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45973#L1482-1 assume !(1 == ~T12_E~0); 45974#L1487-1 assume !(1 == ~T13_E~0); 45003#L1492-1 assume !(1 == ~E_M~0); 45004#L1497-1 assume !(1 == ~E_1~0); 45365#L1502-1 assume !(1 == ~E_2~0); 45366#L1507-1 assume !(1 == ~E_3~0); 44881#L1512-1 assume !(1 == ~E_4~0); 44882#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46292#L1522-1 assume !(1 == ~E_6~0); 45606#L1527-1 assume !(1 == ~E_7~0); 45607#L1532-1 assume !(1 == ~E_8~0); 46480#L1537-1 assume !(1 == ~E_9~0); 45809#L1542-1 assume !(1 == ~E_10~0); 45640#L1547-1 assume !(1 == ~E_11~0); 45641#L1552-1 assume !(1 == ~E_12~0); 44576#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44577#L1562-1 assume { :end_inline_reset_delta_events } true; 45183#L1928-2 [2021-12-19 19:16:57,864 INFO L793 eck$LassoCheckResult]: Loop: 45183#L1928-2 assume !false; 45674#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44837#L1254 assume !false; 45424#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44911#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44912#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45109#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46280#L1067 assume !(0 != eval_~tmp~0#1); 45350#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44927#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44928#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45387#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45369#L1284-3 assume !(0 == ~T2_E~0); 45370#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45348#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45349#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45736#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45737#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45246#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45247#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46243#L1324-3 assume !(0 == ~T10_E~0); 44878#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44879#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45646#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45647#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45945#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45227#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45228#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45956#L1364-3 assume !(0 == ~E_4~0); 46478#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46374#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45007#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45008#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45225#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45226#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45516#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46384#L1404-3 assume !(0 == ~E_12~0); 46348#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46349#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45835#L628-45 assume 1 == ~m_pc~0; 45513#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45515#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44872#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44873#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45261#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45984#L647-45 assume 1 == ~t1_pc~0; 44823#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44824#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45752#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44937#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44938#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45149#L666-45 assume !(1 == ~t2_pc~0); 45150#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45631#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46193#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46108#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46102#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44687#L685-45 assume 1 == ~t3_pc~0; 44688#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45747#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46421#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46290#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46291#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46431#L704-45 assume 1 == ~t4_pc~0; 46310#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44554#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45413#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45756#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46503#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45868#L723-45 assume !(1 == ~t5_pc~0); 45869#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46358#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45460#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45237#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45238#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46262#L742-45 assume 1 == ~t6_pc~0; 46263#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45485#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45954#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45990#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45991#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46079#L761-45 assume !(1 == ~t7_pc~0); 46080#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45478#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45479#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44885#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44886#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46352#L780-45 assume !(1 == ~t8_pc~0); 45264#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 44897#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44898#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46479#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44867#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44868#L799-45 assume !(1 == ~t9_pc~0); 45088#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 45089#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46404#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46033#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46034#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44805#L818-45 assume 1 == ~t10_pc~0; 44806#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44924#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46007#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45411#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45412#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46127#L837-45 assume 1 == ~t11_pc~0; 46416#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45343#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45480#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46145#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44943#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44944#L856-45 assume !(1 == ~t12_pc~0); 44945#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 44946#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44887#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44888#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45750#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45751#L875-45 assume 1 == ~t13_pc~0; 45721#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45722#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45784#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46396#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46397#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46336#L1427-3 assume !(1 == ~M_E~0); 45547#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45548#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46086#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45738#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45739#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44595#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44596#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46278#L1462-3 assume !(1 == ~T8_E~0); 46279#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46142#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46143#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44846#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44847#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 44988#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45161#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45162#L1502-3 assume !(1 == ~E_2~0); 46110#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46241#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45199#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44891#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44892#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44856#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44857#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45957#L1542-3 assume !(1 == ~E_10~0); 46095#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45724#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45725#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45067#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45068#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44487#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45252#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45253#L1947 assume !(0 == start_simulation_~tmp~3#1); 45858#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46063#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45124#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46456#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 46380#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46210#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45969#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45970#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45183#L1928-2 [2021-12-19 19:16:57,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2021-12-19 19:16:57,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591186382] [2021-12-19 19:16:57,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,896 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591186382] [2021-12-19 19:16:57,896 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591186382] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981022898] [2021-12-19 19:16:57,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,900 INFO L85 PathProgramCache]: Analyzing trace with hash 1777204334, now seen corresponding path program 1 times [2021-12-19 19:16:57,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877426365] [2021-12-19 19:16:57,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877426365] [2021-12-19 19:16:57,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877426365] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,975 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919532363] [2021-12-19 19:16:57,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,976 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,977 INFO L87 Difference]: Start difference. First operand 2018 states and 2977 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,008 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2021-12-19 19:16:58,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:58,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2976 transitions. [2021-12-19 19:16:58,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:58,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2976 transitions. [2021-12-19 19:16:58,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:58,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:58,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2976 transitions. [2021-12-19 19:16:58,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,027 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2021-12-19 19:16:58,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2976 transitions. [2021-12-19 19:16:58,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:58,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2976 transitions. [2021-12-19 19:16:58,059 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2021-12-19 19:16:58,059 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2021-12-19 19:16:58,060 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:16:58,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2976 transitions. [2021-12-19 19:16:58,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:58,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,067 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,068 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,068 INFO L791 eck$LassoCheckResult]: Stem: 49444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50481#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49936#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49937#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49426#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49427#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49493#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49494#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49932#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49933#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49459#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49278#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49279#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49723#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49724#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49599#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49600#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49249#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49250#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50473#L1279-2 assume !(0 == ~T1_E~0); 48872#L1284-1 assume !(0 == ~T2_E~0); 48873#L1289-1 assume !(0 == ~T3_E~0); 49596#L1294-1 assume !(0 == ~T4_E~0); 49597#L1299-1 assume !(0 == ~T5_E~0); 49608#L1304-1 assume !(0 == ~T6_E~0); 50539#L1309-1 assume !(0 == ~T7_E~0); 50540#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48802#L1319-1 assume !(0 == ~T9_E~0); 48803#L1324-1 assume !(0 == ~T10_E~0); 48975#L1329-1 assume !(0 == ~T11_E~0); 48976#L1334-1 assume !(0 == ~T12_E~0); 50380#L1339-1 assume !(0 == ~T13_E~0); 50461#L1344-1 assume !(0 == ~E_M~0); 50462#L1349-1 assume !(0 == ~E_1~0); 49783#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49784#L1359-1 assume !(0 == ~E_3~0); 50213#L1364-1 assume !(0 == ~E_4~0); 49104#L1369-1 assume !(0 == ~E_5~0); 49105#L1374-1 assume !(0 == ~E_6~0); 49788#L1379-1 assume !(0 == ~E_7~0); 49789#L1384-1 assume !(0 == ~E_8~0); 49866#L1389-1 assume !(0 == ~E_9~0); 50399#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50400#L1399-1 assume !(0 == ~E_11~0); 50503#L1404-1 assume !(0 == ~E_12~0); 49197#L1409-1 assume !(0 == ~E_13~0); 49198#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50495#L628 assume !(1 == ~m_pc~0); 49101#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49100#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49864#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49865#L1591 assume !(0 != activate_threads_~tmp~1#1); 50508#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49652#L647 assume 1 == ~t1_pc~0; 49021#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49022#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49293#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49294#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50448#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50449#L666 assume 1 == ~t2_pc~0; 48869#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48870#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49036#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50465#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 49984#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49985#L685 assume !(1 == ~t3_pc~0); 50090#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50089#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49712#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49713#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49834#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49320#L704 assume 1 == ~t4_pc~0; 49321#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49845#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49846#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50486#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 49705#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49706#L723 assume !(1 == ~t5_pc~0); 49828#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50064#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50208#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49963#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 49964#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49086#L742 assume 1 == ~t6_pc~0; 49087#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49235#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49236#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48771#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 48772#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49163#L761 assume !(1 == ~t7_pc~0); 49164#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49032#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49033#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49835#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 49836#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48796#L780 assume 1 == ~t8_pc~0; 48797#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49072#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49073#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49796#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 49797#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49916#L799 assume 1 == ~t9_pc~0; 50028#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48799#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48800#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49928#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50135#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49946#L818 assume !(1 == ~t10_pc~0); 48580#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48581#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50021#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49950#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49951#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49991#L837 assume 1 == ~t11_pc~0; 49992#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49826#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50229#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49909#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 49910#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49661#L856 assume !(1 == ~t12_pc~0); 49662#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50315#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50316#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50296#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50297#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50476#L875 assume 1 == ~t13_pc~0; 49606#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49238#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49239#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49178#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49179#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50018#L1427 assume !(1 == ~M_E~0); 50002#L1427-2 assume !(1 == ~T1_E~0); 49150#L1432-1 assume !(1 == ~T2_E~0); 49151#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50219#L1442-1 assume !(1 == ~T4_E~0); 50220#L1447-1 assume !(1 == ~T5_E~0); 50075#L1452-1 assume !(1 == ~T6_E~0); 48715#L1457-1 assume !(1 == ~T7_E~0); 48716#L1462-1 assume !(1 == ~T8_E~0); 50246#L1467-1 assume !(1 == ~T9_E~0); 50264#L1472-1 assume !(1 == ~T10_E~0); 50265#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50016#L1482-1 assume !(1 == ~T12_E~0); 50017#L1487-1 assume !(1 == ~T13_E~0); 49046#L1492-1 assume !(1 == ~E_M~0); 49047#L1497-1 assume !(1 == ~E_1~0); 49408#L1502-1 assume !(1 == ~E_2~0); 49409#L1507-1 assume !(1 == ~E_3~0); 48924#L1512-1 assume !(1 == ~E_4~0); 48925#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50335#L1522-1 assume !(1 == ~E_6~0); 49649#L1527-1 assume !(1 == ~E_7~0); 49650#L1532-1 assume !(1 == ~E_8~0); 50523#L1537-1 assume !(1 == ~E_9~0); 49852#L1542-1 assume !(1 == ~E_10~0); 49683#L1547-1 assume !(1 == ~E_11~0); 49684#L1552-1 assume !(1 == ~E_12~0); 48619#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48620#L1562-1 assume { :end_inline_reset_delta_events } true; 49226#L1928-2 [2021-12-19 19:16:58,069 INFO L793 eck$LassoCheckResult]: Loop: 49226#L1928-2 assume !false; 49717#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48880#L1254 assume !false; 49467#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48954#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48955#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49152#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50323#L1067 assume !(0 != eval_~tmp~0#1); 49393#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48970#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48971#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49430#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49412#L1284-3 assume !(0 == ~T2_E~0); 49413#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49391#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49392#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49779#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49780#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49289#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49290#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50286#L1324-3 assume !(0 == ~T10_E~0); 48921#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48922#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49689#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49690#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49988#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49270#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49271#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49999#L1364-3 assume !(0 == ~E_4~0); 50521#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50417#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49050#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49051#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49268#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49269#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49559#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50427#L1404-3 assume !(0 == ~E_12~0); 50391#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50392#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49878#L628-45 assume 1 == ~m_pc~0; 49556#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49558#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48915#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48916#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49304#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50027#L647-45 assume 1 == ~t1_pc~0; 48866#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48867#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49795#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48980#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48981#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49192#L666-45 assume !(1 == ~t2_pc~0); 49193#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49674#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50236#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50151#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50145#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48730#L685-45 assume 1 == ~t3_pc~0; 48731#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49790#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50464#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50333#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50334#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50474#L704-45 assume 1 == ~t4_pc~0; 50353#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48597#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49456#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49799#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50546#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49911#L723-45 assume !(1 == ~t5_pc~0); 49912#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50401#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49503#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49280#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49281#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50305#L742-45 assume 1 == ~t6_pc~0; 50306#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49528#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49997#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50033#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50034#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50122#L761-45 assume !(1 == ~t7_pc~0); 50123#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49521#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49522#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48928#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48929#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50395#L780-45 assume 1 == ~t8_pc~0; 49306#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48940#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48941#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50522#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48910#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48911#L799-45 assume 1 == ~t9_pc~0; 49687#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49132#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50447#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50076#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50077#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48848#L818-45 assume 1 == ~t10_pc~0; 48849#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48967#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50050#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49454#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49455#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50170#L837-45 assume !(1 == ~t11_pc~0); 49385#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49386#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49523#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50188#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48986#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48987#L856-45 assume 1 == ~t12_pc~0; 50472#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48989#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48930#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48931#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49793#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49794#L875-45 assume 1 == ~t13_pc~0; 49764#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49765#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49827#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50439#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50440#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50379#L1427-3 assume !(1 == ~M_E~0); 49590#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49591#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50129#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49781#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49782#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48638#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48639#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50321#L1462-3 assume !(1 == ~T8_E~0); 50322#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50185#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50186#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48889#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48890#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49031#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49204#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49205#L1502-3 assume !(1 == ~E_2~0); 50153#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50284#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49242#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48934#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48935#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48899#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48900#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50000#L1542-3 assume !(1 == ~E_10~0); 50138#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49767#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49768#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49110#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49111#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48530#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49295#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 49296#L1947 assume !(0 == start_simulation_~tmp~3#1); 49901#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50106#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49167#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50499#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 50423#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50253#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50012#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50013#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49226#L1928-2 [2021-12-19 19:16:58,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,069 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2021-12-19 19:16:58,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184321346] [2021-12-19 19:16:58,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,070 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,099 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184321346] [2021-12-19 19:16:58,099 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184321346] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,100 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593963981] [2021-12-19 19:16:58,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,100 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,101 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 4 times [2021-12-19 19:16:58,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323076043] [2021-12-19 19:16:58,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323076043] [2021-12-19 19:16:58,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323076043] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266088890] [2021-12-19 19:16:58,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,138 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,139 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:58,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:58,139 INFO L87 Difference]: Start difference. First operand 2018 states and 2976 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,168 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2021-12-19 19:16:58,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:58,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2975 transitions. [2021-12-19 19:16:58,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:58,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2975 transitions. [2021-12-19 19:16:58,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2021-12-19 19:16:58,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2021-12-19 19:16:58,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2975 transitions. [2021-12-19 19:16:58,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,187 INFO L681 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2021-12-19 19:16:58,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2975 transitions. [2021-12-19 19:16:58,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2021-12-19 19:16:58,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2975 transitions. [2021-12-19 19:16:58,223 INFO L704 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2021-12-19 19:16:58,224 INFO L587 BuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2021-12-19 19:16:58,224 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:16:58,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2975 transitions. [2021-12-19 19:16:58,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2021-12-19 19:16:58,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,234 INFO L791 eck$LassoCheckResult]: Stem: 53487#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54524#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53979#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53980#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53469#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53470#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53536#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53537#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53975#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53976#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53502#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53321#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53322#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53766#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53767#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53642#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53643#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53292#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53293#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54516#L1279-2 assume !(0 == ~T1_E~0); 52915#L1284-1 assume !(0 == ~T2_E~0); 52916#L1289-1 assume !(0 == ~T3_E~0); 53639#L1294-1 assume !(0 == ~T4_E~0); 53640#L1299-1 assume !(0 == ~T5_E~0); 53651#L1304-1 assume !(0 == ~T6_E~0); 54582#L1309-1 assume !(0 == ~T7_E~0); 54583#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52845#L1319-1 assume !(0 == ~T9_E~0); 52846#L1324-1 assume !(0 == ~T10_E~0); 53018#L1329-1 assume !(0 == ~T11_E~0); 53019#L1334-1 assume !(0 == ~T12_E~0); 54423#L1339-1 assume !(0 == ~T13_E~0); 54504#L1344-1 assume !(0 == ~E_M~0); 54505#L1349-1 assume !(0 == ~E_1~0); 53826#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53827#L1359-1 assume !(0 == ~E_3~0); 54256#L1364-1 assume !(0 == ~E_4~0); 53147#L1369-1 assume !(0 == ~E_5~0); 53148#L1374-1 assume !(0 == ~E_6~0); 53831#L1379-1 assume !(0 == ~E_7~0); 53832#L1384-1 assume !(0 == ~E_8~0); 53909#L1389-1 assume !(0 == ~E_9~0); 54442#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54443#L1399-1 assume !(0 == ~E_11~0); 54546#L1404-1 assume !(0 == ~E_12~0); 53240#L1409-1 assume !(0 == ~E_13~0); 53241#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54538#L628 assume !(1 == ~m_pc~0); 53144#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53143#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53907#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53908#L1591 assume !(0 != activate_threads_~tmp~1#1); 54551#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53695#L647 assume 1 == ~t1_pc~0; 53064#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53065#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53336#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53337#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54491#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54492#L666 assume 1 == ~t2_pc~0; 52912#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52913#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53079#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54508#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54027#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54028#L685 assume !(1 == ~t3_pc~0); 54133#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54132#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53755#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53756#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53877#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53363#L704 assume 1 == ~t4_pc~0; 53364#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53888#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53889#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54529#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 53748#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53749#L723 assume !(1 == ~t5_pc~0); 53871#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54107#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54251#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54006#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54007#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53129#L742 assume 1 == ~t6_pc~0; 53130#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53278#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53279#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52814#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 52815#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53206#L761 assume !(1 == ~t7_pc~0); 53207#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53075#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53076#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53878#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 53879#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52839#L780 assume 1 == ~t8_pc~0; 52840#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53115#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53116#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53839#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 53840#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53959#L799 assume 1 == ~t9_pc~0; 54071#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52842#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52843#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53971#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54178#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53989#L818 assume !(1 == ~t10_pc~0); 52623#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52624#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54064#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53993#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53994#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54034#L837 assume 1 == ~t11_pc~0; 54035#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53869#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54272#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53952#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 53953#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53704#L856 assume !(1 == ~t12_pc~0); 53705#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54358#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54359#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54339#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54340#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54519#L875 assume 1 == ~t13_pc~0; 53649#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53281#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53282#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53221#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53222#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54061#L1427 assume !(1 == ~M_E~0); 54045#L1427-2 assume !(1 == ~T1_E~0); 53193#L1432-1 assume !(1 == ~T2_E~0); 53194#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54262#L1442-1 assume !(1 == ~T4_E~0); 54263#L1447-1 assume !(1 == ~T5_E~0); 54118#L1452-1 assume !(1 == ~T6_E~0); 52758#L1457-1 assume !(1 == ~T7_E~0); 52759#L1462-1 assume !(1 == ~T8_E~0); 54289#L1467-1 assume !(1 == ~T9_E~0); 54307#L1472-1 assume !(1 == ~T10_E~0); 54308#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54059#L1482-1 assume !(1 == ~T12_E~0); 54060#L1487-1 assume !(1 == ~T13_E~0); 53089#L1492-1 assume !(1 == ~E_M~0); 53090#L1497-1 assume !(1 == ~E_1~0); 53451#L1502-1 assume !(1 == ~E_2~0); 53452#L1507-1 assume !(1 == ~E_3~0); 52967#L1512-1 assume !(1 == ~E_4~0); 52968#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54378#L1522-1 assume !(1 == ~E_6~0); 53692#L1527-1 assume !(1 == ~E_7~0); 53693#L1532-1 assume !(1 == ~E_8~0); 54566#L1537-1 assume !(1 == ~E_9~0); 53895#L1542-1 assume !(1 == ~E_10~0); 53726#L1547-1 assume !(1 == ~E_11~0); 53727#L1552-1 assume !(1 == ~E_12~0); 52662#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 52663#L1562-1 assume { :end_inline_reset_delta_events } true; 53269#L1928-2 [2021-12-19 19:16:58,234 INFO L793 eck$LassoCheckResult]: Loop: 53269#L1928-2 assume !false; 53760#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52923#L1254 assume !false; 53510#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52997#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52998#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53195#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54366#L1067 assume !(0 != eval_~tmp~0#1); 53436#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53013#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53014#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53473#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53455#L1284-3 assume !(0 == ~T2_E~0); 53456#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53434#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53435#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53822#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53823#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53332#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53333#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54329#L1324-3 assume !(0 == ~T10_E~0); 52964#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52965#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53732#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53733#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54031#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53313#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53314#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54042#L1364-3 assume !(0 == ~E_4~0); 54564#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54460#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53093#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53094#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53311#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53312#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53602#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54470#L1404-3 assume !(0 == ~E_12~0); 54434#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54435#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53921#L628-45 assume !(1 == ~m_pc~0); 53600#L628-47 is_master_triggered_~__retres1~0#1 := 0; 53601#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52958#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52959#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53347#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54070#L647-45 assume 1 == ~t1_pc~0; 52909#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52910#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53838#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53023#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53024#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53235#L666-45 assume !(1 == ~t2_pc~0); 53236#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53717#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54279#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54194#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54188#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52773#L685-45 assume 1 == ~t3_pc~0; 52774#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53833#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54507#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54376#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54377#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54517#L704-45 assume 1 == ~t4_pc~0; 54396#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52640#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53499#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53842#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54589#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53954#L723-45 assume !(1 == ~t5_pc~0); 53955#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54444#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53546#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53323#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53324#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54348#L742-45 assume !(1 == ~t6_pc~0); 53570#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 53571#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54040#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54076#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54077#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54165#L761-45 assume !(1 == ~t7_pc~0); 54166#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53564#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53565#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52971#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52972#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54438#L780-45 assume 1 == ~t8_pc~0; 53349#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52983#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52984#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54565#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52953#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52954#L799-45 assume 1 == ~t9_pc~0; 53730#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53175#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54490#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54119#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54120#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52891#L818-45 assume 1 == ~t10_pc~0; 52892#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53010#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54093#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53497#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53498#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54213#L837-45 assume !(1 == ~t11_pc~0); 53428#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53429#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53566#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54231#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53029#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53030#L856-45 assume 1 == ~t12_pc~0; 54515#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53032#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52973#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52974#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53836#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53837#L875-45 assume !(1 == ~t13_pc~0); 53809#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 53808#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53870#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54482#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54483#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54422#L1427-3 assume !(1 == ~M_E~0); 53633#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53634#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54172#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53824#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53825#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52681#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52682#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54364#L1462-3 assume !(1 == ~T8_E~0); 54365#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54228#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54229#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52932#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52933#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53074#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53247#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53248#L1502-3 assume !(1 == ~E_2~0); 54196#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54327#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53285#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52977#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52978#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52942#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52943#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54043#L1542-3 assume !(1 == ~E_10~0); 54181#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53810#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53811#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53153#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53154#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52573#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53338#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53339#L1947 assume !(0 == start_simulation_~tmp~3#1); 53944#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54149#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53210#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54542#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 54466#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54296#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54055#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54056#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53269#L1928-2 [2021-12-19 19:16:58,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,235 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2021-12-19 19:16:58,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464466786] [2021-12-19 19:16:58,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464466786] [2021-12-19 19:16:58,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464466786] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:58,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [754109642] [2021-12-19 19:16:58,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,272 INFO L85 PathProgramCache]: Analyzing trace with hash -242294545, now seen corresponding path program 1 times [2021-12-19 19:16:58,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600852069] [2021-12-19 19:16:58,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600852069] [2021-12-19 19:16:58,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600852069] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,309 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,309 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482668896] [2021-12-19 19:16:58,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,310 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:58,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:58,311 INFO L87 Difference]: Start difference. First operand 2018 states and 2975 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,378 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2021-12-19 19:16:58,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:58,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5528 transitions. [2021-12-19 19:16:58,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2021-12-19 19:16:58,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5528 transitions. [2021-12-19 19:16:58,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2021-12-19 19:16:58,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2021-12-19 19:16:58,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5528 transitions. [2021-12-19 19:16:58,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,413 INFO L681 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2021-12-19 19:16:58,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5528 transitions. [2021-12-19 19:16:58,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2021-12-19 19:16:58,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5528 transitions. [2021-12-19 19:16:58,481 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2021-12-19 19:16:58,481 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2021-12-19 19:16:58,481 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:16:58,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5528 transitions. [2021-12-19 19:16:58,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2021-12-19 19:16:58,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,494 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,494 INFO L791 eck$LassoCheckResult]: Stem: 59274#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59275#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60384#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59775#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59776#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59258#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59259#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59324#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59325#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59773#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59774#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59292#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59108#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59109#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59559#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59560#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59436#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59437#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59079#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59080#L1279 assume !(0 == ~M_E~0); 60372#L1279-2 assume !(0 == ~T1_E~0); 58701#L1284-1 assume !(0 == ~T2_E~0); 58702#L1289-1 assume !(0 == ~T3_E~0); 59428#L1294-1 assume !(0 == ~T4_E~0); 59429#L1299-1 assume !(0 == ~T5_E~0); 59440#L1304-1 assume !(0 == ~T6_E~0); 60481#L1309-1 assume !(0 == ~T7_E~0); 60484#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58631#L1319-1 assume !(0 == ~T9_E~0); 58632#L1324-1 assume !(0 == ~T10_E~0); 58804#L1329-1 assume !(0 == ~T11_E~0); 58805#L1334-1 assume !(0 == ~T12_E~0); 60253#L1339-1 assume !(0 == ~T13_E~0); 60356#L1344-1 assume !(0 == ~E_M~0); 60357#L1349-1 assume !(0 == ~E_1~0); 59620#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 59621#L1359-1 assume !(0 == ~E_3~0); 60060#L1364-1 assume !(0 == ~E_4~0); 58934#L1369-1 assume !(0 == ~E_5~0); 58935#L1374-1 assume !(0 == ~E_6~0); 59626#L1379-1 assume !(0 == ~E_7~0); 59627#L1384-1 assume !(0 == ~E_8~0); 59703#L1389-1 assume !(0 == ~E_9~0); 60278#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60279#L1399-1 assume !(0 == ~E_11~0); 60415#L1404-1 assume !(0 == ~E_12~0); 59027#L1409-1 assume !(0 == ~E_13~0); 59028#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60406#L628 assume !(1 == ~m_pc~0); 58931#L628-2 is_master_triggered_~__retres1~0#1 := 0; 58930#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59701#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59702#L1591 assume !(0 != activate_threads_~tmp~1#1); 60422#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59485#L647 assume 1 == ~t1_pc~0; 58850#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58851#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59123#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59124#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60339#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60340#L666 assume 1 == ~t2_pc~0; 58698#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58699#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58865#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60362#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 59824#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59825#L685 assume !(1 == ~t3_pc~0); 59933#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59932#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59548#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59549#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59671#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59150#L704 assume 1 == ~t4_pc~0; 59151#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59682#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59683#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60390#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59539#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59540#L723 assume !(1 == ~t5_pc~0); 59667#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59905#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60054#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59806#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 59807#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58917#L742 assume 1 == ~t6_pc~0; 58918#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59065#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59066#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58602#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 58603#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58993#L761 assume !(1 == ~t7_pc~0); 58994#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58863#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58864#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59673#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 59674#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58625#L780 assume 1 == ~t8_pc~0; 58626#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58902#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58903#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59633#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 59634#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59755#L799 assume 1 == ~t9_pc~0; 59872#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58628#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58629#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59767#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 59980#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59787#L818 assume !(1 == ~t10_pc~0); 58411#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58412#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59862#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59790#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59791#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59832#L837 assume 1 == ~t11_pc~0; 59833#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59664#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60079#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59748#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 59749#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59496#L856 assume !(1 == ~t12_pc~0); 59497#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60174#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60175#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60156#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60157#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60378#L875 assume 1 == ~t13_pc~0; 59438#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59068#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59069#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59008#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59009#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59859#L1427 assume !(1 == ~M_E~0); 59845#L1427-2 assume !(1 == ~T1_E~0); 58980#L1432-1 assume !(1 == ~T2_E~0); 58981#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60067#L1442-1 assume !(1 == ~T4_E~0); 60068#L1447-1 assume !(1 == ~T5_E~0); 59918#L1452-1 assume !(1 == ~T6_E~0); 58544#L1457-1 assume !(1 == ~T7_E~0); 58545#L1462-1 assume !(1 == ~T8_E~0); 60099#L1467-1 assume !(1 == ~T9_E~0); 60119#L1472-1 assume !(1 == ~T10_E~0); 60120#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59857#L1482-1 assume !(1 == ~T12_E~0); 59858#L1487-1 assume !(1 == ~T13_E~0); 58877#L1492-1 assume !(1 == ~E_M~0); 58878#L1497-1 assume !(1 == ~E_1~0); 59238#L1502-1 assume !(1 == ~E_2~0); 59239#L1507-1 assume !(1 == ~E_3~0); 58753#L1512-1 assume !(1 == ~E_4~0); 58754#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60199#L1522-1 assume !(1 == ~E_6~0); 59482#L1527-1 assume !(1 == ~E_7~0); 59483#L1532-1 assume !(1 == ~E_8~0); 60461#L1537-1 assume !(1 == ~E_9~0); 59689#L1542-1 assume !(1 == ~E_10~0); 59518#L1547-1 assume !(1 == ~E_11~0); 59519#L1552-1 assume !(1 == ~E_12~0); 58448#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58449#L1562-1 assume { :end_inline_reset_delta_events } true; 59056#L1928-2 [2021-12-19 19:16:58,495 INFO L793 eck$LassoCheckResult]: Loop: 59056#L1928-2 assume !false; 59551#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58709#L1254 assume !false; 59298#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58783#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58784#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58982#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60183#L1067 assume !(0 != eval_~tmp~0#1); 59223#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58802#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58803#L1279-3 assume !(0 == ~M_E~0); 60604#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60603#L1284-3 assume !(0 == ~T2_E~0); 60425#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59221#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59222#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59616#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59617#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59119#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59120#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60502#L1324-3 assume !(0 == ~T10_E~0); 60598#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60597#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60596#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 60595#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60594#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60593#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60592#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60591#L1364-3 assume !(0 == ~E_4~0); 60455#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60456#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60590#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60216#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59098#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59099#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59390#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60498#L1404-3 assume !(0 == ~E_12~0); 60268#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60269#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60586#L628-45 assume 1 == ~m_pc~0; 59387#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59389#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60585#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60584#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60427#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59868#L647-45 assume 1 == ~t1_pc~0; 58695#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58696#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59632#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58809#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58810#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60577#L666-45 assume 1 == ~t2_pc~0; 60576#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60436#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60437#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60574#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60573#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60572#L685-45 assume 1 == ~t3_pc~0; 60570#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60360#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60361#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60196#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60197#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60413#L704-45 assume !(1 == ~t4_pc~0); 58425#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 58426#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59287#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59636#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60504#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59750#L723-45 assume !(1 == ~t5_pc~0); 59751#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 60280#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60560#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60559#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 60558#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60164#L742-45 assume 1 == ~t6_pc~0; 60165#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59359#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59838#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59874#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59875#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60552#L761-45 assume 1 == ~t7_pc~0; 60550#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60549#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60548#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60547#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60546#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60272#L780-45 assume 1 == ~t8_pc~0; 60273#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60545#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60544#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60543#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60542#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60541#L799-45 assume !(1 == ~t9_pc~0); 60539#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 60538#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60338#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59916#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59917#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58675#L818-45 assume 1 == ~t10_pc~0; 58676#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58796#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59891#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59284#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59285#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60016#L837-45 assume 1 == ~t11_pc~0; 60528#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60526#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60525#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60524#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60523#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60522#L856-45 assume 1 == ~t12_pc~0; 60369#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58818#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60521#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60520#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60519#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60200#L875-45 assume 1 == ~t13_pc~0; 59601#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59602#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59662#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60479#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60514#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60252#L1427-3 assume !(1 == ~M_E~0); 59421#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59422#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59974#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59618#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59619#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58467#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58468#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60181#L1462-3 assume !(1 == ~T8_E~0); 60182#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60031#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60032#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58718#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58719#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58860#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59034#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59035#L1502-3 assume !(1 == ~E_2~0); 59999#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60142#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59072#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58763#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58764#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58728#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58729#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59841#L1542-3 assume !(1 == ~E_10~0); 59983#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59604#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59605#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58940#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58941#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58359#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59125#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59126#L1947 assume !(0 == start_simulation_~tmp~3#1); 59740#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59947#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60647#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60645#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 60643#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60641#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60640#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 60442#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59056#L1928-2 [2021-12-19 19:16:58,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,495 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2021-12-19 19:16:58,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448111223] [2021-12-19 19:16:58,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448111223] [2021-12-19 19:16:58,552 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448111223] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,552 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433567762] [2021-12-19 19:16:58,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,553 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1659409239, now seen corresponding path program 1 times [2021-12-19 19:16:58,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540566638] [2021-12-19 19:16:58,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540566638] [2021-12-19 19:16:58,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540566638] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,595 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933542885] [2021-12-19 19:16:58,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,595 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,595 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:58,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:58,596 INFO L87 Difference]: Start difference. First operand 3761 states and 5528 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,718 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2021-12-19 19:16:58,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:58,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5496 states and 8063 transitions. [2021-12-19 19:16:58,740 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5301 [2021-12-19 19:16:58,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5496 states to 5496 states and 8063 transitions. [2021-12-19 19:16:58,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5496 [2021-12-19 19:16:58,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5496 [2021-12-19 19:16:58,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5496 states and 8063 transitions. [2021-12-19 19:16:58,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,770 INFO L681 BuchiCegarLoop]: Abstraction has 5496 states and 8063 transitions. [2021-12-19 19:16:58,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5496 states and 8063 transitions. [2021-12-19 19:16:58,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5496 to 3761. [2021-12-19 19:16:58,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5525 transitions. [2021-12-19 19:16:58,841 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2021-12-19 19:16:58,842 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2021-12-19 19:16:58,842 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:16:58,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5525 transitions. [2021-12-19 19:16:58,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2021-12-19 19:16:58,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,854 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,855 INFO L791 eck$LassoCheckResult]: Stem: 68542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69580#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69033#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69034#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 68524#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68525#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68589#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68590#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69031#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69032#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68557#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68374#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68375#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68819#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68820#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68700#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68701#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68345#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68346#L1279 assume !(0 == ~M_E~0); 69571#L1279-2 assume !(0 == ~T1_E~0); 67968#L1284-1 assume !(0 == ~T2_E~0); 67969#L1289-1 assume !(0 == ~T3_E~0); 68692#L1294-1 assume !(0 == ~T4_E~0); 68693#L1299-1 assume !(0 == ~T5_E~0); 68704#L1304-1 assume !(0 == ~T6_E~0); 69641#L1309-1 assume !(0 == ~T7_E~0); 69642#L1314-1 assume !(0 == ~T8_E~0); 67900#L1319-1 assume !(0 == ~T9_E~0); 67901#L1324-1 assume !(0 == ~T10_E~0); 68071#L1329-1 assume !(0 == ~T11_E~0); 68072#L1334-1 assume !(0 == ~T12_E~0); 69477#L1339-1 assume !(0 == ~T13_E~0); 69560#L1344-1 assume !(0 == ~E_M~0); 69561#L1349-1 assume !(0 == ~E_1~0); 68881#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68882#L1359-1 assume !(0 == ~E_3~0); 69310#L1364-1 assume !(0 == ~E_4~0); 68200#L1369-1 assume !(0 == ~E_5~0); 68201#L1374-1 assume !(0 == ~E_6~0); 68887#L1379-1 assume !(0 == ~E_7~0); 68888#L1384-1 assume !(0 == ~E_8~0); 68963#L1389-1 assume !(0 == ~E_9~0); 69496#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69497#L1399-1 assume !(0 == ~E_11~0); 69603#L1404-1 assume !(0 == ~E_12~0); 68293#L1409-1 assume !(0 == ~E_13~0); 68294#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69594#L628 assume !(1 == ~m_pc~0); 68197#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68196#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68961#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68962#L1591 assume !(0 != activate_threads_~tmp~1#1); 69609#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68748#L647 assume 1 == ~t1_pc~0; 68117#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68118#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68389#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68390#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 69546#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69547#L666 assume 1 == ~t2_pc~0; 67965#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67966#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68136#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69563#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69081#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69082#L685 assume !(1 == ~t3_pc~0); 69189#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69188#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68810#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68811#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68931#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68416#L704 assume 1 == ~t4_pc~0; 68417#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68942#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68943#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69585#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 68801#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68802#L723 assume !(1 == ~t5_pc~0); 68927#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69163#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69305#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69063#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69064#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68183#L742 assume 1 == ~t6_pc~0; 68184#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68331#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68332#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67869#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 67870#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68259#L761 assume !(1 == ~t7_pc~0); 68260#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68130#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68131#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68933#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 68934#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67892#L780 assume 1 == ~t8_pc~0; 67893#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68169#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68170#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68894#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 68895#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69016#L799 assume 1 == ~t9_pc~0; 69128#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 67895#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67896#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69025#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69234#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69044#L818 assume !(1 == ~t10_pc~0); 67678#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 67679#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69120#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69047#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69048#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69088#L837 assume 1 == ~t11_pc~0; 69089#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68924#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69326#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69006#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69007#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68762#L856 assume !(1 == ~t12_pc~0); 68763#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69412#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69413#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69394#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69395#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69574#L875 assume 1 == ~t13_pc~0; 68702#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68334#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68335#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68274#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68275#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69115#L1427 assume !(1 == ~M_E~0); 69101#L1427-2 assume !(1 == ~T1_E~0); 68246#L1432-1 assume !(1 == ~T2_E~0); 68247#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69316#L1442-1 assume !(1 == ~T4_E~0); 69317#L1447-1 assume !(1 == ~T5_E~0); 69174#L1452-1 assume !(1 == ~T6_E~0); 67811#L1457-1 assume !(1 == ~T7_E~0); 67812#L1462-1 assume !(1 == ~T8_E~0); 69343#L1467-1 assume !(1 == ~T9_E~0); 69361#L1472-1 assume !(1 == ~T10_E~0); 69362#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69113#L1482-1 assume !(1 == ~T12_E~0); 69114#L1487-1 assume !(1 == ~T13_E~0); 68144#L1492-1 assume !(1 == ~E_M~0); 68145#L1497-1 assume !(1 == ~E_1~0); 68504#L1502-1 assume !(1 == ~E_2~0); 68505#L1507-1 assume !(1 == ~E_3~0); 68020#L1512-1 assume !(1 == ~E_4~0); 68021#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69432#L1522-1 assume !(1 == ~E_6~0); 68746#L1527-1 assume !(1 == ~E_7~0); 68747#L1532-1 assume !(1 == ~E_8~0); 69626#L1537-1 assume !(1 == ~E_9~0); 68951#L1542-1 assume !(1 == ~E_10~0); 68780#L1547-1 assume !(1 == ~E_11~0); 68781#L1552-1 assume !(1 == ~E_12~0); 67717#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 67718#L1562-1 assume { :end_inline_reset_delta_events } true; 68322#L1928-2 [2021-12-19 19:16:58,855 INFO L793 eck$LassoCheckResult]: Loop: 68322#L1928-2 assume !false; 68813#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67976#L1254 assume !false; 68563#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68050#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68051#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68248#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69420#L1067 assume !(0 != eval_~tmp~0#1); 68491#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68066#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68067#L1279-3 assume !(0 == ~M_E~0); 68526#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68508#L1284-3 assume !(0 == ~T2_E~0); 68509#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68487#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68488#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68876#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68877#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68385#L1314-3 assume !(0 == ~T8_E~0); 68386#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69383#L1324-3 assume !(0 == ~T10_E~0); 68017#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68018#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68785#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68786#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69085#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68366#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68367#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69096#L1364-3 assume !(0 == ~E_4~0); 69623#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69514#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68146#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68147#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68364#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68365#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68655#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69524#L1404-3 assume !(0 == ~E_12~0); 69488#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69489#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68975#L628-45 assume !(1 == ~m_pc~0); 68653#L628-47 is_master_triggered_~__retres1~0#1 := 0; 68654#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68011#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68012#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68400#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69124#L647-45 assume 1 == ~t1_pc~0; 67962#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67963#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68892#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68076#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68077#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68288#L666-45 assume !(1 == ~t2_pc~0); 68289#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 68770#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69333#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69248#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69242#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67826#L685-45 assume 1 == ~t3_pc~0; 67827#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68886#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69562#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69430#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69431#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69572#L704-45 assume 1 == ~t4_pc~0; 69450#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67696#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68552#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68896#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69648#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69008#L723-45 assume !(1 == ~t5_pc~0); 69009#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 69498#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68599#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68376#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68377#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69402#L742-45 assume !(1 == ~t6_pc~0); 68624#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 68625#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69094#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69130#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69131#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69219#L761-45 assume 1 == ~t7_pc~0; 69221#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68618#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68619#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68026#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68027#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69492#L780-45 assume !(1 == ~t8_pc~0); 68403#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68038#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68039#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69624#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68006#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68007#L799-45 assume !(1 == ~t9_pc~0); 68230#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68231#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69545#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69172#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69173#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67944#L818-45 assume 1 == ~t10_pc~0; 67945#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68065#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69147#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68550#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68551#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69267#L837-45 assume !(1 == ~t11_pc~0); 68480#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 68481#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68617#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69285#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68082#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68083#L856-45 assume 1 == ~t12_pc~0; 69570#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68085#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68024#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68025#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68889#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68890#L875-45 assume 1 == ~t13_pc~0; 68861#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68862#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68922#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69534#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69535#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69476#L1427-3 assume !(1 == ~M_E~0); 68686#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68687#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69226#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68878#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68879#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67734#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67735#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69418#L1462-3 assume !(1 == ~T8_E~0); 69419#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69282#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69283#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67985#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67986#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68127#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68295#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68296#L1502-3 assume !(1 == ~E_2~0); 69250#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69381#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68338#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68030#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68031#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67995#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67996#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69097#L1542-3 assume !(1 == ~E_10~0); 69235#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68864#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68865#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68206#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68207#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67626#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68391#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68392#L1947 assume !(0 == start_simulation_~tmp~3#1); 68998#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69203#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68263#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69598#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 69520#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69347#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69109#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69110#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68322#L1928-2 [2021-12-19 19:16:58,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2021-12-19 19:16:58,856 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804276805] [2021-12-19 19:16:58,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,857 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,888 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804276805] [2021-12-19 19:16:58,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804276805] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,888 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284028032] [2021-12-19 19:16:58,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1614179627, now seen corresponding path program 1 times [2021-12-19 19:16:58,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359747406] [2021-12-19 19:16:58,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359747406] [2021-12-19 19:16:58,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359747406] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,925 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,925 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214196150] [2021-12-19 19:16:58,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,926 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,926 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:58,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:58,926 INFO L87 Difference]: Start difference. First operand 3761 states and 5525 transitions. cyclomatic complexity: 1765 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,106 INFO L93 Difference]: Finished difference Result 5389 states and 7902 transitions. [2021-12-19 19:16:59,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:59,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5389 states and 7902 transitions. [2021-12-19 19:16:59,131 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5201 [2021-12-19 19:16:59,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5389 states to 5389 states and 7902 transitions. [2021-12-19 19:16:59,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5389 [2021-12-19 19:16:59,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5389 [2021-12-19 19:16:59,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5389 states and 7902 transitions. [2021-12-19 19:16:59,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,160 INFO L681 BuchiCegarLoop]: Abstraction has 5389 states and 7902 transitions. [2021-12-19 19:16:59,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5389 states and 7902 transitions. [2021-12-19 19:16:59,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5389 to 3761. [2021-12-19 19:16:59,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4682265354958788) internal successors, (5522), 3760 states have internal predecessors, (5522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5522 transitions. [2021-12-19 19:16:59,230 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5522 transitions. [2021-12-19 19:16:59,230 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5522 transitions. [2021-12-19 19:16:59,230 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:16:59,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5522 transitions. [2021-12-19 19:16:59,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2021-12-19 19:16:59,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,243 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,244 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,244 INFO L791 eck$LassoCheckResult]: Stem: 77704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 77705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 78752#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78197#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78198#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 77686#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77687#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77753#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77754#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78195#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78196#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77719#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77536#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77537#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77983#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77984#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77864#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77865#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 77507#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77508#L1279 assume !(0 == ~M_E~0); 78743#L1279-2 assume !(0 == ~T1_E~0); 77128#L1284-1 assume !(0 == ~T2_E~0); 77129#L1289-1 assume !(0 == ~T3_E~0); 77856#L1294-1 assume !(0 == ~T4_E~0); 77857#L1299-1 assume !(0 == ~T5_E~0); 77868#L1304-1 assume !(0 == ~T6_E~0); 78818#L1309-1 assume !(0 == ~T7_E~0); 78819#L1314-1 assume !(0 == ~T8_E~0); 77060#L1319-1 assume !(0 == ~T9_E~0); 77061#L1324-1 assume !(0 == ~T10_E~0); 77231#L1329-1 assume !(0 == ~T11_E~0); 77232#L1334-1 assume !(0 == ~T12_E~0); 78646#L1339-1 assume !(0 == ~T13_E~0); 78732#L1344-1 assume !(0 == ~E_M~0); 78733#L1349-1 assume !(0 == ~E_1~0); 78044#L1354-1 assume !(0 == ~E_2~0); 78045#L1359-1 assume !(0 == ~E_3~0); 78475#L1364-1 assume !(0 == ~E_4~0); 77362#L1369-1 assume !(0 == ~E_5~0); 77363#L1374-1 assume !(0 == ~E_6~0); 78050#L1379-1 assume !(0 == ~E_7~0); 78051#L1384-1 assume !(0 == ~E_8~0); 78127#L1389-1 assume !(0 == ~E_9~0); 78666#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 78667#L1399-1 assume !(0 == ~E_11~0); 78775#L1404-1 assume !(0 == ~E_12~0); 77455#L1409-1 assume !(0 == ~E_13~0); 77456#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78766#L628 assume !(1 == ~m_pc~0); 77359#L628-2 is_master_triggered_~__retres1~0#1 := 0; 77358#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78125#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78126#L1591 assume !(0 != activate_threads_~tmp~1#1); 78781#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77912#L647 assume 1 == ~t1_pc~0; 77279#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77280#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77551#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77552#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 78718#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78719#L666 assume 1 == ~t2_pc~0; 77125#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 77126#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77298#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78735#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 78246#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78247#L685 assume !(1 == ~t3_pc~0); 78354#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78353#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77974#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77975#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78095#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77578#L704 assume 1 == ~t4_pc~0; 77579#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78106#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78107#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78757#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 77965#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77966#L723 assume !(1 == ~t5_pc~0); 78091#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 78328#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78470#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78228#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 78229#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77345#L742 assume 1 == ~t6_pc~0; 77346#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77493#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77494#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77029#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 77030#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77421#L761 assume !(1 == ~t7_pc~0); 77422#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77292#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77293#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78097#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 78098#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77052#L780 assume 1 == ~t8_pc~0; 77053#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77331#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77332#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78057#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 78058#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78180#L799 assume 1 == ~t9_pc~0; 78293#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77055#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77056#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78189#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 78399#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78208#L818 assume !(1 == ~t10_pc~0); 76838#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76839#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78285#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78211#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78212#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78253#L837 assume 1 == ~t11_pc~0; 78254#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78088#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78491#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78170#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 78171#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77926#L856 assume !(1 == ~t12_pc~0); 77927#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 78577#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78578#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78559#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 78560#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78746#L875 assume 1 == ~t13_pc~0; 77866#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 77496#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 77497#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77436#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 77437#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78280#L1427 assume !(1 == ~M_E~0); 78266#L1427-2 assume !(1 == ~T1_E~0); 77408#L1432-1 assume !(1 == ~T2_E~0); 77409#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78481#L1442-1 assume !(1 == ~T4_E~0); 78482#L1447-1 assume !(1 == ~T5_E~0); 78339#L1452-1 assume !(1 == ~T6_E~0); 76971#L1457-1 assume !(1 == ~T7_E~0); 76972#L1462-1 assume !(1 == ~T8_E~0); 78508#L1467-1 assume !(1 == ~T9_E~0); 78526#L1472-1 assume !(1 == ~T10_E~0); 78527#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78278#L1482-1 assume !(1 == ~T12_E~0); 78279#L1487-1 assume !(1 == ~T13_E~0); 77306#L1492-1 assume !(1 == ~E_M~0); 77307#L1497-1 assume !(1 == ~E_1~0); 77666#L1502-1 assume !(1 == ~E_2~0); 77667#L1507-1 assume !(1 == ~E_3~0); 77180#L1512-1 assume !(1 == ~E_4~0); 77181#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78600#L1522-1 assume !(1 == ~E_6~0); 77910#L1527-1 assume !(1 == ~E_7~0); 77911#L1532-1 assume !(1 == ~E_8~0); 78802#L1537-1 assume !(1 == ~E_9~0); 78115#L1542-1 assume !(1 == ~E_10~0); 77944#L1547-1 assume !(1 == ~E_11~0); 77945#L1552-1 assume !(1 == ~E_12~0); 76877#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 76878#L1562-1 assume { :end_inline_reset_delta_events } true; 77484#L1928-2 [2021-12-19 19:16:59,244 INFO L793 eck$LassoCheckResult]: Loop: 77484#L1928-2 assume !false; 77977#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77136#L1254 assume !false; 77725#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77210#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77211#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77410#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 78588#L1067 assume !(0 != eval_~tmp~0#1); 77653#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77229#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77230#L1279-3 assume !(0 == ~M_E~0); 77688#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77670#L1284-3 assume !(0 == ~T2_E~0); 77671#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77649#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77650#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78039#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78040#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77547#L1314-3 assume !(0 == ~T8_E~0); 77548#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78548#L1324-3 assume !(0 == ~T10_E~0); 77177#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77178#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77950#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77951#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78250#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77528#L1354-3 assume !(0 == ~E_2~0); 77529#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78261#L1364-3 assume !(0 == ~E_4~0); 78798#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78685#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77308#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77309#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77526#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77527#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77819#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78697#L1404-3 assume !(0 == ~E_12~0); 78658#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 78659#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78139#L628-45 assume !(1 == ~m_pc~0); 77817#L628-47 is_master_triggered_~__retres1~0#1 := 0; 77818#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77171#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77172#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77562#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78289#L647-45 assume 1 == ~t1_pc~0; 77122#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77123#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78055#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77238#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77239#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77450#L666-45 assume !(1 == ~t2_pc~0); 77451#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 77934#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78498#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78413#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78407#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76986#L685-45 assume 1 == ~t3_pc~0; 76987#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78049#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78734#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78598#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78599#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78745#L704-45 assume !(1 == ~t4_pc~0); 76855#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 76856#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77714#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78059#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78827#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78172#L723-45 assume !(1 == ~t5_pc~0); 78173#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 78668#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77764#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77538#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 77539#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78567#L742-45 assume 1 == ~t6_pc~0; 78568#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77788#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78259#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78295#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78296#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78384#L761-45 assume !(1 == ~t7_pc~0); 78385#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 77781#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77782#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77184#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77185#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78662#L780-45 assume !(1 == ~t8_pc~0); 77565#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77196#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77197#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78800#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77166#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77167#L799-45 assume 1 == ~t9_pc~0; 77947#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77389#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78717#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78337#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78338#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77102#L818-45 assume !(1 == ~t10_pc~0); 77104#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 77223#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78312#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77711#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77712#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78432#L837-45 assume 1 == ~t11_pc~0; 78729#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77643#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77783#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78450#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77244#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77245#L856-45 assume 1 == ~t12_pc~0; 78742#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77247#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77186#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77187#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78052#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78053#L875-45 assume 1 == ~t13_pc~0; 78024#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78025#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78086#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78708#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78709#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78645#L1427-3 assume !(1 == ~M_E~0); 77850#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77851#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78391#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78041#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78042#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76894#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76895#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78585#L1462-3 assume !(1 == ~T8_E~0); 78586#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78447#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78448#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77145#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77146#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77289#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77462#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77463#L1502-3 assume !(1 == ~E_2~0); 78415#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78546#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77500#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77190#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77191#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77155#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77156#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78262#L1542-3 assume !(1 == ~E_10~0); 78400#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78027#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78028#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77368#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77369#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76786#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77553#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77554#L1947 assume !(0 == start_simulation_~tmp~3#1); 78162#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78368#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77425#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78770#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 78691#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78515#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78274#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 78275#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 77484#L1928-2 [2021-12-19 19:16:59,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1380038403, now seen corresponding path program 1 times [2021-12-19 19:16:59,245 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776021312] [2021-12-19 19:16:59,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776021312] [2021-12-19 19:16:59,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776021312] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,306 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982711884] [2021-12-19 19:16:59,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,307 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1799133097, now seen corresponding path program 1 times [2021-12-19 19:16:59,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236774067] [2021-12-19 19:16:59,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236774067] [2021-12-19 19:16:59,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1236774067] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012284225] [2021-12-19 19:16:59,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,350 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:59,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:59,351 INFO L87 Difference]: Start difference. First operand 3761 states and 5522 transitions. cyclomatic complexity: 1762 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,522 INFO L93 Difference]: Finished difference Result 5381 states and 7882 transitions. [2021-12-19 19:16:59,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:59,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5381 states and 7882 transitions. [2021-12-19 19:16:59,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5201 [2021-12-19 19:16:59,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5381 states to 5381 states and 7882 transitions. [2021-12-19 19:16:59,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5381 [2021-12-19 19:16:59,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5381 [2021-12-19 19:16:59,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5381 states and 7882 transitions. [2021-12-19 19:16:59,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,573 INFO L681 BuchiCegarLoop]: Abstraction has 5381 states and 7882 transitions. [2021-12-19 19:16:59,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5381 states and 7882 transitions. [2021-12-19 19:16:59,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5381 to 3761. [2021-12-19 19:16:59,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4674288752991225) internal successors, (5519), 3760 states have internal predecessors, (5519), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5519 transitions. [2021-12-19 19:16:59,639 INFO L704 BuchiCegarLoop]: Abstraction has 3761 states and 5519 transitions. [2021-12-19 19:16:59,639 INFO L587 BuchiCegarLoop]: Abstraction has 3761 states and 5519 transitions. [2021-12-19 19:16:59,639 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:16:59,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5519 transitions. [2021-12-19 19:16:59,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2021-12-19 19:16:59,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,650 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,651 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,651 INFO L791 eck$LassoCheckResult]: Stem: 86856#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 86857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 87902#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87349#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87350#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 86837#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86838#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86903#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86904#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87347#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87348#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86871#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86686#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86687#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87134#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87135#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87015#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87016#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86657#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86658#L1279 assume !(0 == ~M_E~0); 87893#L1279-2 assume !(0 == ~T1_E~0); 86280#L1284-1 assume !(0 == ~T2_E~0); 86281#L1289-1 assume !(0 == ~T3_E~0); 87007#L1294-1 assume !(0 == ~T4_E~0); 87008#L1299-1 assume !(0 == ~T5_E~0); 87019#L1304-1 assume !(0 == ~T6_E~0); 87965#L1309-1 assume !(0 == ~T7_E~0); 87966#L1314-1 assume !(0 == ~T8_E~0); 86212#L1319-1 assume !(0 == ~T9_E~0); 86213#L1324-1 assume !(0 == ~T10_E~0); 86383#L1329-1 assume !(0 == ~T11_E~0); 86384#L1334-1 assume !(0 == ~T12_E~0); 87796#L1339-1 assume !(0 == ~T13_E~0); 87882#L1344-1 assume !(0 == ~E_M~0); 87883#L1349-1 assume !(0 == ~E_1~0); 87195#L1354-1 assume !(0 == ~E_2~0); 87196#L1359-1 assume !(0 == ~E_3~0); 87628#L1364-1 assume !(0 == ~E_4~0); 86512#L1369-1 assume !(0 == ~E_5~0); 86513#L1374-1 assume !(0 == ~E_6~0); 87201#L1379-1 assume !(0 == ~E_7~0); 87202#L1384-1 assume !(0 == ~E_8~0); 87279#L1389-1 assume !(0 == ~E_9~0); 87815#L1394-1 assume !(0 == ~E_10~0); 87816#L1399-1 assume !(0 == ~E_11~0); 87925#L1404-1 assume !(0 == ~E_12~0); 86605#L1409-1 assume !(0 == ~E_13~0); 86606#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87917#L628 assume !(1 == ~m_pc~0); 86509#L628-2 is_master_triggered_~__retres1~0#1 := 0; 86508#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87277#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87278#L1591 assume !(0 != activate_threads_~tmp~1#1); 87931#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87063#L647 assume 1 == ~t1_pc~0; 86429#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86430#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86701#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86702#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 87868#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87869#L666 assume 1 == ~t2_pc~0; 86277#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86278#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86448#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87885#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 87397#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87398#L685 assume !(1 == ~t3_pc~0); 87506#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 87505#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87125#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87126#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87247#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86728#L704 assume 1 == ~t4_pc~0; 86729#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87258#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87259#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87907#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 87116#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87117#L723 assume !(1 == ~t5_pc~0); 87243#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 87480#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87623#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87379#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 87380#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86495#L742 assume 1 == ~t6_pc~0; 86496#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86643#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86644#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86181#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 86182#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86571#L761 assume !(1 == ~t7_pc~0); 86572#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86442#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86443#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87249#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 87250#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86204#L780 assume 1 == ~t8_pc~0; 86205#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86481#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86482#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87208#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 87209#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87332#L799 assume 1 == ~t9_pc~0; 87445#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86207#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86208#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87341#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 87551#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87360#L818 assume !(1 == ~t10_pc~0); 85990#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85991#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87437#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87363#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87364#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87404#L837 assume 1 == ~t11_pc~0; 87405#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87240#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87644#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87322#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 87323#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87077#L856 assume !(1 == ~t12_pc~0); 87078#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 87731#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 87732#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87713#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 87714#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87896#L875 assume 1 == ~t13_pc~0; 87017#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86646#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86647#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86586#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 86587#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87431#L1427 assume !(1 == ~M_E~0); 87417#L1427-2 assume !(1 == ~T1_E~0); 86558#L1432-1 assume !(1 == ~T2_E~0); 86559#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87634#L1442-1 assume !(1 == ~T4_E~0); 87635#L1447-1 assume !(1 == ~T5_E~0); 87491#L1452-1 assume !(1 == ~T6_E~0); 86123#L1457-1 assume !(1 == ~T7_E~0); 86124#L1462-1 assume !(1 == ~T8_E~0); 87661#L1467-1 assume !(1 == ~T9_E~0); 87679#L1472-1 assume !(1 == ~T10_E~0); 87680#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87429#L1482-1 assume !(1 == ~T12_E~0); 87430#L1487-1 assume !(1 == ~T13_E~0); 86456#L1492-1 assume !(1 == ~E_M~0); 86457#L1497-1 assume !(1 == ~E_1~0); 86816#L1502-1 assume !(1 == ~E_2~0); 86817#L1507-1 assume !(1 == ~E_3~0); 86332#L1512-1 assume !(1 == ~E_4~0); 86333#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 87751#L1522-1 assume !(1 == ~E_6~0); 87061#L1527-1 assume !(1 == ~E_7~0); 87062#L1532-1 assume !(1 == ~E_8~0); 87948#L1537-1 assume !(1 == ~E_9~0); 87267#L1542-1 assume !(1 == ~E_10~0); 87095#L1547-1 assume !(1 == ~E_11~0); 87096#L1552-1 assume !(1 == ~E_12~0); 86029#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86030#L1562-1 assume { :end_inline_reset_delta_events } true; 86634#L1928-2 [2021-12-19 19:16:59,651 INFO L793 eck$LassoCheckResult]: Loop: 86634#L1928-2 assume !false; 87128#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86288#L1254 assume !false; 86877#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86362#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86363#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86560#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 87739#L1067 assume !(0 != eval_~tmp~0#1); 86803#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86381#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86382#L1279-3 assume !(0 == ~M_E~0); 86839#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86820#L1284-3 assume !(0 == ~T2_E~0); 86821#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86799#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86800#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87190#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87191#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 86697#L1314-3 assume !(0 == ~T8_E~0); 86698#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 87702#L1324-3 assume !(0 == ~T10_E~0); 86329#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 86330#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 87104#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 87105#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87401#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86678#L1354-3 assume !(0 == ~E_2~0); 86679#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87412#L1364-3 assume !(0 == ~E_4~0); 87945#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87833#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86458#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86459#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86676#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86677#L1394-3 assume !(0 == ~E_10~0); 86969#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 87843#L1404-3 assume !(0 == ~E_12~0); 87807#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 87808#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87291#L628-45 assume !(1 == ~m_pc~0); 86967#L628-47 is_master_triggered_~__retres1~0#1 := 0; 86968#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86323#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86324#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 86712#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87438#L647-45 assume 1 == ~t1_pc~0; 86274#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86275#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87206#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86388#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86389#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86597#L666-45 assume 1 == ~t2_pc~0; 86599#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87085#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87651#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87565#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87559#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86135#L685-45 assume !(1 == ~t3_pc~0); 86137#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 87199#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87884#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87749#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87750#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87894#L704-45 assume !(1 == ~t4_pc~0); 86004#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 86005#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86866#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87210#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87975#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87324#L723-45 assume !(1 == ~t5_pc~0); 87325#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 87817#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86913#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86688#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 86689#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87721#L742-45 assume !(1 == ~t6_pc~0); 86937#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 86938#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87410#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87447#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87448#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87536#L761-45 assume !(1 == ~t7_pc~0); 87537#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 86931#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86932#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86336#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86337#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87811#L780-45 assume !(1 == ~t8_pc~0); 86715#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 86348#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86349#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87946#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86318#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86319#L799-45 assume !(1 == ~t9_pc~0); 86539#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 86540#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87867#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87489#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87490#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86254#L818-45 assume !(1 == ~t10_pc~0); 86256#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 86375#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87464#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86863#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86864#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87585#L837-45 assume 1 == ~t11_pc~0; 87879#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86793#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86933#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87603#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 86394#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86395#L856-45 assume 1 == ~t12_pc~0; 87892#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86397#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86338#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86339#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 87203#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87204#L875-45 assume 1 == ~t13_pc~0; 87175#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 87176#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87238#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 87859#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 87860#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87795#L1427-3 assume !(1 == ~M_E~0); 87001#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87002#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87543#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87192#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87193#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86046#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86047#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87737#L1462-3 assume !(1 == ~T8_E~0); 87738#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87600#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87601#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86297#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86298#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 86439#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86612#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86613#L1502-3 assume !(1 == ~E_2~0); 87567#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87699#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86650#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86342#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86343#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86307#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86308#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 87413#L1542-3 assume !(1 == ~E_10~0); 87552#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87178#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87179#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86518#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86519#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85938#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86703#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 86704#L1947 assume !(0 == start_simulation_~tmp~3#1); 87314#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87520#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86575#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87921#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 87839#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87668#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87425#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 87426#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 86634#L1928-2 [2021-12-19 19:16:59,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,652 INFO L85 PathProgramCache]: Analyzing trace with hash -462437311, now seen corresponding path program 1 times [2021-12-19 19:16:59,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733886518] [2021-12-19 19:16:59,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,653 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,683 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733886518] [2021-12-19 19:16:59,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733886518] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,683 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,683 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:59,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039979725] [2021-12-19 19:16:59,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,684 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,684 INFO L85 PathProgramCache]: Analyzing trace with hash -513272983, now seen corresponding path program 1 times [2021-12-19 19:16:59,685 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328406719] [2021-12-19 19:16:59,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,685 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,719 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328406719] [2021-12-19 19:16:59,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328406719] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,719 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024853091] [2021-12-19 19:16:59,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:59,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:59,721 INFO L87 Difference]: Start difference. First operand 3761 states and 5519 transitions. cyclomatic complexity: 1759 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,835 INFO L93 Difference]: Finished difference Result 7113 states and 10386 transitions. [2021-12-19 19:16:59,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:59,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7113 states and 10386 transitions. [2021-12-19 19:16:59,867 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6937 [2021-12-19 19:16:59,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7113 states to 7113 states and 10386 transitions. [2021-12-19 19:16:59,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7113 [2021-12-19 19:16:59,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7113 [2021-12-19 19:16:59,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7113 states and 10386 transitions. [2021-12-19 19:16:59,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,909 INFO L681 BuchiCegarLoop]: Abstraction has 7113 states and 10386 transitions. [2021-12-19 19:16:59,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7113 states and 10386 transitions. [2021-12-19 19:17:00,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7113 to 7109. [2021-12-19 19:17:00,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7109 states, 7109 states have (on average 1.4604023069348713) internal successors, (10382), 7108 states have internal predecessors, (10382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7109 states to 7109 states and 10382 transitions. [2021-12-19 19:17:00,067 INFO L704 BuchiCegarLoop]: Abstraction has 7109 states and 10382 transitions. [2021-12-19 19:17:00,067 INFO L587 BuchiCegarLoop]: Abstraction has 7109 states and 10382 transitions. [2021-12-19 19:17:00,067 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:00,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7109 states and 10382 transitions. [2021-12-19 19:17:00,084 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6933 [2021-12-19 19:17:00,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,086 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,087 INFO L791 eck$LassoCheckResult]: Stem: 97751#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 97752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 98984#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98285#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98286#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 97732#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97733#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97806#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97807#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98276#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98277#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97768#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97578#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97579#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98050#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 98051#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97915#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97916#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97545#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97546#L1279 assume !(0 == ~M_E~0); 98976#L1279-2 assume !(0 == ~T1_E~0); 97164#L1284-1 assume !(0 == ~T2_E~0); 97165#L1289-1 assume !(0 == ~T3_E~0); 97912#L1294-1 assume !(0 == ~T4_E~0); 97913#L1299-1 assume !(0 == ~T5_E~0); 97924#L1304-1 assume !(0 == ~T6_E~0); 99100#L1309-1 assume !(0 == ~T7_E~0); 99106#L1314-1 assume !(0 == ~T8_E~0); 97093#L1319-1 assume !(0 == ~T9_E~0); 97094#L1324-1 assume !(0 == ~T10_E~0); 97271#L1329-1 assume !(0 == ~T11_E~0); 97272#L1334-1 assume !(0 == ~T12_E~0); 98838#L1339-1 assume !(0 == ~T13_E~0); 98961#L1344-1 assume !(0 == ~E_M~0); 98962#L1349-1 assume !(0 == ~E_1~0); 98113#L1354-1 assume !(0 == ~E_2~0); 98114#L1359-1 assume !(0 == ~E_3~0); 98617#L1364-1 assume !(0 == ~E_4~0); 97399#L1369-1 assume !(0 == ~E_5~0); 97400#L1374-1 assume !(0 == ~E_6~0); 98118#L1379-1 assume !(0 == ~E_7~0); 98119#L1384-1 assume !(0 == ~E_8~0); 98205#L1389-1 assume !(0 == ~E_9~0); 98866#L1394-1 assume !(0 == ~E_10~0); 98867#L1399-1 assume !(0 == ~E_11~0); 99018#L1404-1 assume !(0 == ~E_12~0); 97492#L1409-1 assume !(0 == ~E_13~0); 97493#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99008#L628 assume !(1 == ~m_pc~0); 97396#L628-2 is_master_triggered_~__retres1~0#1 := 0; 97395#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98203#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 98204#L1591 assume !(0 != activate_threads_~tmp~1#1); 99029#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97972#L647 assume !(1 == ~t1_pc~0); 97973#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98034#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97593#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97594#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 98945#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98946#L666 assume 1 == ~t2_pc~0; 97161#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 97162#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97329#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98966#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 98345#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98346#L685 assume !(1 == ~t3_pc~0); 98461#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98460#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98038#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98039#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98170#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97623#L704 assume 1 == ~t4_pc~0; 97624#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98182#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98183#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98991#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 98030#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98031#L723 assume !(1 == ~t5_pc~0); 98164#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 98433#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98610#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98322#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 98323#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97381#L742 assume 1 == ~t6_pc~0; 97382#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97531#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97532#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97061#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 97062#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97458#L761 assume !(1 == ~t7_pc~0); 97459#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 97325#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97326#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 98172#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 98173#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97087#L780 assume 1 == ~t8_pc~0; 97088#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 97367#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97368#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 98127#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 98128#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 98258#L799 assume 1 == ~t9_pc~0; 98395#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 97090#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97091#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98272#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 98513#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98300#L818 assume !(1 == ~t10_pc~0); 96869#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96870#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98385#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98305#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 98306#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98352#L837 assume 1 == ~t11_pc~0; 98353#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 98161#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98637#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98250#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 98251#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97982#L856 assume !(1 == ~t12_pc~0); 97983#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 98747#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 98748#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98717#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 98718#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 98979#L875 assume 1 == ~t13_pc~0; 97922#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97534#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97535#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 97473#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 97474#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98382#L1427 assume !(1 == ~M_E~0); 98363#L1427-2 assume !(1 == ~T1_E~0); 97445#L1432-1 assume !(1 == ~T2_E~0); 97446#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98624#L1442-1 assume !(1 == ~T4_E~0); 98625#L1447-1 assume !(1 == ~T5_E~0); 98444#L1452-1 assume !(1 == ~T6_E~0); 97005#L1457-1 assume !(1 == ~T7_E~0); 97006#L1462-1 assume !(1 == ~T8_E~0); 98658#L1467-1 assume !(1 == ~T9_E~0); 98681#L1472-1 assume !(1 == ~T10_E~0); 98682#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98380#L1482-1 assume !(1 == ~T12_E~0); 98381#L1487-1 assume !(1 == ~T13_E~0); 97339#L1492-1 assume !(1 == ~E_M~0); 97340#L1497-1 assume !(1 == ~E_1~0); 97712#L1502-1 assume !(1 == ~E_2~0); 97713#L1507-1 assume !(1 == ~E_3~0); 97219#L1512-1 assume !(1 == ~E_4~0); 97220#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 98770#L1522-1 assume !(1 == ~E_6~0); 97969#L1527-1 assume !(1 == ~E_7~0); 97970#L1532-1 assume !(1 == ~E_8~0); 99067#L1537-1 assume !(1 == ~E_9~0); 98189#L1542-1 assume !(1 == ~E_10~0); 98008#L1547-1 assume !(1 == ~E_11~0); 98009#L1552-1 assume !(1 == ~E_12~0); 96908#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 96909#L1562-1 assume { :end_inline_reset_delta_events } true; 97522#L1928-2 [2021-12-19 19:17:00,087 INFO L793 eck$LassoCheckResult]: Loop: 97522#L1928-2 assume !false; 98163#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97776#L1254 assume !false; 97777#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97249#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 97250#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97447#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 98755#L1067 assume !(0 != eval_~tmp~0#1); 98756#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103689#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103688#L1279-3 assume !(0 == ~M_E~0); 103687#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103686#L1284-3 assume !(0 == ~T2_E~0); 103685#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103684#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103683#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103682#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103681#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103680#L1314-3 assume !(0 == ~T8_E~0); 103679#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103678#L1324-3 assume !(0 == ~T10_E~0); 103677#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 103676#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 103675#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 103674#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103673#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103672#L1354-3 assume !(0 == ~E_2~0); 103671#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103670#L1364-3 assume !(0 == ~E_4~0); 103669#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103668#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103667#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103666#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103665#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103664#L1394-3 assume !(0 == ~E_10~0); 103663#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103662#L1404-3 assume !(0 == ~E_12~0); 103661#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 103660#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103659#L628-45 assume !(1 == ~m_pc~0); 103657#L628-47 is_master_triggered_~__retres1~0#1 := 0; 103656#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103655#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97604#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 97605#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98393#L647-45 assume !(1 == ~t1_pc~0); 98394#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 98859#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103825#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103824#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103823#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103822#L666-45 assume 1 == ~t2_pc~0; 103821#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103819#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103818#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103817#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103816#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103815#L685-45 assume 1 == ~t3_pc~0; 103813#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 103812#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98994#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98766#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98767#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98977#L704-45 assume !(1 == ~t4_pc~0); 96885#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 96886#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97765#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98130#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99132#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98252#L723-45 assume !(1 == ~t5_pc~0); 98253#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 98868#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97816#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97580#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 97581#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98730#L742-45 assume 1 == ~t6_pc~0; 98731#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 103794#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98595#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98400#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98401#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98496#L761-45 assume !(1 == ~t7_pc~0); 98497#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 97835#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97836#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97223#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 97224#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98856#L780-45 assume 1 == ~t8_pc~0; 97607#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 97235#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97236#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103538#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 97205#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97206#L799-45 assume !(1 == ~t9_pc~0); 97426#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 97427#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103534#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103533#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103532#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103531#L818-45 assume 1 == ~t10_pc~0; 103529#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 103528#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102963#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 102962#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 102960#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 102958#L837-45 assume !(1 == ~t11_pc~0); 102955#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 102953#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102951#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 102948#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 102946#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102944#L856-45 assume 1 == ~t12_pc~0; 102941#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 102939#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 102937#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102934#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 102932#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102930#L875-45 assume 1 == ~t13_pc~0; 102928#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 102925#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 102924#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102923#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 102919#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102917#L1427-3 assume !(1 == ~M_E~0); 102739#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102915#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102914#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101108#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101107#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101106#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101105#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101104#L1462-3 assume !(1 == ~T8_E~0); 101103#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98578#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 98579#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97184#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97185#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 97324#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97500#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97501#L1502-3 assume !(1 == ~E_2~0); 98538#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98704#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97538#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97229#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97230#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 97194#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97195#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98361#L1542-3 assume !(1 == ~E_10~0); 98517#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98518#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 98862#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 98863#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99129#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96819#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97595#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 97596#L1947 assume !(0 == start_simulation_~tmp~3#1); 98242#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98478#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 97462#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 99012#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 98899#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98668#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98375#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 98376#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 97522#L1928-2 [2021-12-19 19:17:00,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,088 INFO L85 PathProgramCache]: Analyzing trace with hash 908624450, now seen corresponding path program 1 times [2021-12-19 19:17:00,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027328239] [2021-12-19 19:17:00,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027328239] [2021-12-19 19:17:00,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027328239] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,124 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,124 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,124 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339414320] [2021-12-19 19:17:00,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,125 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1489408857, now seen corresponding path program 1 times [2021-12-19 19:17:00,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237770493] [2021-12-19 19:17:00,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,163 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237770493] [2021-12-19 19:17:00,164 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237770493] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,164 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,164 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534691055] [2021-12-19 19:17:00,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,165 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:00,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:00,166 INFO L87 Difference]: Start difference. First operand 7109 states and 10382 transitions. cyclomatic complexity: 3275 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,423 INFO L93 Difference]: Finished difference Result 17043 states and 24731 transitions. [2021-12-19 19:17:00,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:00,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17043 states and 24731 transitions. [2021-12-19 19:17:00,516 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16852 [2021-12-19 19:17:00,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17043 states to 17043 states and 24731 transitions. [2021-12-19 19:17:00,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17043 [2021-12-19 19:17:00,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17043 [2021-12-19 19:17:00,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17043 states and 24731 transitions. [2021-12-19 19:17:00,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,749 INFO L681 BuchiCegarLoop]: Abstraction has 17043 states and 24731 transitions. [2021-12-19 19:17:00,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17043 states and 24731 transitions. [2021-12-19 19:17:00,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17043 to 13577. [2021-12-19 19:17:00,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13577 states, 13577 states have (on average 1.4545186712823157) internal successors, (19748), 13576 states have internal predecessors, (19748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13577 states to 13577 states and 19748 transitions. [2021-12-19 19:17:00,989 INFO L704 BuchiCegarLoop]: Abstraction has 13577 states and 19748 transitions. [2021-12-19 19:17:00,989 INFO L587 BuchiCegarLoop]: Abstraction has 13577 states and 19748 transitions. [2021-12-19 19:17:00,989 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:00,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13577 states and 19748 transitions. [2021-12-19 19:17:01,039 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 13400 [2021-12-19 19:17:01,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,041 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,042 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,042 INFO L791 eck$LassoCheckResult]: Stem: 121900#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 121901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 123020#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122413#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122414#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 121882#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121883#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121952#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121953#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122409#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122410#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121917#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121731#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 121732#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122187#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 122188#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 122059#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 122060#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 121699#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121700#L1279 assume !(0 == ~M_E~0); 123010#L1279-2 assume !(0 == ~T1_E~0); 121319#L1284-1 assume !(0 == ~T2_E~0); 121320#L1289-1 assume !(0 == ~T3_E~0); 122056#L1294-1 assume !(0 == ~T4_E~0); 122057#L1299-1 assume !(0 == ~T5_E~0); 122068#L1304-1 assume !(0 == ~T6_E~0); 123108#L1309-1 assume !(0 == ~T7_E~0); 123110#L1314-1 assume !(0 == ~T8_E~0); 121252#L1319-1 assume !(0 == ~T9_E~0); 121253#L1324-1 assume !(0 == ~T10_E~0); 121423#L1329-1 assume !(0 == ~T11_E~0); 121424#L1334-1 assume !(0 == ~T12_E~0); 122896#L1339-1 assume !(0 == ~T13_E~0); 122995#L1344-1 assume !(0 == ~E_M~0); 122996#L1349-1 assume !(0 == ~E_1~0); 122250#L1354-1 assume !(0 == ~E_2~0); 122251#L1359-1 assume !(0 == ~E_3~0); 122713#L1364-1 assume !(0 == ~E_4~0); 121556#L1369-1 assume !(0 == ~E_5~0); 121557#L1374-1 assume !(0 == ~E_6~0); 122255#L1379-1 assume !(0 == ~E_7~0); 122256#L1384-1 assume !(0 == ~E_8~0); 122339#L1389-1 assume !(0 == ~E_9~0); 122920#L1394-1 assume !(0 == ~E_10~0); 122921#L1399-1 assume !(0 == ~E_11~0); 123051#L1404-1 assume !(0 == ~E_12~0); 121648#L1409-1 assume !(0 == ~E_13~0); 121649#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123039#L628 assume !(1 == ~m_pc~0); 121553#L628-2 is_master_triggered_~__retres1~0#1 := 0; 121552#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122337#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122338#L1591 assume !(0 != activate_threads_~tmp~1#1); 123058#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122111#L647 assume !(1 == ~t1_pc~0); 122112#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122172#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121746#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121747#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 122981#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122982#L666 assume !(1 == ~t2_pc~0); 123034#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 121482#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121483#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123001#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 122462#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122463#L685 assume !(1 == ~t3_pc~0); 122573#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122572#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122176#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122177#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122307#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121774#L704 assume 1 == ~t4_pc~0; 121775#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 122318#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122319#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123025#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 122168#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122169#L723 assume !(1 == ~t5_pc~0); 122301#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122547#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122708#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 122441#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 122442#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121538#L742 assume 1 == ~t6_pc~0; 121539#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 121685#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121686#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 121220#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 121221#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121615#L761 assume !(1 == ~t7_pc~0); 121616#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121478#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121479#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122308#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 122309#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121246#L780 assume 1 == ~t8_pc~0; 121247#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 121522#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 121523#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122267#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 122268#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 122393#L799 assume 1 == ~t9_pc~0; 122508#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 121249#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121250#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 122405#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 122622#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122423#L818 assume !(1 == ~t10_pc~0); 121031#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 121032#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122500#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122427#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122428#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122469#L837 assume 1 == ~t11_pc~0; 122470#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122298#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 122729#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122386#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 122387#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 122121#L856 assume !(1 == ~t12_pc~0); 122122#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 122819#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 122820#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 122797#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 122798#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123015#L875 assume 1 == ~t13_pc~0; 122066#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 121688#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 121689#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 121630#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 121631#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122497#L1427 assume !(1 == ~M_E~0); 122481#L1427-2 assume !(1 == ~T1_E~0); 121602#L1432-1 assume !(1 == ~T2_E~0); 121603#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122719#L1442-1 assume !(1 == ~T4_E~0); 122720#L1447-1 assume !(1 == ~T5_E~0); 122558#L1452-1 assume !(1 == ~T6_E~0); 121165#L1457-1 assume !(1 == ~T7_E~0); 121166#L1462-1 assume !(1 == ~T8_E~0); 122747#L1467-1 assume !(1 == ~T9_E~0); 122765#L1472-1 assume !(1 == ~T10_E~0); 122766#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122495#L1482-1 assume !(1 == ~T12_E~0); 122496#L1487-1 assume !(1 == ~T13_E~0); 121494#L1492-1 assume !(1 == ~E_M~0); 121495#L1497-1 assume !(1 == ~E_1~0); 121864#L1502-1 assume !(1 == ~E_2~0); 121865#L1507-1 assume !(1 == ~E_3~0); 121372#L1512-1 assume !(1 == ~E_4~0); 121373#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 122843#L1522-1 assume !(1 == ~E_6~0); 122108#L1527-1 assume !(1 == ~E_7~0); 122109#L1532-1 assume !(1 == ~E_8~0); 123084#L1537-1 assume !(1 == ~E_9~0); 122325#L1542-1 assume !(1 == ~E_10~0); 122145#L1547-1 assume !(1 == ~E_11~0); 122146#L1552-1 assume !(1 == ~E_12~0); 121069#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 121070#L1562-1 assume { :end_inline_reset_delta_events } true; 121676#L1928-2 [2021-12-19 19:17:01,043 INFO L793 eck$LassoCheckResult]: Loop: 121676#L1928-2 assume !false; 132158#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132152#L1254 assume !false; 132149#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 132106#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 132095#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 132092#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 132087#L1067 assume !(0 != eval_~tmp~0#1); 132088#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121418#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121419#L1279-3 assume !(0 == ~M_E~0); 121886#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 121868#L1284-3 assume !(0 == ~T2_E~0); 121869#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121846#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121847#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122246#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 122247#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121742#L1314-3 assume !(0 == ~T8_E~0); 121743#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 123125#L1324-3 assume !(0 == ~T10_E~0); 134548#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 134547#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 134546#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 134545#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134544#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134543#L1354-3 assume !(0 == ~E_2~0); 134542#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134541#L1364-3 assume !(0 == ~E_4~0); 134540#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134539#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 134538#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 134537#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 121718#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 121719#L1394-3 assume !(0 == ~E_10~0); 122019#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 122957#L1404-3 assume !(0 == ~E_12~0); 122907#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 122908#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122351#L628-45 assume 1 == ~m_pc~0; 122353#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 134530#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134529#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134528#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 134527#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134526#L647-45 assume !(1 == ~t1_pc~0); 134525#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 134524#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134523#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134522#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134521#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134520#L666-45 assume !(1 == ~t2_pc~0); 130086#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 134519#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134518#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134517#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134516#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134515#L685-45 assume 1 == ~t3_pc~0; 122257#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 122258#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123000#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122841#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122842#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123047#L704-45 assume !(1 == ~t4_pc~0); 123049#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 134511#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122270#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122271#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123130#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134509#L723-45 assume 1 == ~t5_pc~0; 134507#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123068#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121962#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121733#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 121734#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122806#L742-45 assume 1 == ~t6_pc~0; 122807#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 134500#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134499#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 134498#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134497#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134496#L761-45 assume 1 == ~t7_pc~0; 134494#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 134493#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134492#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 134491#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134490#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122911#L780-45 assume !(1 == ~t8_pc~0); 122913#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 134489#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134488#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 134487#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 134486#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 134485#L799-45 assume 1 == ~t9_pc~0; 122955#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 121584#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122980#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 122559#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 122560#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 121298#L818-45 assume 1 == ~t10_pc~0; 121299#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 121415#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 134477#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 134476#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 134475#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122992#L837-45 assume 1 == ~t11_pc~0; 122993#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121841#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 121983#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122682#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 121435#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 121436#L856-45 assume 1 == ~t12_pc~0; 123009#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 121438#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121378#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 121379#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 122263#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 122264#L875-45 assume 1 == ~t13_pc~0; 122231#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 122232#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 122299#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122972#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 122973#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122895#L1427-3 assume !(1 == ~M_E~0); 122050#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122051#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 122616#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122248#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122249#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121088#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 121089#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122825#L1462-3 assume !(1 == ~T8_E~0); 122826#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123063#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133456#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 133455#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 133454#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 133453#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133452#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133451#L1502-3 assume !(1 == ~E_2~0); 133450#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 133449#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133448#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133384#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 133381#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 133379#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 133377#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 133375#L1542-3 assume !(1 == ~E_10~0); 133373#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 133371#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 133368#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 133366#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 133361#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 133347#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 133345#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 133342#L1947 assume !(0 == start_simulation_~tmp~3#1); 133339#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 133333#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 133318#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 132837#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 132274#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132194#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132182#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 132171#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 121676#L1928-2 [2021-12-19 19:17:01,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,043 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2021-12-19 19:17:01,045 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,045 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51678149] [2021-12-19 19:17:01,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,045 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,099 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51678149] [2021-12-19 19:17:01,099 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51678149] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:01,100 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230893106] [2021-12-19 19:17:01,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,102 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,103 INFO L85 PathProgramCache]: Analyzing trace with hash -316730140, now seen corresponding path program 1 times [2021-12-19 19:17:01,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347866346] [2021-12-19 19:17:01,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347866346] [2021-12-19 19:17:01,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347866346] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,142 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,143 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668483283] [2021-12-19 19:17:01,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,143 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,143 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:01,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:01,144 INFO L87 Difference]: Start difference. First operand 13577 states and 19748 transitions. cyclomatic complexity: 6173 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,665 INFO L93 Difference]: Finished difference Result 37220 states and 54149 transitions. [2021-12-19 19:17:01,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:01,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37220 states and 54149 transitions. [2021-12-19 19:17:01,864 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 36832 [2021-12-19 19:17:02,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37220 states to 37220 states and 54149 transitions. [2021-12-19 19:17:02,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37220 [2021-12-19 19:17:02,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37220 [2021-12-19 19:17:02,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37220 states and 54149 transitions. [2021-12-19 19:17:02,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:02,092 INFO L681 BuchiCegarLoop]: Abstraction has 37220 states and 54149 transitions. [2021-12-19 19:17:02,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37220 states and 54149 transitions. [2021-12-19 19:17:02,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37220 to 13928. [2021-12-19 19:17:02,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13928 states, 13928 states have (on average 1.4430643308443423) internal successors, (20099), 13927 states have internal predecessors, (20099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13928 states to 13928 states and 20099 transitions. [2021-12-19 19:17:02,548 INFO L704 BuchiCegarLoop]: Abstraction has 13928 states and 20099 transitions. [2021-12-19 19:17:02,548 INFO L587 BuchiCegarLoop]: Abstraction has 13928 states and 20099 transitions. [2021-12-19 19:17:02,548 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:02,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13928 states and 20099 transitions. [2021-12-19 19:17:02,594 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 13748 [2021-12-19 19:17:02,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,597 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,597 INFO L791 eck$LassoCheckResult]: Stem: 172722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 172723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 173913#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173243#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173244#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 172704#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 172705#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172770#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172771#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 173239#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 173240#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 172737#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172546#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 172547#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 173010#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 173011#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 172878#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 172879#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 172513#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 172514#L1279 assume !(0 == ~M_E~0); 173905#L1279-2 assume !(0 == ~T1_E~0); 172129#L1284-1 assume !(0 == ~T2_E~0); 172130#L1289-1 assume !(0 == ~T3_E~0); 172875#L1294-1 assume !(0 == ~T4_E~0); 172876#L1299-1 assume !(0 == ~T5_E~0); 172887#L1304-1 assume !(0 == ~T6_E~0); 174059#L1309-1 assume !(0 == ~T7_E~0); 174064#L1314-1 assume !(0 == ~T8_E~0); 172061#L1319-1 assume !(0 == ~T9_E~0); 172062#L1324-1 assume !(0 == ~T10_E~0); 172236#L1329-1 assume !(0 == ~T11_E~0); 172237#L1334-1 assume !(0 == ~T12_E~0); 173780#L1339-1 assume !(0 == ~T13_E~0); 173892#L1344-1 assume !(0 == ~E_M~0); 173893#L1349-1 assume !(0 == ~E_1~0); 173075#L1354-1 assume !(0 == ~E_2~0); 173076#L1359-1 assume !(0 == ~E_3~0); 173569#L1364-1 assume !(0 == ~E_4~0); 172368#L1369-1 assume !(0 == ~E_5~0); 172369#L1374-1 assume !(0 == ~E_6~0); 173080#L1379-1 assume !(0 == ~E_7~0); 173081#L1384-1 assume !(0 == ~E_8~0); 173167#L1389-1 assume !(0 == ~E_9~0); 173806#L1394-1 assume !(0 == ~E_10~0); 173807#L1399-1 assume !(0 == ~E_11~0); 173963#L1404-1 assume !(0 == ~E_12~0); 172462#L1409-1 assume !(0 == ~E_13~0); 172463#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173951#L628 assume !(1 == ~m_pc~0); 172365#L628-2 is_master_triggered_~__retres1~0#1 := 0; 172364#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173165#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 173166#L1591 assume !(0 != activate_threads_~tmp~1#1); 173974#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172931#L647 assume !(1 == ~t1_pc~0); 172932#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 172995#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172561#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172562#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 173875#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173876#L666 assume !(1 == ~t2_pc~0); 173936#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172295#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172296#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173897#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 173295#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173296#L685 assume !(1 == ~t3_pc~0); 173417#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 173496#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173988#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173130#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 173131#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172593#L704 assume 1 == ~t4_pc~0; 172594#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 173144#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173145#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 173920#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 172991#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172992#L723 assume !(1 == ~t5_pc~0); 173124#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 173388#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173564#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 173273#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 173274#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172350#L742 assume 1 == ~t6_pc~0; 172351#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 172499#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172500#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172031#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 172032#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 172428#L761 assume !(1 == ~t7_pc~0); 172429#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 172291#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172292#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 173132#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 173133#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172055#L780 assume 1 == ~t8_pc~0; 172056#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 172334#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172335#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 173091#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 173092#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 173221#L799 assume 1 == ~t9_pc~0; 173344#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 172058#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172059#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173235#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 173469#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 173253#L818 assume !(1 == ~t10_pc~0); 171841#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 171842#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 173336#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 173259#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 173260#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 173304#L837 assume 1 == ~t11_pc~0; 173305#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 173122#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 173589#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 173214#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 173215#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 172941#L856 assume !(1 == ~t12_pc~0); 172942#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 173693#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 173694#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 173667#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 173668#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 173908#L875 assume 1 == ~t13_pc~0; 172885#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 172502#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 172503#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 172444#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 172445#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173333#L1427 assume !(1 == ~M_E~0); 173316#L1427-2 assume !(1 == ~T1_E~0); 172415#L1432-1 assume !(1 == ~T2_E~0); 172416#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173576#L1442-1 assume !(1 == ~T4_E~0); 173577#L1447-1 assume !(1 == ~T5_E~0); 173401#L1452-1 assume !(1 == ~T6_E~0); 171975#L1457-1 assume !(1 == ~T7_E~0); 171976#L1462-1 assume !(1 == ~T8_E~0); 173612#L1467-1 assume !(1 == ~T9_E~0); 173630#L1472-1 assume !(1 == ~T10_E~0); 173631#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 173331#L1482-1 assume !(1 == ~T12_E~0); 173332#L1487-1 assume !(1 == ~T13_E~0); 172306#L1492-1 assume !(1 == ~E_M~0); 172307#L1497-1 assume !(1 == ~E_1~0); 172684#L1502-1 assume !(1 == ~E_2~0); 172685#L1507-1 assume !(1 == ~E_3~0); 172185#L1512-1 assume !(1 == ~E_4~0); 172186#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 173722#L1522-1 assume !(1 == ~E_6~0); 172928#L1527-1 assume !(1 == ~E_7~0); 172929#L1532-1 assume !(1 == ~E_8~0); 174015#L1537-1 assume !(1 == ~E_9~0); 173151#L1542-1 assume !(1 == ~E_10~0); 172969#L1547-1 assume !(1 == ~E_11~0); 172970#L1552-1 assume !(1 == ~E_12~0); 171879#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 171880#L1562-1 assume { :end_inline_reset_delta_events } true; 172490#L1928-2 [2021-12-19 19:17:02,598 INFO L793 eck$LassoCheckResult]: Loop: 172490#L1928-2 assume !false; 173004#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172139#L1254 assume !false; 172745#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 172215#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 172216#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 172417#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 173925#L1067 assume !(0 != eval_~tmp~0#1); 181635#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 185647#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185646#L1279-3 assume !(0 == ~M_E~0); 185623#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 185621#L1284-3 assume !(0 == ~T2_E~0); 185619#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 185616#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 185614#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 185612#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 185610#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 185608#L1314-3 assume !(0 == ~T8_E~0); 185606#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 185603#L1324-3 assume !(0 == ~T10_E~0); 185602#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 185601#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 185600#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 185599#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 185598#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 185597#L1354-3 assume !(0 == ~E_2~0); 185596#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 185595#L1364-3 assume !(0 == ~E_4~0); 185594#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 185593#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 185592#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 185591#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 185590#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 185589#L1394-3 assume !(0 == ~E_10~0); 185588#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 185587#L1404-3 assume !(0 == ~E_12~0); 185586#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 185585#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178780#L628-45 assume 1 == ~m_pc~0; 178782#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 178775#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178776#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178769#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 178770#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173342#L647-45 assume !(1 == ~t1_pc~0); 173343#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 178427#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178428#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 178423#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 178424#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178420#L666-45 assume !(1 == ~t2_pc~0); 178419#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 178418#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178417#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178416#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 178415#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178414#L685-45 assume 1 == ~t3_pc~0; 178412#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 178410#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178408#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 178406#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178405#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178404#L704-45 assume !(1 == ~t4_pc~0); 178402#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 178401#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178400#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 178399#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 178398#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178397#L723-45 assume 1 == ~t5_pc~0; 178395#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 178394#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178393#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 178392#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 178391#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 178390#L742-45 assume 1 == ~t6_pc~0; 178388#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 178387#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178386#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 178385#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 178384#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 178383#L761-45 assume !(1 == ~t7_pc~0); 178382#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 178380#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178379#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 178378#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 178377#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 178376#L780-45 assume 1 == ~t8_pc~0; 178374#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178373#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 178372#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 178371#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 178370#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 178369#L799-45 assume 1 == ~t9_pc~0; 178368#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 178366#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 178365#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 178364#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 178363#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 178362#L818-45 assume 1 == ~t10_pc~0; 178360#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 178359#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 178358#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 178357#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 178356#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 178355#L837-45 assume 1 == ~t11_pc~0; 178354#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 178352#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 178351#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 178350#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 178349#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 178348#L856-45 assume 1 == ~t12_pc~0; 178346#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 178345#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 178344#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 178343#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 178342#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 178341#L875-45 assume !(1 == ~t13_pc~0); 178339#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 178338#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 178337#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 178336#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 178335#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178165#L1427-3 assume !(1 == ~M_E~0); 178166#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178159#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 178160#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178152#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178153#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 178146#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 178147#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 177258#L1462-3 assume !(1 == ~T8_E~0); 177259#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 177249#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 177250#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 177243#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 177244#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 175194#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 175195#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 175188#L1502-3 assume !(1 == ~E_2~0); 175189#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175181#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175182#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 181099#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 175173#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 175174#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175166#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 175167#L1542-3 assume !(1 == ~E_10~0); 175160#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 175161#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 175154#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 175155#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 174093#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 171791#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 172563#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 172564#L1947 assume !(0 == start_simulation_~tmp~3#1); 173206#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 173432#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 172432#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 173956#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 173838#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 173619#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 173327#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 173328#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 172490#L1928-2 [2021-12-19 19:17:02,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,598 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2021-12-19 19:17:02,598 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254142005] [2021-12-19 19:17:02,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,599 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254142005] [2021-12-19 19:17:02,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254142005] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623585417] [2021-12-19 19:17:02,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,642 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1768006235, now seen corresponding path program 1 times [2021-12-19 19:17:02,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181918727] [2021-12-19 19:17:02,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,685 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181918727] [2021-12-19 19:17:02,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181918727] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,685 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,685 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,685 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608624504] [2021-12-19 19:17:02,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,686 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,686 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,687 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:02,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:02,687 INFO L87 Difference]: Start difference. First operand 13928 states and 20099 transitions. cyclomatic complexity: 6173 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:03,076 INFO L93 Difference]: Finished difference Result 33480 states and 48043 transitions. [2021-12-19 19:17:03,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:03,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33480 states and 48043 transitions. [2021-12-19 19:17:03,237 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 33269 [2021-12-19 19:17:03,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33480 states to 33480 states and 48043 transitions. [2021-12-19 19:17:03,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33480 [2021-12-19 19:17:03,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33480 [2021-12-19 19:17:03,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33480 states and 48043 transitions. [2021-12-19 19:17:03,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:03,551 INFO L681 BuchiCegarLoop]: Abstraction has 33480 states and 48043 transitions. [2021-12-19 19:17:03,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33480 states and 48043 transitions. [2021-12-19 19:17:04,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33480 to 26731. [2021-12-19 19:17:04,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26731 states, 26731 states have (on average 1.4378811118177397) internal successors, (38436), 26730 states have internal predecessors, (38436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:04,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26731 states to 26731 states and 38436 transitions. [2021-12-19 19:17:04,217 INFO L704 BuchiCegarLoop]: Abstraction has 26731 states and 38436 transitions. [2021-12-19 19:17:04,217 INFO L587 BuchiCegarLoop]: Abstraction has 26731 states and 38436 transitions. [2021-12-19 19:17:04,217 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:04,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26731 states and 38436 transitions. [2021-12-19 19:17:04,426 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26548 [2021-12-19 19:17:04,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:04,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:04,430 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:04,430 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:04,430 INFO L791 eck$LassoCheckResult]: Stem: 220130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 220131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 221288#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 220638#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 220639#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 220110#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220111#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 220178#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220179#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220636#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 220637#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 220145#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 219960#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 219961#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 220416#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 220417#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 220291#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 220292#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 219927#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 219928#L1279 assume !(0 == ~M_E~0); 221279#L1279-2 assume !(0 == ~T1_E~0); 219547#L1284-1 assume !(0 == ~T2_E~0); 219548#L1289-1 assume !(0 == ~T3_E~0); 220283#L1294-1 assume !(0 == ~T4_E~0); 220284#L1299-1 assume !(0 == ~T5_E~0); 220295#L1304-1 assume !(0 == ~T6_E~0); 221403#L1309-1 assume !(0 == ~T7_E~0); 221405#L1314-1 assume !(0 == ~T8_E~0); 219481#L1319-1 assume !(0 == ~T9_E~0); 219482#L1324-1 assume !(0 == ~T10_E~0); 219651#L1329-1 assume !(0 == ~T11_E~0); 219652#L1334-1 assume !(0 == ~T12_E~0); 221159#L1339-1 assume !(0 == ~T13_E~0); 221265#L1344-1 assume !(0 == ~E_M~0); 221266#L1349-1 assume !(0 == ~E_1~0); 220479#L1354-1 assume !(0 == ~E_2~0); 220480#L1359-1 assume !(0 == ~E_3~0); 220946#L1364-1 assume !(0 == ~E_4~0); 219784#L1369-1 assume !(0 == ~E_5~0); 219785#L1374-1 assume !(0 == ~E_6~0); 220485#L1379-1 assume !(0 == ~E_7~0); 220486#L1384-1 assume !(0 == ~E_8~0); 220567#L1389-1 assume !(0 == ~E_9~0); 221183#L1394-1 assume !(0 == ~E_10~0); 221184#L1399-1 assume !(0 == ~E_11~0); 221327#L1404-1 assume !(0 == ~E_12~0); 219876#L1409-1 assume !(0 == ~E_13~0); 219877#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221313#L628 assume !(1 == ~m_pc~0); 219781#L628-2 is_master_triggered_~__retres1~0#1 := 0; 219780#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220565#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220566#L1591 assume !(0 != activate_threads_~tmp~1#1); 221334#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220340#L647 assume !(1 == ~t1_pc~0); 220341#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 220401#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219975#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219976#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 221251#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221252#L666 assume !(1 == ~t2_pc~0); 221308#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 219716#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219717#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221268#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 220690#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220691#L685 assume !(1 == ~t3_pc~0); 220808#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 220879#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221345#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220533#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 220534#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220002#L704 assume !(1 == ~t4_pc~0); 220003#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220545#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220546#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221293#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 220397#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220398#L723 assume !(1 == ~t5_pc~0); 220528#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 220780#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220941#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220671#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 220672#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 219766#L742 assume 1 == ~t6_pc~0; 219767#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 219913#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 219914#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 219451#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 219452#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 219843#L761 assume !(1 == ~t7_pc~0); 219844#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 219710#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 219711#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220536#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 220537#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 219473#L780 assume 1 == ~t8_pc~0; 219474#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 219752#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219753#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 220494#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 220495#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220621#L799 assume 1 == ~t9_pc~0; 220742#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 219476#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 219477#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 220630#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 220858#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 220649#L818 assume !(1 == ~t10_pc~0); 219261#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 219262#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 220733#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 220652#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 220653#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 220699#L837 assume 1 == ~t11_pc~0; 220700#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 220524#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 220967#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 220611#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 220612#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 220355#L856 assume !(1 == ~t12_pc~0); 220356#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 221072#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 221073#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 221049#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 221050#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 221283#L875 assume 1 == ~t13_pc~0; 220293#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 219916#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 219917#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 219858#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 219859#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 220728#L1427 assume !(1 == ~M_E~0); 220713#L1427-2 assume !(1 == ~T1_E~0); 219830#L1432-1 assume !(1 == ~T2_E~0); 219831#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 220957#L1442-1 assume !(1 == ~T4_E~0); 220958#L1447-1 assume !(1 == ~T5_E~0); 220793#L1452-1 assume !(1 == ~T6_E~0); 219393#L1457-1 assume !(1 == ~T7_E~0); 219394#L1462-1 assume !(1 == ~T8_E~0); 220986#L1467-1 assume !(1 == ~T9_E~0); 221004#L1472-1 assume !(1 == ~T10_E~0); 221005#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 220726#L1482-1 assume !(1 == ~T12_E~0); 220727#L1487-1 assume !(1 == ~T13_E~0); 219725#L1492-1 assume !(1 == ~E_M~0); 219726#L1497-1 assume !(1 == ~E_1~0); 220090#L1502-1 assume !(1 == ~E_2~0); 220091#L1507-1 assume !(1 == ~E_3~0); 219600#L1512-1 assume !(1 == ~E_4~0); 219601#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 221098#L1522-1 assume !(1 == ~E_6~0); 220338#L1527-1 assume !(1 == ~E_7~0); 220339#L1532-1 assume !(1 == ~E_8~0); 221372#L1537-1 assume !(1 == ~E_9~0); 220554#L1542-1 assume !(1 == ~E_10~0); 220376#L1547-1 assume !(1 == ~E_11~0); 220377#L1552-1 assume !(1 == ~E_12~0); 219299#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 219300#L1562-1 assume { :end_inline_reset_delta_events } true; 219904#L1928-2 [2021-12-19 19:17:04,431 INFO L793 eck$LassoCheckResult]: Loop: 219904#L1928-2 assume !false; 240797#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 240792#L1254 assume !false; 240791#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 240748#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 240732#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 240724#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 240645#L1067 assume !(0 != eval_~tmp~0#1); 240646#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245938#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245937#L1279-3 assume !(0 == ~M_E~0); 245936#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 245935#L1284-3 assume !(0 == ~T2_E~0); 245934#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 245933#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 245932#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 245931#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 245930#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 245929#L1314-3 assume !(0 == ~T8_E~0); 245928#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 245925#L1324-3 assume !(0 == ~T10_E~0); 219597#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 219598#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 245910#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 245909#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 245903#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 245902#L1354-3 assume !(0 == ~E_2~0); 245901#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221401#L1364-3 assume !(0 == ~E_4~0); 221402#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221213#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 221214#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221114#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 219946#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 219947#L1394-3 assume !(0 == ~E_10~0); 221421#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 221227#L1404-3 assume !(0 == ~E_12~0); 221171#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 221172#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220579#L628-45 assume !(1 == ~m_pc~0); 220243#L628-47 is_master_triggered_~__retres1~0#1 := 0; 220244#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219591#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 219592#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 219985#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220734#L647-45 assume !(1 == ~t1_pc~0); 220735#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 220490#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220491#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219659#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 219660#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219872#L666-45 assume !(1 == ~t2_pc~0); 219873#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 220363#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220974#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220871#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 220866#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 219409#L685-45 assume !(1 == ~t3_pc~0); 219411#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 221190#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245881#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221096#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 221097#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221282#L704-45 assume !(1 == ~t4_pc~0); 219275#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 219276#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220140#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220496#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 221428#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220613#L723-45 assume 1 == ~t5_pc~0; 220615#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 221185#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220188#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 219962#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 219963#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221057#L742-45 assume 1 == ~t6_pc~0; 221058#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 220215#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220705#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 220744#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220745#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220840#L761-45 assume 1 == ~t7_pc~0; 220842#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 220208#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220209#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 219604#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 219605#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221174#L780-45 assume 1 == ~t8_pc~0; 219987#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 219616#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219617#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221370#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 219586#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 219587#L799-45 assume !(1 == ~t9_pc~0); 219810#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 219811#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221250#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 220791#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 220792#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 219522#L818-45 assume 1 == ~t10_pc~0; 219523#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 219643#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 220764#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 220137#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 220138#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 220894#L837-45 assume !(1 == ~t11_pc~0); 220066#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 220067#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 220917#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 220918#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 219665#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 219666#L856-45 assume !(1 == ~t12_pc~0); 219667#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 219668#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 219606#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 219607#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 220487#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 220488#L875-45 assume 1 == ~t13_pc~0; 220459#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 220460#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 220522#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 221237#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 221238#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221157#L1427-3 assume !(1 == ~M_E~0); 221158#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 245793#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 245791#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 245789#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 245545#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 245544#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 245543#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 245542#L1462-3 assume !(1 == ~T8_E~0); 245540#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 245397#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 244643#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 244642#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 244641#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 244640#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 244639#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 244638#L1502-3 assume !(1 == ~E_2~0); 244637#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 244635#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 244634#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 244633#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 244632#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 244631#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 244587#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 244586#L1542-3 assume !(1 == ~E_10~0); 244585#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 244584#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 244583#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 244582#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 241525#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 241510#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 241508#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 241506#L1947 assume !(0 == start_simulation_~tmp~3#1); 241503#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 240828#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 240814#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 240812#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 240810#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 240808#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240806#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 240800#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 219904#L1928-2 [2021-12-19 19:17:04,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:04,431 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2021-12-19 19:17:04,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:04,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953794433] [2021-12-19 19:17:04,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:04,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:04,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:04,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:04,472 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:04,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953794433] [2021-12-19 19:17:04,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953794433] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:04,473 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:04,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:04,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951509124] [2021-12-19 19:17:04,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:04,474 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:04,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:04,474 INFO L85 PathProgramCache]: Analyzing trace with hash 118330026, now seen corresponding path program 1 times [2021-12-19 19:17:04,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:04,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882517074] [2021-12-19 19:17:04,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:04,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:04,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:04,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:04,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:04,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882517074] [2021-12-19 19:17:04,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882517074] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:04,508 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:04,508 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:04,508 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684842489] [2021-12-19 19:17:04,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:04,508 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:04,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:04,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:04,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:04,509 INFO L87 Difference]: Start difference. First operand 26731 states and 38436 transitions. cyclomatic complexity: 11707 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:04,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:04,893 INFO L93 Difference]: Finished difference Result 64218 states and 91853 transitions. [2021-12-19 19:17:04,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:04,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64218 states and 91853 transitions. [2021-12-19 19:17:05,609 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 63972 [2021-12-19 19:17:05,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64218 states to 64218 states and 91853 transitions. [2021-12-19 19:17:05,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64218 [2021-12-19 19:17:05,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64218 [2021-12-19 19:17:05,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64218 states and 91853 transitions. [2021-12-19 19:17:05,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:05,922 INFO L681 BuchiCegarLoop]: Abstraction has 64218 states and 91853 transitions. [2021-12-19 19:17:05,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64218 states and 91853 transitions. [2021-12-19 19:17:06,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64218 to 51406. [2021-12-19 19:17:06,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51406 states, 51406 states have (on average 1.4330817414309613) internal successors, (73669), 51405 states have internal predecessors, (73669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:06,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51406 states to 51406 states and 73669 transitions. [2021-12-19 19:17:06,939 INFO L704 BuchiCegarLoop]: Abstraction has 51406 states and 73669 transitions. [2021-12-19 19:17:06,939 INFO L587 BuchiCegarLoop]: Abstraction has 51406 states and 73669 transitions. [2021-12-19 19:17:06,939 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:06,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51406 states and 73669 transitions. [2021-12-19 19:17:07,081 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51216 [2021-12-19 19:17:07,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:07,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:07,085 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:07,085 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:07,086 INFO L791 eck$LassoCheckResult]: Stem: 311086#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 311087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 312271#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 311611#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 311612#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 311068#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 311069#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 311132#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 311133#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 311609#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 311610#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 311101#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 310917#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 310918#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 311381#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 311382#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 311253#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 311254#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 310884#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 310885#L1279 assume !(0 == ~M_E~0); 312263#L1279-2 assume !(0 == ~T1_E~0); 310507#L1284-1 assume !(0 == ~T2_E~0); 310508#L1289-1 assume !(0 == ~T3_E~0); 311245#L1294-1 assume !(0 == ~T4_E~0); 311246#L1299-1 assume !(0 == ~T5_E~0); 311257#L1304-1 assume !(0 == ~T6_E~0); 312401#L1309-1 assume !(0 == ~T7_E~0); 312404#L1314-1 assume !(0 == ~T8_E~0); 310441#L1319-1 assume !(0 == ~T9_E~0); 310442#L1324-1 assume !(0 == ~T10_E~0); 310611#L1329-1 assume !(0 == ~T11_E~0); 310612#L1334-1 assume !(0 == ~T12_E~0); 312132#L1339-1 assume !(0 == ~T13_E~0); 312247#L1344-1 assume !(0 == ~E_M~0); 312248#L1349-1 assume !(0 == ~E_1~0); 311448#L1354-1 assume !(0 == ~E_2~0); 311449#L1359-1 assume !(0 == ~E_3~0); 311927#L1364-1 assume !(0 == ~E_4~0); 310742#L1369-1 assume !(0 == ~E_5~0); 310743#L1374-1 assume !(0 == ~E_6~0); 311454#L1379-1 assume !(0 == ~E_7~0); 311455#L1384-1 assume !(0 == ~E_8~0); 311534#L1389-1 assume !(0 == ~E_9~0); 312160#L1394-1 assume !(0 == ~E_10~0); 312161#L1399-1 assume !(0 == ~E_11~0); 312315#L1404-1 assume !(0 == ~E_12~0); 310834#L1409-1 assume !(0 == ~E_13~0); 310835#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312296#L628 assume !(1 == ~m_pc~0); 310739#L628-2 is_master_triggered_~__retres1~0#1 := 0; 310738#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 311532#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 311533#L1591 assume !(0 != activate_threads_~tmp~1#1); 312323#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 311303#L647 assume !(1 == ~t1_pc~0); 311304#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 311366#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310933#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 310934#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 312231#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312232#L666 assume !(1 == ~t2_pc~0); 312290#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 310675#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 310676#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 312251#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 311662#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 311663#L685 assume !(1 == ~t3_pc~0); 311780#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 311852#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312333#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 311500#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 311501#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 310961#L704 assume !(1 == ~t4_pc~0); 310962#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 311512#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311513#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 312278#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 311362#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311363#L723 assume !(1 == ~t5_pc~0); 311496#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 311752#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311922#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 311644#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 311645#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 310725#L742 assume !(1 == ~t6_pc~0); 310726#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 310870#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 310871#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 310409#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 310410#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 310800#L761 assume !(1 == ~t7_pc~0); 310801#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 310669#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 310670#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 311503#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 311504#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 310433#L780 assume 1 == ~t8_pc~0; 310434#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 310711#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 310712#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 311462#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 311463#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 311592#L799 assume 1 == ~t9_pc~0; 311714#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 310436#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 310437#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 311601#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 311831#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 311622#L818 assume !(1 == ~t10_pc~0); 310220#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 310221#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 311705#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 311625#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 311626#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311671#L837 assume 1 == ~t11_pc~0; 311672#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 311492#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 311947#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 311582#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 311583#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 311318#L856 assume !(1 == ~t12_pc~0); 311319#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 312049#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 312050#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 312026#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 312027#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 312266#L875 assume 1 == ~t13_pc~0; 311255#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 310873#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 310874#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 310815#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 310816#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311700#L1427 assume !(1 == ~M_E~0); 311685#L1427-2 assume !(1 == ~T1_E~0); 310787#L1432-1 assume !(1 == ~T2_E~0); 310788#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 311935#L1442-1 assume !(1 == ~T4_E~0); 311936#L1447-1 assume !(1 == ~T5_E~0); 311765#L1452-1 assume !(1 == ~T6_E~0); 310352#L1457-1 assume !(1 == ~T7_E~0); 310353#L1462-1 assume !(1 == ~T8_E~0); 311967#L1467-1 assume !(1 == ~T9_E~0); 311985#L1472-1 assume !(1 == ~T10_E~0); 311986#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 311698#L1482-1 assume !(1 == ~T12_E~0); 311699#L1487-1 assume !(1 == ~T13_E~0); 310684#L1492-1 assume !(1 == ~E_M~0); 310685#L1497-1 assume !(1 == ~E_1~0); 311048#L1502-1 assume !(1 == ~E_2~0); 311049#L1507-1 assume !(1 == ~E_3~0); 310560#L1512-1 assume !(1 == ~E_4~0); 310561#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 312074#L1522-1 assume !(1 == ~E_6~0); 311301#L1527-1 assume !(1 == ~E_7~0); 311302#L1532-1 assume !(1 == ~E_8~0); 312363#L1537-1 assume !(1 == ~E_9~0); 311521#L1542-1 assume !(1 == ~E_10~0); 311341#L1547-1 assume !(1 == ~E_11~0); 311342#L1552-1 assume !(1 == ~E_12~0); 310258#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 310259#L1562-1 assume { :end_inline_reset_delta_events } true; 310861#L1928-2 [2021-12-19 19:17:07,086 INFO L793 eck$LassoCheckResult]: Loop: 310861#L1928-2 assume !false; 357694#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 357688#L1254 assume !false; 357686#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 340964#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 340954#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 340951#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 340947#L1067 assume !(0 != eval_~tmp~0#1); 340948#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 358026#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 358023#L1279-3 assume !(0 == ~M_E~0); 358021#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 358019#L1284-3 assume !(0 == ~T2_E~0); 358017#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 358015#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 358013#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 358010#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 358008#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 358006#L1314-3 assume !(0 == ~T8_E~0); 358004#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 358002#L1324-3 assume !(0 == ~T10_E~0); 358000#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 357997#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 357995#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 357993#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 357991#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 357989#L1354-3 assume !(0 == ~E_2~0); 357987#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 357984#L1364-3 assume !(0 == ~E_4~0); 357982#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 357980#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 357978#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 357976#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 357974#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 357971#L1394-3 assume !(0 == ~E_10~0); 357969#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 357967#L1404-3 assume !(0 == ~E_12~0); 357965#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 357963#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 357962#L628-45 assume 1 == ~m_pc~0; 357961#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 357956#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357954#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 357952#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 357951#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 357946#L647-45 assume !(1 == ~t1_pc~0); 357941#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 357936#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357935#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 357934#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 357933#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357932#L666-45 assume !(1 == ~t2_pc~0); 354702#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 357931#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 357930#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 357929#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 357928#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 357927#L685-45 assume !(1 == ~t3_pc~0); 357925#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 357923#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357921#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 357920#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 357918#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357917#L704-45 assume !(1 == ~t4_pc~0); 347892#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 357916#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357915#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357914#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 357913#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 357912#L723-45 assume !(1 == ~t5_pc~0); 357911#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 357908#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 357906#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 357904#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 357902#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 357900#L742-45 assume !(1 == ~t6_pc~0); 322391#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 357897#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 357895#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 357893#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 357891#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 357889#L761-45 assume !(1 == ~t7_pc~0); 357887#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 357884#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357882#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 357880#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 357878#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 357876#L780-45 assume 1 == ~t8_pc~0; 357873#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 357871#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 357869#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 357867#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 357865#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 357863#L799-45 assume 1 == ~t9_pc~0; 357861#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 357858#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 357856#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 357855#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 357854#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 357853#L818-45 assume !(1 == ~t10_pc~0); 357852#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 357850#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 357849#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 357848#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 357847#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 357846#L837-45 assume 1 == ~t11_pc~0; 357845#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 357843#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 357842#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 357841#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 357840#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 357839#L856-45 assume 1 == ~t12_pc~0; 357837#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 357836#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 357835#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 357834#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 357833#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 357832#L875-45 assume !(1 == ~t13_pc~0); 357829#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 357827#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 357825#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 357823#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 357821#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 357819#L1427-3 assume !(1 == ~M_E~0); 312131#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 357815#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 357813#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 357811#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 357809#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 357807#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 357804#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 357802#L1462-3 assume !(1 == ~T8_E~0); 357800#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 357798#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 357796#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 357794#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 357791#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 357789#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 357787#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 357785#L1502-3 assume !(1 == ~E_2~0); 357783#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 357781#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 357778#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 357776#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 357774#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 357772#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 357770#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 357768#L1542-3 assume !(1 == ~E_10~0); 357765#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 357763#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 357761#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 357759#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 357751#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 357737#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 357735#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 357733#L1947 assume !(0 == start_simulation_~tmp~3#1); 357729#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 357723#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 357709#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 357706#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 357704#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 357702#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 357700#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 357698#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 310861#L1928-2 [2021-12-19 19:17:07,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:07,087 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2021-12-19 19:17:07,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:07,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453759792] [2021-12-19 19:17:07,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:07,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:07,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:07,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:07,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:07,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453759792] [2021-12-19 19:17:07,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453759792] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:07,125 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:07,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:07,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447294077] [2021-12-19 19:17:07,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:07,126 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:07,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:07,126 INFO L85 PathProgramCache]: Analyzing trace with hash 728513835, now seen corresponding path program 1 times [2021-12-19 19:17:07,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:07,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431942084] [2021-12-19 19:17:07,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:07,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:07,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:07,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:07,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:07,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431942084] [2021-12-19 19:17:07,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431942084] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:07,331 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:07,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:07,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969469301] [2021-12-19 19:17:07,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:07,332 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:07,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:07,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:07,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:07,333 INFO L87 Difference]: Start difference. First operand 51406 states and 73669 transitions. cyclomatic complexity: 22265 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:08,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:08,029 INFO L93 Difference]: Finished difference Result 123169 states and 175630 transitions. [2021-12-19 19:17:08,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:08,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123169 states and 175630 transitions. [2021-12-19 19:17:08,704 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 122852 [2021-12-19 19:17:09,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123169 states to 123169 states and 175630 transitions. [2021-12-19 19:17:09,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123169 [2021-12-19 19:17:09,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123169 [2021-12-19 19:17:09,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123169 states and 175630 transitions. [2021-12-19 19:17:09,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:09,331 INFO L681 BuchiCegarLoop]: Abstraction has 123169 states and 175630 transitions. [2021-12-19 19:17:09,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123169 states and 175630 transitions. [2021-12-19 19:17:10,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123169 to 98909. [2021-12-19 19:17:10,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98909 states, 98909 states have (on average 1.428565651255194) internal successors, (141298), 98908 states have internal predecessors, (141298), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:10,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98909 states to 98909 states and 141298 transitions. [2021-12-19 19:17:10,959 INFO L704 BuchiCegarLoop]: Abstraction has 98909 states and 141298 transitions. [2021-12-19 19:17:10,959 INFO L587 BuchiCegarLoop]: Abstraction has 98909 states and 141298 transitions. [2021-12-19 19:17:10,959 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:17:10,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98909 states and 141298 transitions. [2021-12-19 19:17:11,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 98704 [2021-12-19 19:17:11,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:11,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:11,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:11,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:11,551 INFO L791 eck$LassoCheckResult]: Stem: 485676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 485677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 486928#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 486215#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 486216#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 485658#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 485659#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 485730#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 485731#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 486211#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 486212#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 485694#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 485505#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 485506#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 485978#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 485979#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 485848#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 485849#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 485471#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 485472#L1279 assume !(0 == ~M_E~0); 486917#L1279-2 assume !(0 == ~T1_E~0); 485093#L1284-1 assume !(0 == ~T2_E~0); 485094#L1289-1 assume !(0 == ~T3_E~0); 485845#L1294-1 assume !(0 == ~T4_E~0); 485846#L1299-1 assume !(0 == ~T5_E~0); 485857#L1304-1 assume !(0 == ~T6_E~0); 487082#L1309-1 assume !(0 == ~T7_E~0); 487085#L1314-1 assume !(0 == ~T8_E~0); 485025#L1319-1 assume !(0 == ~T9_E~0); 485026#L1324-1 assume !(0 == ~T10_E~0); 485197#L1329-1 assume !(0 == ~T11_E~0); 485198#L1334-1 assume !(0 == ~T12_E~0); 486776#L1339-1 assume !(0 == ~T13_E~0); 486901#L1344-1 assume !(0 == ~E_M~0); 486902#L1349-1 assume !(0 == ~E_1~0); 486045#L1354-1 assume !(0 == ~E_2~0); 486046#L1359-1 assume !(0 == ~E_3~0); 486544#L1364-1 assume !(0 == ~E_4~0); 485329#L1369-1 assume !(0 == ~E_5~0); 485330#L1374-1 assume !(0 == ~E_6~0); 486050#L1379-1 assume !(0 == ~E_7~0); 486051#L1384-1 assume !(0 == ~E_8~0); 486139#L1389-1 assume !(0 == ~E_9~0); 486805#L1394-1 assume !(0 == ~E_10~0); 486806#L1399-1 assume !(0 == ~E_11~0); 486971#L1404-1 assume !(0 == ~E_12~0); 485419#L1409-1 assume !(0 == ~E_13~0); 485420#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486957#L628 assume !(1 == ~m_pc~0); 485326#L628-2 is_master_triggered_~__retres1~0#1 := 0; 485325#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486137#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486138#L1591 assume !(0 != activate_threads_~tmp~1#1); 486989#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 485902#L647 assume !(1 == ~t1_pc~0); 485903#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 485963#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 485520#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 485521#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 486883#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486884#L666 assume !(1 == ~t2_pc~0); 486947#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 485256#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 485257#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486905#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 486267#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486268#L685 assume !(1 == ~t3_pc~0); 486389#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 486466#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487003#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 486104#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 486105#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485549#L704 assume !(1 == ~t4_pc~0); 485550#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 486118#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486119#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 486936#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 485959#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 485960#L723 assume !(1 == ~t5_pc~0); 486097#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 486357#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486539#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 486246#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 486247#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 485310#L742 assume !(1 == ~t6_pc~0); 485311#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 485457#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 485458#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 484994#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 484995#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 485387#L761 assume !(1 == ~t7_pc~0); 485388#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 485252#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 485253#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 486106#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 486107#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 485020#L780 assume !(1 == ~t8_pc~0); 485021#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 485294#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 485295#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 486059#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 486060#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 486194#L799 assume 1 == ~t9_pc~0; 486319#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 485022#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 485023#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 486207#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 486441#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 486226#L818 assume !(1 == ~t10_pc~0); 484805#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 484806#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 486311#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486230#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 486231#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 486276#L837 assume 1 == ~t11_pc~0; 486277#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 486094#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 486570#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 486186#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 486187#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 485912#L856 assume !(1 == ~t12_pc~0); 485913#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 486679#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 486680#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 486655#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 486656#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 486921#L875 assume 1 == ~t13_pc~0; 485855#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 485460#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 485461#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 485402#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 485403#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486308#L1427 assume !(1 == ~M_E~0); 486289#L1427-2 assume !(1 == ~T1_E~0); 485375#L1432-1 assume !(1 == ~T2_E~0); 485376#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 486557#L1442-1 assume !(1 == ~T4_E~0); 486558#L1447-1 assume !(1 == ~T5_E~0); 486372#L1452-1 assume !(1 == ~T6_E~0); 484939#L1457-1 assume !(1 == ~T7_E~0); 484940#L1462-1 assume !(1 == ~T8_E~0); 486593#L1467-1 assume !(1 == ~T9_E~0); 486614#L1472-1 assume !(1 == ~T10_E~0); 486615#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 486306#L1482-1 assume !(1 == ~T12_E~0); 486307#L1487-1 assume !(1 == ~T13_E~0); 485267#L1492-1 assume !(1 == ~E_M~0); 485268#L1497-1 assume !(1 == ~E_1~0); 485639#L1502-1 assume !(1 == ~E_2~0); 485640#L1507-1 assume !(1 == ~E_3~0); 485146#L1512-1 assume !(1 == ~E_4~0); 485147#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 486706#L1522-1 assume !(1 == ~E_6~0); 485898#L1527-1 assume !(1 == ~E_7~0); 485899#L1532-1 assume !(1 == ~E_8~0); 487038#L1537-1 assume !(1 == ~E_9~0); 486125#L1542-1 assume !(1 == ~E_10~0); 485937#L1547-1 assume !(1 == ~E_11~0); 485938#L1552-1 assume !(1 == ~E_12~0); 484843#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 484844#L1562-1 assume { :end_inline_reset_delta_events } true; 485448#L1928-2 [2021-12-19 19:17:11,552 INFO L793 eck$LassoCheckResult]: Loop: 485448#L1928-2 assume !false; 485972#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 485101#L1254 assume !false; 485702#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 485176#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 485177#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 485377#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 486688#L1067 assume !(0 != eval_~tmp~0#1); 486689#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581281#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 581277#L1279-3 assume !(0 == ~M_E~0); 581275#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 581273#L1284-3 assume !(0 == ~T2_E~0); 581271#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 581268#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 581266#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 581265#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 581261#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 581258#L1314-3 assume !(0 == ~T8_E~0); 581256#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 581254#L1324-3 assume !(0 == ~T10_E~0); 581252#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 581250#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 581246#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 581243#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 581240#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 581238#L1354-3 assume !(0 == ~E_2~0); 581235#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 581233#L1364-3 assume !(0 == ~E_4~0); 581232#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 581231#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 581229#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 581227#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 581224#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 581222#L1394-3 assume !(0 == ~E_10~0); 581220#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 581219#L1404-3 assume !(0 == ~E_12~0); 581218#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 581217#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 581216#L628-45 assume !(1 == ~m_pc~0); 581214#L628-47 is_master_triggered_~__retres1~0#1 := 0; 581213#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581212#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 581211#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 581210#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 581208#L647-45 assume !(1 == ~t1_pc~0); 581209#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 581673#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 581670#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 581668#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 581666#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 485415#L666-45 assume !(1 == ~t2_pc~0); 485416#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 485925#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486579#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486459#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 486453#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486454#L685-45 assume 1 == ~t3_pc~0; 582067#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 582062#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 582056#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 582052#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 486918#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486919#L704-45 assume !(1 == ~t4_pc~0); 484821#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 484822#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 485691#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 486062#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 487127#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486189#L723-45 assume 1 == ~t5_pc~0; 486191#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 486807#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 485740#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 485507#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 485508#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 486666#L742-45 assume !(1 == ~t6_pc~0); 485766#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 485767#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486283#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 486324#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 486325#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486424#L761-45 assume 1 == ~t7_pc~0; 486426#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 485759#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 485760#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 485150#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 485151#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 486798#L780-45 assume !(1 == ~t8_pc~0); 486606#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 485162#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 485163#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 487037#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 485130#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 485131#L799-45 assume 1 == ~t9_pc~0; 485941#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 485357#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 486882#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 486373#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 486374#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 485071#L818-45 assume !(1 == ~t10_pc~0); 485073#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 485189#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 486344#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 485689#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 485690#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 486490#L837-45 assume 1 == ~t11_pc~0; 486899#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 485616#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 485761#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 486511#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 485208#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 485209#L856-45 assume 1 == ~t12_pc~0; 486915#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 485211#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 485152#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 485153#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 486055#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 486056#L875-45 assume !(1 == ~t13_pc~0); 486028#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 486027#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 582877#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 582875#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 582873#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 582870#L1427-3 assume !(1 == ~M_E~0); 573432#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 486924#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 486434#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 486435#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 582839#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 582837#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 582835#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 582834#L1462-3 assume !(1 == ~T8_E~0); 486999#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 486508#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 486509#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 487015#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 485250#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 485251#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 485426#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 485427#L1502-3 assume !(1 == ~E_2~0); 486639#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 486640#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 487099#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 582715#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 487000#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 485120#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 485121#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 486287#L1542-3 assume !(1 == ~E_10~0); 486445#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 486029#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 486030#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 485335#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 485336#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 484755#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 485522#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 485523#L1947 assume !(0 == start_simulation_~tmp~3#1); 486178#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 486407#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 485391#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 486963#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 486847#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 486600#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 486300#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 486301#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 485448#L1928-2 [2021-12-19 19:17:11,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:11,553 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2021-12-19 19:17:11,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:11,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987102863] [2021-12-19 19:17:11,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:11,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:11,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:11,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:11,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:11,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987102863] [2021-12-19 19:17:11,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987102863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:11,594 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:11,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:11,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160339002] [2021-12-19 19:17:11,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:11,595 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:11,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:11,596 INFO L85 PathProgramCache]: Analyzing trace with hash -703701592, now seen corresponding path program 1 times [2021-12-19 19:17:11,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:11,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368626778] [2021-12-19 19:17:11,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:11,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:11,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:11,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:11,639 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:11,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368626778] [2021-12-19 19:17:11,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368626778] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:11,639 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:11,640 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:11,640 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562659421] [2021-12-19 19:17:11,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:11,640 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:11,640 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:11,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:11,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:11,641 INFO L87 Difference]: Start difference. First operand 98909 states and 141298 transitions. cyclomatic complexity: 42391 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:12,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:12,769 INFO L93 Difference]: Finished difference Result 236508 states and 336255 transitions. [2021-12-19 19:17:12,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:12,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236508 states and 336255 transitions. [2021-12-19 19:17:13,872 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236048 [2021-12-19 19:17:14,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236508 states to 236508 states and 336255 transitions. [2021-12-19 19:17:14,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 236508 [2021-12-19 19:17:15,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 236508 [2021-12-19 19:17:15,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236508 states and 336255 transitions. [2021-12-19 19:17:15,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:15,143 INFO L681 BuchiCegarLoop]: Abstraction has 236508 states and 336255 transitions. [2021-12-19 19:17:15,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236508 states and 336255 transitions. [2021-12-19 19:17:16,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236508 to 190252. [2021-12-19 19:17:17,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190252 states, 190252 states have (on average 1.4242951453861195) internal successors, (270975), 190251 states have internal predecessors, (270975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:17,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190252 states to 190252 states and 270975 transitions. [2021-12-19 19:17:17,379 INFO L704 BuchiCegarLoop]: Abstraction has 190252 states and 270975 transitions. [2021-12-19 19:17:17,379 INFO L587 BuchiCegarLoop]: Abstraction has 190252 states and 270975 transitions. [2021-12-19 19:17:17,379 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:17:17,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190252 states and 270975 transitions. [2021-12-19 19:17:18,490 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190016 [2021-12-19 19:17:18,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:18,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:18,502 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:18,502 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:18,503 INFO L791 eck$LassoCheckResult]: Stem: 821103#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 821104#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 822324#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 821634#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 821635#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 821085#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 821086#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 821153#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 821154#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 821630#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 821631#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 821120#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 820934#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 820935#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 821404#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 821405#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 821269#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 821270#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 820900#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 820901#L1279 assume !(0 == ~M_E~0); 822316#L1279-2 assume !(0 == ~T1_E~0); 820520#L1284-1 assume !(0 == ~T2_E~0); 820521#L1289-1 assume !(0 == ~T3_E~0); 821262#L1294-1 assume !(0 == ~T4_E~0); 821263#L1299-1 assume !(0 == ~T5_E~0); 821278#L1304-1 assume !(0 == ~T6_E~0); 822466#L1309-1 assume !(0 == ~T7_E~0); 822468#L1314-1 assume !(0 == ~T8_E~0); 820452#L1319-1 assume !(0 == ~T9_E~0); 820453#L1324-1 assume !(0 == ~T10_E~0); 820625#L1329-1 assume !(0 == ~T11_E~0); 820626#L1334-1 assume !(0 == ~T12_E~0); 822173#L1339-1 assume !(0 == ~T13_E~0); 822300#L1344-1 assume !(0 == ~E_M~0); 822301#L1349-1 assume !(0 == ~E_1~0); 821469#L1354-1 assume !(0 == ~E_2~0); 821470#L1359-1 assume !(0 == ~E_3~0); 821955#L1364-1 assume !(0 == ~E_4~0); 820756#L1369-1 assume !(0 == ~E_5~0); 820757#L1374-1 assume !(0 == ~E_6~0); 821474#L1379-1 assume !(0 == ~E_7~0); 821475#L1384-1 assume !(0 == ~E_8~0); 821562#L1389-1 assume !(0 == ~E_9~0); 822204#L1394-1 assume !(0 == ~E_10~0); 822205#L1399-1 assume !(0 == ~E_11~0); 822368#L1404-1 assume !(0 == ~E_12~0); 820846#L1409-1 assume !(0 == ~E_13~0); 820847#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 822351#L628 assume !(1 == ~m_pc~0); 820753#L628-2 is_master_triggered_~__retres1~0#1 := 0; 820752#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 821560#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 821561#L1591 assume !(0 != activate_threads_~tmp~1#1); 822377#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 821323#L647 assume !(1 == ~t1_pc~0); 821324#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 821389#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 820949#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 820950#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 822282#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 822283#L666 assume !(1 == ~t2_pc~0); 822339#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 820684#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 820685#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 822305#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 821686#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 821687#L685 assume !(1 == ~t3_pc~0); 821802#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 821875#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 822389#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 821528#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 821529#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 820979#L704 assume !(1 == ~t4_pc~0); 820980#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 821540#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 821541#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 822330#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 821385#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 821386#L723 assume !(1 == ~t5_pc~0); 821522#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 821773#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 821950#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 821665#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 821666#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 820738#L742 assume !(1 == ~t6_pc~0); 820739#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 820886#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 820887#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 820422#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 820423#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 820814#L761 assume !(1 == ~t7_pc~0); 820815#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 820680#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 820681#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 821530#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 821531#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 820449#L780 assume !(1 == ~t8_pc~0); 820450#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 820722#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 820723#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 821484#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 821485#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 821613#L799 assume !(1 == ~t9_pc~0); 820958#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 820447#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 820448#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 821626#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 821854#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 821644#L818 assume !(1 == ~t10_pc~0); 820234#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 820235#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 821730#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 821648#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 821649#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 821695#L837 assume 1 == ~t11_pc~0; 821696#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 821519#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 821977#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 821606#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 821607#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 821334#L856 assume !(1 == ~t12_pc~0); 821335#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 822086#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 822087#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 822061#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 822062#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 822319#L875 assume 1 == ~t13_pc~0; 821276#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 820889#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 820890#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 820829#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 820830#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 821727#L1427 assume !(1 == ~M_E~0); 821707#L1427-2 assume !(1 == ~T1_E~0); 820802#L1432-1 assume !(1 == ~T2_E~0); 820803#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 821964#L1442-1 assume !(1 == ~T4_E~0); 821965#L1447-1 assume !(1 == ~T5_E~0); 821787#L1452-1 assume !(1 == ~T6_E~0); 820367#L1457-1 assume !(1 == ~T7_E~0); 820368#L1462-1 assume !(1 == ~T8_E~0); 821998#L1467-1 assume !(1 == ~T9_E~0); 822020#L1472-1 assume !(1 == ~T10_E~0); 822021#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 821725#L1482-1 assume !(1 == ~T12_E~0); 821726#L1487-1 assume !(1 == ~T13_E~0); 820695#L1492-1 assume !(1 == ~E_M~0); 820696#L1497-1 assume !(1 == ~E_1~0); 821066#L1502-1 assume !(1 == ~E_2~0); 821067#L1507-1 assume !(1 == ~E_3~0); 820575#L1512-1 assume !(1 == ~E_4~0); 820576#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 822117#L1522-1 assume !(1 == ~E_6~0); 821319#L1527-1 assume !(1 == ~E_7~0); 821320#L1532-1 assume !(1 == ~E_8~0); 822421#L1537-1 assume !(1 == ~E_9~0); 821547#L1542-1 assume !(1 == ~E_10~0); 821360#L1547-1 assume !(1 == ~E_11~0); 821361#L1552-1 assume !(1 == ~E_12~0); 820271#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 820272#L1562-1 assume { :end_inline_reset_delta_events } true; 820877#L1928-2 [2021-12-19 19:17:18,503 INFO L793 eck$LassoCheckResult]: Loop: 820877#L1928-2 assume !false; 957760#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 957754#L1254 assume !false; 957752#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 957737#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 957727#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 957725#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 957722#L1067 assume !(0 != eval_~tmp~0#1); 957723#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1010392#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1010377#L1279-3 assume !(0 == ~M_E~0); 1010374#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1010373#L1284-3 assume !(0 == ~T2_E~0); 1010369#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1010366#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1010365#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1010364#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1010350#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1010349#L1314-3 assume !(0 == ~T8_E~0); 1010348#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1010347#L1324-3 assume !(0 == ~T10_E~0); 1010346#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1010345#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1010344#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1010343#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1010342#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 820922#L1354-3 assume !(0 == ~E_2~0); 820923#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 821704#L1364-3 assume !(0 == ~E_4~0); 822416#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 822235#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 820699#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 820700#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 820920#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 820921#L1394-3 assume !(0 == ~E_10~0); 821222#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 822254#L1404-3 assume !(0 == ~E_12~0); 822189#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 822190#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 821575#L628-45 assume !(1 == ~m_pc~0); 821220#L628-47 is_master_triggered_~__retres1~0#1 := 0; 821221#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 820564#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 820565#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 820959#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 821736#L647-45 assume !(1 == ~t1_pc~0); 821737#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 821482#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 821483#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 820631#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 820632#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 820842#L666-45 assume !(1 == ~t2_pc~0); 820843#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 821347#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 821986#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 821869#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 821864#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 820383#L685-45 assume 1 == ~t3_pc~0; 820384#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 821476#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1010361#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1010360#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 822115#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 822317#L704-45 assume !(1 == ~t4_pc~0); 1005815#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1005812#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1005810#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1005808#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1005806#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1005804#L723-45 assume !(1 == ~t5_pc~0); 1005802#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 1005799#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1005797#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1005795#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1005791#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 987382#L742-45 assume !(1 == ~t6_pc~0); 987381#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 987378#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 987376#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 987374#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 987372#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 987370#L761-45 assume !(1 == ~t7_pc~0); 987368#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 987344#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 987335#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 987326#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 987317#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 958012#L780-45 assume !(1 == ~t8_pc~0); 958010#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 958007#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 958005#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 958003#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 958001#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 957999#L799-45 assume !(1 == ~t9_pc~0); 864481#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 957995#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 957993#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 957991#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 957989#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 957987#L818-45 assume 1 == ~t10_pc~0; 957982#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 957979#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 957977#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 957975#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 957973#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 957971#L837-45 assume !(1 == ~t11_pc~0); 957968#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 957967#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 957965#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 957963#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 957961#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 957959#L856-45 assume 1 == ~t12_pc~0; 957956#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 957953#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 957951#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 957949#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 957947#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 957945#L875-45 assume !(1 == ~t13_pc~0); 957942#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 957939#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 957937#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 957935#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 957933#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 957931#L1427-3 assume !(1 == ~M_E~0); 940374#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 957927#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 957925#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 957923#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 957921#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 957919#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 957917#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 957914#L1462-3 assume !(1 == ~T8_E~0); 957912#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 957910#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 957908#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 957906#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 957905#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 957901#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 957899#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 957897#L1502-3 assume !(1 == ~E_2~0); 957896#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 957891#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957886#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 957881#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 957880#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 957878#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 957876#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 957874#L1542-3 assume !(1 == ~E_10~0); 957872#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 957870#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 957868#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 957866#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 957861#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 957847#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 957845#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 957842#L1947 assume !(0 == start_simulation_~tmp~3#1); 957839#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 957794#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 957780#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 957779#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 957774#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 957769#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 957764#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 957763#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 820877#L1928-2 [2021-12-19 19:17:18,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:18,503 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2021-12-19 19:17:18,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:18,504 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247611180] [2021-12-19 19:17:18,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:18,504 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:18,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:18,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:18,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:18,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247611180] [2021-12-19 19:17:18,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247611180] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:18,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:18,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:18,559 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318730463] [2021-12-19 19:17:18,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:18,560 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:18,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:18,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1300253333, now seen corresponding path program 1 times [2021-12-19 19:17:18,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:18,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984050677] [2021-12-19 19:17:18,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:18,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:18,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:18,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:18,601 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:18,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984050677] [2021-12-19 19:17:18,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984050677] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:18,601 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:18,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:18,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279578051] [2021-12-19 19:17:18,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:18,602 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:18,602 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:18,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:18,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:18,603 INFO L87 Difference]: Start difference. First operand 190252 states and 270975 transitions. cyclomatic complexity: 80725 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:20,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:20,545 INFO L93 Difference]: Finished difference Result 443925 states and 637616 transitions. [2021-12-19 19:17:20,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:20,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 443925 states and 637616 transitions. [2021-12-19 19:17:23,101 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 443456 [2021-12-19 19:17:24,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 443925 states to 443925 states and 637616 transitions. [2021-12-19 19:17:24,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 443925 [2021-12-19 19:17:24,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 443925 [2021-12-19 19:17:24,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 443925 states and 637616 transitions. [2021-12-19 19:17:24,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,789 INFO L681 BuchiCegarLoop]: Abstraction has 443925 states and 637616 transitions. [2021-12-19 19:17:24,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443925 states and 637616 transitions. [2021-12-19 19:17:27,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443925 to 195055. [2021-12-19 19:17:27,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195055 states, 195055 states have (on average 1.4138473763810206) internal successors, (275778), 195054 states have internal predecessors, (275778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195055 states to 195055 states and 275778 transitions. [2021-12-19 19:17:28,307 INFO L704 BuchiCegarLoop]: Abstraction has 195055 states and 275778 transitions. [2021-12-19 19:17:28,307 INFO L587 BuchiCegarLoop]: Abstraction has 195055 states and 275778 transitions. [2021-12-19 19:17:28,307 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:17:28,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195055 states and 275778 transitions. [2021-12-19 19:17:28,864 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 194816 [2021-12-19 19:17:28,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,874 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,874 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,875 INFO L791 eck$LassoCheckResult]: Stem: 1455300#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1455301#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1456576#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1455844#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1455845#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1455280#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1455281#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1455349#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1455350#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1455842#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1455843#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1455316#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1455126#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1455127#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1455606#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1455607#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1455471#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1455472#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1455091#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1455092#L1279 assume !(0 == ~M_E~0); 1456567#L1279-2 assume !(0 == ~T1_E~0); 1454711#L1284-1 assume !(0 == ~T2_E~0); 1454712#L1289-1 assume !(0 == ~T3_E~0); 1455462#L1294-1 assume !(0 == ~T4_E~0); 1455463#L1299-1 assume !(0 == ~T5_E~0); 1455475#L1304-1 assume !(0 == ~T6_E~0); 1456723#L1309-1 assume !(0 == ~T7_E~0); 1456727#L1314-1 assume !(0 == ~T8_E~0); 1454643#L1319-1 assume !(0 == ~T9_E~0); 1454644#L1324-1 assume !(0 == ~T10_E~0); 1454814#L1329-1 assume !(0 == ~T11_E~0); 1454815#L1334-1 assume !(0 == ~T12_E~0); 1456421#L1339-1 assume !(0 == ~T13_E~0); 1456547#L1344-1 assume !(0 == ~E_M~0); 1456548#L1349-1 assume !(0 == ~E_1~0); 1455675#L1354-1 assume !(0 == ~E_2~0); 1455676#L1359-1 assume !(0 == ~E_3~0); 1456172#L1364-1 assume !(0 == ~E_4~0); 1454945#L1369-1 assume !(0 == ~E_5~0); 1454946#L1374-1 assume !(0 == ~E_6~0); 1455681#L1379-1 assume !(0 == ~E_7~0); 1455682#L1384-1 assume !(0 == ~E_8~0); 1455771#L1389-1 assume !(0 == ~E_9~0); 1456448#L1394-1 assume !(0 == ~E_10~0); 1456449#L1399-1 assume !(0 == ~E_11~0); 1456615#L1404-1 assume !(0 == ~E_12~0); 1455035#L1409-1 assume !(0 == ~E_13~0); 1455036#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1456599#L628 assume !(1 == ~m_pc~0); 1454942#L628-2 is_master_triggered_~__retres1~0#1 := 0; 1454941#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1455769#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1455770#L1591 assume !(0 != activate_threads_~tmp~1#1); 1456625#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1455520#L647 assume !(1 == ~t1_pc~0); 1455521#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1455590#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1455141#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1455142#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 1456529#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1456530#L666 assume !(1 == ~t2_pc~0); 1456589#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1454877#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1454878#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1456550#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 1455896#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1455897#L685 assume !(1 == ~t3_pc~0); 1456017#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1456092#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1456637#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1455736#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 1455737#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1455172#L704 assume !(1 == ~t4_pc~0); 1455173#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1455749#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1455750#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1456581#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 1455586#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1455587#L723 assume !(1 == ~t5_pc~0); 1455731#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1455989#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1456167#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1455878#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 1455879#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1454929#L742 assume !(1 == ~t6_pc~0); 1454930#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1455077#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1455078#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1454615#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 1454616#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1455003#L761 assume !(1 == ~t7_pc~0); 1455004#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1454871#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1454872#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1455739#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 1455740#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1454638#L780 assume !(1 == ~t8_pc~0); 1454639#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1454915#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1454916#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1455690#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 1455691#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1455826#L799 assume !(1 == ~t9_pc~0); 1455150#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1454636#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1454637#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1455836#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 1456069#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1455856#L818 assume !(1 == ~t10_pc~0); 1454426#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1454427#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1455942#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1455859#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 1455860#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1455905#L837 assume 1 == ~t11_pc~0; 1455906#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1455727#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1456198#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1455816#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 1455817#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1455538#L856 assume !(1 == ~t12_pc~0); 1455539#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1456318#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1456319#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1456289#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 1456290#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1456571#L875 assume 1 == ~t13_pc~0; 1455473#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1455080#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1455081#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1455018#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 1455019#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1455937#L1427 assume !(1 == ~M_E~0); 1455920#L1427-2 assume !(1 == ~T1_E~0); 1454991#L1432-1 assume !(1 == ~T2_E~0); 1454992#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1456185#L1442-1 assume !(1 == ~T4_E~0); 1456186#L1447-1 assume !(1 == ~T5_E~0); 1456002#L1452-1 assume !(1 == ~T6_E~0); 1454558#L1457-1 assume !(1 == ~T7_E~0); 1454559#L1462-1 assume !(1 == ~T8_E~0); 1456222#L1467-1 assume !(1 == ~T9_E~0); 1456250#L1472-1 assume !(1 == ~T10_E~0); 1456251#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1455935#L1482-1 assume !(1 == ~T12_E~0); 1455936#L1487-1 assume !(1 == ~T13_E~0); 1454887#L1492-1 assume !(1 == ~E_M~0); 1454888#L1497-1 assume !(1 == ~E_1~0); 1455261#L1502-1 assume !(1 == ~E_2~0); 1455262#L1507-1 assume !(1 == ~E_3~0); 1454763#L1512-1 assume !(1 == ~E_4~0); 1454764#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1456349#L1522-1 assume !(1 == ~E_6~0); 1455518#L1527-1 assume !(1 == ~E_7~0); 1455519#L1532-1 assume !(1 == ~E_8~0); 1456679#L1537-1 assume !(1 == ~E_9~0); 1455758#L1542-1 assume !(1 == ~E_10~0); 1455564#L1547-1 assume !(1 == ~E_11~0); 1455565#L1552-1 assume !(1 == ~E_12~0); 1454463#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1454464#L1562-1 assume { :end_inline_reset_delta_events } true; 1455067#L1928-2 [2021-12-19 19:17:28,875 INFO L793 eck$LassoCheckResult]: Loop: 1455067#L1928-2 assume !false; 1612291#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1612286#L1254 assume !false; 1612285#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1611928#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1611920#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1611919#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1611917#L1067 assume !(0 != eval_~tmp~0#1); 1611918#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1648837#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1648835#L1279-3 assume !(0 == ~M_E~0); 1648833#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1648831#L1284-3 assume !(0 == ~T2_E~0); 1648829#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1648827#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1648825#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1648823#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1648821#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1648819#L1314-3 assume !(0 == ~T8_E~0); 1648817#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1648815#L1324-3 assume !(0 == ~T10_E~0); 1648813#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1648811#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1648809#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1648807#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1648805#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1648803#L1354-3 assume !(0 == ~E_2~0); 1648801#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1648799#L1364-3 assume !(0 == ~E_4~0); 1648797#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1648795#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1648793#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1648791#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1648789#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1648787#L1394-3 assume !(0 == ~E_10~0); 1648785#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1648282#L1404-3 assume !(0 == ~E_12~0); 1647966#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1646380#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1646378#L628-45 assume 1 == ~m_pc~0; 1646376#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1646375#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1647583#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1647581#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1646364#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1646362#L647-45 assume !(1 == ~t1_pc~0); 1646359#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1646360#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1647567#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1646352#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1646350#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646351#L666-45 assume !(1 == ~t2_pc~0); 1627189#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1647558#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1646405#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1646404#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1646403#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1642409#L685-45 assume !(1 == ~t3_pc~0); 1642405#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1642402#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1642400#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1642398#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 1642395#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1642393#L704-45 assume !(1 == ~t4_pc~0); 1611639#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1642391#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1642388#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1642386#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1642384#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1642382#L723-45 assume 1 == ~t5_pc~0; 1642379#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1642378#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1642374#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1642372#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1642370#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1642368#L742-45 assume !(1 == ~t6_pc~0); 1642066#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1642364#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1642362#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1642361#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1642358#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1642356#L761-45 assume !(1 == ~t7_pc~0); 1642339#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1642335#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1642333#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1642331#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1642329#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1612454#L780-45 assume !(1 == ~t8_pc~0); 1612453#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1612452#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1612451#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1612450#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1612449#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1612448#L799-45 assume !(1 == ~t9_pc~0); 1581899#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1612447#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1612446#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1612445#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612444#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1612443#L818-45 assume 1 == ~t10_pc~0; 1612441#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1612439#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1612437#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1612435#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1612434#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1612433#L837-45 assume !(1 == ~t11_pc~0); 1612431#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1612430#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1612429#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1612428#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1612426#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1612425#L856-45 assume !(1 == ~t12_pc~0); 1612424#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1612422#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1612421#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1612418#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1612416#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1612415#L875-45 assume !(1 == ~t13_pc~0); 1612413#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1612412#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1612411#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1612409#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1612408#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1612407#L1427-3 assume !(1 == ~M_E~0); 1577324#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1612406#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1612404#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1612402#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1612400#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1612398#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1612396#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1612394#L1462-3 assume !(1 == ~T8_E~0); 1612392#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1612390#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1612388#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1612386#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1612384#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1612382#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1612380#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1612378#L1502-3 assume !(1 == ~E_2~0); 1612376#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1612374#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1612372#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1612370#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1612368#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1612366#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1612364#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1612362#L1542-3 assume !(1 == ~E_10~0); 1612360#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1612358#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1612356#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1612354#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1612348#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1612334#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1612332#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1612331#L1947 assume !(0 == start_simulation_~tmp~3#1); 1612329#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1612327#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1612311#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1612309#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1612307#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1612306#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1612301#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1612296#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 1455067#L1928-2 [2021-12-19 19:17:28,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,876 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2021-12-19 19:17:28,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875699027] [2021-12-19 19:17:28,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,877 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,915 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875699027] [2021-12-19 19:17:28,915 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875699027] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,916 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,916 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,916 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39792538] [2021-12-19 19:17:28,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,916 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,917 INFO L85 PathProgramCache]: Analyzing trace with hash -329829523, now seen corresponding path program 1 times [2021-12-19 19:17:28,917 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917662002] [2021-12-19 19:17:28,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,918 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917662002] [2021-12-19 19:17:28,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917662002] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,950 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384720941] [2021-12-19 19:17:28,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,951 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,951 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:28,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:28,952 INFO L87 Difference]: Start difference. First operand 195055 states and 275778 transitions. cyclomatic complexity: 80725 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:31,032 INFO L93 Difference]: Finished difference Result 464126 states and 653295 transitions. [2021-12-19 19:17:31,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:31,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 464126 states and 653295 transitions. [2021-12-19 19:17:33,766 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463376 [2021-12-19 19:17:35,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 464126 states to 464126 states and 653295 transitions. [2021-12-19 19:17:35,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 464126 [2021-12-19 19:17:35,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 464126 [2021-12-19 19:17:35,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 464126 states and 653295 transitions. [2021-12-19 19:17:35,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:35,899 INFO L681 BuchiCegarLoop]: Abstraction has 464126 states and 653295 transitions. [2021-12-19 19:17:36,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464126 states and 653295 transitions. [2021-12-19 19:17:39,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464126 to 374894. [2021-12-19 19:17:40,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 374894 states, 374894 states have (on average 1.4099318740764055) internal successors, (528575), 374893 states have internal predecessors, (528575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374894 states to 374894 states and 528575 transitions. [2021-12-19 19:17:41,071 INFO L704 BuchiCegarLoop]: Abstraction has 374894 states and 528575 transitions. [2021-12-19 19:17:41,071 INFO L587 BuchiCegarLoop]: Abstraction has 374894 states and 528575 transitions. [2021-12-19 19:17:41,071 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:17:41,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 374894 states and 528575 transitions.