./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:16:50,391 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:16:50,430 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:16:50,479 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:16:50,479 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:16:50,482 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:16:50,484 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:16:50,486 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:16:50,488 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:16:50,490 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:16:50,491 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:16:50,493 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:16:50,494 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:16:50,499 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:16:50,500 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:16:50,502 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:16:50,506 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:16:50,507 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:16:50,509 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:16:50,511 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:16:50,512 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:16:50,516 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:16:50,517 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:16:50,519 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:16:50,521 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:16:50,522 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:16:50,522 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:16:50,523 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:16:50,524 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:16:50,525 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:16:50,525 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:16:50,526 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:16:50,527 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:16:50,528 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:16:50,529 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:16:50,529 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:16:50,530 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:16:50,530 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:16:50,530 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:16:50,531 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:16:50,532 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:16:50,532 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:16:50,568 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:16:50,569 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:16:50,569 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:16:50,569 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:16:50,570 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:16:50,571 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:16:50,571 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:16:50,571 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:16:50,571 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:16:50,571 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:16:50,572 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:16:50,573 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:16:50,573 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:16:50,573 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:16:50,573 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:16:50,573 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:16:50,574 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:16:50,575 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:16:50,575 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:16:50,575 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:16:50,575 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:16:50,575 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:16:50,576 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:16:50,576 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:16:50,576 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:16:50,577 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:16:50,578 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:16:50,578 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2021-12-19 19:16:50,799 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:16:50,823 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:16:50,825 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:16:50,826 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:16:50,827 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:16:50,828 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2021-12-19 19:16:50,884 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eee84c80c/f3c2bcf9cef3493da09a722435d8e0b2/FLAGca71a4764 [2021-12-19 19:16:51,317 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:16:51,318 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2021-12-19 19:16:51,334 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eee84c80c/f3c2bcf9cef3493da09a722435d8e0b2/FLAGca71a4764 [2021-12-19 19:16:51,657 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eee84c80c/f3c2bcf9cef3493da09a722435d8e0b2 [2021-12-19 19:16:51,659 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:16:51,660 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:16:51,662 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:51,662 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:16:51,665 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:16:51,665 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:51" (1/1) ... [2021-12-19 19:16:51,667 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ad93680 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:51, skipping insertion in model container [2021-12-19 19:16:51,667 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:51" (1/1) ... [2021-12-19 19:16:51,673 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:16:51,720 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:16:51,869 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2021-12-19 19:16:51,955 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:51,963 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:16:51,972 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2021-12-19 19:16:52,040 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:52,065 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:16:52,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52 WrapperNode [2021-12-19 19:16:52,066 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:52,067 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:52,067 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:16:52,067 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:16:52,072 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,084 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,177 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4144 [2021-12-19 19:16:52,177 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:52,178 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:16:52,178 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:16:52,179 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:16:52,185 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,205 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,211 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,243 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,273 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,280 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,292 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:16:52,294 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:16:52,294 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:16:52,294 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:16:52,296 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (1/1) ... [2021-12-19 19:16:52,305 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:52,330 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:52,340 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:52,341 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:16:52,371 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:16:52,372 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:16:52,372 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:16:52,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:16:52,499 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:16:52,500 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:16:54,326 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:16:54,344 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:16:54,344 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-12-19 19:16:54,347 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:54 BoogieIcfgContainer [2021-12-19 19:16:54,347 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:16:54,348 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:16:54,348 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:16:54,351 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:16:54,351 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,352 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:16:51" (1/3) ... [2021-12-19 19:16:54,352 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d06f382 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:54, skipping insertion in model container [2021-12-19 19:16:54,353 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,353 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:52" (2/3) ... [2021-12-19 19:16:54,353 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d06f382 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:54, skipping insertion in model container [2021-12-19 19:16:54,353 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:54,353 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:54" (3/3) ... [2021-12-19 19:16:54,354 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2021-12-19 19:16:54,393 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:16:54,393 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:16:54,393 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:16:54,393 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:16:54,394 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:16:54,394 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:16:54,394 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:16:54,394 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:16:54,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:54,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2021-12-19 19:16:54,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:54,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:54,519 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,519 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,520 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:16:54,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:54,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2021-12-19 19:16:54,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:54,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:54,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,570 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:54,583 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1703#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 148#L1773true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174#L841true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1363#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1469#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 431#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 749#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 843#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1599#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1565#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1650#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 384#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 773#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1774#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 696#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 408#L1201true assume !(0 == ~M_E~0); 1177#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L1206-1true assume !(0 == ~T2_E~0); 1156#L1211-1true assume !(0 == ~T3_E~0); 1303#L1216-1true assume !(0 == ~T4_E~0); 298#L1221-1true assume !(0 == ~T5_E~0); 1244#L1226-1true assume !(0 == ~T6_E~0); 105#L1231-1true assume !(0 == ~T7_E~0); 1388#L1236-1true assume !(0 == ~T8_E~0); 1225#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 406#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 9#L1261-1true assume !(0 == ~E_M~0); 1568#L1266-1true assume !(0 == ~E_1~0); 1508#L1271-1true assume !(0 == ~E_2~0); 831#L1276-1true assume !(0 == ~E_3~0); 1503#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 786#L1286-1true assume !(0 == ~E_5~0); 238#L1291-1true assume !(0 == ~E_6~0); 1594#L1296-1true assume !(0 == ~E_7~0); 610#L1301-1true assume !(0 == ~E_8~0); 1099#L1306-1true assume !(0 == ~E_9~0); 1072#L1311-1true assume !(0 == ~E_10~0); 213#L1316-1true assume !(0 == ~E_11~0); 1457#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 623#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 739#L593true assume 1 == ~m_pc~0; 863#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1468#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1724#L605true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 794#L1492true assume !(0 != activate_threads_~tmp~1#1); 1227#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1125#L612true assume !(1 == ~t1_pc~0); 1658#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1534#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364#L624true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 437#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390#L631true assume 1 == ~t2_pc~0; 351#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 917#L643true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1307#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192#L650true assume !(1 == ~t3_pc~0); 960#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1217#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L662true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 970#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 767#L669true assume 1 == ~t4_pc~0; 1269#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1782#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383#L681true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984#L688true assume !(1 == ~t5_pc~0); 130#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1467#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 719#L700true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 664#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 779#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1293#L707true assume 1 == ~t6_pc~0; 1339#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 504#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1289#L719true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1369#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 726#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407#L726true assume 1 == ~t7_pc~0; 343#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 911#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1578#L738true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1304#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 63#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 295#L745true assume !(1 == ~t8_pc~0); 1109#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1191#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 948#L757true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 553#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1787#L764true assume 1 == ~t9_pc~0; 404#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 797#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1557#L776true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1434#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 72#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1390#L783true assume !(1 == ~t10_pc~0); 99#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 194#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119#L795true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1168#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1273#L802true assume 1 == ~t11_pc~0; 1142#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 751#L814true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 299#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 363#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 534#L821true assume !(1 == ~t12_pc~0); 602#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1329#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48#L833true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1243#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1250#L1588-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804#L1339true assume !(1 == ~M_E~0); 1455#L1339-2true assume !(1 == ~T1_E~0); 1311#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1722#L1349-1true assume !(1 == ~T3_E~0); 619#L1354-1true assume !(1 == ~T4_E~0); 992#L1359-1true assume !(1 == ~T5_E~0); 1541#L1364-1true assume !(1 == ~T6_E~0); 268#L1369-1true assume !(1 == ~T7_E~0); 963#L1374-1true assume !(1 == ~T8_E~0); 621#L1379-1true assume !(1 == ~T9_E~0); 691#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1760#L1389-1true assume !(1 == ~T11_E~0); 1232#L1394-1true assume !(1 == ~T12_E~0); 1628#L1399-1true assume !(1 == ~E_M~0); 1437#L1404-1true assume !(1 == ~E_1~0); 323#L1409-1true assume !(1 == ~E_2~0); 1406#L1414-1true assume !(1 == ~E_3~0); 864#L1419-1true assume !(1 == ~E_4~0); 126#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 627#L1429-1true assume !(1 == ~E_6~0); 1264#L1434-1true assume !(1 == ~E_7~0); 1602#L1439-1true assume !(1 == ~E_8~0); 146#L1444-1true assume !(1 == ~E_9~0); 816#L1449-1true assume !(1 == ~E_10~0); 354#L1454-1true assume !(1 == ~E_11~0); 1302#L1459-1true assume !(1 == ~E_12~0); 724#L1464-1true assume { :end_inline_reset_delta_events } true; 490#L1810-2true [2021-12-19 19:16:54,594 INFO L793 eck$LassoCheckResult]: Loop: 490#L1810-2true assume !false; 1335#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1770#L1176true assume false; 158#L1191true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1414#L841-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1054#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 821#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1598#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 722#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 190#L1216-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 467#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume !(0 == ~T7_E~0); 370#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1772#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1334#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1145#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 199#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 518#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume !(0 == ~E_2~0); 488#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 451#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1201#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 861#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1610#L1296-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1535#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1425#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 530#L1311-3true assume !(0 == ~E_10~0); 159#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 200#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 601#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1210#L593-42true assume 1 == ~m_pc~0; 949#L594-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1757#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1501#L605-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1720#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 681#L612-42true assume 1 == ~t1_pc~0; 1728#L613-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1582#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1291#L624-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1754#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 41#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 568#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1748#L643-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1635#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240#L650-42true assume !(1 == ~t3_pc~0); 135#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1716#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1348#L662-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1375#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1268#L669-42true assume 1 == ~t4_pc~0; 537#L670-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 998#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1496#L681-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 871#L1524-42true assume !(0 != activate_threads_~tmp___3~0#1); 778#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 860#L688-42true assume !(1 == ~t5_pc~0); 1101#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1351#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86#L700-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1431#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36#L707-42true assume !(1 == ~t6_pc~0); 1679#L707-44true is_transmit6_triggered_~__retres1~6#1 := 0; 1695#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1004#L719-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1292#L1540-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 753#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume 1 == ~t7_pc~0; 1330#L727-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1070#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1600#L738-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 532#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 605#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1186#L745-42true assume 1 == ~t8_pc~0; 632#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1429#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 206#L757-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 422#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 515#L764-42true assume 1 == ~t9_pc~0; 1659#L765-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 792#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 996#L776-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 166#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 195#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 11#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 315#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 392#L795-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1537#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1517#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume !(1 == ~t11_pc~0); 1075#L802-44true is_transmit11_triggered_~__retres1~11#1 := 0; 75#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1188#L814-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1550#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L821-42true assume !(1 == ~t12_pc~0); 337#L821-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1007#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10#L833-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1159#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 560#L1588-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#L1339-3true assume !(1 == ~M_E~0); 666#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 808#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 766#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 342#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 775#L1359-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1607#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1499#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1263#L1374-3true assume !(1 == ~T8_E~0); 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1149#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 341#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 479#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1707#L1399-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1279#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1224#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1333#L1414-3true assume !(1 == ~E_3~0); 1356#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 962#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 176#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 774#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 925#L1439-3true assume 1 == ~E_8~0;~E_8~0 := 2; 140#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 204#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1424#L1454-3true assume !(1 == ~E_11~0); 770#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1769#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 505#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1727#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 232#L989-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1456#L1829true assume !(0 == start_simulation_~tmp~3#1); 88#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 556#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 931#L989-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 787#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1543#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 493#L1792true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 219#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 490#L1810-2true [2021-12-19 19:16:54,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:54,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2021-12-19 19:16:54,620 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:54,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684081399] [2021-12-19 19:16:54,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:54,622 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:54,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:54,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:54,829 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:54,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684081399] [2021-12-19 19:16:54,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684081399] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:54,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:54,830 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:54,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933977513] [2021-12-19 19:16:54,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:54,836 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:54,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:54,836 INFO L85 PathProgramCache]: Analyzing trace with hash -1810120649, now seen corresponding path program 1 times [2021-12-19 19:16:54,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:54,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187947509] [2021-12-19 19:16:54,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:54,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:54,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:54,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:54,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:54,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187947509] [2021-12-19 19:16:54,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187947509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:54,881 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:54,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:54,882 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208132948] [2021-12-19 19:16:54,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:54,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:54,884 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:54,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-19 19:16:54,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-19 19:16:54,914 INFO L87 Difference]: Start difference. First operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,035 INFO L93 Difference]: Finished difference Result 1794 states and 2657 transitions. [2021-12-19 19:16:55,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-19 19:16:55,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1794 states and 2657 transitions. [2021-12-19 19:16:55,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1794 states to 1788 states and 2651 transitions. [2021-12-19 19:16:55,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:55,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:55,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2651 transitions. [2021-12-19 19:16:55,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:55,085 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-19 19:16:55,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2651 transitions. [2021-12-19 19:16:55,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:55,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2651 transitions. [2021-12-19 19:16:55,175 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-19 19:16:55,175 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-19 19:16:55,175 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:16:55,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2651 transitions. [2021-12-19 19:16:55,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,206 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,207 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,207 INFO L791 eck$LassoCheckResult]: Stem: 4388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3909#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3910#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3964#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5303#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4397#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4200#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3599#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4822#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4933#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5369#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5370#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4328#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4329#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4851#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4770#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4363#L1201 assume !(0 == ~M_E~0); 4364#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5210#L1206-1 assume !(0 == ~T2_E~0); 5196#L1211-1 assume !(0 == ~T3_E~0); 5197#L1216-1 assume !(0 == ~T4_E~0); 4184#L1221-1 assume !(0 == ~T5_E~0); 4185#L1226-1 assume !(0 == ~T6_E~0); 3824#L1231-1 assume !(0 == ~T7_E~0); 3825#L1236-1 assume !(0 == ~T8_E~0); 5233#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4221#L1246-1 assume !(0 == ~T10_E~0); 4222#L1251-1 assume !(0 == ~T11_E~0); 4361#L1256-1 assume !(0 == ~T12_E~0); 3610#L1261-1 assume !(0 == ~E_M~0); 3611#L1266-1 assume !(0 == ~E_1~0); 5355#L1271-1 assume !(0 == ~E_2~0); 4917#L1276-1 assume !(0 == ~E_3~0); 4918#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4865#L1286-1 assume !(0 == ~E_5~0); 4075#L1291-1 assume !(0 == ~E_6~0); 4076#L1296-1 assume !(0 == ~E_7~0); 4651#L1301-1 assume !(0 == ~E_8~0); 4652#L1306-1 assume !(0 == ~E_9~0); 5132#L1311-1 assume !(0 == ~E_10~0); 4026#L1316-1 assume !(0 == ~E_11~0); 4027#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4669#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4670#L593 assume 1 == ~m_pc~0; 4814#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3916#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5342#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4876#L1492 assume !(0 != activate_threads_~tmp~1#1); 4877#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5168#L612 assume !(1 == ~t1_pc~0); 5169#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5298#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4298#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3920#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3921#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4340#L631 assume 1 == ~t2_pc~0; 4275#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3697#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4534#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4535#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3993#L650 assume !(1 == ~t3_pc~0); 3994#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4694#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3917#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3650#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3651#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4843#L669 assume 1 == ~t4_pc~0; 4844#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5202#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4327#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3859#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3860#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4084#L688 assume !(1 == ~t5_pc~0); 3875#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3876#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4794#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4728#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4729#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4858#L707 assume 1 == ~t6_pc~0; 5267#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4504#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4505#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5265#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4800#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4362#L726 assume 1 == ~t7_pc~0; 4261#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3960#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5001#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5275#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3729#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3730#L745 assume !(1 == ~t8_pc~0); 4177#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4196#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5034#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4582#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4583#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5093#L764 assume 1 == ~t9_pc~0; 4360#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4202#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4879#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5326#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3749#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3750#L783 assume !(1 == ~t10_pc~0); 3811#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3812#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3853#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3854#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4316#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5204#L802 assume 1 == ~t11_pc~0; 5186#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3694#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3695#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4186#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4187#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4297#L821 assume !(1 == ~t12_pc~0); 4548#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4644#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3699#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3700#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5242#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L1339 assume !(1 == ~M_E~0); 4889#L1339-2 assume !(1 == ~T1_E~0); 5277#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5278#L1349-1 assume !(1 == ~T3_E~0); 4662#L1354-1 assume !(1 == ~T4_E~0); 4663#L1359-1 assume !(1 == ~T5_E~0); 5064#L1364-1 assume !(1 == ~T6_E~0); 4127#L1369-1 assume !(1 == ~T7_E~0); 4128#L1374-1 assume !(1 == ~T8_E~0); 4665#L1379-1 assume !(1 == ~T9_E~0); 4666#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4765#L1389-1 assume !(1 == ~T11_E~0); 5236#L1394-1 assume !(1 == ~T12_E~0); 5237#L1399-1 assume !(1 == ~E_M~0); 5327#L1404-1 assume !(1 == ~E_1~0); 4226#L1409-1 assume !(1 == ~E_2~0); 4227#L1414-1 assume !(1 == ~E_3~0); 4953#L1419-1 assume !(1 == ~E_4~0); 3867#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L1429-1 assume !(1 == ~E_6~0); 4678#L1434-1 assume !(1 == ~E_7~0); 5257#L1439-1 assume !(1 == ~E_8~0); 3905#L1444-1 assume !(1 == ~E_9~0); 3906#L1449-1 assume !(1 == ~E_10~0); 4280#L1454-1 assume !(1 == ~E_11~0); 4281#L1459-1 assume !(1 == ~E_12~0); 4799#L1464-1 assume { :end_inline_reset_delta_events } true; 4039#L1810-2 [2021-12-19 19:16:55,210 INFO L793 eck$LassoCheckResult]: Loop: 4039#L1810-2 assume !false; 4483#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4399#L1176 assume !false; 4961#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4531#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3737#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4287#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4288#L1003 assume !(0 != eval_~tmp~0#1); 3929#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5120#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4903#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4904#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3988#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3989#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4455#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4059#L1231-3 assume !(0 == ~T7_E~0); 4060#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4306#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5288#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5189#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4894#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4005#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4006#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4051#L1271-3 assume !(0 == ~E_2~0); 4052#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4428#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4429#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4950#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4951#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5366#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5323#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4540#L1311-3 assume !(0 == ~E_10~0); 3931#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3932#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4007#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4643#L593-42 assume !(1 == ~m_pc~0); 4801#L593-44 is_master_triggered_~__retres1~0#1 := 0; 4802#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5351#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5352#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3830#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3831#L612-42 assume !(1 == ~t1_pc~0); 4752#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5145#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3918#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3919#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4614#L631-42 assume 1 == ~t2_pc~0; 3683#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3684#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4603#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4479#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4480#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4080#L650-42 assume 1 == ~t3_pc~0; 3642#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3643#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5294#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4273#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4274#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L669-42 assume !(1 == ~t4_pc~0); 3640#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3641#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5069#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4959#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4856#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4857#L688-42 assume 1 == ~t5_pc~0; 4948#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5149#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3781#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3782#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3858#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3672#L707-42 assume !(1 == ~t6_pc~0); 3673#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5330#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5074#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5075#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4824#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4825#L726-42 assume 1 == ~t7_pc~0; 5102#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5128#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4543#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4544#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4647#L745-42 assume 1 == ~t8_pc~0; 4684#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4686#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4013#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3658#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3659#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4384#L764-42 assume 1 == ~t9_pc~0; 4520#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4873#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4874#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3944#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3945#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3998#L783-42 assume !(1 == ~t10_pc~0); 3616#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 3615#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4210#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4343#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5360#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L802-42 assume 1 == ~t11_pc~0; 4145#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3756#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3757#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3707#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3708#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4884#L821-42 assume 1 == ~t12_pc~0; 4885#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4250#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3612#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3613#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4590#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4580#L1339-3 assume !(1 == ~M_E~0); 4581#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4732#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4842#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4259#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4260#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4853#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5349#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5256#L1374-3 assume !(1 == ~T8_E~0); 4081#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4082#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4257#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4258#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4467#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5263#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5231#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5232#L1414-3 assume !(1 == ~E_3~0); 5287#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5046#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3965#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3966#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4852#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3893#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3894#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4010#L1454-3 assume !(1 == ~E_11~0); 4847#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4848#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4506#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3803#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4063#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4064#L1829 assume !(0 == start_simulation_~tmp~3#1); 3785#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3786#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4586#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4587#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4866#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4867#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4487#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4038#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4039#L1810-2 [2021-12-19 19:16:55,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2021-12-19 19:16:55,212 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819394545] [2021-12-19 19:16:55,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819394545] [2021-12-19 19:16:55,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819394545] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,298 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939177810] [2021-12-19 19:16:55,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,299 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,299 INFO L85 PathProgramCache]: Analyzing trace with hash -830311852, now seen corresponding path program 1 times [2021-12-19 19:16:55,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348965580] [2021-12-19 19:16:55,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,300 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348965580] [2021-12-19 19:16:55,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348965580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,447 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353490558] [2021-12-19 19:16:55,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,448 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:55,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:55,449 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,499 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2021-12-19 19:16:55,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:55,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2650 transitions. [2021-12-19 19:16:55,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2650 transitions. [2021-12-19 19:16:55,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:55,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:55,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2650 transitions. [2021-12-19 19:16:55,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:55,526 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-19 19:16:55,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2650 transitions. [2021-12-19 19:16:55,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:55,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2650 transitions. [2021-12-19 19:16:55,556 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-19 19:16:55,556 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-19 19:16:55,556 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:16:55,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2650 transitions. [2021-12-19 19:16:55,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,566 INFO L791 eck$LassoCheckResult]: Stem: 7971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7492#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7493#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7547#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8886#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7980#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7783#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7182#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7183#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8405#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8516#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8952#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8953#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7911#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7912#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8434#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8353#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7946#L1201 assume !(0 == ~M_E~0); 7947#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8793#L1206-1 assume !(0 == ~T2_E~0); 8779#L1211-1 assume !(0 == ~T3_E~0); 8780#L1216-1 assume !(0 == ~T4_E~0); 7767#L1221-1 assume !(0 == ~T5_E~0); 7768#L1226-1 assume !(0 == ~T6_E~0); 7407#L1231-1 assume !(0 == ~T7_E~0); 7408#L1236-1 assume !(0 == ~T8_E~0); 8816#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7804#L1246-1 assume !(0 == ~T10_E~0); 7805#L1251-1 assume !(0 == ~T11_E~0); 7944#L1256-1 assume !(0 == ~T12_E~0); 7193#L1261-1 assume !(0 == ~E_M~0); 7194#L1266-1 assume !(0 == ~E_1~0); 8938#L1271-1 assume !(0 == ~E_2~0); 8500#L1276-1 assume !(0 == ~E_3~0); 8501#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8448#L1286-1 assume !(0 == ~E_5~0); 7658#L1291-1 assume !(0 == ~E_6~0); 7659#L1296-1 assume !(0 == ~E_7~0); 8234#L1301-1 assume !(0 == ~E_8~0); 8235#L1306-1 assume !(0 == ~E_9~0); 8715#L1311-1 assume !(0 == ~E_10~0); 7609#L1316-1 assume !(0 == ~E_11~0); 7610#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8252#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8253#L593 assume 1 == ~m_pc~0; 8397#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7499#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8925#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8459#L1492 assume !(0 != activate_threads_~tmp~1#1); 8460#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8751#L612 assume !(1 == ~t1_pc~0); 8752#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8881#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7881#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7503#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7504#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7923#L631 assume 1 == ~t2_pc~0; 7858#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7280#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7281#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8118#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7576#L650 assume !(1 == ~t3_pc~0); 7577#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8277#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7500#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7233#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7234#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8426#L669 assume 1 == ~t4_pc~0; 8427#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8785#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7910#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7442#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7443#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7667#L688 assume !(1 == ~t5_pc~0); 7458#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7459#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8377#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8311#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8312#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8441#L707 assume 1 == ~t6_pc~0; 8850#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8087#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8848#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8383#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7945#L726 assume 1 == ~t7_pc~0; 7844#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7543#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8584#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8858#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7312#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7313#L745 assume !(1 == ~t8_pc~0); 7760#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7779#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8617#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8165#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8166#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8676#L764 assume 1 == ~t9_pc~0; 7943#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7785#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8462#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8909#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7332#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7333#L783 assume !(1 == ~t10_pc~0); 7394#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7395#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7436#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7437#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7899#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8787#L802 assume 1 == ~t11_pc~0; 8769#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7277#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7278#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7769#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7770#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7880#L821 assume !(1 == ~t12_pc~0); 8131#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8227#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7282#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7283#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8825#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8471#L1339 assume !(1 == ~M_E~0); 8472#L1339-2 assume !(1 == ~T1_E~0); 8860#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8861#L1349-1 assume !(1 == ~T3_E~0); 8245#L1354-1 assume !(1 == ~T4_E~0); 8246#L1359-1 assume !(1 == ~T5_E~0); 8647#L1364-1 assume !(1 == ~T6_E~0); 7710#L1369-1 assume !(1 == ~T7_E~0); 7711#L1374-1 assume !(1 == ~T8_E~0); 8248#L1379-1 assume !(1 == ~T9_E~0); 8249#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8348#L1389-1 assume !(1 == ~T11_E~0); 8819#L1394-1 assume !(1 == ~T12_E~0); 8820#L1399-1 assume !(1 == ~E_M~0); 8910#L1404-1 assume !(1 == ~E_1~0); 7809#L1409-1 assume !(1 == ~E_2~0); 7810#L1414-1 assume !(1 == ~E_3~0); 8536#L1419-1 assume !(1 == ~E_4~0); 7450#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7451#L1429-1 assume !(1 == ~E_6~0); 8261#L1434-1 assume !(1 == ~E_7~0); 8840#L1439-1 assume !(1 == ~E_8~0); 7488#L1444-1 assume !(1 == ~E_9~0); 7489#L1449-1 assume !(1 == ~E_10~0); 7863#L1454-1 assume !(1 == ~E_11~0); 7864#L1459-1 assume !(1 == ~E_12~0); 8382#L1464-1 assume { :end_inline_reset_delta_events } true; 7622#L1810-2 [2021-12-19 19:16:55,567 INFO L793 eck$LassoCheckResult]: Loop: 7622#L1810-2 assume !false; 8066#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7982#L1176 assume !false; 8544#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8114#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7320#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7870#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7871#L1003 assume !(0 != eval_~tmp~0#1); 7512#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7513#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8703#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8486#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8487#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8380#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7571#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7572#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8038#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7642#L1231-3 assume !(0 == ~T7_E~0); 7643#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7889#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8871#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8772#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8477#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7588#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7589#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7634#L1271-3 assume !(0 == ~E_2~0); 7635#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8011#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8012#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8533#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8534#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8949#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8906#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8123#L1311-3 assume !(0 == ~E_10~0); 7514#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7515#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7590#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8226#L593-42 assume !(1 == ~m_pc~0); 8384#L593-44 is_master_triggered_~__retres1~0#1 := 0; 8385#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8934#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8935#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7413#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7414#L612-42 assume 1 == ~t1_pc~0; 8336#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8728#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8849#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7501#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7502#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8197#L631-42 assume 1 == ~t2_pc~0; 7266#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7267#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8186#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8062#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8063#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7663#L650-42 assume 1 == ~t3_pc~0; 7225#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7226#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8877#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7856#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7857#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8841#L669-42 assume !(1 == ~t4_pc~0); 7223#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7224#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8652#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8542#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 8439#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L688-42 assume 1 == ~t5_pc~0; 8531#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8732#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7364#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7365#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7441#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7255#L707-42 assume !(1 == ~t6_pc~0); 7256#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8913#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8657#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8658#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8407#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L726-42 assume 1 == ~t7_pc~0; 8685#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8711#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8712#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8126#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8127#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8230#L745-42 assume 1 == ~t8_pc~0; 8267#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8269#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7596#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7241#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7242#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7967#L764-42 assume 1 == ~t9_pc~0; 8103#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8456#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8457#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7527#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7528#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7581#L783-42 assume 1 == ~t10_pc~0; 7197#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7198#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7793#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7926#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8943#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8627#L802-42 assume 1 == ~t11_pc~0; 7728#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7339#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7340#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7290#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7291#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8467#L821-42 assume 1 == ~t12_pc~0; 8468#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7833#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7195#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7196#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8173#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8163#L1339-3 assume !(1 == ~M_E~0); 8164#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8315#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8425#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7842#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7843#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8436#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8932#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8839#L1374-3 assume !(1 == ~T8_E~0); 7664#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7665#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7840#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7841#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8050#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8814#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8815#L1414-3 assume !(1 == ~E_3~0); 8870#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7548#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7549#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8435#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7476#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7477#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7593#L1454-3 assume !(1 == ~E_11~0); 8430#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8431#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8089#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7386#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7646#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7647#L1829 assume !(0 == start_simulation_~tmp~3#1); 7368#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7369#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8169#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8170#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8449#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8450#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8070#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7621#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7622#L1810-2 [2021-12-19 19:16:55,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,570 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2021-12-19 19:16:55,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690171628] [2021-12-19 19:16:55,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690171628] [2021-12-19 19:16:55,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690171628] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078884854] [2021-12-19 19:16:55,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1795658606, now seen corresponding path program 1 times [2021-12-19 19:16:55,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765121846] [2021-12-19 19:16:55,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,651 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,771 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,771 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765121846] [2021-12-19 19:16:55,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765121846] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,772 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181748951] [2021-12-19 19:16:55,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,773 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,773 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:55,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:55,774 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:55,806 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2021-12-19 19:16:55,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:55,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2649 transitions. [2021-12-19 19:16:55,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2649 transitions. [2021-12-19 19:16:55,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:55,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:55,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2649 transitions. [2021-12-19 19:16:55,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:55,832 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-19 19:16:55,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2649 transitions. [2021-12-19 19:16:55,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:55,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:55,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2649 transitions. [2021-12-19 19:16:55,860 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-19 19:16:55,861 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-19 19:16:55,861 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:16:55,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2649 transitions. [2021-12-19 19:16:55,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:55,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:55,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:55,870 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,870 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:55,870 INFO L791 eck$LassoCheckResult]: Stem: 11554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11075#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11076#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11130#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12469#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11563#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11366#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10765#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10766#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11988#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12099#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12535#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12536#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11494#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11495#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12017#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11936#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11529#L1201 assume !(0 == ~M_E~0); 11530#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12376#L1206-1 assume !(0 == ~T2_E~0); 12362#L1211-1 assume !(0 == ~T3_E~0); 12363#L1216-1 assume !(0 == ~T4_E~0); 11350#L1221-1 assume !(0 == ~T5_E~0); 11351#L1226-1 assume !(0 == ~T6_E~0); 10990#L1231-1 assume !(0 == ~T7_E~0); 10991#L1236-1 assume !(0 == ~T8_E~0); 12399#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11387#L1246-1 assume !(0 == ~T10_E~0); 11388#L1251-1 assume !(0 == ~T11_E~0); 11527#L1256-1 assume !(0 == ~T12_E~0); 10776#L1261-1 assume !(0 == ~E_M~0); 10777#L1266-1 assume !(0 == ~E_1~0); 12521#L1271-1 assume !(0 == ~E_2~0); 12083#L1276-1 assume !(0 == ~E_3~0); 12084#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12031#L1286-1 assume !(0 == ~E_5~0); 11241#L1291-1 assume !(0 == ~E_6~0); 11242#L1296-1 assume !(0 == ~E_7~0); 11817#L1301-1 assume !(0 == ~E_8~0); 11818#L1306-1 assume !(0 == ~E_9~0); 12298#L1311-1 assume !(0 == ~E_10~0); 11192#L1316-1 assume !(0 == ~E_11~0); 11193#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11835#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11836#L593 assume 1 == ~m_pc~0; 11980#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11082#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12508#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12042#L1492 assume !(0 != activate_threads_~tmp~1#1); 12043#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L612 assume !(1 == ~t1_pc~0); 12335#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12464#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11086#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11087#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11506#L631 assume 1 == ~t2_pc~0; 11441#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10863#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10864#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11700#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11701#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11159#L650 assume !(1 == ~t3_pc~0); 11160#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11860#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11083#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10816#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10817#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12009#L669 assume 1 == ~t4_pc~0; 12010#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12368#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11493#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11025#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11026#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11250#L688 assume !(1 == ~t5_pc~0); 11041#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11042#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11960#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11894#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11895#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L707 assume 1 == ~t6_pc~0; 12433#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11670#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11671#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12431#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 11966#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11528#L726 assume 1 == ~t7_pc~0; 11427#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11126#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12167#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12441#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10895#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10896#L745 assume !(1 == ~t8_pc~0); 11343#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11362#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12200#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11748#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11749#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12259#L764 assume 1 == ~t9_pc~0; 11526#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11368#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12045#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12492#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10915#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10916#L783 assume !(1 == ~t10_pc~0); 10977#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10978#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11019#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11020#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11482#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12370#L802 assume 1 == ~t11_pc~0; 12352#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10860#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10861#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11352#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11353#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11463#L821 assume !(1 == ~t12_pc~0); 11714#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11810#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10865#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10866#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12408#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12054#L1339 assume !(1 == ~M_E~0); 12055#L1339-2 assume !(1 == ~T1_E~0); 12443#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12444#L1349-1 assume !(1 == ~T3_E~0); 11828#L1354-1 assume !(1 == ~T4_E~0); 11829#L1359-1 assume !(1 == ~T5_E~0); 12230#L1364-1 assume !(1 == ~T6_E~0); 11293#L1369-1 assume !(1 == ~T7_E~0); 11294#L1374-1 assume !(1 == ~T8_E~0); 11831#L1379-1 assume !(1 == ~T9_E~0); 11832#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11931#L1389-1 assume !(1 == ~T11_E~0); 12402#L1394-1 assume !(1 == ~T12_E~0); 12403#L1399-1 assume !(1 == ~E_M~0); 12493#L1404-1 assume !(1 == ~E_1~0); 11392#L1409-1 assume !(1 == ~E_2~0); 11393#L1414-1 assume !(1 == ~E_3~0); 12119#L1419-1 assume !(1 == ~E_4~0); 11033#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11034#L1429-1 assume !(1 == ~E_6~0); 11844#L1434-1 assume !(1 == ~E_7~0); 12423#L1439-1 assume !(1 == ~E_8~0); 11071#L1444-1 assume !(1 == ~E_9~0); 11072#L1449-1 assume !(1 == ~E_10~0); 11446#L1454-1 assume !(1 == ~E_11~0); 11447#L1459-1 assume !(1 == ~E_12~0); 11965#L1464-1 assume { :end_inline_reset_delta_events } true; 11205#L1810-2 [2021-12-19 19:16:55,871 INFO L793 eck$LassoCheckResult]: Loop: 11205#L1810-2 assume !false; 11649#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11565#L1176 assume !false; 12127#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11697#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10903#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11453#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11454#L1003 assume !(0 != eval_~tmp~0#1); 11095#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11096#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12286#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12069#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12070#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11963#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11154#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11155#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11621#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11225#L1231-3 assume !(0 == ~T7_E~0); 11226#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11472#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12454#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12355#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12060#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11171#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11172#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11217#L1271-3 assume !(0 == ~E_2~0); 11218#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11594#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11595#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12116#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12117#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12532#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12489#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11706#L1311-3 assume !(0 == ~E_10~0); 11097#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11098#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11173#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11809#L593-42 assume 1 == ~m_pc~0; 12202#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11968#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12517#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12518#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10996#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10997#L612-42 assume !(1 == ~t1_pc~0); 11918#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12311#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12432#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11084#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11085#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11780#L631-42 assume 1 == ~t2_pc~0; 10849#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10850#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11769#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11645#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11646#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11246#L650-42 assume 1 == ~t3_pc~0; 10808#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10809#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12460#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11439#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11440#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12424#L669-42 assume !(1 == ~t4_pc~0); 10806#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10807#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12235#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12125#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 12022#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12023#L688-42 assume 1 == ~t5_pc~0; 12114#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12315#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10947#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10948#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11024#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10838#L707-42 assume !(1 == ~t6_pc~0); 10839#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12496#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12240#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12241#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11990#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11991#L726-42 assume 1 == ~t7_pc~0; 12268#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12294#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12295#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11709#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11710#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11813#L745-42 assume 1 == ~t8_pc~0; 11850#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11852#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11179#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10824#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10825#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11550#L764-42 assume 1 == ~t9_pc~0; 11686#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12039#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12040#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11110#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11111#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11164#L783-42 assume 1 == ~t10_pc~0; 10780#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10781#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11376#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11509#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12526#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12210#L802-42 assume !(1 == ~t11_pc~0); 11312#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 10922#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10923#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10873#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10874#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12050#L821-42 assume 1 == ~t12_pc~0; 12051#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11416#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10778#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10779#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11756#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11746#L1339-3 assume !(1 == ~M_E~0); 11747#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12008#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11425#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11426#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12019#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12515#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12422#L1374-3 assume !(1 == ~T8_E~0); 11247#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11248#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11423#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11424#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11633#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12429#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12397#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12398#L1414-3 assume !(1 == ~E_3~0); 12453#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12212#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11131#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11132#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12018#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11059#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11060#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11176#L1454-3 assume !(1 == ~E_11~0); 12013#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12014#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11672#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10969#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11229#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11230#L1829 assume !(0 == start_simulation_~tmp~3#1); 10951#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10952#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11752#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11753#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12032#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12033#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11653#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11204#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11205#L1810-2 [2021-12-19 19:16:55,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,872 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2021-12-19 19:16:55,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100015410] [2021-12-19 19:16:55,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100015410] [2021-12-19 19:16:55,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100015410] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,911 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075344067] [2021-12-19 19:16:55,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:55,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:55,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1706034771, now seen corresponding path program 1 times [2021-12-19 19:16:55,916 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:55,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099607213] [2021-12-19 19:16:55,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:55,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:55,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:55,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:55,973 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:55,973 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099607213] [2021-12-19 19:16:55,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099607213] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:55,974 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:55,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:55,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610235102] [2021-12-19 19:16:55,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:55,974 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:55,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:55,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:55,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:55,976 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,006 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2021-12-19 19:16:56,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2648 transitions. [2021-12-19 19:16:56,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2648 transitions. [2021-12-19 19:16:56,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2648 transitions. [2021-12-19 19:16:56,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,031 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-19 19:16:56,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2648 transitions. [2021-12-19 19:16:56,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2648 transitions. [2021-12-19 19:16:56,079 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-19 19:16:56,079 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-19 19:16:56,079 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:16:56,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2648 transitions. [2021-12-19 19:16:56,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,089 INFO L791 eck$LassoCheckResult]: Stem: 15137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14658#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14659#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14713#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16052#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15146#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14949#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14348#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14349#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15571#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15682#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16118#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16119#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15077#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15078#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15600#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15519#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15112#L1201 assume !(0 == ~M_E~0); 15113#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15959#L1206-1 assume !(0 == ~T2_E~0); 15945#L1211-1 assume !(0 == ~T3_E~0); 15946#L1216-1 assume !(0 == ~T4_E~0); 14933#L1221-1 assume !(0 == ~T5_E~0); 14934#L1226-1 assume !(0 == ~T6_E~0); 14573#L1231-1 assume !(0 == ~T7_E~0); 14574#L1236-1 assume !(0 == ~T8_E~0); 15982#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14970#L1246-1 assume !(0 == ~T10_E~0); 14971#L1251-1 assume !(0 == ~T11_E~0); 15110#L1256-1 assume !(0 == ~T12_E~0); 14359#L1261-1 assume !(0 == ~E_M~0); 14360#L1266-1 assume !(0 == ~E_1~0); 16104#L1271-1 assume !(0 == ~E_2~0); 15666#L1276-1 assume !(0 == ~E_3~0); 15667#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15614#L1286-1 assume !(0 == ~E_5~0); 14824#L1291-1 assume !(0 == ~E_6~0); 14825#L1296-1 assume !(0 == ~E_7~0); 15400#L1301-1 assume !(0 == ~E_8~0); 15401#L1306-1 assume !(0 == ~E_9~0); 15881#L1311-1 assume !(0 == ~E_10~0); 14775#L1316-1 assume !(0 == ~E_11~0); 14776#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15418#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15419#L593 assume 1 == ~m_pc~0; 15563#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14665#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16091#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15625#L1492 assume !(0 != activate_threads_~tmp~1#1); 15626#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15917#L612 assume !(1 == ~t1_pc~0); 15918#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16047#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15047#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14669#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14670#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15089#L631 assume 1 == ~t2_pc~0; 15024#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14446#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14447#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15283#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15284#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14742#L650 assume !(1 == ~t3_pc~0); 14743#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15443#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14666#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14399#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14400#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15592#L669 assume 1 == ~t4_pc~0; 15593#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15951#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15076#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14608#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14609#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14833#L688 assume !(1 == ~t5_pc~0); 14624#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14625#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15543#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15477#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15478#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15607#L707 assume 1 == ~t6_pc~0; 16016#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15253#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15254#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16014#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15549#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15111#L726 assume 1 == ~t7_pc~0; 15010#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14709#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15750#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16024#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14478#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14479#L745 assume !(1 == ~t8_pc~0); 14926#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14945#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15331#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15332#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15842#L764 assume 1 == ~t9_pc~0; 15109#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14951#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15628#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16075#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14498#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14499#L783 assume !(1 == ~t10_pc~0); 14560#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14561#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14602#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14603#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15065#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15953#L802 assume 1 == ~t11_pc~0; 15935#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14443#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14444#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14935#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 14936#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15046#L821 assume !(1 == ~t12_pc~0); 15297#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15393#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14448#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14449#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 15991#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15637#L1339 assume !(1 == ~M_E~0); 15638#L1339-2 assume !(1 == ~T1_E~0); 16026#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16027#L1349-1 assume !(1 == ~T3_E~0); 15411#L1354-1 assume !(1 == ~T4_E~0); 15412#L1359-1 assume !(1 == ~T5_E~0); 15813#L1364-1 assume !(1 == ~T6_E~0); 14876#L1369-1 assume !(1 == ~T7_E~0); 14877#L1374-1 assume !(1 == ~T8_E~0); 15414#L1379-1 assume !(1 == ~T9_E~0); 15415#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15514#L1389-1 assume !(1 == ~T11_E~0); 15985#L1394-1 assume !(1 == ~T12_E~0); 15986#L1399-1 assume !(1 == ~E_M~0); 16076#L1404-1 assume !(1 == ~E_1~0); 14975#L1409-1 assume !(1 == ~E_2~0); 14976#L1414-1 assume !(1 == ~E_3~0); 15702#L1419-1 assume !(1 == ~E_4~0); 14616#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14617#L1429-1 assume !(1 == ~E_6~0); 15427#L1434-1 assume !(1 == ~E_7~0); 16006#L1439-1 assume !(1 == ~E_8~0); 14654#L1444-1 assume !(1 == ~E_9~0); 14655#L1449-1 assume !(1 == ~E_10~0); 15029#L1454-1 assume !(1 == ~E_11~0); 15030#L1459-1 assume !(1 == ~E_12~0); 15548#L1464-1 assume { :end_inline_reset_delta_events } true; 14788#L1810-2 [2021-12-19 19:16:56,089 INFO L793 eck$LassoCheckResult]: Loop: 14788#L1810-2 assume !false; 15232#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15148#L1176 assume !false; 15710#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15280#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14486#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15036#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15037#L1003 assume !(0 != eval_~tmp~0#1); 14678#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14679#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15869#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15652#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15653#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15546#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14737#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14738#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15204#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14808#L1231-3 assume !(0 == ~T7_E~0); 14809#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15055#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16037#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15938#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15643#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14754#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14755#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14800#L1271-3 assume !(0 == ~E_2~0); 14801#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15177#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15178#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15699#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15700#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16115#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16072#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15289#L1311-3 assume !(0 == ~E_10~0); 14680#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14681#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14756#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15392#L593-42 assume 1 == ~m_pc~0; 15785#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15551#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16100#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16101#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14579#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14580#L612-42 assume !(1 == ~t1_pc~0); 15501#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 15894#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16015#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14667#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14668#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15363#L631-42 assume 1 == ~t2_pc~0; 14432#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14433#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15352#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15228#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15229#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14829#L650-42 assume 1 == ~t3_pc~0; 14391#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14392#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16043#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15022#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15023#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16007#L669-42 assume !(1 == ~t4_pc~0); 14389#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15818#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15708#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 15605#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15606#L688-42 assume 1 == ~t5_pc~0; 15697#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15898#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14530#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14531#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14607#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14421#L707-42 assume !(1 == ~t6_pc~0); 14422#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16079#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15823#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15824#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15574#L726-42 assume 1 == ~t7_pc~0; 15851#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15877#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15878#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15292#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15293#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15396#L745-42 assume 1 == ~t8_pc~0; 15433#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15435#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14762#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14407#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14408#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15133#L764-42 assume 1 == ~t9_pc~0; 15269#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15622#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15623#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14693#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14694#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14747#L783-42 assume 1 == ~t10_pc~0; 14363#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14364#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14959#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15092#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16109#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15793#L802-42 assume 1 == ~t11_pc~0; 14894#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14505#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14506#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14456#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14457#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15633#L821-42 assume 1 == ~t12_pc~0; 15634#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14999#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14361#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14362#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15339#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15329#L1339-3 assume !(1 == ~M_E~0); 15330#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15481#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15591#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15008#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15009#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15602#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16098#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16005#L1374-3 assume !(1 == ~T8_E~0); 14830#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14831#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15006#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15007#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15216#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16012#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15980#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15981#L1414-3 assume !(1 == ~E_3~0); 16036#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15795#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14714#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14715#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15601#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14642#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14643#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14759#L1454-3 assume !(1 == ~E_11~0); 15596#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15597#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15255#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14552#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14812#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14813#L1829 assume !(0 == start_simulation_~tmp~3#1); 14534#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14535#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15335#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15336#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15615#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15616#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15236#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14787#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14788#L1810-2 [2021-12-19 19:16:56,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2021-12-19 19:16:56,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123390338] [2021-12-19 19:16:56,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,123 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123390338] [2021-12-19 19:16:56,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123390338] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,123 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,123 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,123 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815932015] [2021-12-19 19:16:56,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,124 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,124 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 1 times [2021-12-19 19:16:56,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804185223] [2021-12-19 19:16:56,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,125 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,168 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804185223] [2021-12-19 19:16:56,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804185223] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,169 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,169 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836097220] [2021-12-19 19:16:56,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,169 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,170 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,201 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2021-12-19 19:16:56,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2647 transitions. [2021-12-19 19:16:56,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2647 transitions. [2021-12-19 19:16:56,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,224 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,224 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2647 transitions. [2021-12-19 19:16:56,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,227 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-19 19:16:56,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2647 transitions. [2021-12-19 19:16:56,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2647 transitions. [2021-12-19 19:16:56,255 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-19 19:16:56,255 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-19 19:16:56,256 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:16:56,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2647 transitions. [2021-12-19 19:16:56,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,263 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,263 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,264 INFO L791 eck$LassoCheckResult]: Stem: 18720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18241#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18242#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18296#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19635#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18729#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18532#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17931#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17932#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19154#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19267#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19701#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19702#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18660#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18661#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19183#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19102#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18695#L1201 assume !(0 == ~M_E~0); 18696#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19542#L1206-1 assume !(0 == ~T2_E~0); 19528#L1211-1 assume !(0 == ~T3_E~0); 19529#L1216-1 assume !(0 == ~T4_E~0); 18517#L1221-1 assume !(0 == ~T5_E~0); 18518#L1226-1 assume !(0 == ~T6_E~0); 18156#L1231-1 assume !(0 == ~T7_E~0); 18157#L1236-1 assume !(0 == ~T8_E~0); 19565#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18556#L1246-1 assume !(0 == ~T10_E~0); 18557#L1251-1 assume !(0 == ~T11_E~0); 18693#L1256-1 assume !(0 == ~T12_E~0); 17944#L1261-1 assume !(0 == ~E_M~0); 17945#L1266-1 assume !(0 == ~E_1~0); 19687#L1271-1 assume !(0 == ~E_2~0); 19249#L1276-1 assume !(0 == ~E_3~0); 19250#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19197#L1286-1 assume !(0 == ~E_5~0); 18407#L1291-1 assume !(0 == ~E_6~0); 18408#L1296-1 assume !(0 == ~E_7~0); 18983#L1301-1 assume !(0 == ~E_8~0); 18984#L1306-1 assume !(0 == ~E_9~0); 19464#L1311-1 assume !(0 == ~E_10~0); 18358#L1316-1 assume !(0 == ~E_11~0); 18359#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19001#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19002#L593 assume 1 == ~m_pc~0; 19146#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19674#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19208#L1492 assume !(0 != activate_threads_~tmp~1#1); 19209#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19500#L612 assume !(1 == ~t1_pc~0); 19501#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19630#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18630#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18252#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18253#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18672#L631 assume 1 == ~t2_pc~0; 18607#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18029#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18030#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18866#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 18867#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18325#L650 assume !(1 == ~t3_pc~0); 18326#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19026#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18249#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 17983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19175#L669 assume 1 == ~t4_pc~0; 19176#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19534#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18659#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18191#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18192#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18416#L688 assume !(1 == ~t5_pc~0); 18207#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18208#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19126#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19062#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19063#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19193#L707 assume 1 == ~t6_pc~0; 19599#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18836#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18837#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19597#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19134#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18694#L726 assume 1 == ~t7_pc~0; 18595#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19333#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19608#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18061#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18062#L745 assume !(1 == ~t8_pc~0); 18509#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18528#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19366#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18914#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18915#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19425#L764 assume 1 == ~t9_pc~0; 18692#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18534#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19211#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19658#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18082#L783 assume !(1 == ~t10_pc~0); 18143#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18144#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18185#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18186#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18653#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19536#L802 assume 1 == ~t11_pc~0; 19518#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18026#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18027#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18519#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18520#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18629#L821 assume !(1 == ~t12_pc~0); 18880#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18976#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18033#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18034#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19574#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19220#L1339 assume !(1 == ~M_E~0); 19221#L1339-2 assume !(1 == ~T1_E~0); 19609#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19610#L1349-1 assume !(1 == ~T3_E~0); 18995#L1354-1 assume !(1 == ~T4_E~0); 18996#L1359-1 assume !(1 == ~T5_E~0); 19398#L1364-1 assume !(1 == ~T6_E~0); 18459#L1369-1 assume !(1 == ~T7_E~0); 18460#L1374-1 assume !(1 == ~T8_E~0); 18999#L1379-1 assume !(1 == ~T9_E~0); 19000#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19097#L1389-1 assume !(1 == ~T11_E~0); 19568#L1394-1 assume !(1 == ~T12_E~0); 19569#L1399-1 assume !(1 == ~E_M~0); 19659#L1404-1 assume !(1 == ~E_1~0); 18560#L1409-1 assume !(1 == ~E_2~0); 18561#L1414-1 assume !(1 == ~E_3~0); 19285#L1419-1 assume !(1 == ~E_4~0); 18199#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18200#L1429-1 assume !(1 == ~E_6~0); 19010#L1434-1 assume !(1 == ~E_7~0); 19589#L1439-1 assume !(1 == ~E_8~0); 18237#L1444-1 assume !(1 == ~E_9~0); 18238#L1449-1 assume !(1 == ~E_10~0); 18612#L1454-1 assume !(1 == ~E_11~0); 18613#L1459-1 assume !(1 == ~E_12~0); 19131#L1464-1 assume { :end_inline_reset_delta_events } true; 18371#L1810-2 [2021-12-19 19:16:56,264 INFO L793 eck$LassoCheckResult]: Loop: 18371#L1810-2 assume !false; 18815#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18731#L1176 assume !false; 19293#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18865#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18069#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18619#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18620#L1003 assume !(0 != eval_~tmp~0#1); 18263#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18264#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19452#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19235#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19236#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19130#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18320#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18321#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18787#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18391#L1231-3 assume !(0 == ~T7_E~0); 18392#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18638#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19620#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19521#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19226#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18337#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18338#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18383#L1271-3 assume !(0 == ~E_2~0); 18384#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18760#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18761#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19282#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19283#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19698#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19655#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18872#L1311-3 assume !(0 == ~E_10~0); 18261#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18262#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18339#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18975#L593-42 assume 1 == ~m_pc~0; 19368#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19133#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19682#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19683#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18162#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18163#L612-42 assume !(1 == ~t1_pc~0); 19084#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19477#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19598#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18250#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18251#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18946#L631-42 assume !(1 == ~t2_pc~0); 18017#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18016#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18935#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18811#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18812#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18412#L650-42 assume 1 == ~t3_pc~0; 17974#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19626#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18605#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18606#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19590#L669-42 assume !(1 == ~t4_pc~0); 17972#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 17973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19401#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19291#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19189#L688-42 assume 1 == ~t5_pc~0; 19280#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19481#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18113#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18114#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18187#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18004#L707-42 assume !(1 == ~t6_pc~0); 18005#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19662#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19406#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19407#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19156#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19157#L726-42 assume 1 == ~t7_pc~0; 19434#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19460#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19461#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18875#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18876#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18979#L745-42 assume 1 == ~t8_pc~0; 19016#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19018#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18345#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L764-42 assume 1 == ~t9_pc~0; 18852#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19205#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19206#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18276#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18277#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18330#L783-42 assume 1 == ~t10_pc~0; 17946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17947#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18542#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18675#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19692#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19376#L802-42 assume 1 == ~t11_pc~0; 18477#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18089#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18039#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18040#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19216#L821-42 assume 1 == ~t12_pc~0; 19217#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18582#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17942#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17943#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18922#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18912#L1339-3 assume !(1 == ~M_E~0); 18913#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19064#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19174#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18591#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18592#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19185#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19681#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19588#L1374-3 assume !(1 == ~T8_E~0); 18413#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18414#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18589#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18590#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18799#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19595#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19563#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19564#L1414-3 assume !(1 == ~E_3~0); 19619#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19378#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18297#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18298#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19184#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18342#L1454-3 assume !(1 == ~E_11~0); 19179#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19180#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18838#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18135#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18395#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18396#L1829 assume !(0 == start_simulation_~tmp~3#1); 18117#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18118#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18918#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18919#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19198#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19199#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18819#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18370#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18371#L1810-2 [2021-12-19 19:16:56,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,268 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2021-12-19 19:16:56,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54065883] [2021-12-19 19:16:56,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,269 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54065883] [2021-12-19 19:16:56,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54065883] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755177489] [2021-12-19 19:16:56,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,336 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,338 INFO L85 PathProgramCache]: Analyzing trace with hash -200631405, now seen corresponding path program 1 times [2021-12-19 19:16:56,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961962467] [2021-12-19 19:16:56,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961962467] [2021-12-19 19:16:56,388 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961962467] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,388 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,389 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499814515] [2021-12-19 19:16:56,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,389 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,390 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,391 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,423 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2021-12-19 19:16:56,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2646 transitions. [2021-12-19 19:16:56,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2646 transitions. [2021-12-19 19:16:56,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2646 transitions. [2021-12-19 19:16:56,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,446 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-19 19:16:56,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2646 transitions. [2021-12-19 19:16:56,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2646 transitions. [2021-12-19 19:16:56,477 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-19 19:16:56,477 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-19 19:16:56,477 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:16:56,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2646 transitions. [2021-12-19 19:16:56,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,486 INFO L791 eck$LassoCheckResult]: Stem: 22303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21824#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21825#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21879#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23218#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22312#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22115#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21514#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21515#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22737#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22850#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23284#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23285#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22243#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22244#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22766#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22685#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22278#L1201 assume !(0 == ~M_E~0); 22279#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23125#L1206-1 assume !(0 == ~T2_E~0); 23111#L1211-1 assume !(0 == ~T3_E~0); 23112#L1216-1 assume !(0 == ~T4_E~0); 22100#L1221-1 assume !(0 == ~T5_E~0); 22101#L1226-1 assume !(0 == ~T6_E~0); 21739#L1231-1 assume !(0 == ~T7_E~0); 21740#L1236-1 assume !(0 == ~T8_E~0); 23148#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22139#L1246-1 assume !(0 == ~T10_E~0); 22140#L1251-1 assume !(0 == ~T11_E~0); 22276#L1256-1 assume !(0 == ~T12_E~0); 21527#L1261-1 assume !(0 == ~E_M~0); 21528#L1266-1 assume !(0 == ~E_1~0); 23270#L1271-1 assume !(0 == ~E_2~0); 22832#L1276-1 assume !(0 == ~E_3~0); 22833#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22780#L1286-1 assume !(0 == ~E_5~0); 21990#L1291-1 assume !(0 == ~E_6~0); 21991#L1296-1 assume !(0 == ~E_7~0); 22566#L1301-1 assume !(0 == ~E_8~0); 22567#L1306-1 assume !(0 == ~E_9~0); 23047#L1311-1 assume !(0 == ~E_10~0); 21941#L1316-1 assume !(0 == ~E_11~0); 21942#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22584#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22585#L593 assume 1 == ~m_pc~0; 22729#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21831#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23257#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22791#L1492 assume !(0 != activate_threads_~tmp~1#1); 22792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23083#L612 assume !(1 == ~t1_pc~0); 23084#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23213#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22213#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21835#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21836#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22255#L631 assume 1 == ~t2_pc~0; 22190#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21612#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21613#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22449#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22450#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21908#L650 assume !(1 == ~t3_pc~0); 21909#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22609#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21832#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21565#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21566#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22758#L669 assume 1 == ~t4_pc~0; 22759#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23117#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22242#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21774#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21775#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21999#L688 assume !(1 == ~t5_pc~0); 21790#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21791#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22709#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22643#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22644#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22776#L707 assume 1 == ~t6_pc~0; 23182#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22419#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22420#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23180#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22715#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22277#L726 assume 1 == ~t7_pc~0; 22178#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21875#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22916#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21644#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21645#L745 assume !(1 == ~t8_pc~0); 22092#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22111#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22949#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22497#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22498#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23008#L764 assume 1 == ~t9_pc~0; 22275#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22117#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22794#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23241#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21664#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21665#L783 assume !(1 == ~t10_pc~0); 21726#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21727#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21768#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21769#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22236#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23119#L802 assume 1 == ~t11_pc~0; 23101#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21609#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21610#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22102#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22103#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22212#L821 assume !(1 == ~t12_pc~0); 22463#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22559#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21616#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21617#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23157#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22803#L1339 assume !(1 == ~M_E~0); 22804#L1339-2 assume !(1 == ~T1_E~0); 23192#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23193#L1349-1 assume !(1 == ~T3_E~0); 22578#L1354-1 assume !(1 == ~T4_E~0); 22579#L1359-1 assume !(1 == ~T5_E~0); 22979#L1364-1 assume !(1 == ~T6_E~0); 22042#L1369-1 assume !(1 == ~T7_E~0); 22043#L1374-1 assume !(1 == ~T8_E~0); 22580#L1379-1 assume !(1 == ~T9_E~0); 22581#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22680#L1389-1 assume !(1 == ~T11_E~0); 23151#L1394-1 assume !(1 == ~T12_E~0); 23152#L1399-1 assume !(1 == ~E_M~0); 23242#L1404-1 assume !(1 == ~E_1~0); 22141#L1409-1 assume !(1 == ~E_2~0); 22142#L1414-1 assume !(1 == ~E_3~0); 22868#L1419-1 assume !(1 == ~E_4~0); 21782#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21783#L1429-1 assume !(1 == ~E_6~0); 22593#L1434-1 assume !(1 == ~E_7~0); 23172#L1439-1 assume !(1 == ~E_8~0); 21820#L1444-1 assume !(1 == ~E_9~0); 21821#L1449-1 assume !(1 == ~E_10~0); 22195#L1454-1 assume !(1 == ~E_11~0); 22196#L1459-1 assume !(1 == ~E_12~0); 22714#L1464-1 assume { :end_inline_reset_delta_events } true; 21954#L1810-2 [2021-12-19 19:16:56,486 INFO L793 eck$LassoCheckResult]: Loop: 21954#L1810-2 assume !false; 22398#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22314#L1176 assume !false; 22876#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22448#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21652#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22202#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22203#L1003 assume !(0 != eval_~tmp~0#1); 21844#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21845#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23035#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22818#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22819#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22712#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21903#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21904#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22370#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21976#L1231-3 assume !(0 == ~T7_E~0); 21977#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22223#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23203#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23105#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22809#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21920#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21921#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21966#L1271-3 assume !(0 == ~E_2~0); 21967#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22343#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22344#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22866#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22867#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23281#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23238#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22455#L1311-3 assume !(0 == ~E_10~0); 21846#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21847#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21922#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L593-42 assume 1 == ~m_pc~0; 22952#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22717#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23267#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21748#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21749#L612-42 assume !(1 == ~t1_pc~0); 22667#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23181#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21833#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21834#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22528#L631-42 assume !(1 == ~t2_pc~0); 21600#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 21599#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22516#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22394#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22395#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21992#L650-42 assume 1 == ~t3_pc~0; 21557#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21558#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23209#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22188#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22189#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23173#L669-42 assume !(1 == ~t4_pc~0); 21553#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21554#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22984#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22874#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 22771#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22772#L688-42 assume !(1 == ~t5_pc~0); 22864#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23064#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21696#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21697#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21770#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21585#L707-42 assume !(1 == ~t6_pc~0); 21586#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23245#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22989#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22990#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22739#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22740#L726-42 assume 1 == ~t7_pc~0; 23017#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23043#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23044#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22458#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22459#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22562#L745-42 assume 1 == ~t8_pc~0; 22598#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22600#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21928#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21573#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21574#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22299#L764-42 assume 1 == ~t9_pc~0; 22435#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22788#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22789#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21859#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21860#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21913#L783-42 assume 1 == ~t10_pc~0; 21529#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21530#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22125#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22258#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23275#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22959#L802-42 assume 1 == ~t11_pc~0; 22060#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21671#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21672#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21622#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21623#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22799#L821-42 assume 1 == ~t12_pc~0; 22800#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22165#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21525#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21526#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22505#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22495#L1339-3 assume !(1 == ~M_E~0); 22496#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22647#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22757#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22174#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22175#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22768#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23264#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23171#L1374-3 assume !(1 == ~T8_E~0); 21996#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21997#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22172#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22173#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22382#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23178#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23146#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23147#L1414-3 assume !(1 == ~E_3~0); 23202#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22961#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21880#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21881#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22767#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21808#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21809#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21925#L1454-3 assume !(1 == ~E_11~0); 22762#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22763#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22421#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21718#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21978#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 21979#L1829 assume !(0 == start_simulation_~tmp~3#1); 21700#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21701#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22501#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22502#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22781#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22782#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22402#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21953#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 21954#L1810-2 [2021-12-19 19:16:56,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,487 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2021-12-19 19:16:56,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588934730] [2021-12-19 19:16:56,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,536 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588934730] [2021-12-19 19:16:56,536 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588934730] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,536 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,536 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761750942] [2021-12-19 19:16:56,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,537 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,537 INFO L85 PathProgramCache]: Analyzing trace with hash -1685871596, now seen corresponding path program 1 times [2021-12-19 19:16:56,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458298715] [2021-12-19 19:16:56,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458298715] [2021-12-19 19:16:56,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458298715] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,578 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321921678] [2021-12-19 19:16:56,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,578 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,579 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,579 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,606 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2021-12-19 19:16:56,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2645 transitions. [2021-12-19 19:16:56,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2645 transitions. [2021-12-19 19:16:56,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2645 transitions. [2021-12-19 19:16:56,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,626 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-19 19:16:56,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2645 transitions. [2021-12-19 19:16:56,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2645 transitions. [2021-12-19 19:16:56,671 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-19 19:16:56,671 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-19 19:16:56,671 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:16:56,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2645 transitions. [2021-12-19 19:16:56,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,679 INFO L791 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25407#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25408#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25462#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 26801#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25895#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25698#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25097#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25098#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26320#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26431#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26867#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26868#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25826#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25827#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26349#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26268#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25861#L1201 assume !(0 == ~M_E~0); 25862#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26708#L1206-1 assume !(0 == ~T2_E~0); 26694#L1211-1 assume !(0 == ~T3_E~0); 26695#L1216-1 assume !(0 == ~T4_E~0); 25683#L1221-1 assume !(0 == ~T5_E~0); 25684#L1226-1 assume !(0 == ~T6_E~0); 25322#L1231-1 assume !(0 == ~T7_E~0); 25323#L1236-1 assume !(0 == ~T8_E~0); 26731#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25719#L1246-1 assume !(0 == ~T10_E~0); 25720#L1251-1 assume !(0 == ~T11_E~0); 25859#L1256-1 assume !(0 == ~T12_E~0); 25110#L1261-1 assume !(0 == ~E_M~0); 25111#L1266-1 assume !(0 == ~E_1~0); 26853#L1271-1 assume !(0 == ~E_2~0); 26415#L1276-1 assume !(0 == ~E_3~0); 26416#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26363#L1286-1 assume !(0 == ~E_5~0); 25573#L1291-1 assume !(0 == ~E_6~0); 25574#L1296-1 assume !(0 == ~E_7~0); 26149#L1301-1 assume !(0 == ~E_8~0); 26150#L1306-1 assume !(0 == ~E_9~0); 26630#L1311-1 assume !(0 == ~E_10~0); 25524#L1316-1 assume !(0 == ~E_11~0); 25525#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26167#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26168#L593 assume 1 == ~m_pc~0; 26312#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25414#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26840#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26374#L1492 assume !(0 != activate_threads_~tmp~1#1); 26375#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26666#L612 assume !(1 == ~t1_pc~0); 26667#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26796#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25796#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25418#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25419#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25838#L631 assume 1 == ~t2_pc~0; 25773#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25195#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25196#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26032#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26033#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25491#L650 assume !(1 == ~t3_pc~0); 25492#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26192#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25415#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25148#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25149#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26341#L669 assume 1 == ~t4_pc~0; 26342#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26700#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25825#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25357#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25358#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25582#L688 assume !(1 == ~t5_pc~0); 25373#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25374#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26292#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26226#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26227#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26359#L707 assume 1 == ~t6_pc~0; 26765#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26002#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26003#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26763#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26298#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25860#L726 assume 1 == ~t7_pc~0; 25761#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25458#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26499#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26773#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25227#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25228#L745 assume !(1 == ~t8_pc~0); 25675#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25694#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26532#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26080#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26081#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26591#L764 assume 1 == ~t9_pc~0; 25858#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25700#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26377#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26824#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25247#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25248#L783 assume !(1 == ~t10_pc~0); 25309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25351#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25352#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 25816#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26702#L802 assume 1 == ~t11_pc~0; 26684#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25192#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25193#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25685#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25686#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25795#L821 assume !(1 == ~t12_pc~0); 26046#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26142#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25199#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25200#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26740#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26386#L1339 assume !(1 == ~M_E~0); 26387#L1339-2 assume !(1 == ~T1_E~0); 26775#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26776#L1349-1 assume !(1 == ~T3_E~0); 26161#L1354-1 assume !(1 == ~T4_E~0); 26162#L1359-1 assume !(1 == ~T5_E~0); 26562#L1364-1 assume !(1 == ~T6_E~0); 25625#L1369-1 assume !(1 == ~T7_E~0); 25626#L1374-1 assume !(1 == ~T8_E~0); 26163#L1379-1 assume !(1 == ~T9_E~0); 26164#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26263#L1389-1 assume !(1 == ~T11_E~0); 26734#L1394-1 assume !(1 == ~T12_E~0); 26735#L1399-1 assume !(1 == ~E_M~0); 26825#L1404-1 assume !(1 == ~E_1~0); 25724#L1409-1 assume !(1 == ~E_2~0); 25725#L1414-1 assume !(1 == ~E_3~0); 26451#L1419-1 assume !(1 == ~E_4~0); 25365#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25366#L1429-1 assume !(1 == ~E_6~0); 26176#L1434-1 assume !(1 == ~E_7~0); 26755#L1439-1 assume !(1 == ~E_8~0); 25403#L1444-1 assume !(1 == ~E_9~0); 25404#L1449-1 assume !(1 == ~E_10~0); 25778#L1454-1 assume !(1 == ~E_11~0); 25779#L1459-1 assume !(1 == ~E_12~0); 26297#L1464-1 assume { :end_inline_reset_delta_events } true; 25537#L1810-2 [2021-12-19 19:16:56,679 INFO L793 eck$LassoCheckResult]: Loop: 25537#L1810-2 assume !false; 25981#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25897#L1176 assume !false; 26459#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26029#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25235#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25785#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25786#L1003 assume !(0 != eval_~tmp~0#1); 25427#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25428#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26618#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26401#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26402#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26295#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25486#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25487#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25953#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25557#L1231-3 assume !(0 == ~T7_E~0); 25558#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25806#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26786#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26687#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26392#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25503#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25504#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25549#L1271-3 assume !(0 == ~E_2~0); 25550#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25926#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25927#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26449#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26450#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26864#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26821#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26038#L1311-3 assume !(0 == ~E_10~0); 25429#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25430#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25505#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26141#L593-42 assume 1 == ~m_pc~0; 26535#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26300#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26849#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25328#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25329#L612-42 assume !(1 == ~t1_pc~0); 26250#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26643#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26764#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25416#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25417#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26112#L631-42 assume 1 == ~t2_pc~0; 25184#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25185#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26101#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25977#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25978#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25578#L650-42 assume 1 == ~t3_pc~0; 25143#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25144#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26792#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25771#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25772#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26756#L669-42 assume !(1 == ~t4_pc~0); 25138#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25139#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26567#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26457#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 26354#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26355#L688-42 assume 1 == ~t5_pc~0; 26446#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26647#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25281#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25282#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25356#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25170#L707-42 assume !(1 == ~t6_pc~0); 25171#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26830#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26572#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26573#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26321#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26322#L726-42 assume 1 == ~t7_pc~0; 26598#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26626#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26627#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26041#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26042#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26145#L745-42 assume 1 == ~t8_pc~0; 26181#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26183#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25509#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25156#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25157#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25882#L764-42 assume 1 == ~t9_pc~0; 26018#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26371#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26372#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25442#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25443#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25496#L783-42 assume 1 == ~t10_pc~0; 25112#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25113#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25708#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25841#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26858#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26542#L802-42 assume 1 == ~t11_pc~0; 25641#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25254#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25255#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25205#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25206#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26382#L821-42 assume !(1 == ~t12_pc~0); 25747#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25748#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25108#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25109#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26088#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26075#L1339-3 assume !(1 == ~M_E~0); 26076#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26230#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26340#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25757#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25758#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26351#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26847#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26754#L1374-3 assume !(1 == ~T8_E~0); 25579#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25580#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25755#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25756#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25965#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26761#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26729#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26730#L1414-3 assume !(1 == ~E_3~0); 26785#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26544#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25463#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25464#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26350#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25391#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25392#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25508#L1454-3 assume !(1 == ~E_11~0); 26345#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26346#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26004#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25301#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25561#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25562#L1829 assume !(0 == start_simulation_~tmp~3#1); 25283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26084#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26085#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26364#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26365#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25985#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25536#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25537#L1810-2 [2021-12-19 19:16:56,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,680 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2021-12-19 19:16:56,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084756092] [2021-12-19 19:16:56,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,709 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084756092] [2021-12-19 19:16:56,709 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084756092] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,710 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,710 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328417921] [2021-12-19 19:16:56,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,710 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 1 times [2021-12-19 19:16:56,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713439308] [2021-12-19 19:16:56,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,712 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,745 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713439308] [2021-12-19 19:16:56,745 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713439308] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,746 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,746 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,746 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166186318] [2021-12-19 19:16:56,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,746 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,747 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,747 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,774 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2021-12-19 19:16:56,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2644 transitions. [2021-12-19 19:16:56,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2644 transitions. [2021-12-19 19:16:56,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2644 transitions. [2021-12-19 19:16:56,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,792 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-19 19:16:56,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2644 transitions. [2021-12-19 19:16:56,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2644 transitions. [2021-12-19 19:16:56,818 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-19 19:16:56,818 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-19 19:16:56,818 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:16:56,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2644 transitions. [2021-12-19 19:16:56,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,825 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,826 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,826 INFO L791 eck$LassoCheckResult]: Stem: 29469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28990#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28991#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29045#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30384#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29478#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29281#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28680#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28681#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29903#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30014#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30450#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30451#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29409#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29410#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29932#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29851#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29444#L1201 assume !(0 == ~M_E~0); 29445#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30291#L1206-1 assume !(0 == ~T2_E~0); 30277#L1211-1 assume !(0 == ~T3_E~0); 30278#L1216-1 assume !(0 == ~T4_E~0); 29265#L1221-1 assume !(0 == ~T5_E~0); 29266#L1226-1 assume !(0 == ~T6_E~0); 28905#L1231-1 assume !(0 == ~T7_E~0); 28906#L1236-1 assume !(0 == ~T8_E~0); 30314#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29302#L1246-1 assume !(0 == ~T10_E~0); 29303#L1251-1 assume !(0 == ~T11_E~0); 29442#L1256-1 assume !(0 == ~T12_E~0); 28691#L1261-1 assume !(0 == ~E_M~0); 28692#L1266-1 assume !(0 == ~E_1~0); 30436#L1271-1 assume !(0 == ~E_2~0); 29998#L1276-1 assume !(0 == ~E_3~0); 29999#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29946#L1286-1 assume !(0 == ~E_5~0); 29156#L1291-1 assume !(0 == ~E_6~0); 29157#L1296-1 assume !(0 == ~E_7~0); 29732#L1301-1 assume !(0 == ~E_8~0); 29733#L1306-1 assume !(0 == ~E_9~0); 30213#L1311-1 assume !(0 == ~E_10~0); 29107#L1316-1 assume !(0 == ~E_11~0); 29108#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29750#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29751#L593 assume 1 == ~m_pc~0; 29895#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28997#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30423#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29957#L1492 assume !(0 != activate_threads_~tmp~1#1); 29958#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30249#L612 assume !(1 == ~t1_pc~0); 30250#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30379#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29379#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29001#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29002#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29421#L631 assume 1 == ~t2_pc~0; 29356#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28778#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28779#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29615#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29616#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29074#L650 assume !(1 == ~t3_pc~0); 29075#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29775#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28998#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28731#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28732#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29924#L669 assume 1 == ~t4_pc~0; 29925#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30283#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29408#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28940#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 28941#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29165#L688 assume !(1 == ~t5_pc~0); 28956#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28957#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29875#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29809#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 29810#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29939#L707 assume 1 == ~t6_pc~0; 30348#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29585#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29586#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30346#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 29881#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29443#L726 assume 1 == ~t7_pc~0; 29342#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29041#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30082#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30356#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 28810#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28811#L745 assume !(1 == ~t8_pc~0); 29258#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29277#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30115#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29663#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29664#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30174#L764 assume 1 == ~t9_pc~0; 29441#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29283#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29960#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30407#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 28830#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28831#L783 assume !(1 == ~t10_pc~0); 28892#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28893#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28934#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28935#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29397#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30285#L802 assume 1 == ~t11_pc~0; 30267#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28775#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28776#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29267#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29268#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29378#L821 assume !(1 == ~t12_pc~0); 29629#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29725#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28780#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28781#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30323#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29969#L1339 assume !(1 == ~M_E~0); 29970#L1339-2 assume !(1 == ~T1_E~0); 30358#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30359#L1349-1 assume !(1 == ~T3_E~0); 29743#L1354-1 assume !(1 == ~T4_E~0); 29744#L1359-1 assume !(1 == ~T5_E~0); 30145#L1364-1 assume !(1 == ~T6_E~0); 29208#L1369-1 assume !(1 == ~T7_E~0); 29209#L1374-1 assume !(1 == ~T8_E~0); 29746#L1379-1 assume !(1 == ~T9_E~0); 29747#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29846#L1389-1 assume !(1 == ~T11_E~0); 30317#L1394-1 assume !(1 == ~T12_E~0); 30318#L1399-1 assume !(1 == ~E_M~0); 30408#L1404-1 assume !(1 == ~E_1~0); 29307#L1409-1 assume !(1 == ~E_2~0); 29308#L1414-1 assume !(1 == ~E_3~0); 30034#L1419-1 assume !(1 == ~E_4~0); 28948#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 28949#L1429-1 assume !(1 == ~E_6~0); 29759#L1434-1 assume !(1 == ~E_7~0); 30338#L1439-1 assume !(1 == ~E_8~0); 28986#L1444-1 assume !(1 == ~E_9~0); 28987#L1449-1 assume !(1 == ~E_10~0); 29361#L1454-1 assume !(1 == ~E_11~0); 29362#L1459-1 assume !(1 == ~E_12~0); 29880#L1464-1 assume { :end_inline_reset_delta_events } true; 29120#L1810-2 [2021-12-19 19:16:56,826 INFO L793 eck$LassoCheckResult]: Loop: 29120#L1810-2 assume !false; 29564#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29480#L1176 assume !false; 30042#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28818#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29368#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29369#L1003 assume !(0 != eval_~tmp~0#1); 29010#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29011#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30201#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29984#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29985#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29878#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29070#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29536#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29140#L1231-3 assume !(0 == ~T7_E~0); 29141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29387#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30369#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30270#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29975#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29086#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29087#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29132#L1271-3 assume !(0 == ~E_2~0); 29133#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29509#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29510#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30031#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30032#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30447#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30404#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29621#L1311-3 assume !(0 == ~E_10~0); 29012#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29013#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29088#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29724#L593-42 assume 1 == ~m_pc~0; 30117#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29883#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30432#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30433#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28911#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28912#L612-42 assume !(1 == ~t1_pc~0); 29833#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30226#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30347#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28999#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29000#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29695#L631-42 assume 1 == ~t2_pc~0; 28764#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28765#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29684#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29560#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29561#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29161#L650-42 assume 1 == ~t3_pc~0; 28723#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28724#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30375#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29354#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29355#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30339#L669-42 assume !(1 == ~t4_pc~0); 28721#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28722#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30150#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30040#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 29937#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29938#L688-42 assume 1 == ~t5_pc~0; 30029#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30230#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28862#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28863#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28939#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28753#L707-42 assume !(1 == ~t6_pc~0); 28754#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30411#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30155#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30156#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29905#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29906#L726-42 assume 1 == ~t7_pc~0; 30183#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30209#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30210#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29624#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29625#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29728#L745-42 assume 1 == ~t8_pc~0; 29765#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29767#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29094#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28739#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28740#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29465#L764-42 assume 1 == ~t9_pc~0; 29601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29954#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29955#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29025#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29026#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29079#L783-42 assume 1 == ~t10_pc~0; 28695#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28696#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29291#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29424#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30441#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30125#L802-42 assume 1 == ~t11_pc~0; 29226#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28837#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28838#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28788#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28789#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29965#L821-42 assume !(1 == ~t12_pc~0); 29330#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29331#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28693#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28694#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29671#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29661#L1339-3 assume !(1 == ~M_E~0); 29662#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29813#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29923#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29340#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29341#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29934#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30430#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30337#L1374-3 assume !(1 == ~T8_E~0); 29162#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29163#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29338#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29339#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29548#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30344#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30312#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30313#L1414-3 assume !(1 == ~E_3~0); 30368#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30127#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29046#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29047#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29933#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28974#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28975#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29091#L1454-3 assume !(1 == ~E_11~0); 29928#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29929#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29587#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28884#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29144#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29145#L1829 assume !(0 == start_simulation_~tmp~3#1); 28866#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28867#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29667#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29668#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29947#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29948#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29568#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29119#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29120#L1810-2 [2021-12-19 19:16:56,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,827 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2021-12-19 19:16:56,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520183641] [2021-12-19 19:16:56,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,828 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520183641] [2021-12-19 19:16:56,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520183641] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542195011] [2021-12-19 19:16:56,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,853 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:56,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 2 times [2021-12-19 19:16:56,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683047845] [2021-12-19 19:16:56,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:56,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:56,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:56,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683047845] [2021-12-19 19:16:56,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683047845] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:56,889 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:56,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:56,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373193931] [2021-12-19 19:16:56,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:56,890 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:56,890 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:56,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:56,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:56,891 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:56,918 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2021-12-19 19:16:56,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:56,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2643 transitions. [2021-12-19 19:16:56,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2643 transitions. [2021-12-19 19:16:56,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:56,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:56,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2643 transitions. [2021-12-19 19:16:56,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:56,956 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-19 19:16:56,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2643 transitions. [2021-12-19 19:16:56,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:56,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:56,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2643 transitions. [2021-12-19 19:16:56,979 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-19 19:16:56,979 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-19 19:16:56,979 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:16:56,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2643 transitions. [2021-12-19 19:16:56,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:56,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:56,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:56,986 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,986 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:56,986 INFO L791 eck$LassoCheckResult]: Stem: 33052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32573#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32574#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32628#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 33967#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33061#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32864#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33486#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33597#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34033#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34034#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32992#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32993#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33515#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33434#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33027#L1201 assume !(0 == ~M_E~0); 33028#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33874#L1206-1 assume !(0 == ~T2_E~0); 33860#L1211-1 assume !(0 == ~T3_E~0); 33861#L1216-1 assume !(0 == ~T4_E~0); 32848#L1221-1 assume !(0 == ~T5_E~0); 32849#L1226-1 assume !(0 == ~T6_E~0); 32488#L1231-1 assume !(0 == ~T7_E~0); 32489#L1236-1 assume !(0 == ~T8_E~0); 33897#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32885#L1246-1 assume !(0 == ~T10_E~0); 32886#L1251-1 assume !(0 == ~T11_E~0); 33025#L1256-1 assume !(0 == ~T12_E~0); 32274#L1261-1 assume !(0 == ~E_M~0); 32275#L1266-1 assume !(0 == ~E_1~0); 34019#L1271-1 assume !(0 == ~E_2~0); 33581#L1276-1 assume !(0 == ~E_3~0); 33582#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33529#L1286-1 assume !(0 == ~E_5~0); 32739#L1291-1 assume !(0 == ~E_6~0); 32740#L1296-1 assume !(0 == ~E_7~0); 33315#L1301-1 assume !(0 == ~E_8~0); 33316#L1306-1 assume !(0 == ~E_9~0); 33796#L1311-1 assume !(0 == ~E_10~0); 32690#L1316-1 assume !(0 == ~E_11~0); 32691#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33333#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33334#L593 assume 1 == ~m_pc~0; 33478#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32580#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34006#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33540#L1492 assume !(0 != activate_threads_~tmp~1#1); 33541#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33832#L612 assume !(1 == ~t1_pc~0); 33833#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33962#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32962#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32584#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32585#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33004#L631 assume 1 == ~t2_pc~0; 32939#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32361#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32362#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33198#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33199#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32657#L650 assume !(1 == ~t3_pc~0); 32658#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33358#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32581#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32314#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32315#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33507#L669 assume 1 == ~t4_pc~0; 33508#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33866#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32991#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32523#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32524#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32748#L688 assume !(1 == ~t5_pc~0); 32539#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32540#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33458#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33392#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33393#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33522#L707 assume 1 == ~t6_pc~0; 33931#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33168#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33169#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33929#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33464#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33026#L726 assume 1 == ~t7_pc~0; 32925#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32624#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33665#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33939#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32393#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32394#L745 assume !(1 == ~t8_pc~0); 32841#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32860#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33698#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33246#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33247#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33757#L764 assume 1 == ~t9_pc~0; 33024#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32866#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33543#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33990#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32413#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32414#L783 assume !(1 == ~t10_pc~0); 32475#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32476#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32517#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32518#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 32980#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33868#L802 assume 1 == ~t11_pc~0; 33850#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32358#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32359#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32850#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 32851#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32961#L821 assume !(1 == ~t12_pc~0); 33212#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33308#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32363#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32364#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 33906#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33552#L1339 assume !(1 == ~M_E~0); 33553#L1339-2 assume !(1 == ~T1_E~0); 33941#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33942#L1349-1 assume !(1 == ~T3_E~0); 33326#L1354-1 assume !(1 == ~T4_E~0); 33327#L1359-1 assume !(1 == ~T5_E~0); 33728#L1364-1 assume !(1 == ~T6_E~0); 32791#L1369-1 assume !(1 == ~T7_E~0); 32792#L1374-1 assume !(1 == ~T8_E~0); 33329#L1379-1 assume !(1 == ~T9_E~0); 33330#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33429#L1389-1 assume !(1 == ~T11_E~0); 33900#L1394-1 assume !(1 == ~T12_E~0); 33901#L1399-1 assume !(1 == ~E_M~0); 33991#L1404-1 assume !(1 == ~E_1~0); 32890#L1409-1 assume !(1 == ~E_2~0); 32891#L1414-1 assume !(1 == ~E_3~0); 33617#L1419-1 assume !(1 == ~E_4~0); 32531#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32532#L1429-1 assume !(1 == ~E_6~0); 33342#L1434-1 assume !(1 == ~E_7~0); 33921#L1439-1 assume !(1 == ~E_8~0); 32569#L1444-1 assume !(1 == ~E_9~0); 32570#L1449-1 assume !(1 == ~E_10~0); 32944#L1454-1 assume !(1 == ~E_11~0); 32945#L1459-1 assume !(1 == ~E_12~0); 33463#L1464-1 assume { :end_inline_reset_delta_events } true; 32703#L1810-2 [2021-12-19 19:16:56,986 INFO L793 eck$LassoCheckResult]: Loop: 32703#L1810-2 assume !false; 33147#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33063#L1176 assume !false; 33625#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33195#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32401#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32951#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32952#L1003 assume !(0 != eval_~tmp~0#1); 32593#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32594#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33784#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33567#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33568#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33461#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32652#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32653#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33119#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32723#L1231-3 assume !(0 == ~T7_E~0); 32724#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32970#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33952#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33853#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33558#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32669#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32670#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32715#L1271-3 assume !(0 == ~E_2~0); 32716#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33092#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33093#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33614#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33615#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34030#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33987#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33204#L1311-3 assume !(0 == ~E_10~0); 32595#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32596#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32671#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33307#L593-42 assume 1 == ~m_pc~0; 33700#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33466#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34015#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34016#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32494#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32495#L612-42 assume !(1 == ~t1_pc~0); 33416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 33809#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33930#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32582#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32583#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33278#L631-42 assume 1 == ~t2_pc~0; 32347#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32348#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33267#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33143#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33144#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32744#L650-42 assume 1 == ~t3_pc~0; 32306#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32307#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33958#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32937#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32938#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33922#L669-42 assume !(1 == ~t4_pc~0); 32304#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32305#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33733#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33623#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 33520#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33521#L688-42 assume 1 == ~t5_pc~0; 33612#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33813#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32445#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32446#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32522#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32336#L707-42 assume !(1 == ~t6_pc~0); 32337#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33994#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33738#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33739#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33488#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33489#L726-42 assume 1 == ~t7_pc~0; 33766#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33792#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33793#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33207#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33208#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33311#L745-42 assume 1 == ~t8_pc~0; 33348#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33350#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32677#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32322#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32323#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33048#L764-42 assume 1 == ~t9_pc~0; 33184#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33537#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33538#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32608#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32609#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32662#L783-42 assume 1 == ~t10_pc~0; 32278#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32279#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32874#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33007#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34024#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33708#L802-42 assume 1 == ~t11_pc~0; 32809#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32420#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32421#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32371#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32372#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33548#L821-42 assume !(1 == ~t12_pc~0); 32913#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 32914#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32276#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32277#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33254#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33244#L1339-3 assume !(1 == ~M_E~0); 33245#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33396#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33506#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32923#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32924#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33517#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34013#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33920#L1374-3 assume !(1 == ~T8_E~0); 32745#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32746#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32921#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32922#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33131#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33927#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33895#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33896#L1414-3 assume !(1 == ~E_3~0); 33951#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33710#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32629#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32630#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33516#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32557#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32558#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32674#L1454-3 assume !(1 == ~E_11~0); 33511#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33512#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33170#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32467#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32727#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32728#L1829 assume !(0 == start_simulation_~tmp~3#1); 32449#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32450#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33250#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33251#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33530#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33531#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33151#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32702#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32703#L1810-2 [2021-12-19 19:16:56,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:56,987 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2021-12-19 19:16:56,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:56,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362211890] [2021-12-19 19:16:56,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:56,988 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:56,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362211890] [2021-12-19 19:16:57,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362211890] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902316729] [2021-12-19 19:16:57,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 3 times [2021-12-19 19:16:57,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771659648] [2021-12-19 19:16:57,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771659648] [2021-12-19 19:16:57,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771659648] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,052 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308905533] [2021-12-19 19:16:57,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,054 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,078 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2021-12-19 19:16:57,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2642 transitions. [2021-12-19 19:16:57,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2642 transitions. [2021-12-19 19:16:57,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:57,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:57,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2642 transitions. [2021-12-19 19:16:57,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,104 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-19 19:16:57,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2642 transitions. [2021-12-19 19:16:57,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:57,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2642 transitions. [2021-12-19 19:16:57,131 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-19 19:16:57,131 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-19 19:16:57,131 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:16:57,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2642 transitions. [2021-12-19 19:16:57,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,137 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,137 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,138 INFO L791 eck$LassoCheckResult]: Stem: 36635#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36156#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36157#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36211#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37550#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36644#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36447#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35846#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35847#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37069#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37180#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37616#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37617#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36575#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36576#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37098#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37017#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36610#L1201 assume !(0 == ~M_E~0); 36611#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37457#L1206-1 assume !(0 == ~T2_E~0); 37443#L1211-1 assume !(0 == ~T3_E~0); 37444#L1216-1 assume !(0 == ~T4_E~0); 36431#L1221-1 assume !(0 == ~T5_E~0); 36432#L1226-1 assume !(0 == ~T6_E~0); 36071#L1231-1 assume !(0 == ~T7_E~0); 36072#L1236-1 assume !(0 == ~T8_E~0); 37480#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36468#L1246-1 assume !(0 == ~T10_E~0); 36469#L1251-1 assume !(0 == ~T11_E~0); 36608#L1256-1 assume !(0 == ~T12_E~0); 35857#L1261-1 assume !(0 == ~E_M~0); 35858#L1266-1 assume !(0 == ~E_1~0); 37602#L1271-1 assume !(0 == ~E_2~0); 37164#L1276-1 assume !(0 == ~E_3~0); 37165#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37112#L1286-1 assume !(0 == ~E_5~0); 36322#L1291-1 assume !(0 == ~E_6~0); 36323#L1296-1 assume !(0 == ~E_7~0); 36898#L1301-1 assume !(0 == ~E_8~0); 36899#L1306-1 assume !(0 == ~E_9~0); 37379#L1311-1 assume !(0 == ~E_10~0); 36273#L1316-1 assume !(0 == ~E_11~0); 36274#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36916#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36917#L593 assume 1 == ~m_pc~0; 37061#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36163#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37589#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37123#L1492 assume !(0 != activate_threads_~tmp~1#1); 37124#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37415#L612 assume !(1 == ~t1_pc~0); 37416#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37545#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36545#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36167#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36168#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36587#L631 assume 1 == ~t2_pc~0; 36522#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35944#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35945#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36781#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 36782#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36240#L650 assume !(1 == ~t3_pc~0); 36241#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36941#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36164#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35897#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 35898#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37090#L669 assume 1 == ~t4_pc~0; 37091#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37449#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36574#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36106#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36107#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36331#L688 assume !(1 == ~t5_pc~0); 36122#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36123#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37041#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36975#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 36976#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37105#L707 assume 1 == ~t6_pc~0; 37514#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36751#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36752#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37512#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37047#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36609#L726 assume 1 == ~t7_pc~0; 36508#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36207#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37248#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37522#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35977#L745 assume !(1 == ~t8_pc~0); 36424#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36443#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37281#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36829#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36830#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37340#L764 assume 1 == ~t9_pc~0; 36607#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36449#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37126#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37573#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 35996#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35997#L783 assume !(1 == ~t10_pc~0); 36058#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36059#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36100#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36101#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36563#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37451#L802 assume 1 == ~t11_pc~0; 37433#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35941#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35942#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36433#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36434#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36544#L821 assume !(1 == ~t12_pc~0); 36795#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36891#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35946#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35947#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37489#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37135#L1339 assume !(1 == ~M_E~0); 37136#L1339-2 assume !(1 == ~T1_E~0); 37524#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37525#L1349-1 assume !(1 == ~T3_E~0); 36909#L1354-1 assume !(1 == ~T4_E~0); 36910#L1359-1 assume !(1 == ~T5_E~0); 37311#L1364-1 assume !(1 == ~T6_E~0); 36374#L1369-1 assume !(1 == ~T7_E~0); 36375#L1374-1 assume !(1 == ~T8_E~0); 36912#L1379-1 assume !(1 == ~T9_E~0); 36913#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37012#L1389-1 assume !(1 == ~T11_E~0); 37483#L1394-1 assume !(1 == ~T12_E~0); 37484#L1399-1 assume !(1 == ~E_M~0); 37574#L1404-1 assume !(1 == ~E_1~0); 36473#L1409-1 assume !(1 == ~E_2~0); 36474#L1414-1 assume !(1 == ~E_3~0); 37200#L1419-1 assume !(1 == ~E_4~0); 36114#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36115#L1429-1 assume !(1 == ~E_6~0); 36925#L1434-1 assume !(1 == ~E_7~0); 37504#L1439-1 assume !(1 == ~E_8~0); 36152#L1444-1 assume !(1 == ~E_9~0); 36153#L1449-1 assume !(1 == ~E_10~0); 36527#L1454-1 assume !(1 == ~E_11~0); 36528#L1459-1 assume !(1 == ~E_12~0); 37046#L1464-1 assume { :end_inline_reset_delta_events } true; 36286#L1810-2 [2021-12-19 19:16:57,138 INFO L793 eck$LassoCheckResult]: Loop: 36286#L1810-2 assume !false; 36730#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36646#L1176 assume !false; 37208#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36778#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35984#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36534#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36535#L1003 assume !(0 != eval_~tmp~0#1); 36176#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36177#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37367#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37150#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37151#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37044#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36235#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36236#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36702#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36306#L1231-3 assume !(0 == ~T7_E~0); 36307#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36553#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37535#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37436#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37141#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36298#L1271-3 assume !(0 == ~E_2~0); 36299#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36675#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36676#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37197#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37198#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37613#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37570#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36787#L1311-3 assume !(0 == ~E_10~0); 36178#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36179#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36890#L593-42 assume 1 == ~m_pc~0; 37283#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37049#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37598#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37599#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36077#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36078#L612-42 assume !(1 == ~t1_pc~0); 36999#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37392#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37513#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36165#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36166#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36861#L631-42 assume 1 == ~t2_pc~0; 35930#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35931#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36850#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36726#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36727#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36327#L650-42 assume 1 == ~t3_pc~0; 35889#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35890#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37541#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36520#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36521#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37505#L669-42 assume 1 == ~t4_pc~0; 36801#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35888#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37316#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37206#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 37103#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37104#L688-42 assume 1 == ~t5_pc~0; 37195#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37396#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36028#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36029#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36105#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35919#L707-42 assume !(1 == ~t6_pc~0); 35920#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37577#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37321#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37322#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37071#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37072#L726-42 assume 1 == ~t7_pc~0; 37349#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37375#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37376#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36790#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36791#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36894#L745-42 assume 1 == ~t8_pc~0; 36931#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36933#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36260#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35905#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35906#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36631#L764-42 assume !(1 == ~t9_pc~0); 36768#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 37120#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37121#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36191#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36192#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36245#L783-42 assume 1 == ~t10_pc~0; 35861#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35862#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36457#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36590#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37607#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37291#L802-42 assume 1 == ~t11_pc~0; 36392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36003#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36004#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35954#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35955#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37131#L821-42 assume !(1 == ~t12_pc~0); 36496#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36497#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35859#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35860#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36837#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36827#L1339-3 assume !(1 == ~M_E~0); 36828#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36979#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37089#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36506#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36507#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37100#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37596#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37503#L1374-3 assume !(1 == ~T8_E~0); 36328#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36329#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36504#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36505#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36714#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37510#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37478#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37479#L1414-3 assume !(1 == ~E_3~0); 37534#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37293#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36212#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36213#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37099#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36140#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36141#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36257#L1454-3 assume !(1 == ~E_11~0); 37094#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37095#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36753#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36050#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36310#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36311#L1829 assume !(0 == start_simulation_~tmp~3#1); 36032#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36033#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36833#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36834#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37113#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37114#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36734#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36285#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36286#L1810-2 [2021-12-19 19:16:57,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2021-12-19 19:16:57,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058500418] [2021-12-19 19:16:57,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058500418] [2021-12-19 19:16:57,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058500418] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,177 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,177 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,177 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129114484] [2021-12-19 19:16:57,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,178 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1901825325, now seen corresponding path program 1 times [2021-12-19 19:16:57,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880578146] [2021-12-19 19:16:57,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880578146] [2021-12-19 19:16:57,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880578146] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,215 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,215 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803630143] [2021-12-19 19:16:57,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,215 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,216 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,217 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,254 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2021-12-19 19:16:57,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2641 transitions. [2021-12-19 19:16:57,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2641 transitions. [2021-12-19 19:16:57,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:57,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:57,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2641 transitions. [2021-12-19 19:16:57,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,270 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-19 19:16:57,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2641 transitions. [2021-12-19 19:16:57,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:57,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2641 transitions. [2021-12-19 19:16:57,309 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-19 19:16:57,309 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-19 19:16:57,309 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:16:57,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2641 transitions. [2021-12-19 19:16:57,313 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,316 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,316 INFO L791 eck$LassoCheckResult]: Stem: 40218#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39739#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39740#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39794#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41133#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40227#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40030#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39429#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39430#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40652#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40763#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41199#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41200#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40158#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40159#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40681#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40600#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40193#L1201 assume !(0 == ~M_E~0); 40194#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41040#L1206-1 assume !(0 == ~T2_E~0); 41026#L1211-1 assume !(0 == ~T3_E~0); 41027#L1216-1 assume !(0 == ~T4_E~0); 40014#L1221-1 assume !(0 == ~T5_E~0); 40015#L1226-1 assume !(0 == ~T6_E~0); 39654#L1231-1 assume !(0 == ~T7_E~0); 39655#L1236-1 assume !(0 == ~T8_E~0); 41063#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40051#L1246-1 assume !(0 == ~T10_E~0); 40052#L1251-1 assume !(0 == ~T11_E~0); 40191#L1256-1 assume !(0 == ~T12_E~0); 39440#L1261-1 assume !(0 == ~E_M~0); 39441#L1266-1 assume !(0 == ~E_1~0); 41185#L1271-1 assume !(0 == ~E_2~0); 40747#L1276-1 assume !(0 == ~E_3~0); 40748#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40695#L1286-1 assume !(0 == ~E_5~0); 39905#L1291-1 assume !(0 == ~E_6~0); 39906#L1296-1 assume !(0 == ~E_7~0); 40481#L1301-1 assume !(0 == ~E_8~0); 40482#L1306-1 assume !(0 == ~E_9~0); 40962#L1311-1 assume !(0 == ~E_10~0); 39856#L1316-1 assume !(0 == ~E_11~0); 39857#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40499#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40500#L593 assume 1 == ~m_pc~0; 40644#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39746#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41172#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40706#L1492 assume !(0 != activate_threads_~tmp~1#1); 40707#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40998#L612 assume !(1 == ~t1_pc~0); 40999#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41128#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40128#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39750#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39751#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40170#L631 assume 1 == ~t2_pc~0; 40105#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39527#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39528#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40364#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40365#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39823#L650 assume !(1 == ~t3_pc~0); 39824#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40524#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39747#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39480#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39481#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40673#L669 assume 1 == ~t4_pc~0; 40674#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41032#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40157#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39689#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39690#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39914#L688 assume !(1 == ~t5_pc~0); 39705#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39706#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40624#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40558#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40559#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40688#L707 assume 1 == ~t6_pc~0; 41097#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40334#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40335#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41095#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40630#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40192#L726 assume 1 == ~t7_pc~0; 40091#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39790#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40831#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41105#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39559#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39560#L745 assume !(1 == ~t8_pc~0); 40007#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40026#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40864#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40412#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40413#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40923#L764 assume 1 == ~t9_pc~0; 40190#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40032#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40709#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41156#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39579#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39580#L783 assume !(1 == ~t10_pc~0); 39641#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39642#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39683#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39684#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40146#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41034#L802 assume 1 == ~t11_pc~0; 41016#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39524#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39525#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40016#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40017#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40127#L821 assume !(1 == ~t12_pc~0); 40378#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40474#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39529#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39530#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41072#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40718#L1339 assume !(1 == ~M_E~0); 40719#L1339-2 assume !(1 == ~T1_E~0); 41107#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41108#L1349-1 assume !(1 == ~T3_E~0); 40492#L1354-1 assume !(1 == ~T4_E~0); 40493#L1359-1 assume !(1 == ~T5_E~0); 40894#L1364-1 assume !(1 == ~T6_E~0); 39957#L1369-1 assume !(1 == ~T7_E~0); 39958#L1374-1 assume !(1 == ~T8_E~0); 40495#L1379-1 assume !(1 == ~T9_E~0); 40496#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40595#L1389-1 assume !(1 == ~T11_E~0); 41066#L1394-1 assume !(1 == ~T12_E~0); 41067#L1399-1 assume !(1 == ~E_M~0); 41157#L1404-1 assume !(1 == ~E_1~0); 40056#L1409-1 assume !(1 == ~E_2~0); 40057#L1414-1 assume !(1 == ~E_3~0); 40783#L1419-1 assume !(1 == ~E_4~0); 39697#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39698#L1429-1 assume !(1 == ~E_6~0); 40508#L1434-1 assume !(1 == ~E_7~0); 41087#L1439-1 assume !(1 == ~E_8~0); 39735#L1444-1 assume !(1 == ~E_9~0); 39736#L1449-1 assume !(1 == ~E_10~0); 40110#L1454-1 assume !(1 == ~E_11~0); 40111#L1459-1 assume !(1 == ~E_12~0); 40629#L1464-1 assume { :end_inline_reset_delta_events } true; 39869#L1810-2 [2021-12-19 19:16:57,316 INFO L793 eck$LassoCheckResult]: Loop: 39869#L1810-2 assume !false; 40313#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40229#L1176 assume !false; 40791#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40361#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39567#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40117#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40118#L1003 assume !(0 != eval_~tmp~0#1); 39759#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39760#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40950#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40733#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40734#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40627#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39818#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39819#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40285#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39889#L1231-3 assume !(0 == ~T7_E~0); 39890#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40136#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41118#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41019#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40724#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39835#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39836#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39881#L1271-3 assume !(0 == ~E_2~0); 39882#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40258#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40259#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40780#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40781#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41196#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41153#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40370#L1311-3 assume !(0 == ~E_10~0); 39761#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39762#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39837#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40473#L593-42 assume 1 == ~m_pc~0; 40866#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40632#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41181#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41182#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39660#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39661#L612-42 assume !(1 == ~t1_pc~0); 40582#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40975#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41096#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39748#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39749#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40444#L631-42 assume 1 == ~t2_pc~0; 39513#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39514#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40433#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40309#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40310#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39910#L650-42 assume 1 == ~t3_pc~0; 39472#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39473#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41124#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40103#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40104#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41088#L669-42 assume 1 == ~t4_pc~0; 40384#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39471#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40899#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40789#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 40686#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40687#L688-42 assume 1 == ~t5_pc~0; 40778#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40979#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39611#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39612#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39688#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39502#L707-42 assume 1 == ~t6_pc~0; 39504#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41160#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40904#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40905#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40654#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40655#L726-42 assume 1 == ~t7_pc~0; 40932#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40958#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40959#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40373#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40374#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40477#L745-42 assume 1 == ~t8_pc~0; 40514#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40516#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39843#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39488#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39489#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40214#L764-42 assume 1 == ~t9_pc~0; 40350#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40703#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40704#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39774#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39775#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39828#L783-42 assume 1 == ~t10_pc~0; 39444#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39445#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40040#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40173#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41190#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40874#L802-42 assume 1 == ~t11_pc~0; 39975#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39586#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39587#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39537#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39538#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40714#L821-42 assume 1 == ~t12_pc~0; 40715#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40080#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39442#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39443#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40420#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40410#L1339-3 assume !(1 == ~M_E~0); 40411#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40562#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40672#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40089#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40090#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40683#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41179#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41086#L1374-3 assume !(1 == ~T8_E~0); 39911#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39912#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40087#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40088#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40297#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41093#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41061#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41062#L1414-3 assume !(1 == ~E_3~0); 41117#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40876#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39795#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39796#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40682#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39723#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39724#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39840#L1454-3 assume !(1 == ~E_11~0); 40677#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40678#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40336#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39633#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39893#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39894#L1829 assume !(0 == start_simulation_~tmp~3#1); 39615#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39616#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40416#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40417#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40696#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40697#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40317#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39868#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 39869#L1810-2 [2021-12-19 19:16:57,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,317 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2021-12-19 19:16:57,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318325283] [2021-12-19 19:16:57,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,318 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,344 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318325283] [2021-12-19 19:16:57,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318325283] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072484959] [2021-12-19 19:16:57,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,348 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1229697104, now seen corresponding path program 1 times [2021-12-19 19:16:57,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485381836] [2021-12-19 19:16:57,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,349 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485381836] [2021-12-19 19:16:57,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485381836] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,383 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826791618] [2021-12-19 19:16:57,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,384 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,384 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:57,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:57,386 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,411 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2021-12-19 19:16:57,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:57,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2640 transitions. [2021-12-19 19:16:57,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2640 transitions. [2021-12-19 19:16:57,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-19 19:16:57,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-19 19:16:57,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2640 transitions. [2021-12-19 19:16:57,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,426 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-19 19:16:57,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2640 transitions. [2021-12-19 19:16:57,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-19 19:16:57,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2640 transitions. [2021-12-19 19:16:57,451 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-19 19:16:57,451 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-19 19:16:57,451 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:16:57,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2640 transitions. [2021-12-19 19:16:57,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-19 19:16:57,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,458 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,458 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,458 INFO L791 eck$LassoCheckResult]: Stem: 43801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43322#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43323#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43377#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 44716#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43810#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43613#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43012#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43013#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44235#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44346#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44782#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44783#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43741#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43742#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44264#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44183#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43776#L1201 assume !(0 == ~M_E~0); 43777#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44623#L1206-1 assume !(0 == ~T2_E~0); 44609#L1211-1 assume !(0 == ~T3_E~0); 44610#L1216-1 assume !(0 == ~T4_E~0); 43597#L1221-1 assume !(0 == ~T5_E~0); 43598#L1226-1 assume !(0 == ~T6_E~0); 43237#L1231-1 assume !(0 == ~T7_E~0); 43238#L1236-1 assume !(0 == ~T8_E~0); 44646#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43634#L1246-1 assume !(0 == ~T10_E~0); 43635#L1251-1 assume !(0 == ~T11_E~0); 43774#L1256-1 assume !(0 == ~T12_E~0); 43023#L1261-1 assume !(0 == ~E_M~0); 43024#L1266-1 assume !(0 == ~E_1~0); 44768#L1271-1 assume !(0 == ~E_2~0); 44330#L1276-1 assume !(0 == ~E_3~0); 44331#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44278#L1286-1 assume !(0 == ~E_5~0); 43488#L1291-1 assume !(0 == ~E_6~0); 43489#L1296-1 assume !(0 == ~E_7~0); 44064#L1301-1 assume !(0 == ~E_8~0); 44065#L1306-1 assume !(0 == ~E_9~0); 44545#L1311-1 assume !(0 == ~E_10~0); 43439#L1316-1 assume !(0 == ~E_11~0); 43440#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44082#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44083#L593 assume 1 == ~m_pc~0; 44227#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43329#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44755#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44289#L1492 assume !(0 != activate_threads_~tmp~1#1); 44290#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44581#L612 assume !(1 == ~t1_pc~0); 44582#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44711#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43711#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43333#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43334#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43753#L631 assume 1 == ~t2_pc~0; 43688#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43110#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43111#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43947#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 43948#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43406#L650 assume !(1 == ~t3_pc~0); 43407#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44107#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43330#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43063#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43064#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44256#L669 assume 1 == ~t4_pc~0; 44257#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44615#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43740#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43272#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43273#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43497#L688 assume !(1 == ~t5_pc~0); 43288#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43289#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44207#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44141#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44142#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44271#L707 assume 1 == ~t6_pc~0; 44680#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43917#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43918#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44678#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44213#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43775#L726 assume 1 == ~t7_pc~0; 43674#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43373#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44414#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44688#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43142#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43143#L745 assume !(1 == ~t8_pc~0); 43590#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43609#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44447#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43995#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43996#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44506#L764 assume 1 == ~t9_pc~0; 43773#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43615#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44292#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44739#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43162#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43163#L783 assume !(1 == ~t10_pc~0); 43224#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43225#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43266#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43267#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 43729#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44617#L802 assume 1 == ~t11_pc~0; 44599#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43107#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43108#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43599#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43600#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43710#L821 assume !(1 == ~t12_pc~0); 43961#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44057#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43112#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43113#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44655#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44301#L1339 assume !(1 == ~M_E~0); 44302#L1339-2 assume !(1 == ~T1_E~0); 44690#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44691#L1349-1 assume !(1 == ~T3_E~0); 44075#L1354-1 assume !(1 == ~T4_E~0); 44076#L1359-1 assume !(1 == ~T5_E~0); 44477#L1364-1 assume !(1 == ~T6_E~0); 43540#L1369-1 assume !(1 == ~T7_E~0); 43541#L1374-1 assume !(1 == ~T8_E~0); 44078#L1379-1 assume !(1 == ~T9_E~0); 44079#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44178#L1389-1 assume !(1 == ~T11_E~0); 44649#L1394-1 assume !(1 == ~T12_E~0); 44650#L1399-1 assume !(1 == ~E_M~0); 44740#L1404-1 assume !(1 == ~E_1~0); 43639#L1409-1 assume !(1 == ~E_2~0); 43640#L1414-1 assume !(1 == ~E_3~0); 44366#L1419-1 assume !(1 == ~E_4~0); 43280#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43281#L1429-1 assume !(1 == ~E_6~0); 44091#L1434-1 assume !(1 == ~E_7~0); 44670#L1439-1 assume !(1 == ~E_8~0); 43318#L1444-1 assume !(1 == ~E_9~0); 43319#L1449-1 assume !(1 == ~E_10~0); 43693#L1454-1 assume !(1 == ~E_11~0); 43694#L1459-1 assume !(1 == ~E_12~0); 44212#L1464-1 assume { :end_inline_reset_delta_events } true; 43452#L1810-2 [2021-12-19 19:16:57,459 INFO L793 eck$LassoCheckResult]: Loop: 43452#L1810-2 assume !false; 43896#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43812#L1176 assume !false; 44374#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43944#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43150#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43700#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43701#L1003 assume !(0 != eval_~tmp~0#1); 43342#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43343#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44533#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44316#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44317#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44210#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43401#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43402#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43868#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43472#L1231-3 assume !(0 == ~T7_E~0); 43473#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43719#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44701#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44602#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44307#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43418#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43419#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43464#L1271-3 assume !(0 == ~E_2~0); 43465#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43841#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43842#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44363#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44364#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44779#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44736#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43953#L1311-3 assume !(0 == ~E_10~0); 43344#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43345#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43420#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44056#L593-42 assume 1 == ~m_pc~0; 44449#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44215#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44764#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44765#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43243#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43244#L612-42 assume !(1 == ~t1_pc~0); 44165#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44558#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44679#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43331#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43332#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44027#L631-42 assume 1 == ~t2_pc~0; 43096#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43097#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44016#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43892#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43893#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43493#L650-42 assume !(1 == ~t3_pc~0); 43057#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 43056#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44707#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43686#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43687#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44671#L669-42 assume !(1 == ~t4_pc~0); 43053#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43054#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44482#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44372#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 44269#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44270#L688-42 assume 1 == ~t5_pc~0; 44361#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44562#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43194#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43195#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43271#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43085#L707-42 assume !(1 == ~t6_pc~0); 43086#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44743#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44487#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44488#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44237#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44238#L726-42 assume 1 == ~t7_pc~0; 44515#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44541#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44542#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43956#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43957#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44060#L745-42 assume 1 == ~t8_pc~0; 44097#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44099#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43426#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43071#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43072#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43797#L764-42 assume 1 == ~t9_pc~0; 43933#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44286#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44287#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43357#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43358#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43411#L783-42 assume 1 == ~t10_pc~0; 43027#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43028#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43623#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43756#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44773#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44457#L802-42 assume 1 == ~t11_pc~0; 43558#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43169#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43170#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43120#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43121#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44297#L821-42 assume 1 == ~t12_pc~0; 44298#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43663#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43025#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43026#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44003#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43993#L1339-3 assume !(1 == ~M_E~0); 43994#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44145#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44255#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43672#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43673#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44266#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44762#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44669#L1374-3 assume !(1 == ~T8_E~0); 43494#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43495#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43670#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43671#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43880#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44676#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44644#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44645#L1414-3 assume !(1 == ~E_3~0); 44700#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44459#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43378#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43379#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44265#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43306#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43307#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43423#L1454-3 assume !(1 == ~E_11~0); 44260#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44261#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43919#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43216#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43476#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43477#L1829 assume !(0 == start_simulation_~tmp~3#1); 43198#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43199#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43999#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44000#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 44279#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44280#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43900#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43451#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43452#L1810-2 [2021-12-19 19:16:57,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2021-12-19 19:16:57,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935065260] [2021-12-19 19:16:57,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,460 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,500 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935065260] [2021-12-19 19:16:57,500 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935065260] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,501 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,501 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,501 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452529739] [2021-12-19 19:16:57,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,502 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,502 INFO L85 PathProgramCache]: Analyzing trace with hash 1696309331, now seen corresponding path program 1 times [2021-12-19 19:16:57,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889971049] [2021-12-19 19:16:57,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,504 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889971049] [2021-12-19 19:16:57,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889971049] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,540 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832117985] [2021-12-19 19:16:57,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,540 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:57,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:57,541 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. cyclomatic complexity: 853 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:57,690 INFO L93 Difference]: Finished difference Result 3320 states and 4886 transitions. [2021-12-19 19:16:57,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:57,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3320 states and 4886 transitions. [2021-12-19 19:16:57,705 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3131 [2021-12-19 19:16:57,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3320 states to 3320 states and 4886 transitions. [2021-12-19 19:16:57,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3320 [2021-12-19 19:16:57,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3320 [2021-12-19 19:16:57,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3320 states and 4886 transitions. [2021-12-19 19:16:57,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:57,732 INFO L681 BuchiCegarLoop]: Abstraction has 3320 states and 4886 transitions. [2021-12-19 19:16:57,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3320 states and 4886 transitions. [2021-12-19 19:16:57,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3320 to 3320. [2021-12-19 19:16:57,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3320 states, 3320 states have (on average 1.4716867469879518) internal successors, (4886), 3319 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:57,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3320 states to 3320 states and 4886 transitions. [2021-12-19 19:16:57,801 INFO L704 BuchiCegarLoop]: Abstraction has 3320 states and 4886 transitions. [2021-12-19 19:16:57,801 INFO L587 BuchiCegarLoop]: Abstraction has 3320 states and 4886 transitions. [2021-12-19 19:16:57,801 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:16:57,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3320 states and 4886 transitions. [2021-12-19 19:16:57,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3131 [2021-12-19 19:16:57,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:57,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:57,813 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,813 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:57,813 INFO L791 eck$LassoCheckResult]: Stem: 48919#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 48920#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48440#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48441#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48495#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 49868#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48928#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48731#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48130#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48131#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49358#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49474#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49943#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49944#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48859#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48860#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49388#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49303#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48894#L1201 assume !(0 == ~M_E~0); 48895#L1201-2 assume !(0 == ~T1_E~0); 49764#L1206-1 assume !(0 == ~T2_E~0); 49750#L1211-1 assume !(0 == ~T3_E~0); 49751#L1216-1 assume !(0 == ~T4_E~0); 48715#L1221-1 assume !(0 == ~T5_E~0); 48716#L1226-1 assume !(0 == ~T6_E~0); 48355#L1231-1 assume !(0 == ~T7_E~0); 48356#L1236-1 assume !(0 == ~T8_E~0); 49789#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48752#L1246-1 assume !(0 == ~T10_E~0); 48753#L1251-1 assume !(0 == ~T11_E~0); 48892#L1256-1 assume !(0 == ~T12_E~0); 48141#L1261-1 assume !(0 == ~E_M~0); 48142#L1266-1 assume !(0 == ~E_1~0); 49926#L1271-1 assume !(0 == ~E_2~0); 49458#L1276-1 assume !(0 == ~E_3~0); 49459#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 49404#L1286-1 assume !(0 == ~E_5~0); 48606#L1291-1 assume !(0 == ~E_6~0); 48607#L1296-1 assume !(0 == ~E_7~0); 49184#L1301-1 assume !(0 == ~E_8~0); 49185#L1306-1 assume !(0 == ~E_9~0); 49684#L1311-1 assume !(0 == ~E_10~0); 48557#L1316-1 assume !(0 == ~E_11~0); 48558#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 49202#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49203#L593 assume 1 == ~m_pc~0; 49350#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48447#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49912#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49415#L1492 assume !(0 != activate_threads_~tmp~1#1); 49416#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49722#L612 assume !(1 == ~t1_pc~0); 49723#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49863#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48829#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48451#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48452#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48871#L631 assume 1 == ~t2_pc~0; 48806#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48228#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48229#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49067#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 49068#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48524#L650 assume !(1 == ~t3_pc~0); 48525#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49227#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48448#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48181#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 48182#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49380#L669 assume 1 == ~t4_pc~0; 49381#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49756#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48858#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48390#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 48391#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48615#L688 assume !(1 == ~t5_pc~0); 48406#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48407#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49328#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49261#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 49262#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49397#L707 assume 1 == ~t6_pc~0; 49828#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49037#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49038#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49826#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 49334#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48893#L726 assume 1 == ~t7_pc~0; 48792#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48491#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49545#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49837#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 48260#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48261#L745 assume !(1 == ~t8_pc~0); 48708#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48727#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49581#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49115#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49116#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49640#L764 assume 1 == ~t9_pc~0; 48891#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48733#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49418#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49895#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 48280#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48281#L783 assume !(1 == ~t10_pc~0); 48342#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48343#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48384#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48385#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 48847#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49758#L802 assume 1 == ~t11_pc~0; 49740#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48225#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48226#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48717#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 48718#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48828#L821 assume !(1 == ~t12_pc~0); 49081#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49177#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48230#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48231#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 49798#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49428#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 49429#L1339-2 assume !(1 == ~T1_E~0); 49908#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50040#L1349-1 assume !(1 == ~T3_E~0); 50039#L1354-1 assume !(1 == ~T4_E~0); 50038#L1359-1 assume !(1 == ~T5_E~0); 50037#L1364-1 assume !(1 == ~T6_E~0); 50036#L1369-1 assume !(1 == ~T7_E~0); 50035#L1374-1 assume !(1 == ~T8_E~0); 50034#L1379-1 assume !(1 == ~T9_E~0); 50033#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50032#L1389-1 assume !(1 == ~T11_E~0); 50031#L1394-1 assume !(1 == ~T12_E~0); 50030#L1399-1 assume !(1 == ~E_M~0); 50029#L1404-1 assume !(1 == ~E_1~0); 50028#L1409-1 assume !(1 == ~E_2~0); 50027#L1414-1 assume !(1 == ~E_3~0); 50026#L1419-1 assume !(1 == ~E_4~0); 50025#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50024#L1429-1 assume !(1 == ~E_6~0); 50023#L1434-1 assume !(1 == ~E_7~0); 50022#L1439-1 assume !(1 == ~E_8~0); 50021#L1444-1 assume !(1 == ~E_9~0); 50020#L1449-1 assume !(1 == ~E_10~0); 50019#L1454-1 assume !(1 == ~E_11~0); 50018#L1459-1 assume !(1 == ~E_12~0); 49333#L1464-1 assume { :end_inline_reset_delta_events } true; 48570#L1810-2 [2021-12-19 19:16:57,814 INFO L793 eck$LassoCheckResult]: Loop: 48570#L1810-2 assume !false; 49015#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49978#L1176 assume !false; 49503#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49504#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49557#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49558#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49818#L1003 assume !(0 != eval_~tmp~0#1); 49820#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49887#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49888#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49444#L1201-5 assume !(0 == ~T1_E~0); 49445#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49331#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48519#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48520#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48986#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48590#L1231-3 assume !(0 == ~T7_E~0); 48591#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48837#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49851#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49743#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49435#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48536#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48537#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48582#L1271-3 assume !(0 == ~E_2~0); 48583#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48959#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48960#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49492#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49493#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49938#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49892#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49073#L1311-3 assume !(0 == ~E_10~0); 48462#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48463#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48538#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49176#L593-42 assume !(1 == ~m_pc~0); 49337#L593-44 is_master_triggered_~__retres1~0#1 := 0; 49338#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49922#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49923#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48361#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48362#L612-42 assume !(1 == ~t1_pc~0); 49285#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 49699#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49827#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48449#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48450#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49147#L631-42 assume 1 == ~t2_pc~0; 48214#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48215#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49136#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49011#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49012#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48611#L650-42 assume 1 == ~t3_pc~0; 48173#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48174#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49858#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48804#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48805#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49814#L669-42 assume !(1 == ~t4_pc~0); 48171#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 48172#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49616#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49501#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 49395#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49396#L688-42 assume 1 == ~t5_pc~0; 49490#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49703#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48312#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48313#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48389#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48203#L707-42 assume !(1 == ~t6_pc~0); 48204#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 49899#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49621#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49622#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49360#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49361#L726-42 assume 1 == ~t7_pc~0; 49649#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49680#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49681#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49076#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49077#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49180#L745-42 assume 1 == ~t8_pc~0; 49217#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49219#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48544#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48189#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48190#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48915#L764-42 assume 1 == ~t9_pc~0; 49053#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49412#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49413#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48475#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48476#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48529#L783-42 assume 1 == ~t10_pc~0; 48145#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48146#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48741#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48874#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49931#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49591#L802-42 assume 1 == ~t11_pc~0; 48676#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48287#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48288#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48238#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48239#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49423#L821-42 assume 1 == ~t12_pc~0; 49424#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48781#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48143#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48144#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49123#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49113#L1339-3 assume !(1 == ~M_E~0); 49114#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49265#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49379#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48790#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48791#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49390#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49920#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49812#L1374-3 assume !(1 == ~T8_E~0); 48612#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48613#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48788#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48789#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48999#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49824#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49787#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49788#L1414-3 assume !(1 == ~E_3~0); 49850#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49593#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48496#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48497#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49389#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48424#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 48425#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48541#L1454-3 assume !(1 == ~E_11~0); 49384#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49385#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49039#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 48334#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48594#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48595#L1829 assume !(0 == start_simulation_~tmp~3#1); 49319#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49653#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49119#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49120#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 49405#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49406#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49940#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48569#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 48570#L1810-2 [2021-12-19 19:16:57,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,815 INFO L85 PathProgramCache]: Analyzing trace with hash 282356976, now seen corresponding path program 1 times [2021-12-19 19:16:57,815 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187378304] [2021-12-19 19:16:57,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,815 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187378304] [2021-12-19 19:16:57,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187378304] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082973802] [2021-12-19 19:16:57,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,871 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:57,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:57,874 INFO L85 PathProgramCache]: Analyzing trace with hash -644024683, now seen corresponding path program 1 times [2021-12-19 19:16:57,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:57,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189002530] [2021-12-19 19:16:57,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:57,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:57,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:57,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:57,911 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:57,911 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189002530] [2021-12-19 19:16:57,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189002530] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:57,911 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:57,911 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:57,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919208981] [2021-12-19 19:16:57,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:57,912 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:57,912 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:57,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:57,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:57,913 INFO L87 Difference]: Start difference. First operand 3320 states and 4886 transitions. cyclomatic complexity: 1568 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,023 INFO L93 Difference]: Finished difference Result 6374 states and 9359 transitions. [2021-12-19 19:16:58,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:58,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6374 states and 9359 transitions. [2021-12-19 19:16:58,048 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6143 [2021-12-19 19:16:58,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6374 states to 6374 states and 9359 transitions. [2021-12-19 19:16:58,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6374 [2021-12-19 19:16:58,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6374 [2021-12-19 19:16:58,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6374 states and 9359 transitions. [2021-12-19 19:16:58,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,081 INFO L681 BuchiCegarLoop]: Abstraction has 6374 states and 9359 transitions. [2021-12-19 19:16:58,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6374 states and 9359 transitions. [2021-12-19 19:16:58,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6374 to 6374. [2021-12-19 19:16:58,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6374 states, 6374 states have (on average 1.4683087543144022) internal successors, (9359), 6373 states have internal predecessors, (9359), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6374 states to 6374 states and 9359 transitions. [2021-12-19 19:16:58,255 INFO L704 BuchiCegarLoop]: Abstraction has 6374 states and 9359 transitions. [2021-12-19 19:16:58,255 INFO L587 BuchiCegarLoop]: Abstraction has 6374 states and 9359 transitions. [2021-12-19 19:16:58,255 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:16:58,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6374 states and 9359 transitions. [2021-12-19 19:16:58,272 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6143 [2021-12-19 19:16:58,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,274 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,275 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,275 INFO L791 eck$LassoCheckResult]: Stem: 58626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 58627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 58145#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58146#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58200#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 59565#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58636#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58437#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57834#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57835#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59070#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59182#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59640#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59641#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58565#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58566#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59099#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59017#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58601#L1201 assume !(0 == ~M_E~0); 58602#L1201-2 assume !(0 == ~T1_E~0); 59467#L1206-1 assume !(0 == ~T2_E~0); 59451#L1211-1 assume !(0 == ~T3_E~0); 59452#L1216-1 assume !(0 == ~T4_E~0); 58421#L1221-1 assume !(0 == ~T5_E~0); 58422#L1226-1 assume !(0 == ~T6_E~0); 58060#L1231-1 assume !(0 == ~T7_E~0); 58061#L1236-1 assume !(0 == ~T8_E~0); 59492#L1241-1 assume !(0 == ~T9_E~0); 58458#L1246-1 assume !(0 == ~T10_E~0); 58459#L1251-1 assume !(0 == ~T11_E~0); 58599#L1256-1 assume !(0 == ~T12_E~0); 57845#L1261-1 assume !(0 == ~E_M~0); 57846#L1266-1 assume !(0 == ~E_1~0); 59622#L1271-1 assume !(0 == ~E_2~0); 59166#L1276-1 assume !(0 == ~E_3~0); 59167#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 59113#L1286-1 assume !(0 == ~E_5~0); 58311#L1291-1 assume !(0 == ~E_6~0); 58312#L1296-1 assume !(0 == ~E_7~0); 58894#L1301-1 assume !(0 == ~E_8~0); 58895#L1306-1 assume !(0 == ~E_9~0); 59386#L1311-1 assume !(0 == ~E_10~0); 58262#L1316-1 assume !(0 == ~E_11~0); 58263#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 58913#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58914#L593 assume 1 == ~m_pc~0; 59062#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 58152#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59607#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59124#L1492 assume !(0 != activate_threads_~tmp~1#1); 59125#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59423#L612 assume !(1 == ~t1_pc~0); 59424#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59559#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58535#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58156#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58157#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58577#L631 assume 1 == ~t2_pc~0; 58512#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57933#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57934#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58773#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 58774#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58229#L650 assume !(1 == ~t3_pc~0); 58230#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58939#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58153#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57885#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 57886#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59091#L669 assume 1 == ~t4_pc~0; 59092#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59458#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58564#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58095#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 58096#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58321#L688 assume !(1 == ~t5_pc~0); 58111#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58112#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59042#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58973#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 58974#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59106#L707 assume 1 == ~t6_pc~0; 59528#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58743#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58744#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59526#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 59048#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58600#L726 assume 1 == ~t7_pc~0; 58498#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58196#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59252#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59536#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 57965#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57966#L745 assume !(1 == ~t8_pc~0); 58414#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58433#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59285#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58823#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58824#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59347#L764 assume 1 == ~t9_pc~0; 58598#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58439#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59127#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59590#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 57985#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57986#L783 assume !(1 == ~t10_pc~0); 58047#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58048#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58089#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58090#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 58553#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59460#L802 assume 1 == ~t11_pc~0; 59441#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57929#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57930#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58423#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 58424#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58534#L821 assume !(1 == ~t12_pc~0); 58788#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58887#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57935#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57936#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 59501#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59136#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 59137#L1339-2 assume !(1 == ~T1_E~0); 59603#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60939#L1349-1 assume !(1 == ~T3_E~0); 60931#L1354-1 assume !(1 == ~T4_E~0); 60925#L1359-1 assume !(1 == ~T5_E~0); 60915#L1364-1 assume !(1 == ~T6_E~0); 60913#L1369-1 assume !(1 == ~T7_E~0); 59298#L1374-1 assume !(1 == ~T8_E~0); 59299#L1379-1 assume !(1 == ~T9_E~0); 60892#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60890#L1389-1 assume !(1 == ~T11_E~0); 60888#L1394-1 assume !(1 == ~T12_E~0); 60886#L1399-1 assume !(1 == ~E_M~0); 60884#L1404-1 assume !(1 == ~E_1~0); 60882#L1409-1 assume !(1 == ~E_2~0); 60112#L1414-1 assume !(1 == ~E_3~0); 60088#L1419-1 assume !(1 == ~E_4~0); 60086#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60057#L1429-1 assume !(1 == ~E_6~0); 60027#L1434-1 assume !(1 == ~E_7~0); 60003#L1439-1 assume !(1 == ~E_8~0); 59974#L1444-1 assume !(1 == ~E_9~0); 59943#L1449-1 assume !(1 == ~E_10~0); 59918#L1454-1 assume !(1 == ~E_11~0); 59809#L1459-1 assume !(1 == ~E_12~0); 59783#L1464-1 assume { :end_inline_reset_delta_events } true; 59692#L1810-2 [2021-12-19 19:16:58,275 INFO L793 eck$LassoCheckResult]: Loop: 59692#L1810-2 assume !false; 59689#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59685#L1176 assume !false; 59684#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59681#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59670#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59669#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59667#L1003 assume !(0 != eval_~tmp~0#1); 59666#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59665#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59663#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59664#L1201-5 assume !(0 == ~T1_E~0); 61633#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61631#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61628#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61626#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61624#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61622#L1231-3 assume !(0 == ~T7_E~0); 61620#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61618#L1241-3 assume !(0 == ~T9_E~0); 61615#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 61613#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61611#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61609#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61607#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61605#L1271-3 assume !(0 == ~E_2~0); 61602#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61600#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61598#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61596#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61594#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61592#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61589#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61587#L1311-3 assume !(0 == ~E_10~0); 61585#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61583#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 61581#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61579#L593-42 assume 1 == ~m_pc~0; 61575#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61573#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61571#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61569#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61567#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61565#L612-42 assume !(1 == ~t1_pc~0); 61540#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 61538#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61536#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61534#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61531#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61529#L631-42 assume 1 == ~t2_pc~0; 61526#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61524#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61522#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61520#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61519#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61516#L650-42 assume !(1 == ~t3_pc~0); 61513#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 61511#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61509#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61507#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61505#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61502#L669-42 assume 1 == ~t4_pc~0; 61498#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61496#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61494#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61492#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 61489#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61487#L688-42 assume 1 == ~t5_pc~0; 61484#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61482#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61480#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61478#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61199#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61196#L707-42 assume 1 == ~t6_pc~0; 61193#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61191#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61189#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61187#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61185#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61182#L726-42 assume 1 == ~t7_pc~0; 61179#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61177#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61060#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61057#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61055#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61053#L745-42 assume !(1 == ~t8_pc~0); 61050#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 61048#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61046#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61045#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61021#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61010#L764-42 assume 1 == ~t9_pc~0; 60998#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60973#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60970#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60968#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60966#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60964#L783-42 assume !(1 == ~t10_pc~0); 60961#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 60940#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60932#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60926#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60921#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60903#L802-42 assume !(1 == ~t11_pc~0); 60672#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 60669#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60667#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60666#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60657#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60656#L821-42 assume !(1 == ~t12_pc~0); 60648#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 60641#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60635#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60107#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60082#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60080#L1339-3 assume !(1 == ~M_E~0); 58822#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58977#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60050#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60022#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60020#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59994#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59967#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 59515#L1374-3 assume !(1 == ~T8_E~0); 59516#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59913#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59911#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59908#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59906#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59904#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59902#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59900#L1414-3 assume !(1 == ~E_3~0); 59898#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59895#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59893#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59891#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59889#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59887#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59885#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59882#L1454-3 assume !(1 == ~E_11~0); 59880#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59878#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59866#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59858#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59856#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 59854#L1829 assume !(0 == start_simulation_~tmp~3#1); 59033#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59839#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59834#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59832#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 59830#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59808#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59806#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59782#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 59692#L1810-2 [2021-12-19 19:16:58,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2021-12-19 19:16:58,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698042832] [2021-12-19 19:16:58,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698042832] [2021-12-19 19:16:58,311 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698042832] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,311 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,311 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,311 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705887193] [2021-12-19 19:16:58,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,312 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,312 INFO L85 PathProgramCache]: Analyzing trace with hash -651784167, now seen corresponding path program 1 times [2021-12-19 19:16:58,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022295745] [2021-12-19 19:16:58,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,313 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022295745] [2021-12-19 19:16:58,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022295745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866728969] [2021-12-19 19:16:58,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,347 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,347 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:58,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:58,348 INFO L87 Difference]: Start difference. First operand 6374 states and 9359 transitions. cyclomatic complexity: 2989 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:58,531 INFO L93 Difference]: Finished difference Result 12074 states and 17698 transitions. [2021-12-19 19:16:58,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:58,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12074 states and 17698 transitions. [2021-12-19 19:16:58,588 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11795 [2021-12-19 19:16:58,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12074 states to 12074 states and 17698 transitions. [2021-12-19 19:16:58,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12074 [2021-12-19 19:16:58,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12074 [2021-12-19 19:16:58,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12074 states and 17698 transitions. [2021-12-19 19:16:58,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:58,654 INFO L681 BuchiCegarLoop]: Abstraction has 12074 states and 17698 transitions. [2021-12-19 19:16:58,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12074 states and 17698 transitions. [2021-12-19 19:16:58,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12074 to 12070. [2021-12-19 19:16:58,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12070 states, 12070 states have (on average 1.4659486329743165) internal successors, (17694), 12069 states have internal predecessors, (17694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12070 states to 12070 states and 17694 transitions. [2021-12-19 19:16:58,957 INFO L704 BuchiCegarLoop]: Abstraction has 12070 states and 17694 transitions. [2021-12-19 19:16:58,957 INFO L587 BuchiCegarLoop]: Abstraction has 12070 states and 17694 transitions. [2021-12-19 19:16:58,958 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:16:58,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12070 states and 17694 transitions. [2021-12-19 19:16:58,997 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11795 [2021-12-19 19:16:58,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,000 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,000 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,001 INFO L791 eck$LassoCheckResult]: Stem: 77084#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 77085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 76602#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76603#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76657#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 78037#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77093#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76896#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76292#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76293#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77526#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77643#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78116#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 78117#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77024#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77025#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77556#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77470#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77059#L1201 assume !(0 == ~M_E~0); 77060#L1201-2 assume !(0 == ~T1_E~0); 77935#L1206-1 assume !(0 == ~T2_E~0); 77921#L1211-1 assume !(0 == ~T3_E~0); 77922#L1216-1 assume !(0 == ~T4_E~0); 76881#L1221-1 assume !(0 == ~T5_E~0); 76882#L1226-1 assume !(0 == ~T6_E~0); 76517#L1231-1 assume !(0 == ~T7_E~0); 76518#L1236-1 assume !(0 == ~T8_E~0); 77963#L1241-1 assume !(0 == ~T9_E~0); 76920#L1246-1 assume !(0 == ~T10_E~0); 76921#L1251-1 assume !(0 == ~T11_E~0); 77057#L1256-1 assume !(0 == ~T12_E~0); 76305#L1261-1 assume !(0 == ~E_M~0); 76306#L1266-1 assume !(0 == ~E_1~0); 78098#L1271-1 assume !(0 == ~E_2~0); 77625#L1276-1 assume !(0 == ~E_3~0); 77626#L1281-1 assume !(0 == ~E_4~0); 77570#L1286-1 assume !(0 == ~E_5~0); 76768#L1291-1 assume !(0 == ~E_6~0); 76769#L1296-1 assume !(0 == ~E_7~0); 77348#L1301-1 assume !(0 == ~E_8~0); 77349#L1306-1 assume !(0 == ~E_9~0); 77852#L1311-1 assume !(0 == ~E_10~0); 76719#L1316-1 assume !(0 == ~E_11~0); 76720#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 77367#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77368#L593 assume 1 == ~m_pc~0; 77518#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76609#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78085#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77581#L1492 assume !(0 != activate_threads_~tmp~1#1); 77582#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77890#L612 assume !(1 == ~t1_pc~0); 77891#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 78031#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76994#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76613#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76614#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77036#L631 assume 1 == ~t2_pc~0; 76971#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76390#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76391#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77230#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 77231#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76686#L650 assume !(1 == ~t3_pc~0); 76687#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77392#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76610#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76343#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 76344#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77548#L669 assume 1 == ~t4_pc~0; 77549#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77927#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77023#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76552#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 76553#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76777#L688 assume !(1 == ~t5_pc~0); 76568#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76569#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77495#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77428#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 77429#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77566#L707 assume 1 == ~t6_pc~0; 77998#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77200#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77201#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77996#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 77504#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77058#L726 assume 1 == ~t7_pc~0; 76959#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76653#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77712#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78006#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 76422#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76423#L745 assume !(1 == ~t8_pc~0); 76872#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76892#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77745#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77278#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77279#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77810#L764 assume 1 == ~t9_pc~0; 77056#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76898#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77584#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78067#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 76442#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76443#L783 assume !(1 == ~t10_pc~0); 76504#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76505#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76546#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76547#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 77017#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77929#L802 assume 1 == ~t11_pc~0; 77909#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76387#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76388#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76883#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 76884#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76993#L821 assume !(1 == ~t12_pc~0); 77244#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77341#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76394#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76395#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 77972#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77594#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 77595#L1339-2 assume !(1 == ~T1_E~0); 78009#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78010#L1349-1 assume !(1 == ~T3_E~0); 77360#L1354-1 assume !(1 == ~T4_E~0); 77361#L1359-1 assume !(1 == ~T5_E~0); 78111#L1364-1 assume !(1 == ~T6_E~0); 78112#L1369-1 assume !(1 == ~T7_E~0); 77760#L1374-1 assume !(1 == ~T8_E~0); 77761#L1379-1 assume !(1 == ~T9_E~0); 78245#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78242#L1389-1 assume !(1 == ~T11_E~0); 78239#L1394-1 assume !(1 == ~T12_E~0); 78236#L1399-1 assume !(1 == ~E_M~0); 78233#L1404-1 assume !(1 == ~E_1~0); 78230#L1409-1 assume !(1 == ~E_2~0); 78226#L1414-1 assume !(1 == ~E_3~0); 78223#L1419-1 assume !(1 == ~E_4~0); 78219#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78217#L1429-1 assume !(1 == ~E_6~0); 78215#L1434-1 assume !(1 == ~E_7~0); 78211#L1439-1 assume !(1 == ~E_8~0); 78209#L1444-1 assume !(1 == ~E_9~0); 78207#L1449-1 assume !(1 == ~E_10~0); 78205#L1454-1 assume !(1 == ~E_11~0); 78192#L1459-1 assume !(1 == ~E_12~0); 78182#L1464-1 assume { :end_inline_reset_delta_events } true; 78175#L1810-2 [2021-12-19 19:16:59,001 INFO L793 eck$LassoCheckResult]: Loop: 78175#L1810-2 assume !false; 78172#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78168#L1176 assume !false; 78167#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78164#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78153#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78152#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 78150#L1003 assume !(0 != eval_~tmp~0#1); 78149#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78148#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78146#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78147#L1201-5 assume !(0 == ~T1_E~0); 80624#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80623#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80619#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80617#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80589#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80564#L1231-3 assume !(0 == ~T7_E~0); 80459#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 80445#L1241-3 assume !(0 == ~T9_E~0); 80443#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 80441#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 80438#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 80436#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 80414#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80406#L1271-3 assume !(0 == ~E_2~0); 80397#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80388#L1281-3 assume !(0 == ~E_4~0); 80380#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80372#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80363#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80355#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 80347#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 80339#L1311-3 assume !(0 == ~E_10~0); 80331#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 80323#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 80314#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80306#L593-42 assume 1 == ~m_pc~0; 80297#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 80289#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80281#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80273#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80264#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80256#L612-42 assume !(1 == ~t1_pc~0); 80247#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 80239#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80231#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80223#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80213#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80205#L631-42 assume !(1 == ~t2_pc~0); 80197#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 80188#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80179#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80171#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80162#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80161#L650-42 assume 1 == ~t3_pc~0; 80151#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 80142#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80133#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80123#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80114#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80101#L669-42 assume !(1 == ~t4_pc~0); 80091#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 80081#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80065#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80059#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 80052#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80046#L688-42 assume !(1 == ~t5_pc~0); 80015#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 80013#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80011#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80008#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80006#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80004#L707-42 assume 1 == ~t6_pc~0; 80001#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79976#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79973#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 79971#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79969#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79967#L726-42 assume !(1 == ~t7_pc~0); 79965#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 79923#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79872#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79870#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79868#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79866#L745-42 assume !(1 == ~t8_pc~0); 79863#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 79861#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79858#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79856#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79854#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 79852#L764-42 assume !(1 == ~t9_pc~0); 79803#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 79800#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79798#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79795#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 79770#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79716#L783-42 assume !(1 == ~t10_pc~0); 79713#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 79711#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79709#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 79701#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 79700#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79699#L802-42 assume !(1 == ~t11_pc~0); 76839#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 76449#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76450#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76400#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76401#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77589#L821-42 assume !(1 == ~t12_pc~0); 77591#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 79501#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76303#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76304#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77286#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77276#L1339-3 assume !(1 == ~M_E~0); 77277#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77431#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79397#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79392#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79387#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79381#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79376#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79371#L1374-3 assume !(1 == ~T8_E~0); 79366#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 79360#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 79357#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 79353#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 79350#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 79347#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 79344#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 79341#L1414-3 assume !(1 == ~E_3~0); 79338#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79333#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79331#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 79329#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 79327#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 79325#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 79323#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 79320#L1454-3 assume !(1 == ~E_11~0); 79318#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 79316#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 79308#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 79300#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 79298#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 79295#L1829 assume !(0 == start_simulation_~tmp~3#1); 77486#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 79284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 79279#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78208#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 78206#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78204#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78191#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 78181#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 78175#L1810-2 [2021-12-19 19:16:59,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,002 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2021-12-19 19:16:59,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877131222] [2021-12-19 19:16:59,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,039 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,039 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877131222] [2021-12-19 19:16:59,040 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877131222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,040 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,040 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005823702] [2021-12-19 19:16:59,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,041 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1661709727, now seen corresponding path program 1 times [2021-12-19 19:16:59,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757595493] [2021-12-19 19:16:59,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,042 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757595493] [2021-12-19 19:16:59,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757595493] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311426447] [2021-12-19 19:16:59,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,149 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,149 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:16:59,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:16:59,149 INFO L87 Difference]: Start difference. First operand 12070 states and 17694 transitions. cyclomatic complexity: 5632 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,362 INFO L93 Difference]: Finished difference Result 23026 states and 33693 transitions. [2021-12-19 19:16:59,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:16:59,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23026 states and 33693 transitions. [2021-12-19 19:16:59,535 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22727 [2021-12-19 19:16:59,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23026 states to 23026 states and 33693 transitions. [2021-12-19 19:16:59,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23026 [2021-12-19 19:16:59,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23026 [2021-12-19 19:16:59,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23026 states and 33693 transitions. [2021-12-19 19:16:59,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,667 INFO L681 BuchiCegarLoop]: Abstraction has 23026 states and 33693 transitions. [2021-12-19 19:16:59,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23026 states and 33693 transitions. [2021-12-19 19:16:59,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23026 to 23018. [2021-12-19 19:16:59,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23018 states, 23018 states have (on average 1.4634199322269528) internal successors, (33685), 23017 states have internal predecessors, (33685), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23018 states to 23018 states and 33685 transitions. [2021-12-19 19:17:00,230 INFO L704 BuchiCegarLoop]: Abstraction has 23018 states and 33685 transitions. [2021-12-19 19:17:00,230 INFO L587 BuchiCegarLoop]: Abstraction has 23018 states and 33685 transitions. [2021-12-19 19:17:00,230 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:00,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23018 states and 33685 transitions. [2021-12-19 19:17:00,294 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22727 [2021-12-19 19:17:00,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,296 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,297 INFO L791 eck$LassoCheckResult]: Stem: 112189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 112190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 111708#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111709#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111763#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 113161#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112198#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112000#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111398#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111399#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112636#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112758#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 113239#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 113240#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112129#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 112130#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 112666#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112583#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112164#L1201 assume !(0 == ~M_E~0); 112165#L1201-2 assume !(0 == ~T1_E~0); 113052#L1206-1 assume !(0 == ~T2_E~0); 113035#L1211-1 assume !(0 == ~T3_E~0); 113036#L1216-1 assume !(0 == ~T4_E~0); 111985#L1221-1 assume !(0 == ~T5_E~0); 111986#L1226-1 assume !(0 == ~T6_E~0); 111623#L1231-1 assume !(0 == ~T7_E~0); 111624#L1236-1 assume !(0 == ~T8_E~0); 113077#L1241-1 assume !(0 == ~T9_E~0); 112025#L1246-1 assume !(0 == ~T10_E~0); 112026#L1251-1 assume !(0 == ~T11_E~0); 112162#L1256-1 assume !(0 == ~T12_E~0); 111411#L1261-1 assume !(0 == ~E_M~0); 111412#L1266-1 assume !(0 == ~E_1~0); 113219#L1271-1 assume !(0 == ~E_2~0); 112739#L1276-1 assume !(0 == ~E_3~0); 112740#L1281-1 assume !(0 == ~E_4~0); 112680#L1286-1 assume !(0 == ~E_5~0); 111874#L1291-1 assume !(0 == ~E_6~0); 111875#L1296-1 assume !(0 == ~E_7~0); 112457#L1301-1 assume !(0 == ~E_8~0); 112458#L1306-1 assume !(0 == ~E_9~0); 112966#L1311-1 assume !(0 == ~E_10~0); 111825#L1316-1 assume !(0 == ~E_11~0); 111826#L1321-1 assume !(0 == ~E_12~0); 112478#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112479#L593 assume 1 == ~m_pc~0; 112628#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 111715#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113204#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112691#L1492 assume !(0 != activate_threads_~tmp~1#1); 112692#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113005#L612 assume !(1 == ~t1_pc~0); 113006#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113156#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112099#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111719#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 111720#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112141#L631 assume 1 == ~t2_pc~0; 112076#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 111496#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111497#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112337#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 112338#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111792#L650 assume !(1 == ~t3_pc~0); 111793#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112503#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111716#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111449#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 111450#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112657#L669 assume 1 == ~t4_pc~0; 112658#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113041#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112128#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111658#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 111659#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111884#L688 assume !(1 == ~t5_pc~0); 111674#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111675#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112608#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112538#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 112539#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112676#L707 assume 1 == ~t6_pc~0; 113116#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112307#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112308#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113114#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 112614#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112163#L726 assume 1 == ~t7_pc~0; 112064#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111759#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112828#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113126#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 111528#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111529#L745 assume !(1 == ~t8_pc~0); 111977#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 111996#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112864#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112387#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112388#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112927#L764 assume 1 == ~t9_pc~0; 112161#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112002#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112694#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 113185#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 111548#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111549#L783 assume !(1 == ~t10_pc~0); 111610#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 111611#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111652#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111653#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 112122#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113044#L802 assume 1 == ~t11_pc~0; 113023#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111493#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 111494#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111987#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 111988#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112098#L821 assume !(1 == ~t12_pc~0); 112352#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112450#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111500#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 111501#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 113088#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112703#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 112704#L1339-2 assume !(1 == ~T1_E~0); 113199#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 113542#L1349-1 assume !(1 == ~T3_E~0); 112471#L1354-1 assume !(1 == ~T4_E~0); 112472#L1359-1 assume !(1 == ~T5_E~0); 112895#L1364-1 assume !(1 == ~T6_E~0); 111927#L1369-1 assume !(1 == ~T7_E~0); 111928#L1374-1 assume !(1 == ~T8_E~0); 112877#L1379-1 assume !(1 == ~T9_E~0); 113488#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113486#L1389-1 assume !(1 == ~T11_E~0); 113484#L1394-1 assume !(1 == ~T12_E~0); 113481#L1399-1 assume !(1 == ~E_M~0); 113479#L1404-1 assume !(1 == ~E_1~0); 113477#L1409-1 assume !(1 == ~E_2~0); 113475#L1414-1 assume !(1 == ~E_3~0); 113473#L1419-1 assume !(1 == ~E_4~0); 113471#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 113468#L1429-1 assume !(1 == ~E_6~0); 113401#L1434-1 assume !(1 == ~E_7~0); 113399#L1439-1 assume !(1 == ~E_8~0); 113368#L1444-1 assume !(1 == ~E_9~0); 113347#L1449-1 assume !(1 == ~E_10~0); 113331#L1454-1 assume !(1 == ~E_11~0); 113321#L1459-1 assume !(1 == ~E_12~0); 113309#L1464-1 assume { :end_inline_reset_delta_events } true; 113302#L1810-2 [2021-12-19 19:17:00,297 INFO L793 eck$LassoCheckResult]: Loop: 113302#L1810-2 assume !false; 113299#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113295#L1176 assume !false; 113294#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113291#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113280#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113279#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 113277#L1003 assume !(0 != eval_~tmp~0#1); 113276#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113275#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113273#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113274#L1201-5 assume !(0 == ~T1_E~0); 118763#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 118761#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118759#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118757#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 118756#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117299#L1231-3 assume !(0 == ~T7_E~0); 117297#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117295#L1241-3 assume !(0 == ~T9_E~0); 117292#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117290#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117289#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117288#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117287#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117286#L1271-3 assume !(0 == ~E_2~0); 117285#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116534#L1281-3 assume !(0 == ~E_4~0); 116531#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116529#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 116527#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116525#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 116523#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 116521#L1311-3 assume !(0 == ~E_10~0); 116517#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 116071#L1321-3 assume !(0 == ~E_12~0); 116069#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116067#L593-42 assume 1 == ~m_pc~0; 115625#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 115622#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115620#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115618#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 115616#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115614#L612-42 assume !(1 == ~t1_pc~0); 115611#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 115608#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115606#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115604#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115220#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115217#L631-42 assume !(1 == ~t2_pc~0); 115216#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 114957#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114954#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114952#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114950#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114948#L650-42 assume !(1 == ~t3_pc~0); 114945#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 114943#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114940#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114938#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114936#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114934#L669-42 assume !(1 == ~t4_pc~0); 114929#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 114926#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114924#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114922#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 114920#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114918#L688-42 assume !(1 == ~t5_pc~0); 114915#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 114912#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114910#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114908#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 114906#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114904#L707-42 assume 1 == ~t6_pc~0; 114651#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 114649#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114647#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114644#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 114642#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 114640#L726-42 assume 1 == ~t7_pc~0; 114637#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114483#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114480#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 114478#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 114476#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114474#L745-42 assume 1 == ~t8_pc~0; 114471#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 114467#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114465#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 114463#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114461#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114459#L764-42 assume !(1 == ~t9_pc~0); 114337#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 114334#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114332#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114330#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 114327#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 114325#L783-42 assume 1 == ~t10_pc~0; 114323#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 114320#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 114318#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 114316#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 114313#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114312#L802-42 assume !(1 == ~t11_pc~0); 114161#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 114158#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 114156#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 114043#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 114040#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 114038#L821-42 assume !(1 == ~t12_pc~0); 114035#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 114033#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 114031#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 114029#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 114028#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114026#L1339-3 assume !(1 == ~M_E~0); 112386#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114020#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114018#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114014#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114012#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 114010#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 114008#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 114006#L1374-3 assume !(1 == ~T8_E~0); 114004#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 113945#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113943#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 113899#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 113844#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 113798#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 113764#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113762#L1414-3 assume !(1 == ~E_3~0); 113760#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113758#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113756#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 113754#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 113724#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 113722#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 113720#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 113694#L1454-3 assume !(1 == ~E_11~0); 113652#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 113648#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113608#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113569#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113538#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 113508#L1829 assume !(0 == start_simulation_~tmp~3#1); 112599#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113388#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113383#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113365#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 113345#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 113329#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 113318#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 113308#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 113302#L1810-2 [2021-12-19 19:17:00,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,298 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2021-12-19 19:17:00,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356542092] [2021-12-19 19:17:00,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,299 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356542092] [2021-12-19 19:17:00,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356542092] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,330 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,330 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:00,330 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983266647] [2021-12-19 19:17:00,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,331 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1044942367, now seen corresponding path program 1 times [2021-12-19 19:17:00,331 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,331 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747825014] [2021-12-19 19:17:00,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,363 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747825014] [2021-12-19 19:17:00,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747825014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,364 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310614217] [2021-12-19 19:17:00,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,364 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,365 INFO L87 Difference]: Start difference. First operand 23018 states and 33685 transitions. cyclomatic complexity: 10683 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,718 INFO L93 Difference]: Finished difference Result 45455 states and 66120 transitions. [2021-12-19 19:17:00,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45455 states and 66120 transitions. [2021-12-19 19:17:00,939 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45133 [2021-12-19 19:17:01,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45455 states to 45455 states and 66120 transitions. [2021-12-19 19:17:01,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45455 [2021-12-19 19:17:01,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45455 [2021-12-19 19:17:01,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45455 states and 66120 transitions. [2021-12-19 19:17:01,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,186 INFO L681 BuchiCegarLoop]: Abstraction has 45455 states and 66120 transitions. [2021-12-19 19:17:01,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45455 states and 66120 transitions. [2021-12-19 19:17:01,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45455 to 44015. [2021-12-19 19:17:01,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44015 states, 44015 states have (on average 1.456049074179257) internal successors, (64088), 44014 states have internal predecessors, (64088), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44015 states to 44015 states and 64088 transitions. [2021-12-19 19:17:01,954 INFO L704 BuchiCegarLoop]: Abstraction has 44015 states and 64088 transitions. [2021-12-19 19:17:01,954 INFO L587 BuchiCegarLoop]: Abstraction has 44015 states and 64088 transitions. [2021-12-19 19:17:01,954 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:01,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44015 states and 64088 transitions. [2021-12-19 19:17:02,110 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43693 [2021-12-19 19:17:02,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,113 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,114 INFO L791 eck$LassoCheckResult]: Stem: 180687#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 180688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 180187#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180188#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180242#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 181854#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180696#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180489#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 179878#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 179879#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 181204#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 181331#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 181999#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 182000#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 180623#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 180624#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 181237#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 181134#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180659#L1201 assume !(0 == ~M_E~0); 180660#L1201-2 assume !(0 == ~T1_E~0); 181684#L1206-1 assume !(0 == ~T2_E~0); 181664#L1211-1 assume !(0 == ~T3_E~0); 181665#L1216-1 assume !(0 == ~T4_E~0); 180471#L1221-1 assume !(0 == ~T5_E~0); 180472#L1226-1 assume !(0 == ~T6_E~0); 180102#L1231-1 assume !(0 == ~T7_E~0); 180103#L1236-1 assume !(0 == ~T8_E~0); 181726#L1241-1 assume !(0 == ~T9_E~0); 180512#L1246-1 assume !(0 == ~T10_E~0); 180513#L1251-1 assume !(0 == ~T11_E~0); 180657#L1256-1 assume !(0 == ~T12_E~0); 179888#L1261-1 assume !(0 == ~E_M~0); 179889#L1266-1 assume !(0 == ~E_1~0); 181967#L1271-1 assume !(0 == ~E_2~0); 181310#L1276-1 assume !(0 == ~E_3~0); 181311#L1281-1 assume !(0 == ~E_4~0); 181252#L1286-1 assume !(0 == ~E_5~0); 180357#L1291-1 assume !(0 == ~E_6~0); 180358#L1296-1 assume !(0 == ~E_7~0); 180984#L1301-1 assume !(0 == ~E_8~0); 180985#L1306-1 assume !(0 == ~E_9~0); 181575#L1311-1 assume !(0 == ~E_10~0); 180305#L1316-1 assume !(0 == ~E_11~0); 180306#L1321-1 assume !(0 == ~E_12~0); 181006#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181007#L593 assume !(1 == ~m_pc~0); 180193#L593-2 is_master_triggered_~__retres1~0#1 := 0; 180194#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181942#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 181263#L1492 assume !(0 != activate_threads_~tmp~1#1); 181264#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181628#L612 assume !(1 == ~t1_pc~0); 181629#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 181846#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180590#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180198#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 180199#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180636#L631 assume 1 == ~t2_pc~0; 180566#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 179975#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179976#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180845#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 180846#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180271#L650 assume !(1 == ~t3_pc~0); 180272#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 181032#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180195#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 179928#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 179929#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 181229#L669 assume 1 == ~t4_pc~0; 181230#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181671#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180622#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 180137#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 180138#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180366#L688 assume !(1 == ~t5_pc~0); 180153#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 180154#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181166#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 181077#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 181078#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 181244#L707 assume 1 == ~t6_pc~0; 181782#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 180812#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180813#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 181779#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 181173#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 180658#L726 assume 1 == ~t7_pc~0; 180552#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180238#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 181413#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 181794#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 180008#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180009#L745 assume !(1 == ~t8_pc~0); 180464#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 180484#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 181451#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 180900#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180901#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 181527#L764 assume 1 == ~t9_pc~0; 180656#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 180491#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 181266#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 181907#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 180028#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 180029#L783 assume !(1 == ~t10_pc~0); 180090#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 180091#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 180131#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 180132#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 180611#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 181674#L802 assume 1 == ~t11_pc~0; 181652#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 179972#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 179973#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 180473#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 180474#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 180589#L821 assume !(1 == ~t12_pc~0); 180861#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 180975#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 179977#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 179978#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 181739#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181275#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 181276#L1339-2 assume !(1 == ~T1_E~0); 181800#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 181801#L1349-1 assume !(1 == ~T3_E~0); 180998#L1354-1 assume !(1 == ~T4_E~0); 180999#L1359-1 assume !(1 == ~T5_E~0); 181490#L1364-1 assume !(1 == ~T6_E~0); 180412#L1369-1 assume !(1 == ~T7_E~0); 180413#L1374-1 assume !(1 == ~T8_E~0); 181467#L1379-1 assume !(1 == ~T9_E~0); 193470#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 193465#L1389-1 assume !(1 == ~T11_E~0); 193460#L1394-1 assume !(1 == ~T12_E~0); 193454#L1399-1 assume !(1 == ~E_M~0); 193449#L1404-1 assume !(1 == ~E_1~0); 193442#L1409-1 assume !(1 == ~E_2~0); 193438#L1414-1 assume !(1 == ~E_3~0); 193433#L1419-1 assume !(1 == ~E_4~0); 193428#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 183453#L1429-1 assume !(1 == ~E_6~0); 183451#L1434-1 assume !(1 == ~E_7~0); 183410#L1439-1 assume !(1 == ~E_8~0); 183406#L1444-1 assume !(1 == ~E_9~0); 183377#L1449-1 assume !(1 == ~E_10~0); 183375#L1454-1 assume !(1 == ~E_11~0); 183353#L1459-1 assume !(1 == ~E_12~0); 183332#L1464-1 assume { :end_inline_reset_delta_events } true; 183319#L1810-2 [2021-12-19 19:17:02,114 INFO L793 eck$LassoCheckResult]: Loop: 183319#L1810-2 assume !false; 183311#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183306#L1176 assume !false; 183304#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 183288#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 183276#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 183274#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 183270#L1003 assume !(0 != eval_~tmp~0#1); 183269#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 183268#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 183266#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 183267#L1201-5 assume !(0 == ~T1_E~0); 203717#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 203715#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 203713#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 203711#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 203709#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 203707#L1231-3 assume !(0 == ~T7_E~0); 203704#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 203702#L1241-3 assume !(0 == ~T9_E~0); 203700#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 203698#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 203696#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 203694#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 203691#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 203689#L1271-3 assume !(0 == ~E_2~0); 203687#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 203685#L1281-3 assume !(0 == ~E_4~0); 203683#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 203681#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 203680#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 203677#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 203675#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 203673#L1311-3 assume !(0 == ~E_10~0); 203671#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 203669#L1321-3 assume !(0 == ~E_12~0); 203667#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 203664#L593-42 assume !(1 == ~m_pc~0); 203662#L593-44 is_master_triggered_~__retres1~0#1 := 0; 203660#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 203658#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 203656#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 203654#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203651#L612-42 assume 1 == ~t1_pc~0; 203649#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 203646#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203644#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 203642#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 203640#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203637#L631-42 assume !(1 == ~t2_pc~0); 203634#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 203631#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203629#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 203627#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203624#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203622#L650-42 assume !(1 == ~t3_pc~0); 203619#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 203617#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 203615#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203613#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 203612#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 203609#L669-42 assume !(1 == ~t4_pc~0); 203607#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 203604#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 203602#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 203600#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 203598#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 203596#L688-42 assume !(1 == ~t5_pc~0); 203593#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 203590#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 203588#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 203586#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 203584#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 203583#L707-42 assume !(1 == ~t6_pc~0); 203579#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 203576#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 203574#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 203573#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 203568#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203563#L726-42 assume !(1 == ~t7_pc~0); 203558#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 203556#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 203555#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 203554#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 202450#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 202447#L745-42 assume 1 == ~t8_pc~0; 202445#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 202442#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 202440#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 202438#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 202436#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 202433#L764-42 assume !(1 == ~t9_pc~0); 202431#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 202428#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 202426#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 202424#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 202422#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 202419#L783-42 assume 1 == ~t10_pc~0; 202416#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 202413#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 202411#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 202409#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 202091#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 202088#L802-42 assume !(1 == ~t11_pc~0); 202086#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 202083#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 202081#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202079#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 202077#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 202074#L821-42 assume !(1 == ~t12_pc~0); 202071#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 202069#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 202067#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 202065#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 202063#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 202060#L1339-3 assume !(1 == ~M_E~0); 180899#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 201694#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 201692#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201689#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 201687#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 201685#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 201683#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 201490#L1374-3 assume !(1 == ~T8_E~0); 201488#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 201484#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 201482#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 201478#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 201231#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 201229#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 201226#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 201100#L1414-3 assume !(1 == ~E_3~0); 201096#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 201092#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201090#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 201085#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 201084#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 201083#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 201081#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 200875#L1454-3 assume !(1 == ~E_11~0); 193539#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 193532#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 183994#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 183961#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 183959#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 183957#L1829 assume !(0 == start_simulation_~tmp~3#1); 181153#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 183438#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 183433#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 183404#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 183400#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 183372#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183349#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 183331#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 183319#L1810-2 [2021-12-19 19:17:02,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,115 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2021-12-19 19:17:02,115 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347196519] [2021-12-19 19:17:02,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,116 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347196519] [2021-12-19 19:17:02,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347196519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,156 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:02,156 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249795704] [2021-12-19 19:17:02,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,156 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1338468513, now seen corresponding path program 1 times [2021-12-19 19:17:02,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514282610] [2021-12-19 19:17:02,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514282610] [2021-12-19 19:17:02,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514282610] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,192 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,192 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522214720] [2021-12-19 19:17:02,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,193 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,193 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:02,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:02,194 INFO L87 Difference]: Start difference. First operand 44015 states and 64088 transitions. cyclomatic complexity: 20105 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:03,119 INFO L93 Difference]: Finished difference Result 125679 states and 182612 transitions. [2021-12-19 19:17:03,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:03,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125679 states and 182612 transitions. [2021-12-19 19:17:03,902 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 124824 [2021-12-19 19:17:04,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125679 states to 125679 states and 182612 transitions. [2021-12-19 19:17:04,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125679 [2021-12-19 19:17:04,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125679 [2021-12-19 19:17:04,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125679 states and 182612 transitions. [2021-12-19 19:17:04,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:04,582 INFO L681 BuchiCegarLoop]: Abstraction has 125679 states and 182612 transitions. [2021-12-19 19:17:04,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125679 states and 182612 transitions. [2021-12-19 19:17:05,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125679 to 45224. [2021-12-19 19:17:05,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45224 states, 45224 states have (on average 1.44385724394127) internal successors, (65297), 45223 states have internal predecessors, (65297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:05,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45224 states to 45224 states and 65297 transitions. [2021-12-19 19:17:05,568 INFO L704 BuchiCegarLoop]: Abstraction has 45224 states and 65297 transitions. [2021-12-19 19:17:05,568 INFO L587 BuchiCegarLoop]: Abstraction has 45224 states and 65297 transitions. [2021-12-19 19:17:05,569 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:05,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45224 states and 65297 transitions. [2021-12-19 19:17:05,698 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44899 [2021-12-19 19:17:05,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:05,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:05,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:05,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:05,701 INFO L791 eck$LassoCheckResult]: Stem: 350393#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 350394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 349894#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 349895#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 349949#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 351531#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 350402#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350196#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349585#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349586#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 350893#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351027#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351667#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 351668#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350331#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 350332#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 350924#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 350826#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350367#L1201 assume !(0 == ~M_E~0); 350368#L1201-2 assume !(0 == ~T1_E~0); 351385#L1206-1 assume !(0 == ~T2_E~0); 351361#L1211-1 assume !(0 == ~T3_E~0); 351362#L1216-1 assume !(0 == ~T4_E~0); 350180#L1221-1 assume !(0 == ~T5_E~0); 350181#L1226-1 assume !(0 == ~T6_E~0); 349809#L1231-1 assume !(0 == ~T7_E~0); 349810#L1236-1 assume !(0 == ~T8_E~0); 351415#L1241-1 assume !(0 == ~T9_E~0); 350222#L1246-1 assume !(0 == ~T10_E~0); 350223#L1251-1 assume !(0 == ~T11_E~0); 350365#L1256-1 assume !(0 == ~T12_E~0); 349597#L1261-1 assume !(0 == ~E_M~0); 349598#L1266-1 assume !(0 == ~E_1~0); 351636#L1271-1 assume !(0 == ~E_2~0); 351003#L1276-1 assume !(0 == ~E_3~0); 351004#L1281-1 assume !(0 == ~E_4~0); 350938#L1286-1 assume !(0 == ~E_5~0); 350065#L1291-1 assume !(0 == ~E_6~0); 350066#L1296-1 assume !(0 == ~E_7~0); 350677#L1301-1 assume !(0 == ~E_8~0); 350678#L1306-1 assume !(0 == ~E_9~0); 351271#L1311-1 assume !(0 == ~E_10~0); 350014#L1316-1 assume !(0 == ~E_11~0); 350015#L1321-1 assume !(0 == ~E_12~0); 350696#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350697#L593 assume !(1 == ~m_pc~0); 349900#L593-2 is_master_triggered_~__retres1~0#1 := 0; 349901#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351608#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350953#L1492 assume !(0 != activate_threads_~tmp~1#1); 350954#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 351322#L612 assume !(1 == ~t1_pc~0); 351323#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 351652#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351653#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 349905#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 349906#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350343#L631 assume 1 == ~t2_pc~0; 350273#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 349682#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349683#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350544#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 350545#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349979#L650 assume !(1 == ~t3_pc~0); 349980#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350722#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349902#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 349635#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 349636#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350916#L669 assume 1 == ~t4_pc~0; 350917#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 351371#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350330#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 349844#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 349845#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350075#L688 assume !(1 == ~t5_pc~0); 349860#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 349861#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350857#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350767#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 350768#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350934#L707 assume 1 == ~t6_pc~0; 351468#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 350512#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350513#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 351466#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 350868#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 350366#L726 assume 1 == ~t7_pc~0; 350261#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 349945#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 351100#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 351479#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 349715#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 349716#L745 assume !(1 == ~t8_pc~0); 350171#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 350191#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 351137#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350596#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 350597#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 351219#L764 assume 1 == ~t9_pc~0; 350364#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 350198#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350956#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 351577#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 349735#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 349736#L783 assume !(1 == ~t10_pc~0); 349797#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 349798#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 349838#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 349839#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 350324#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 351374#L802 assume 1 == ~t11_pc~0; 351348#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 349679#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 349680#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350182#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 350183#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 350296#L821 assume !(1 == ~t12_pc~0); 350558#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 350669#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 349686#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 349687#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 351433#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350965#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 350966#L1339-2 assume !(1 == ~T1_E~0); 351599#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 367319#L1349-1 assume !(1 == ~T3_E~0); 367317#L1354-1 assume !(1 == ~T4_E~0); 367315#L1359-1 assume !(1 == ~T5_E~0); 367314#L1364-1 assume !(1 == ~T6_E~0); 350120#L1369-1 assume !(1 == ~T7_E~0); 350121#L1374-1 assume !(1 == ~T8_E~0); 350694#L1379-1 assume !(1 == ~T9_E~0); 350695#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 350820#L1389-1 assume !(1 == ~T11_E~0); 351420#L1394-1 assume !(1 == ~T12_E~0); 351421#L1399-1 assume !(1 == ~E_M~0); 351578#L1404-1 assume !(1 == ~E_1~0); 350224#L1409-1 assume !(1 == ~E_2~0); 350225#L1414-1 assume !(1 == ~E_3~0); 351045#L1419-1 assume !(1 == ~E_4~0); 349852#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 349853#L1429-1 assume !(1 == ~E_6~0); 350705#L1434-1 assume !(1 == ~E_7~0); 351450#L1439-1 assume !(1 == ~E_8~0); 349890#L1444-1 assume !(1 == ~E_9~0); 349891#L1449-1 assume !(1 == ~E_10~0); 350278#L1454-1 assume !(1 == ~E_11~0); 350279#L1459-1 assume !(1 == ~E_12~0); 350862#L1464-1 assume { :end_inline_reset_delta_events } true; 350863#L1810-2 [2021-12-19 19:17:05,701 INFO L793 eck$LassoCheckResult]: Loop: 350863#L1810-2 assume !false; 352628#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 352626#L1176 assume !false; 352625#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 351890#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 351876#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 351874#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 351871#L1003 assume !(0 != eval_~tmp~0#1); 351872#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 394715#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 394712#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 350988#L1201-5 assume !(0 == ~T1_E~0); 350989#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 350860#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 349974#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 349975#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 350460#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 350049#L1231-3 assume !(0 == ~T7_E~0); 350050#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 350308#L1241-3 assume !(0 == ~T9_E~0); 351505#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 351506#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 394323#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 394322#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 394321#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 394320#L1271-3 assume !(0 == ~E_2~0); 394319#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 394318#L1281-3 assume !(0 == ~E_4~0); 394317#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 394316#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 394315#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 352966#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 352965#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 352964#L1311-3 assume !(0 == ~E_10~0); 352963#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 352962#L1321-3 assume !(0 == ~E_12~0); 350667#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350668#L593-42 assume !(1 == ~m_pc~0); 350866#L593-44 is_master_triggered_~__retres1~0#1 := 0; 350867#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351629#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 351630#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349818#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 349819#L612-42 assume 1 == ~t1_pc~0; 351753#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 351754#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 394185#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 394101#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 394100#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 394099#L631-42 assume !(1 == ~t2_pc~0); 394098#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 394096#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 394095#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 394094#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 394091#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 394089#L650-42 assume !(1 == ~t3_pc~0); 394086#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 394083#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 394081#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 394079#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 394077#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 394075#L669-42 assume 1 == ~t4_pc~0; 394072#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 394069#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 394067#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 394065#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 394063#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 394061#L688-42 assume 1 == ~t5_pc~0; 394058#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 394055#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 394053#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 394052#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 394051#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 394050#L707-42 assume 1 == ~t6_pc~0; 394048#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 394047#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 394046#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 394045#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 394044#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 394043#L726-42 assume !(1 == ~t7_pc~0); 394042#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 394040#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 394039#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 394038#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 394037#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 394036#L745-42 assume !(1 == ~t8_pc~0); 394034#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 394033#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 394032#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 394031#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 394029#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 394027#L764-42 assume 1 == ~t9_pc~0; 394023#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 394021#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 394019#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 394017#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 394015#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 394013#L783-42 assume 1 == ~t10_pc~0; 394010#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 394007#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 394005#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 394003#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 394001#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 393999#L802-42 assume !(1 == ~t11_pc~0); 393996#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 393993#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 393991#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 393989#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 393987#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 393985#L821-42 assume 1 == ~t12_pc~0; 393982#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 393979#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 393977#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 393975#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 393973#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 393971#L1339-3 assume !(1 == ~M_E~0); 352852#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 352765#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 393966#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 393964#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 393962#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 393960#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 393957#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 393955#L1374-3 assume !(1 == ~T8_E~0); 393953#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 374516#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 393950#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 393948#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 393947#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 393944#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 393942#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 393938#L1414-3 assume !(1 == ~E_3~0); 393937#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 367656#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 393936#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 393935#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 393934#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 393933#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 393932#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 393931#L1454-3 assume !(1 == ~E_11~0); 393930#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 389033#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352728#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352721#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352720#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 351600#L1829 assume !(0 == start_simulation_~tmp~3#1); 351601#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352648#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352643#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352641#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 352640#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352638#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 352636#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 352632#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 350863#L1810-2 [2021-12-19 19:17:05,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:05,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2021-12-19 19:17:05,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:05,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681461378] [2021-12-19 19:17:05,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:05,703 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:05,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:05,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:05,733 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:05,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681461378] [2021-12-19 19:17:05,733 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681461378] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:05,734 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:05,734 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:05,734 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709485001] [2021-12-19 19:17:05,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:05,735 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:05,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:05,737 INFO L85 PathProgramCache]: Analyzing trace with hash 1680707741, now seen corresponding path program 1 times [2021-12-19 19:17:05,737 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:05,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816698488] [2021-12-19 19:17:05,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:05,737 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:05,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:05,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:05,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:05,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816698488] [2021-12-19 19:17:05,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816698488] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:05,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:05,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:05,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885024636] [2021-12-19 19:17:05,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:05,769 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:05,769 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:05,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:05,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:05,770 INFO L87 Difference]: Start difference. First operand 45224 states and 65297 transitions. cyclomatic complexity: 20105 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:06,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:06,499 INFO L93 Difference]: Finished difference Result 126189 states and 180823 transitions. [2021-12-19 19:17:06,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:06,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126189 states and 180823 transitions. [2021-12-19 19:17:07,266 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125549 [2021-12-19 19:17:07,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126189 states to 126189 states and 180823 transitions. [2021-12-19 19:17:07,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126189 [2021-12-19 19:17:07,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126189 [2021-12-19 19:17:07,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126189 states and 180823 transitions. [2021-12-19 19:17:07,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:07,739 INFO L681 BuchiCegarLoop]: Abstraction has 126189 states and 180823 transitions. [2021-12-19 19:17:07,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126189 states and 180823 transitions. [2021-12-19 19:17:09,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126189 to 123501. [2021-12-19 19:17:09,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123501 states, 123501 states have (on average 1.4340855539631259) internal successors, (177111), 123500 states have internal predecessors, (177111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:09,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123501 states to 123501 states and 177111 transitions. [2021-12-19 19:17:09,483 INFO L704 BuchiCegarLoop]: Abstraction has 123501 states and 177111 transitions. [2021-12-19 19:17:09,483 INFO L587 BuchiCegarLoop]: Abstraction has 123501 states and 177111 transitions. [2021-12-19 19:17:09,483 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:09,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123501 states and 177111 transitions. [2021-12-19 19:17:09,762 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123053 [2021-12-19 19:17:09,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:09,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:09,767 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:09,767 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:09,767 INFO L791 eck$LassoCheckResult]: Stem: 521806#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 521807#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 521317#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521318#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521373#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 522899#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 521819#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 521615#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 521008#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 521009#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 522284#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 522418#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 523022#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 523023#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 521744#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 521745#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 522320#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 522221#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 521781#L1201 assume !(0 == ~M_E~0); 521782#L1201-2 assume !(0 == ~T1_E~0); 522757#L1206-1 assume !(0 == ~T2_E~0); 522738#L1211-1 assume !(0 == ~T3_E~0); 522739#L1216-1 assume !(0 == ~T4_E~0); 521598#L1221-1 assume !(0 == ~T5_E~0); 521599#L1226-1 assume !(0 == ~T6_E~0); 521232#L1231-1 assume !(0 == ~T7_E~0); 521233#L1236-1 assume !(0 == ~T8_E~0); 522792#L1241-1 assume !(0 == ~T9_E~0); 521636#L1246-1 assume !(0 == ~T10_E~0); 521637#L1251-1 assume !(0 == ~T11_E~0); 521779#L1256-1 assume !(0 == ~T12_E~0); 521019#L1261-1 assume !(0 == ~E_M~0); 521020#L1266-1 assume !(0 == ~E_1~0); 522992#L1271-1 assume !(0 == ~E_2~0); 522396#L1276-1 assume !(0 == ~E_3~0); 522397#L1281-1 assume !(0 == ~E_4~0); 522335#L1286-1 assume !(0 == ~E_5~0); 521484#L1291-1 assume !(0 == ~E_6~0); 521485#L1296-1 assume !(0 == ~E_7~0); 522096#L1301-1 assume !(0 == ~E_8~0); 522097#L1306-1 assume !(0 == ~E_9~0); 522660#L1311-1 assume !(0 == ~E_10~0); 521435#L1316-1 assume !(0 == ~E_11~0); 521436#L1321-1 assume !(0 == ~E_12~0); 522117#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 522118#L593 assume !(1 == ~m_pc~0); 521323#L593-2 is_master_triggered_~__retres1~0#1 := 0; 521324#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 522966#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 522349#L1492 assume !(0 != activate_threads_~tmp~1#1); 522350#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 522704#L612 assume !(1 == ~t1_pc~0); 522705#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 523009#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521712#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 521328#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 521329#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 521757#L631 assume !(1 == ~t2_pc~0); 521758#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 521105#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 521106#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 521967#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 521968#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 521402#L650 assume !(1 == ~t3_pc~0); 521403#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 522142#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 521325#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 521059#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 521060#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 522309#L669 assume 1 == ~t4_pc~0; 522310#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 522745#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521743#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 521267#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 521268#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 521493#L688 assume !(1 == ~t5_pc~0); 521283#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 521284#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522251#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 522176#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 522177#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 522327#L707 assume 1 == ~t6_pc~0; 522846#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 521936#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 521937#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 522844#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 522258#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 521780#L726 assume 1 == ~t7_pc~0; 521676#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 521369#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 522503#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 522856#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 521137#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 521138#L745 assume !(1 == ~t8_pc~0); 521592#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 521611#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 522542#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 522016#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 522017#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 522611#L764 assume 1 == ~t9_pc~0; 521778#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 521617#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 522352#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 522944#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 521157#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 521158#L783 assume !(1 == ~t10_pc~0); 521219#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 521220#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 521261#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 521262#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 521732#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 522747#L802 assume 1 == ~t11_pc~0; 522725#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 521102#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 521103#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 521600#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 521601#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 521711#L821 assume !(1 == ~t12_pc~0); 521981#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 522088#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 521107#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 521108#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 522808#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522361#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 522362#L1339-2 assume !(1 == ~T1_E~0); 526493#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 526243#L1349-1 assume !(1 == ~T3_E~0); 526241#L1354-1 assume !(1 == ~T4_E~0); 526239#L1359-1 assume !(1 == ~T5_E~0); 526236#L1364-1 assume !(1 == ~T6_E~0); 526234#L1369-1 assume !(1 == ~T7_E~0); 526232#L1374-1 assume !(1 == ~T8_E~0); 526230#L1379-1 assume !(1 == ~T9_E~0); 526218#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 526212#L1389-1 assume !(1 == ~T11_E~0); 526206#L1394-1 assume !(1 == ~T12_E~0); 526200#L1399-1 assume !(1 == ~E_M~0); 526192#L1404-1 assume !(1 == ~E_1~0); 526185#L1409-1 assume !(1 == ~E_2~0); 526177#L1414-1 assume !(1 == ~E_3~0); 526171#L1419-1 assume !(1 == ~E_4~0); 526165#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 526159#L1429-1 assume !(1 == ~E_6~0); 526148#L1434-1 assume !(1 == ~E_7~0); 526140#L1439-1 assume !(1 == ~E_8~0); 526135#L1444-1 assume !(1 == ~E_9~0); 526131#L1449-1 assume !(1 == ~E_10~0); 525737#L1454-1 assume !(1 == ~E_11~0); 525705#L1459-1 assume !(1 == ~E_12~0); 525695#L1464-1 assume { :end_inline_reset_delta_events } true; 525689#L1810-2 [2021-12-19 19:17:09,767 INFO L793 eck$LassoCheckResult]: Loop: 525689#L1810-2 assume !false; 525686#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 525682#L1176 assume !false; 525681#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 525678#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 525667#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 525666#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 525664#L1003 assume !(0 != eval_~tmp~0#1); 525663#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 525662#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525659#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 525660#L1201-5 assume !(0 == ~T1_E~0); 529584#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 529582#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 529580#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 529578#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 529576#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 529574#L1231-3 assume !(0 == ~T7_E~0); 529572#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 529570#L1241-3 assume !(0 == ~T9_E~0); 529568#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 529566#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 529564#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 529562#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 529560#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 529558#L1271-3 assume !(0 == ~E_2~0); 529556#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 529554#L1281-3 assume !(0 == ~E_4~0); 529552#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 529549#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 529547#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 529545#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 529543#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 529541#L1311-3 assume !(0 == ~E_10~0); 529539#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 529536#L1321-3 assume !(0 == ~E_12~0); 529534#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 529532#L593-42 assume !(1 == ~m_pc~0); 529530#L593-44 is_master_triggered_~__retres1~0#1 := 0; 529528#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 529526#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 529523#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 529521#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 529519#L612-42 assume !(1 == ~t1_pc~0); 529517#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 529515#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 529513#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 529510#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 529508#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 529506#L631-42 assume !(1 == ~t2_pc~0); 529504#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 529502#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 529500#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 529497#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 529495#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 529493#L650-42 assume !(1 == ~t3_pc~0); 529490#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 529488#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 529486#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 529483#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 529481#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 529479#L669-42 assume 1 == ~t4_pc~0; 529476#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 529432#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527782#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 527780#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 527779#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527778#L688-42 assume 1 == ~t5_pc~0; 527776#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 527775#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527772#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 527770#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 527768#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 527766#L707-42 assume 1 == ~t6_pc~0; 527763#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 527761#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527758#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 527756#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 527754#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 527752#L726-42 assume 1 == ~t7_pc~0; 527749#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 527747#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 527744#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 527742#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 527740#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 527738#L745-42 assume 1 == ~t8_pc~0; 527720#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 527717#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 527715#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 527713#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 527711#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 527708#L764-42 assume 1 == ~t9_pc~0; 527705#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 527703#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 527701#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 527699#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 527698#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 527694#L783-42 assume !(1 == ~t10_pc~0); 527691#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 527689#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 527688#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 527687#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 527331#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 527329#L802-42 assume 1 == ~t11_pc~0; 527326#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 527324#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 527322#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 527319#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 527317#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 527315#L821-42 assume !(1 == ~t12_pc~0); 527310#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 527308#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 527305#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 527303#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 527085#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527083#L1339-3 assume !(1 == ~M_E~0); 525411#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 527078#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 527076#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 527074#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 527072#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 527070#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 527068#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 527066#L1374-3 assume !(1 == ~T8_E~0); 527064#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 527060#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 527058#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 527056#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 527054#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 527052#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 527050#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 526861#L1414-3 assume !(1 == ~E_3~0); 526750#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 526713#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 526704#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 526564#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 526559#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 526557#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 526554#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 526552#L1454-3 assume !(1 == ~E_11~0); 526549#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 526546#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 526512#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 526501#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 526287#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 525827#L1829 assume !(0 == start_simulation_~tmp~3#1); 525825#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 525727#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 525722#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 525720#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 525719#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 525715#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 525702#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 525694#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 525689#L1810-2 [2021-12-19 19:17:09,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:09,768 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2021-12-19 19:17:09,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:09,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508105396] [2021-12-19 19:17:09,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:09,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:09,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:09,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:09,801 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:09,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508105396] [2021-12-19 19:17:09,801 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508105396] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:09,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:09,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:09,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328397925] [2021-12-19 19:17:09,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:09,802 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:09,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:09,802 INFO L85 PathProgramCache]: Analyzing trace with hash 452829151, now seen corresponding path program 1 times [2021-12-19 19:17:09,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:09,803 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090918159] [2021-12-19 19:17:09,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:09,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:09,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:09,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:09,831 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:09,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090918159] [2021-12-19 19:17:09,832 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090918159] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:09,832 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:09,832 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:09,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755252934] [2021-12-19 19:17:09,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:09,833 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:09,833 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:09,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:09,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:09,833 INFO L87 Difference]: Start difference. First operand 123501 states and 177111 transitions. cyclomatic complexity: 53674 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:11,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:11,609 INFO L93 Difference]: Finished difference Result 347050 states and 494558 transitions. [2021-12-19 19:17:11,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:11,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 347050 states and 494558 transitions. [2021-12-19 19:17:13,313 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 345643 [2021-12-19 19:17:14,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 347050 states to 347050 states and 494558 transitions. [2021-12-19 19:17:14,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 347050 [2021-12-19 19:17:14,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 347050 [2021-12-19 19:17:14,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 347050 states and 494558 transitions. [2021-12-19 19:17:14,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:14,445 INFO L681 BuchiCegarLoop]: Abstraction has 347050 states and 494558 transitions. [2021-12-19 19:17:14,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347050 states and 494558 transitions. [2021-12-19 19:17:17,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347050 to 340266. [2021-12-19 19:17:17,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340266 states, 340266 states have (on average 1.4259843769286382) internal successors, (485214), 340265 states have internal predecessors, (485214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:19,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340266 states to 340266 states and 485214 transitions. [2021-12-19 19:17:19,071 INFO L704 BuchiCegarLoop]: Abstraction has 340266 states and 485214 transitions. [2021-12-19 19:17:19,071 INFO L587 BuchiCegarLoop]: Abstraction has 340266 states and 485214 transitions. [2021-12-19 19:17:19,071 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:19,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340266 states and 485214 transitions. [2021-12-19 19:17:19,859 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 339499 [2021-12-19 19:17:19,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:19,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:19,861 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:19,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:19,861 INFO L791 eck$LassoCheckResult]: Stem: 992362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 992363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 991877#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 991878#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 991931#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 993393#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 992373#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 992175#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 991569#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 991570#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 992824#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 992944#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 993497#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 993498#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 992301#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 992302#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 992854#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 992768#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 992337#L1201 assume !(0 == ~M_E~0); 992338#L1201-2 assume !(0 == ~T1_E~0); 993269#L1206-1 assume !(0 == ~T2_E~0); 993251#L1211-1 assume !(0 == ~T3_E~0); 993252#L1216-1 assume !(0 == ~T4_E~0); 992159#L1221-1 assume !(0 == ~T5_E~0); 992160#L1226-1 assume !(0 == ~T6_E~0); 991792#L1231-1 assume !(0 == ~T7_E~0); 991793#L1236-1 assume !(0 == ~T8_E~0); 993302#L1241-1 assume !(0 == ~T9_E~0); 992196#L1246-1 assume !(0 == ~T10_E~0); 992197#L1251-1 assume !(0 == ~T11_E~0); 992335#L1256-1 assume !(0 == ~T12_E~0); 991580#L1261-1 assume !(0 == ~E_M~0); 991581#L1266-1 assume !(0 == ~E_1~0); 993473#L1271-1 assume !(0 == ~E_2~0); 992928#L1276-1 assume !(0 == ~E_3~0); 992929#L1281-1 assume !(0 == ~E_4~0); 992868#L1286-1 assume !(0 == ~E_5~0); 992045#L1291-1 assume !(0 == ~E_6~0); 992046#L1296-1 assume !(0 == ~E_7~0); 992643#L1301-1 assume !(0 == ~E_8~0); 992644#L1306-1 assume !(0 == ~E_9~0); 993176#L1311-1 assume !(0 == ~E_10~0); 991994#L1316-1 assume !(0 == ~E_11~0); 991995#L1321-1 assume !(0 == ~E_12~0); 992662#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 992663#L593 assume !(1 == ~m_pc~0); 991883#L593-2 is_master_triggered_~__retres1~0#1 := 0; 991884#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 993452#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 992881#L1492 assume !(0 != activate_threads_~tmp~1#1); 992882#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 993223#L612 assume !(1 == ~t1_pc~0); 993224#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 993486#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 992271#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 991888#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 991889#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 992313#L631 assume !(1 == ~t2_pc~0); 992314#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 991665#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991666#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 992513#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 992514#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 991961#L650 assume !(1 == ~t3_pc~0); 991962#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 992690#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 991885#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 991620#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 991621#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 992847#L669 assume !(1 == ~t4_pc~0); 992848#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 993258#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 992300#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991827#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 991828#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 992056#L688 assume !(1 == ~t5_pc~0); 991843#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 991844#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 992793#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 992724#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 992725#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992861#L707 assume 1 == ~t6_pc~0; 993348#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 992482#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992483#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 993346#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 992800#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 992336#L726 assume 1 == ~t7_pc~0; 992236#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 991927#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 993016#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 993358#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 991697#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 991698#L745 assume !(1 == ~t8_pc~0); 992153#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 992171#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993053#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 992563#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 992564#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 993128#L764 assume 1 == ~t9_pc~0; 992334#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 992177#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 992884#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 993426#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 991717#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 991718#L783 assume !(1 == ~t10_pc~0); 991779#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 991780#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 991821#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 991822#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 992289#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993260#L802 assume 1 == ~t11_pc~0; 993241#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 991662#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 991663#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 992161#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 992162#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 992270#L821 assume !(1 == ~t12_pc~0); 992528#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 992634#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 991667#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 991668#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 993313#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 992893#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 992894#L1339-2 assume !(1 == ~T1_E~0); 993446#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 993541#L1349-1 assume !(1 == ~T3_E~0); 992654#L1354-1 assume !(1 == ~T4_E~0); 992655#L1359-1 assume !(1 == ~T5_E~0); 993097#L1364-1 assume !(1 == ~T6_E~0); 1172551#L1369-1 assume !(1 == ~T7_E~0); 1172521#L1374-1 assume !(1 == ~T8_E~0); 992658#L1379-1 assume !(1 == ~T9_E~0); 992659#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 993556#L1389-1 assume !(1 == ~T11_E~0); 993557#L1394-1 assume !(1 == ~T12_E~0); 993513#L1399-1 assume !(1 == ~E_M~0); 993514#L1404-1 assume !(1 == ~E_1~0); 992201#L1409-1 assume !(1 == ~E_2~0); 992202#L1414-1 assume !(1 == ~E_3~0); 992967#L1419-1 assume !(1 == ~E_4~0); 991835#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 991836#L1429-1 assume !(1 == ~E_6~0); 992671#L1434-1 assume !(1 == ~E_7~0); 993330#L1439-1 assume !(1 == ~E_8~0); 993509#L1444-1 assume !(1 == ~E_9~0); 992911#L1449-1 assume !(1 == ~E_10~0); 992253#L1454-1 assume !(1 == ~E_11~0); 992254#L1459-1 assume !(1 == ~E_12~0); 993357#L1464-1 assume { :end_inline_reset_delta_events } true; 1274598#L1810-2 [2021-12-19 19:17:19,862 INFO L793 eck$LassoCheckResult]: Loop: 1274598#L1810-2 assume !false; 1274596#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1274592#L1176 assume !false; 1274591#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1274419#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1274402#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1274395#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1274387#L1003 assume !(0 != eval_~tmp~0#1); 1274388#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1275855#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1275853#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1275852#L1201-5 assume !(0 == ~T1_E~0); 1275851#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1275849#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1275847#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1275845#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1275843#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1275842#L1231-3 assume !(0 == ~T7_E~0); 1275841#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1275838#L1241-3 assume !(0 == ~T9_E~0); 1275836#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1275834#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1275832#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1275830#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1275828#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1275825#L1271-3 assume !(0 == ~E_2~0); 1275823#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1275821#L1281-3 assume !(0 == ~E_4~0); 1275819#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1275817#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1275815#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1275812#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1275810#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1275808#L1311-3 assume !(0 == ~E_10~0); 1275806#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1275804#L1321-3 assume !(0 == ~E_12~0); 1275802#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1275799#L593-42 assume !(1 == ~m_pc~0); 1275797#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1275795#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1275793#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1275791#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1275790#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1275789#L612-42 assume !(1 == ~t1_pc~0); 1275788#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1275787#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1275784#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1275782#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 1275781#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1275780#L631-42 assume !(1 == ~t2_pc~0); 1275779#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1275778#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1275777#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1275776#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1275775#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1275774#L650-42 assume 1 == ~t3_pc~0; 1275690#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1275687#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1275685#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1275683#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1275681#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1275680#L669-42 assume !(1 == ~t4_pc~0); 1275679#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1275678#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1275676#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1275674#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 1275672#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275671#L688-42 assume !(1 == ~t5_pc~0); 1275670#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1275668#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1275564#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1275051#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1275038#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1275036#L707-42 assume !(1 == ~t6_pc~0); 1275034#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1275030#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1275028#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1275026#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1275024#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1275022#L726-42 assume 1 == ~t7_pc~0; 1275019#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1275017#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1275015#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1275013#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1275011#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1275009#L745-42 assume 1 == ~t8_pc~0; 1275007#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1275004#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1275002#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1275000#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1274998#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1274996#L764-42 assume !(1 == ~t9_pc~0); 1274994#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1274991#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1274989#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1274987#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1274985#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1274983#L783-42 assume 1 == ~t10_pc~0; 1274981#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1274978#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1274976#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1274974#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1274972#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1274970#L802-42 assume 1 == ~t11_pc~0; 1274967#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1274965#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1274963#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1274961#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1274959#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1274957#L821-42 assume 1 == ~t12_pc~0; 1274955#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1274952#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1274950#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1274948#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1274946#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1274866#L1339-3 assume !(1 == ~M_E~0); 1145710#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1245800#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1274863#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1274861#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1274859#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1274857#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1274855#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1274853#L1374-3 assume !(1 == ~T8_E~0); 1274851#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1274849#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1274847#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1274845#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1274843#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1274841#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1274839#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1274837#L1414-3 assume !(1 == ~E_3~0); 1274836#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1274833#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1274832#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1274831#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1274829#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1274827#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1274825#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1274823#L1454-3 assume !(1 == ~E_11~0); 1274820#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1265837#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1274804#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1274796#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1274794#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1274644#L1829 assume !(0 == start_simulation_~tmp~3#1); 1274641#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1274616#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1274611#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1274609#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1274607#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1274606#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1274605#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1274599#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1274598#L1810-2 [2021-12-19 19:17:19,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:19,863 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2021-12-19 19:17:19,863 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:19,863 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115056355] [2021-12-19 19:17:19,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:19,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:19,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:19,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:19,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:19,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115056355] [2021-12-19 19:17:19,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115056355] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:19,899 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:19,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:19,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067633689] [2021-12-19 19:17:19,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:19,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:19,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:19,900 INFO L85 PathProgramCache]: Analyzing trace with hash 570506208, now seen corresponding path program 1 times [2021-12-19 19:17:19,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:19,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375770944] [2021-12-19 19:17:19,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:19,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:19,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:19,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:19,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:19,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375770944] [2021-12-19 19:17:19,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375770944] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:19,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:19,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:19,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172176909] [2021-12-19 19:17:19,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:19,929 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:19,929 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:19,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:19,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:19,930 INFO L87 Difference]: Start difference. First operand 340266 states and 485214 transitions. cyclomatic complexity: 145076 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:23,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:23,593 INFO L93 Difference]: Finished difference Result 957947 states and 1358613 transitions. [2021-12-19 19:17:23,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:23,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957947 states and 1358613 transitions. [2021-12-19 19:17:29,128 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 954557 [2021-12-19 19:17:32,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957947 states to 957947 states and 1358613 transitions. [2021-12-19 19:17:32,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957947 [2021-12-19 19:17:32,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957947 [2021-12-19 19:17:32,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957947 states and 1358613 transitions. [2021-12-19 19:17:33,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,263 INFO L681 BuchiCegarLoop]: Abstraction has 957947 states and 1358613 transitions. [2021-12-19 19:17:33,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957947 states and 1358613 transitions.