./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:16:54,659 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:16:54,669 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:16:54,707 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:16:54,707 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:16:54,708 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:16:54,709 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:16:54,710 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:16:54,711 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:16:54,711 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:16:54,712 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:16:54,713 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:16:54,713 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:16:54,714 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:16:54,715 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:16:54,715 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:16:54,716 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:16:54,717 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:16:54,718 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:16:54,719 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:16:54,720 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:16:54,721 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:16:54,724 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:16:54,724 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:16:54,726 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:16:54,727 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:16:54,727 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:16:54,727 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:16:54,728 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:16:54,728 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:16:54,729 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:16:54,729 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:16:54,730 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:16:54,730 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:16:54,731 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:16:54,731 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:16:54,732 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:16:54,732 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:16:54,732 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:16:54,733 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:16:54,733 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:16:54,734 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:16:54,748 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:16:54,749 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:16:54,749 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:16:54,749 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:16:54,750 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:16:54,750 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:16:54,750 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:16:54,750 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:16:54,751 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:16:54,751 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:16:54,751 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:16:54,751 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:16:54,751 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:16:54,751 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:16:54,752 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:16:54,753 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:16:54,753 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:16:54,753 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:16:54,753 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:16:54,753 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:16:54,753 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:16:54,754 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:16:54,754 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:16:54,754 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:16:54,754 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:16:54,755 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:16:54,755 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2021-12-19 19:16:54,907 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:16:54,920 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:16:54,922 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:16:54,923 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:16:54,924 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:16:54,925 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-12-19 19:16:54,967 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c97cc70c5/a71e08854a1b4145a659166f73e831ac/FLAG3ac43281e [2021-12-19 19:16:55,310 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:16:55,310 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-12-19 19:16:55,327 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c97cc70c5/a71e08854a1b4145a659166f73e831ac/FLAG3ac43281e [2021-12-19 19:16:55,727 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c97cc70c5/a71e08854a1b4145a659166f73e831ac [2021-12-19 19:16:55,735 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:16:55,736 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:16:55,737 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:55,737 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:16:55,753 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:16:55,754 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:55" (1/1) ... [2021-12-19 19:16:55,754 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@580c4c68 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:55, skipping insertion in model container [2021-12-19 19:16:55,754 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:16:55" (1/1) ... [2021-12-19 19:16:55,759 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:16:55,807 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:16:55,944 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-12-19 19:16:56,176 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:56,211 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:16:56,218 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-12-19 19:16:56,343 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:16:56,390 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:16:56,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56 WrapperNode [2021-12-19 19:16:56,393 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:16:56,395 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:56,395 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:16:56,395 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:16:56,407 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,426 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,558 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4663 [2021-12-19 19:16:56,559 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:16:56,559 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:16:56,559 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:16:56,560 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:16:56,566 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,566 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,574 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,575 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,600 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,626 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,633 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,682 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:16:56,682 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:16:56,699 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:16:56,700 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:16:56,701 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (1/1) ... [2021-12-19 19:16:56,709 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:16:56,718 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:16:56,773 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:16:56,785 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:16:56,807 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:16:56,808 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:16:56,808 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:16:56,808 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:16:56,914 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:16:56,915 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:16:58,380 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:16:58,410 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:16:58,411 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-19 19:16:58,414 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:58 BoogieIcfgContainer [2021-12-19 19:16:58,414 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:16:58,415 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:16:58,415 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:16:58,417 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:16:58,418 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:58,418 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:16:55" (1/3) ... [2021-12-19 19:16:58,419 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@473f2333 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:58, skipping insertion in model container [2021-12-19 19:16:58,419 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:58,420 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:16:56" (2/3) ... [2021-12-19 19:16:58,420 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@473f2333 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:16:58, skipping insertion in model container [2021-12-19 19:16:58,420 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:16:58,420 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:16:58" (3/3) ... [2021-12-19 19:16:58,421 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2021-12-19 19:16:58,449 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:16:58,449 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:16:58,449 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:16:58,449 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:16:58,449 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:16:58,449 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:16:58,450 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:16:58,450 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:16:58,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2021-12-19 19:16:58,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,612 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,613 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:16:58,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2021-12-19 19:16:58,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:58,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:58,633 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,634 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:58,640 INFO L791 eck$LassoCheckResult]: Stem: 462#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1953#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 302#L1898true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1870#L902true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1830#L909true assume !(1 == ~m_i~0);~m_st~0 := 2; 1941#L909-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 410#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 434#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1230#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1102#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1858#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1268#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1672#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 305#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1321#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1962#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 631#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1172#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1763#L974-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1911#L1286true assume 0 == ~M_E~0;~M_E~0 := 1; 1445#L1286-2true assume !(0 == ~T1_E~0); 257#L1291-1true assume !(0 == ~T2_E~0); 1845#L1296-1true assume !(0 == ~T3_E~0); 691#L1301-1true assume !(0 == ~T4_E~0); 1217#L1306-1true assume !(0 == ~T5_E~0); 1185#L1311-1true assume !(0 == ~T6_E~0); 235#L1316-1true assume !(0 == ~T7_E~0); 1681#L1321-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 706#L1326-1true assume !(0 == ~T9_E~0); 141#L1331-1true assume !(0 == ~T10_E~0); 5#L1336-1true assume !(0 == ~T11_E~0); 1065#L1341-1true assume !(0 == ~T12_E~0); 29#L1346-1true assume !(0 == ~T13_E~0); 1489#L1351-1true assume !(0 == ~E_M~0); 205#L1356-1true assume !(0 == ~E_1~0); 1970#L1361-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1648#L1366-1true assume !(0 == ~E_3~0); 230#L1371-1true assume !(0 == ~E_4~0); 1452#L1376-1true assume !(0 == ~E_5~0); 743#L1381-1true assume !(0 == ~E_6~0); 1738#L1386-1true assume !(0 == ~E_7~0); 1882#L1391-1true assume !(0 == ~E_8~0); 1794#L1396-1true assume !(0 == ~E_9~0); 654#L1401-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1280#L1406-1true assume !(0 == ~E_11~0); 901#L1411-1true assume !(0 == ~E_12~0); 1704#L1416-1true assume !(0 == ~E_13~0); 606#L1421-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 499#L635true assume !(1 == ~m_pc~0); 38#L635-2true is_master_triggered_~__retres1~0#1 := 0; 201#L646true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 584#L647true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1305#L1598true assume !(0 != activate_threads_~tmp~1#1); 121#L1598-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 569#L654true assume 1 == ~t1_pc~0; 510#L655true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1728#L665true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1924#L666true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 568#L1606true assume !(0 != activate_threads_~tmp___0~0#1); 818#L1606-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143#L673true assume 1 == ~t2_pc~0; 1785#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 871#L684true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1857#L685true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1885#L1614true assume !(0 != activate_threads_~tmp___1~0#1); 1985#L1614-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 621#L692true assume !(1 == ~t3_pc~0); 500#L692-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1777#L703true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 412#L704true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 390#L1622true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1710#L1622-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154#L711true assume 1 == ~t4_pc~0; 421#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1316#L722true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723#L723true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16#L1630true assume !(0 != activate_threads_~tmp___3~0#1); 1831#L1630-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1828#L730true assume !(1 == ~t5_pc~0); 1966#L730-2true is_transmit5_triggered_~__retres1~5#1 := 0; 101#L741true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 276#L742true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1638true assume !(0 != activate_threads_~tmp___4~0#1); 342#L1638-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 869#L749true assume 1 == ~t6_pc~0; 218#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 411#L760true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 325#L761true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1448#L1646true assume !(0 != activate_threads_~tmp___5~0#1); 458#L1646-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7#L768true assume !(1 == ~t7_pc~0); 1661#L768-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1384#L779true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118#L780true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1360#L1654true assume !(0 != activate_threads_~tmp___6~0#1); 780#L1654-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 236#L787true assume 1 == ~t8_pc~0; 1118#L788true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1690#L798true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1373#L799true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1900#L1662true assume !(0 != activate_threads_~tmp___7~0#1); 28#L1662-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1186#L806true assume 1 == ~t9_pc~0; 1131#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45#L817true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 806#L818true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 159#L1670true assume !(0 != activate_threads_~tmp___8~0#1); 1593#L1670-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1110#L825true assume !(1 == ~t10_pc~0); 1378#L825-2true is_transmit10_triggered_~__retres1~10#1 := 0; 736#L836true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 845#L837true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202#L1678true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2017#L1678-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 541#L844true assume 1 == ~t11_pc~0; 353#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259#L855true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 588#L856true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1168#L1686true assume !(0 != activate_threads_~tmp___10~0#1); 1097#L1686-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1400#L863true assume !(1 == ~t12_pc~0); 1460#L863-2true is_transmit12_triggered_~__retres1~12#1 := 0; 195#L874true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1526#L875true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1224#L1694true assume !(0 != activate_threads_~tmp___11~0#1); 1617#L1694-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 629#L882true assume 1 == ~t13_pc~0; 900#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1852#L893true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1548#L894true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1175#L1702true assume !(0 != activate_threads_~tmp___12~0#1); 842#L1702-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1574#L1434true assume !(1 == ~M_E~0); 1940#L1434-2true assume !(1 == ~T1_E~0); 1850#L1439-1true assume !(1 == ~T2_E~0); 151#L1444-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 905#L1449-1true assume !(1 == ~T4_E~0); 388#L1454-1true assume !(1 == ~T5_E~0); 1484#L1459-1true assume !(1 == ~T6_E~0); 781#L1464-1true assume !(1 == ~T7_E~0); 851#L1469-1true assume !(1 == ~T8_E~0); 1725#L1474-1true assume !(1 == ~T9_E~0); 607#L1479-1true assume !(1 == ~T10_E~0); 789#L1484-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1248#L1489-1true assume !(1 == ~T12_E~0); 520#L1494-1true assume !(1 == ~T13_E~0); 1836#L1499-1true assume !(1 == ~E_M~0); 645#L1504-1true assume !(1 == ~E_1~0); 1534#L1509-1true assume !(1 == ~E_2~0); 1247#L1514-1true assume !(1 == ~E_3~0); 880#L1519-1true assume !(1 == ~E_4~0); 1954#L1524-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1692#L1529-1true assume !(1 == ~E_6~0); 1767#L1534-1true assume !(1 == ~E_7~0); 53#L1539-1true assume !(1 == ~E_8~0); 267#L1544-1true assume !(1 == ~E_9~0); 1609#L1549-1true assume !(1 == ~E_10~0); 1633#L1554-1true assume !(1 == ~E_11~0); 1606#L1559-1true assume !(1 == ~E_12~0); 1306#L1564-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1673#L1569-1true assume { :end_inline_reset_delta_events } true; 1981#L1935-2true [2021-12-19 19:16:58,655 INFO L793 eck$LassoCheckResult]: Loop: 1981#L1935-2true assume !false; 57#L1936true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1722#L1261true assume false; 814#L1276true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1261#L902-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1349#L1286-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1483#L1286-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1861#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1772#L1301-3true assume !(0 == ~T4_E~0); 1632#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 579#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 165#L1316-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 222#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 667#L1326-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1597#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 883#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1519#L1341-3true assume !(0 == ~T12_E~0); 384#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 376#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 348#L1356-3true assume 0 == ~E_1~0;~E_1~0 := 1; 728#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 757#L1366-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1276#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1563#L1381-3true assume !(0 == ~E_6~0); 1068#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1696#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1325#L1396-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1977#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 200#L1406-3true assume 0 == ~E_11~0;~E_11~0 := 1; 122#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1771#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 466#L1421-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66#L635-45true assume !(1 == ~m_pc~0); 758#L635-47true is_master_triggered_~__retres1~0#1 := 0; 843#L646-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1406#L647-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1096#L1598-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 211#L1598-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720#L654-45true assume 1 == ~t1_pc~0; 1750#L655-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L665-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L666-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59#L1606-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1606-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L673-45true assume !(1 == ~t2_pc~0); 1343#L673-47true is_transmit2_triggered_~__retres1~2#1 := 0; 732#L684-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1561#L685-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1497#L1614-45true assume !(0 != activate_threads_~tmp___1~0#1); 1171#L1614-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282#L692-45true assume !(1 == ~t3_pc~0); 139#L692-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1201#L703-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 786#L704-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 309#L1622-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 498#L1622-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L711-45true assume !(1 == ~t4_pc~0); 627#L711-47true is_transmit4_triggered_~__retres1~4#1 := 0; 1971#L722-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484#L723-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1695#L1630-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 765#L1630-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224#L730-45true assume 1 == ~t5_pc~0; 144#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2031#L741-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 359#L742-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888#L1638-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 991#L1638-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132#L749-45true assume !(1 == ~t6_pc~0); 1542#L749-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1205#L760-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 866#L761-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1413#L1646-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1014#L1646-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295#L768-45true assume 1 == ~t7_pc~0; 368#L769-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1173#L779-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 954#L780-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1841#L1654-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993#L1654-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1898#L787-45true assume !(1 == ~t8_pc~0); 2020#L787-47true is_transmit8_triggered_~__retres1~8#1 := 0; 373#L798-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1683#L799-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 644#L1662-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 887#L1662-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1765#L806-45true assume !(1 == ~t9_pc~0); 74#L806-47true is_transmit9_triggered_~__retres1~9#1 := 0; 521#L817-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1136#L818-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 418#L1670-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 361#L1670-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1817#L825-45true assume 1 == ~t10_pc~0; 777#L826-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1837#L836-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 793#L837-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 922#L1678-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1015#L1678-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171#L844-45true assume !(1 == ~t11_pc~0); 1536#L844-47true is_transmit11_triggered_~__retres1~11#1 := 0; 467#L855-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 477#L856-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 762#L1686-45true assume !(0 != activate_threads_~tmp___10~0#1); 1330#L1686-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 189#L863-45true assume !(1 == ~t12_pc~0); 648#L863-47true is_transmit12_triggered_~__retres1~12#1 := 0; 4#L874-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1423#L875-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 255#L1694-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 769#L1694-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1107#L882-45true assume 1 == ~t13_pc~0; 1367#L883-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12#L893-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 316#L894-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1315#L1702-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1369#L1702-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 855#L1434-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1071#L1434-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1036#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 149#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 231#L1449-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1631#L1454-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 848#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 2008#L1464-3true assume !(1 == ~T7_E~0); 1407#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1279#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1639#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1415#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 582#L1489-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1167#L1494-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1791#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 795#L1504-3true assume !(1 == ~E_1~0); 1294#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1358#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1892#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 522#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1470#L1529-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1691#L1534-3true assume 1 == ~E_7~0;~E_7~0 := 2; 735#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 369#L1544-3true assume !(1 == ~E_9~0); 1422#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 707#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 173#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1192#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 933#L1569-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1111#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 427#L1059-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1099#L1060-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 914#L1954true assume !(0 == start_simulation_~tmp~3#1); 1674#L1954-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1194#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 990#L1059-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1381#L1060-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1150#L1909true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1288#L1916true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1398#L1917true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1793#L1967true assume !(0 != start_simulation_~tmp___0~1#1); 1981#L1935-2true [2021-12-19 19:16:58,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2021-12-19 19:16:58,679 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950271993] [2021-12-19 19:16:58,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,829 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950271993] [2021-12-19 19:16:58,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950271993] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:58,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308168454] [2021-12-19 19:16:58,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,835 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:58,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:58,836 INFO L85 PathProgramCache]: Analyzing trace with hash -855363910, now seen corresponding path program 1 times [2021-12-19 19:16:58,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:58,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135311227] [2021-12-19 19:16:58,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:58,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:58,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:58,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:58,897 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:58,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135311227] [2021-12-19 19:16:58,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135311227] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:58,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:58,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:16:58,898 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885085255] [2021-12-19 19:16:58,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:58,899 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:58,900 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:58,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-19 19:16:58,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-19 19:16:58,923 INFO L87 Difference]: Start difference. First operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:58,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,005 INFO L93 Difference]: Finished difference Result 2027 states and 2998 transitions. [2021-12-19 19:16:59,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-19 19:16:59,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2027 states and 2998 transitions. [2021-12-19 19:16:59,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2027 states to 2021 states and 2992 transitions. [2021-12-19 19:16:59,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:16:59,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:16:59,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2992 transitions. [2021-12-19 19:16:59,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,055 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-12-19 19:16:59,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2992 transitions. [2021-12-19 19:16:59,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:16:59,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2992 transitions. [2021-12-19 19:16:59,130 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-12-19 19:16:59,130 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2021-12-19 19:16:59,130 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:16:59,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2992 transitions. [2021-12-19 19:16:59,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,144 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,145 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,146 INFO L791 eck$LassoCheckResult]: Stem: 4941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4673#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4674#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6064#L909 assume !(1 == ~m_i~0);~m_st~0 := 2; 6065#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4860#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4861#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4895#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5732#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5733#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5845#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5846#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4679#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4680#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5882#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5204#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5205#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5786#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6052#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 5942#L1286-2 assume !(0 == ~T1_E~0); 4588#L1291-1 assume !(0 == ~T2_E~0); 4589#L1296-1 assume !(0 == ~T3_E~0); 5294#L1301-1 assume !(0 == ~T4_E~0); 5295#L1306-1 assume !(0 == ~T5_E~0); 5795#L1311-1 assume !(0 == ~T6_E~0); 4548#L1316-1 assume !(0 == ~T7_E~0); 4549#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5314#L1326-1 assume !(0 == ~T9_E~0); 4363#L1331-1 assume !(0 == ~T10_E~0); 4069#L1336-1 assume !(0 == ~T11_E~0); 4070#L1341-1 assume !(0 == ~T12_E~0); 4121#L1346-1 assume !(0 == ~T13_E~0); 4122#L1351-1 assume !(0 == ~E_M~0); 4495#L1356-1 assume !(0 == ~E_1~0); 4496#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6015#L1366-1 assume !(0 == ~E_3~0); 4541#L1371-1 assume !(0 == ~E_4~0); 4542#L1376-1 assume !(0 == ~E_5~0); 5355#L1381-1 assume !(0 == ~E_6~0); 5356#L1386-1 assume !(0 == ~E_7~0); 6043#L1391-1 assume !(0 == ~E_8~0); 6056#L1396-1 assume !(0 == ~E_9~0); 5238#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5239#L1406-1 assume !(0 == ~E_11~0); 5541#L1411-1 assume !(0 == ~E_12~0); 5542#L1416-1 assume !(0 == ~E_13~0); 5162#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5000#L635 assume !(1 == ~m_pc~0); 4139#L635-2 is_master_triggered_~__retres1~0#1 := 0; 4140#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4490#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5126#L1598 assume !(0 != activate_threads_~tmp~1#1); 4318#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4319#L654 assume 1 == ~t1_pc~0; 5024#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5025#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6040#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5106#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 5107#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4366#L673 assume 1 == ~t2_pc~0; 4367#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5511#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5512#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6070#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 6077#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5185#L692 assume !(1 == ~t3_pc~0); 5002#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5003#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4862#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4830#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4831#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4391#L711 assume 1 == ~t4_pc~0; 4392#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4875#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5332#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4094#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 4095#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6063#L730 assume !(1 == ~t5_pc~0); 5445#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4273#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4274#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4401#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 4402#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4744#L749 assume 1 == ~t6_pc~0; 4518#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4278#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4710#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4711#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 4933#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4074#L768 assume !(1 == ~t7_pc~0); 4075#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5379#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4311#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4312#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 5398#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4550#L787 assume 1 == ~t8_pc~0; 4551#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5746#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5910#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5911#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 4119#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4120#L806 assume 1 == ~t9_pc~0; 5757#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4154#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4155#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4403#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 4404#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5740#L825 assume !(1 == ~t10_pc~0); 5741#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5346#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5347#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4491#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4492#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5075#L844 assume 1 == ~t11_pc~0; 4765#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4766#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5132#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5133#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 5728#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5729#L863 assume !(1 == ~t12_pc~0); 4254#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4253#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4481#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5820#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 5821#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5199#L882 assume 1 == ~t13_pc~0; 5200#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5484#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5985#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5788#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 5471#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5472#L1434 assume !(1 == ~M_E~0); 5993#L1434-2 assume !(1 == ~T1_E~0); 6069#L1439-1 assume !(1 == ~T2_E~0); 4384#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4385#L1449-1 assume !(1 == ~T4_E~0); 4827#L1454-1 assume !(1 == ~T5_E~0); 4828#L1459-1 assume !(1 == ~T6_E~0); 5399#L1464-1 assume !(1 == ~T7_E~0); 5400#L1469-1 assume !(1 == ~T8_E~0); 5485#L1474-1 assume !(1 == ~T9_E~0); 5163#L1479-1 assume !(1 == ~T10_E~0); 5164#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5407#L1489-1 assume !(1 == ~T12_E~0); 5041#L1494-1 assume !(1 == ~T13_E~0); 5042#L1499-1 assume !(1 == ~E_M~0); 5223#L1504-1 assume !(1 == ~E_1~0); 5224#L1509-1 assume !(1 == ~E_2~0); 5837#L1514-1 assume !(1 == ~E_3~0); 5522#L1519-1 assume !(1 == ~E_4~0); 5523#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6027#L1529-1 assume !(1 == ~E_6~0); 6028#L1534-1 assume !(1 == ~E_7~0); 4174#L1539-1 assume !(1 == ~E_8~0); 4175#L1544-1 assume !(1 == ~E_9~0); 4605#L1549-1 assume !(1 == ~E_10~0); 6005#L1554-1 assume !(1 == ~E_11~0); 6003#L1559-1 assume !(1 == ~E_12~0); 5865#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5866#L1569-1 assume { :end_inline_reset_delta_events } true; 6021#L1935-2 [2021-12-19 19:16:59,148 INFO L793 eck$LassoCheckResult]: Loop: 6021#L1935-2 assume !false; 4183#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4184#L1261 assume !false; 5411#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5412#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4314#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4484#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4485#L1074 assume !(0 != eval_~tmp~0#1); 4842#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5440#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5841#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5897#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5616#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5617#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6053#L1301-3 assume !(0 == ~T4_E~0); 6011#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5119#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4418#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4419#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4524#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5260#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5525#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5526#L1341-3 assume !(0 == ~T12_E~0); 4820#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4811#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4755#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4756#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5336#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4110#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5852#L1381-3 assume !(0 == ~E_6~0); 5701#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5702#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5883#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5884#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4489#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4320#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4321#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4948#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4198#L635-45 assume 1 == ~m_pc~0; 4199#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4993#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5473#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5727#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4507#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4508#L654-45 assume 1 == ~t1_pc~0; 5328#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5676#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4161#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5014#L673-45 assume !(1 == ~t2_pc~0); 5015#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5339#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5340#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5965#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 5785#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4632#L692-45 assume !(1 == ~t3_pc~0); 4358#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4359#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5403#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4686#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4687#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4999#L711-45 assume 1 == ~t4_pc~0; 5123#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5124#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4976#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4977#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5380#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4531#L730-45 assume 1 == ~t5_pc~0; 4369#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4370#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4780#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5531#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4342#L749-45 assume !(1 == ~t6_pc~0); 4343#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5743#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5506#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5507#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5658#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L768-45 assume 1 == ~t7_pc~0; 4659#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4798#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5602#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5603#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5642#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5643#L787-45 assume 1 == ~t8_pc~0; 5811#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4804#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4805#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5221#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5222#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5530#L806-45 assume 1 == ~t9_pc~0; 6006#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4218#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5043#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4871#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4783#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4784#L825-45 assume 1 == ~t10_pc~0; 5395#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5308#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5413#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5414#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5566#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4426#L844-45 assume !(1 == ~t11_pc~0); 4427#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4949#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4950#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4966#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 5377#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4466#L863-45 assume 1 == ~t12_pc~0; 4467#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4067#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4068#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4583#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4584#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5383#L882-45 assume !(1 == ~t13_pc~0); 4913#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4086#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4087#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4695#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5874#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5491#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5675#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4380#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4381#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5480#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5481#L1464-3 assume !(1 == ~T7_E~0); 5927#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5854#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5855#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5929#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5121#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5122#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5782#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5417#L1504-3 assume !(1 == ~E_1~0); 5418#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5863#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5903#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5044#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5045#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5950#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5345#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4799#L1544-3 assume !(1 == ~E_9~0); 4800#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5315#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4431#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4432#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5581#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5582#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4316#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4881#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5552#L1954 assume !(0 == start_simulation_~tmp~3#1); 5554#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5804#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4599#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5640#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5770#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5771#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5861#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5923#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 6021#L1935-2 [2021-12-19 19:16:59,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2021-12-19 19:16:59,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591799558] [2021-12-19 19:16:59,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,218 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591799558] [2021-12-19 19:16:59,219 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591799558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,219 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,219 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,219 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888051432] [2021-12-19 19:16:59,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,220 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,220 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 1 times [2021-12-19 19:16:59,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248698112] [2021-12-19 19:16:59,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248698112] [2021-12-19 19:16:59,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248698112] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54634666] [2021-12-19 19:16:59,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,378 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,378 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:59,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:59,379 INFO L87 Difference]: Start difference. First operand 2021 states and 2992 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,425 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2021-12-19 19:16:59,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:59,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2991 transitions. [2021-12-19 19:16:59,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2991 transitions. [2021-12-19 19:16:59,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:16:59,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:16:59,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2991 transitions. [2021-12-19 19:16:59,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,484 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-12-19 19:16:59,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2991 transitions. [2021-12-19 19:16:59,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:16:59,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2991 transitions. [2021-12-19 19:16:59,509 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-12-19 19:16:59,509 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2021-12-19 19:16:59,509 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:16:59,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2991 transitions. [2021-12-19 19:16:59,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,521 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,522 INFO L791 eck$LassoCheckResult]: Stem: 8990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8722#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8723#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10113#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 10114#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8909#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8910#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8944#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9781#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9782#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9894#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9895#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8728#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8729#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9931#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9253#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9254#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9835#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10101#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 9991#L1286-2 assume !(0 == ~T1_E~0); 8637#L1291-1 assume !(0 == ~T2_E~0); 8638#L1296-1 assume !(0 == ~T3_E~0); 9343#L1301-1 assume !(0 == ~T4_E~0); 9344#L1306-1 assume !(0 == ~T5_E~0); 9844#L1311-1 assume !(0 == ~T6_E~0); 8597#L1316-1 assume !(0 == ~T7_E~0); 8598#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9363#L1326-1 assume !(0 == ~T9_E~0); 8412#L1331-1 assume !(0 == ~T10_E~0); 8118#L1336-1 assume !(0 == ~T11_E~0); 8119#L1341-1 assume !(0 == ~T12_E~0); 8170#L1346-1 assume !(0 == ~T13_E~0); 8171#L1351-1 assume !(0 == ~E_M~0); 8544#L1356-1 assume !(0 == ~E_1~0); 8545#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10064#L1366-1 assume !(0 == ~E_3~0); 8590#L1371-1 assume !(0 == ~E_4~0); 8591#L1376-1 assume !(0 == ~E_5~0); 9404#L1381-1 assume !(0 == ~E_6~0); 9405#L1386-1 assume !(0 == ~E_7~0); 10092#L1391-1 assume !(0 == ~E_8~0); 10105#L1396-1 assume !(0 == ~E_9~0); 9287#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9288#L1406-1 assume !(0 == ~E_11~0); 9590#L1411-1 assume !(0 == ~E_12~0); 9591#L1416-1 assume !(0 == ~E_13~0); 9211#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9049#L635 assume !(1 == ~m_pc~0); 8188#L635-2 is_master_triggered_~__retres1~0#1 := 0; 8189#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8539#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9175#L1598 assume !(0 != activate_threads_~tmp~1#1); 8367#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8368#L654 assume 1 == ~t1_pc~0; 9073#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9074#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10089#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9155#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 9156#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8415#L673 assume 1 == ~t2_pc~0; 8416#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9560#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9561#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10119#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 10126#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9234#L692 assume !(1 == ~t3_pc~0); 9051#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9052#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8879#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8880#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8440#L711 assume 1 == ~t4_pc~0; 8441#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8924#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9381#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8143#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 8144#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10112#L730 assume !(1 == ~t5_pc~0); 9494#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8322#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8323#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8450#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 8451#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8793#L749 assume 1 == ~t6_pc~0; 8567#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8327#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8759#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8760#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 8982#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8123#L768 assume !(1 == ~t7_pc~0); 8124#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9428#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8360#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8361#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 9447#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8599#L787 assume 1 == ~t8_pc~0; 8600#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9795#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9959#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9960#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 8168#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8169#L806 assume 1 == ~t9_pc~0; 9806#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8203#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8204#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8452#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 8453#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9789#L825 assume !(1 == ~t10_pc~0); 9790#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9395#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9396#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8540#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8541#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9124#L844 assume 1 == ~t11_pc~0; 8814#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8815#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9181#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9182#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 9777#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9778#L863 assume !(1 == ~t12_pc~0); 8303#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8302#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8530#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9869#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 9870#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9248#L882 assume 1 == ~t13_pc~0; 9249#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9533#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 10034#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9837#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 9520#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9521#L1434 assume !(1 == ~M_E~0); 10042#L1434-2 assume !(1 == ~T1_E~0); 10118#L1439-1 assume !(1 == ~T2_E~0); 8433#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8434#L1449-1 assume !(1 == ~T4_E~0); 8876#L1454-1 assume !(1 == ~T5_E~0); 8877#L1459-1 assume !(1 == ~T6_E~0); 9448#L1464-1 assume !(1 == ~T7_E~0); 9449#L1469-1 assume !(1 == ~T8_E~0); 9534#L1474-1 assume !(1 == ~T9_E~0); 9212#L1479-1 assume !(1 == ~T10_E~0); 9213#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9456#L1489-1 assume !(1 == ~T12_E~0); 9090#L1494-1 assume !(1 == ~T13_E~0); 9091#L1499-1 assume !(1 == ~E_M~0); 9272#L1504-1 assume !(1 == ~E_1~0); 9273#L1509-1 assume !(1 == ~E_2~0); 9886#L1514-1 assume !(1 == ~E_3~0); 9571#L1519-1 assume !(1 == ~E_4~0); 9572#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10076#L1529-1 assume !(1 == ~E_6~0); 10077#L1534-1 assume !(1 == ~E_7~0); 8223#L1539-1 assume !(1 == ~E_8~0); 8224#L1544-1 assume !(1 == ~E_9~0); 8654#L1549-1 assume !(1 == ~E_10~0); 10054#L1554-1 assume !(1 == ~E_11~0); 10052#L1559-1 assume !(1 == ~E_12~0); 9914#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 9915#L1569-1 assume { :end_inline_reset_delta_events } true; 10070#L1935-2 [2021-12-19 19:16:59,523 INFO L793 eck$LassoCheckResult]: Loop: 10070#L1935-2 assume !false; 8232#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8233#L1261 assume !false; 9460#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9461#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8363#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8533#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8534#L1074 assume !(0 != eval_~tmp~0#1); 8891#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9489#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9890#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9946#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9665#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9666#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10102#L1301-3 assume !(0 == ~T4_E~0); 10060#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9168#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8467#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8468#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8573#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9309#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9574#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9575#L1341-3 assume !(0 == ~T12_E~0); 8869#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8860#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8804#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8805#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9385#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8158#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8159#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9901#L1381-3 assume !(0 == ~E_6~0); 9750#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9751#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9932#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9933#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8538#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8369#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8370#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 8997#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8247#L635-45 assume 1 == ~m_pc~0; 8248#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9042#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9522#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9776#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8556#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8557#L654-45 assume 1 == ~t1_pc~0; 9377#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9725#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8210#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8211#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8236#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9063#L673-45 assume !(1 == ~t2_pc~0); 9064#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9388#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9389#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10014#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 9834#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8681#L692-45 assume !(1 == ~t3_pc~0); 8407#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 8408#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9452#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8735#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8736#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9048#L711-45 assume 1 == ~t4_pc~0; 9172#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9173#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9025#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9026#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9429#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8580#L730-45 assume 1 == ~t5_pc~0; 8418#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8419#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8828#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8829#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9580#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8391#L749-45 assume !(1 == ~t6_pc~0); 8392#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 9792#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9555#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9556#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9707#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8707#L768-45 assume 1 == ~t7_pc~0; 8708#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8847#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9651#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9652#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9691#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9692#L787-45 assume 1 == ~t8_pc~0; 9860#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8853#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8854#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9270#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9271#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9579#L806-45 assume 1 == ~t9_pc~0; 10055#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8267#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9092#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8920#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8832#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8833#L825-45 assume 1 == ~t10_pc~0; 9444#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9357#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9462#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9463#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9615#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8475#L844-45 assume !(1 == ~t11_pc~0); 8476#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8998#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8999#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9015#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 9426#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8515#L863-45 assume 1 == ~t12_pc~0; 8516#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8116#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8117#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8632#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8633#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9432#L882-45 assume !(1 == ~t13_pc~0); 8962#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8135#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8136#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8744#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9923#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9539#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9540#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9724#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8429#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8430#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8592#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9529#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9530#L1464-3 assume !(1 == ~T7_E~0); 9976#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9903#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9904#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9978#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9170#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9171#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9831#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9466#L1504-3 assume !(1 == ~E_1~0); 9467#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9912#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9952#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9093#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9094#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9999#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9394#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8848#L1544-3 assume !(1 == ~E_9~0); 8849#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9364#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8480#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8481#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9630#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9631#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8365#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8930#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9601#L1954 assume !(0 == start_simulation_~tmp~3#1); 9603#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8648#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9689#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9819#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9820#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9910#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 9972#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 10070#L1935-2 [2021-12-19 19:16:59,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2021-12-19 19:16:59,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60578309] [2021-12-19 19:16:59,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,526 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,582 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60578309] [2021-12-19 19:16:59,582 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60578309] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389980580] [2021-12-19 19:16:59,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,584 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,584 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 2 times [2021-12-19 19:16:59,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249971748] [2021-12-19 19:16:59,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,650 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249971748] [2021-12-19 19:16:59,651 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [249971748] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,651 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,651 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,651 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663904905] [2021-12-19 19:16:59,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,652 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,652 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:59,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:59,653 INFO L87 Difference]: Start difference. First operand 2021 states and 2991 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,679 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2021-12-19 19:16:59,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:59,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2990 transitions. [2021-12-19 19:16:59,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2990 transitions. [2021-12-19 19:16:59,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:16:59,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:16:59,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2990 transitions. [2021-12-19 19:16:59,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,700 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-12-19 19:16:59,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2990 transitions. [2021-12-19 19:16:59,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:16:59,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2990 transitions. [2021-12-19 19:16:59,723 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-12-19 19:16:59,723 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2021-12-19 19:16:59,723 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:16:59,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2990 transitions. [2021-12-19 19:16:59,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,732 INFO L791 eck$LassoCheckResult]: Stem: 13039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12771#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12772#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14162#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 14163#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12958#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12959#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12993#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13830#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13831#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13943#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13944#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12777#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12778#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13980#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13302#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13303#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13884#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14150#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 14040#L1286-2 assume !(0 == ~T1_E~0); 12686#L1291-1 assume !(0 == ~T2_E~0); 12687#L1296-1 assume !(0 == ~T3_E~0); 13392#L1301-1 assume !(0 == ~T4_E~0); 13393#L1306-1 assume !(0 == ~T5_E~0); 13893#L1311-1 assume !(0 == ~T6_E~0); 12646#L1316-1 assume !(0 == ~T7_E~0); 12647#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13412#L1326-1 assume !(0 == ~T9_E~0); 12461#L1331-1 assume !(0 == ~T10_E~0); 12167#L1336-1 assume !(0 == ~T11_E~0); 12168#L1341-1 assume !(0 == ~T12_E~0); 12219#L1346-1 assume !(0 == ~T13_E~0); 12220#L1351-1 assume !(0 == ~E_M~0); 12593#L1356-1 assume !(0 == ~E_1~0); 12594#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14113#L1366-1 assume !(0 == ~E_3~0); 12639#L1371-1 assume !(0 == ~E_4~0); 12640#L1376-1 assume !(0 == ~E_5~0); 13453#L1381-1 assume !(0 == ~E_6~0); 13454#L1386-1 assume !(0 == ~E_7~0); 14141#L1391-1 assume !(0 == ~E_8~0); 14154#L1396-1 assume !(0 == ~E_9~0); 13336#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13337#L1406-1 assume !(0 == ~E_11~0); 13639#L1411-1 assume !(0 == ~E_12~0); 13640#L1416-1 assume !(0 == ~E_13~0); 13260#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13098#L635 assume !(1 == ~m_pc~0); 12237#L635-2 is_master_triggered_~__retres1~0#1 := 0; 12238#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12588#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13224#L1598 assume !(0 != activate_threads_~tmp~1#1); 12416#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12417#L654 assume 1 == ~t1_pc~0; 13122#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13123#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14138#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13204#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 13205#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12464#L673 assume 1 == ~t2_pc~0; 12465#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13609#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13610#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 14175#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13283#L692 assume !(1 == ~t3_pc~0); 13100#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13101#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12960#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12928#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12929#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12489#L711 assume 1 == ~t4_pc~0; 12490#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12973#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13430#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12192#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 12193#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14161#L730 assume !(1 == ~t5_pc~0); 13543#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12371#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12372#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12499#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 12500#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12842#L749 assume 1 == ~t6_pc~0; 12616#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12376#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12808#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12809#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 13031#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12172#L768 assume !(1 == ~t7_pc~0); 12173#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13477#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12409#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12410#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 13496#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12648#L787 assume 1 == ~t8_pc~0; 12649#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13844#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14008#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14009#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 12217#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12218#L806 assume 1 == ~t9_pc~0; 13855#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12252#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12253#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12501#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 12502#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13838#L825 assume !(1 == ~t10_pc~0); 13839#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13444#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13445#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12589#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12590#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13173#L844 assume 1 == ~t11_pc~0; 12863#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12864#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13230#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13231#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 13826#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13827#L863 assume !(1 == ~t12_pc~0); 12352#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12351#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12579#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13918#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 13919#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13297#L882 assume 1 == ~t13_pc~0; 13298#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13582#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14083#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13886#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 13569#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13570#L1434 assume !(1 == ~M_E~0); 14091#L1434-2 assume !(1 == ~T1_E~0); 14167#L1439-1 assume !(1 == ~T2_E~0); 12482#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12483#L1449-1 assume !(1 == ~T4_E~0); 12925#L1454-1 assume !(1 == ~T5_E~0); 12926#L1459-1 assume !(1 == ~T6_E~0); 13497#L1464-1 assume !(1 == ~T7_E~0); 13498#L1469-1 assume !(1 == ~T8_E~0); 13583#L1474-1 assume !(1 == ~T9_E~0); 13261#L1479-1 assume !(1 == ~T10_E~0); 13262#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13505#L1489-1 assume !(1 == ~T12_E~0); 13139#L1494-1 assume !(1 == ~T13_E~0); 13140#L1499-1 assume !(1 == ~E_M~0); 13321#L1504-1 assume !(1 == ~E_1~0); 13322#L1509-1 assume !(1 == ~E_2~0); 13935#L1514-1 assume !(1 == ~E_3~0); 13620#L1519-1 assume !(1 == ~E_4~0); 13621#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14125#L1529-1 assume !(1 == ~E_6~0); 14126#L1534-1 assume !(1 == ~E_7~0); 12272#L1539-1 assume !(1 == ~E_8~0); 12273#L1544-1 assume !(1 == ~E_9~0); 12703#L1549-1 assume !(1 == ~E_10~0); 14103#L1554-1 assume !(1 == ~E_11~0); 14101#L1559-1 assume !(1 == ~E_12~0); 13963#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 13964#L1569-1 assume { :end_inline_reset_delta_events } true; 14119#L1935-2 [2021-12-19 19:16:59,732 INFO L793 eck$LassoCheckResult]: Loop: 14119#L1935-2 assume !false; 12281#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12282#L1261 assume !false; 13509#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13510#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12412#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12582#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12583#L1074 assume !(0 != eval_~tmp~0#1); 12940#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13538#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13939#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13995#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13714#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13715#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14151#L1301-3 assume !(0 == ~T4_E~0); 14109#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13217#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12516#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12517#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12622#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13358#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13623#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13624#L1341-3 assume !(0 == ~T12_E~0); 12918#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12909#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12853#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12854#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13434#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12207#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12208#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13950#L1381-3 assume !(0 == ~E_6~0); 13799#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13800#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13981#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13982#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12587#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12418#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12419#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13046#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12296#L635-45 assume 1 == ~m_pc~0; 12297#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13091#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13571#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13825#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12605#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12606#L654-45 assume 1 == ~t1_pc~0; 13426#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13774#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12259#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12260#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12285#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13112#L673-45 assume !(1 == ~t2_pc~0); 13113#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13437#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13438#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14063#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 13883#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12730#L692-45 assume !(1 == ~t3_pc~0); 12456#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 12457#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13501#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12784#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12785#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13097#L711-45 assume 1 == ~t4_pc~0; 13221#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13222#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13074#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13075#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13478#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12629#L730-45 assume 1 == ~t5_pc~0; 12467#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12468#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12877#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12878#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13629#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12440#L749-45 assume !(1 == ~t6_pc~0); 12441#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13841#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13604#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13605#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13756#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12756#L768-45 assume 1 == ~t7_pc~0; 12757#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12896#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13700#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13701#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13740#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13741#L787-45 assume 1 == ~t8_pc~0; 13909#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12902#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12903#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13319#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13320#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13628#L806-45 assume 1 == ~t9_pc~0; 14104#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12316#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13141#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12969#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12881#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12882#L825-45 assume 1 == ~t10_pc~0; 13493#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13406#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13511#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13512#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13664#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12524#L844-45 assume !(1 == ~t11_pc~0); 12525#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13047#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13048#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13064#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 13475#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12564#L863-45 assume 1 == ~t12_pc~0; 12565#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12165#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12166#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12681#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12682#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13481#L882-45 assume !(1 == ~t13_pc~0); 13011#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12184#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12185#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12793#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13972#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13588#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13589#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13773#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12478#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12479#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12641#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13578#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13579#L1464-3 assume !(1 == ~T7_E~0); 14025#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13952#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13953#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14027#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13219#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13220#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13880#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13515#L1504-3 assume !(1 == ~E_1~0); 13516#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13961#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14001#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13142#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13143#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14048#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13443#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12897#L1544-3 assume !(1 == ~E_9~0); 12898#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13413#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12529#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12530#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13679#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13680#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12414#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12979#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13650#L1954 assume !(0 == start_simulation_~tmp~3#1); 13652#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13902#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12697#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13738#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13868#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13869#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13959#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14021#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 14119#L1935-2 [2021-12-19 19:16:59,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,734 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2021-12-19 19:16:59,735 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139012661] [2021-12-19 19:16:59,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,796 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139012661] [2021-12-19 19:16:59,796 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139012661] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,797 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,797 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019158688] [2021-12-19 19:16:59,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,800 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,800 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 3 times [2021-12-19 19:16:59,801 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,803 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267737846] [2021-12-19 19:16:59,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267737846] [2021-12-19 19:16:59,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267737846] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,852 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191477428] [2021-12-19 19:16:59,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,853 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,853 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:59,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:16:59,855 INFO L87 Difference]: Start difference. First operand 2021 states and 2990 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:16:59,879 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2021-12-19 19:16:59,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:16:59,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2989 transitions. [2021-12-19 19:16:59,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2989 transitions. [2021-12-19 19:16:59,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:16:59,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:16:59,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2989 transitions. [2021-12-19 19:16:59,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:16:59,899 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-12-19 19:16:59,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2989 transitions. [2021-12-19 19:16:59,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:16:59,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:16:59,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2989 transitions. [2021-12-19 19:16:59,927 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-12-19 19:16:59,927 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2021-12-19 19:16:59,927 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:16:59,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2989 transitions. [2021-12-19 19:16:59,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:16:59,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:16:59,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:16:59,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:16:59,936 INFO L791 eck$LassoCheckResult]: Stem: 17088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16820#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16821#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18211#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 18212#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17007#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17008#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17042#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17879#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17880#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17992#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17993#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16826#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16827#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18029#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17351#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17352#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17933#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18199#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 18089#L1286-2 assume !(0 == ~T1_E~0); 16735#L1291-1 assume !(0 == ~T2_E~0); 16736#L1296-1 assume !(0 == ~T3_E~0); 17441#L1301-1 assume !(0 == ~T4_E~0); 17442#L1306-1 assume !(0 == ~T5_E~0); 17942#L1311-1 assume !(0 == ~T6_E~0); 16695#L1316-1 assume !(0 == ~T7_E~0); 16696#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17461#L1326-1 assume !(0 == ~T9_E~0); 16510#L1331-1 assume !(0 == ~T10_E~0); 16216#L1336-1 assume !(0 == ~T11_E~0); 16217#L1341-1 assume !(0 == ~T12_E~0); 16268#L1346-1 assume !(0 == ~T13_E~0); 16269#L1351-1 assume !(0 == ~E_M~0); 16642#L1356-1 assume !(0 == ~E_1~0); 16643#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 18162#L1366-1 assume !(0 == ~E_3~0); 16688#L1371-1 assume !(0 == ~E_4~0); 16689#L1376-1 assume !(0 == ~E_5~0); 17502#L1381-1 assume !(0 == ~E_6~0); 17503#L1386-1 assume !(0 == ~E_7~0); 18190#L1391-1 assume !(0 == ~E_8~0); 18203#L1396-1 assume !(0 == ~E_9~0); 17385#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17386#L1406-1 assume !(0 == ~E_11~0); 17688#L1411-1 assume !(0 == ~E_12~0); 17689#L1416-1 assume !(0 == ~E_13~0); 17309#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17147#L635 assume !(1 == ~m_pc~0); 16286#L635-2 is_master_triggered_~__retres1~0#1 := 0; 16287#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16637#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17273#L1598 assume !(0 != activate_threads_~tmp~1#1); 16465#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16466#L654 assume 1 == ~t1_pc~0; 17171#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17172#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18187#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17253#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 17254#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16513#L673 assume 1 == ~t2_pc~0; 16514#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17658#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17659#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18217#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 18224#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17332#L692 assume !(1 == ~t3_pc~0); 17149#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17150#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17009#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16977#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16978#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16538#L711 assume 1 == ~t4_pc~0; 16539#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17022#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16241#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 16242#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18210#L730 assume !(1 == ~t5_pc~0); 17592#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16420#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16421#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16548#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 16549#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16891#L749 assume 1 == ~t6_pc~0; 16665#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16425#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16857#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16858#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 17080#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16221#L768 assume !(1 == ~t7_pc~0); 16222#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17526#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16458#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16459#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 17545#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16697#L787 assume 1 == ~t8_pc~0; 16698#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17893#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18057#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18058#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 16266#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16267#L806 assume 1 == ~t9_pc~0; 17904#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16301#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16302#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16550#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 16551#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17887#L825 assume !(1 == ~t10_pc~0); 17888#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17493#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17494#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16638#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16639#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17222#L844 assume 1 == ~t11_pc~0; 16912#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16913#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17279#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17280#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 17875#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17876#L863 assume !(1 == ~t12_pc~0); 16401#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 16400#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16628#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17967#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 17968#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17346#L882 assume 1 == ~t13_pc~0; 17347#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17631#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18132#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17935#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 17618#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17619#L1434 assume !(1 == ~M_E~0); 18140#L1434-2 assume !(1 == ~T1_E~0); 18216#L1439-1 assume !(1 == ~T2_E~0); 16531#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16532#L1449-1 assume !(1 == ~T4_E~0); 16974#L1454-1 assume !(1 == ~T5_E~0); 16975#L1459-1 assume !(1 == ~T6_E~0); 17546#L1464-1 assume !(1 == ~T7_E~0); 17547#L1469-1 assume !(1 == ~T8_E~0); 17632#L1474-1 assume !(1 == ~T9_E~0); 17310#L1479-1 assume !(1 == ~T10_E~0); 17311#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17554#L1489-1 assume !(1 == ~T12_E~0); 17188#L1494-1 assume !(1 == ~T13_E~0); 17189#L1499-1 assume !(1 == ~E_M~0); 17370#L1504-1 assume !(1 == ~E_1~0); 17371#L1509-1 assume !(1 == ~E_2~0); 17984#L1514-1 assume !(1 == ~E_3~0); 17669#L1519-1 assume !(1 == ~E_4~0); 17670#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18174#L1529-1 assume !(1 == ~E_6~0); 18175#L1534-1 assume !(1 == ~E_7~0); 16321#L1539-1 assume !(1 == ~E_8~0); 16322#L1544-1 assume !(1 == ~E_9~0); 16752#L1549-1 assume !(1 == ~E_10~0); 18152#L1554-1 assume !(1 == ~E_11~0); 18150#L1559-1 assume !(1 == ~E_12~0); 18012#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18013#L1569-1 assume { :end_inline_reset_delta_events } true; 18168#L1935-2 [2021-12-19 19:16:59,937 INFO L793 eck$LassoCheckResult]: Loop: 18168#L1935-2 assume !false; 16330#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16331#L1261 assume !false; 17558#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17559#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16461#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16631#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16632#L1074 assume !(0 != eval_~tmp~0#1); 16989#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17587#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17988#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18044#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17763#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17764#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18200#L1301-3 assume !(0 == ~T4_E~0); 18158#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17266#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16565#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16566#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16671#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17407#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17672#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17673#L1341-3 assume !(0 == ~T12_E~0); 16967#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16958#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16902#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16903#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17483#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16256#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16257#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17999#L1381-3 assume !(0 == ~E_6~0); 17848#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17849#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18030#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18031#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16636#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16467#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16468#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17095#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16345#L635-45 assume 1 == ~m_pc~0; 16346#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17140#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17620#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17874#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16654#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16655#L654-45 assume 1 == ~t1_pc~0; 17475#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17823#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16308#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16309#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16334#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17161#L673-45 assume !(1 == ~t2_pc~0); 17162#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17486#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17487#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18112#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 17932#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16779#L692-45 assume !(1 == ~t3_pc~0); 16505#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 16506#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17550#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16833#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16834#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17146#L711-45 assume 1 == ~t4_pc~0; 17270#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17271#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17123#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17124#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17527#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16678#L730-45 assume 1 == ~t5_pc~0; 16516#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16517#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16926#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16927#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17678#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16489#L749-45 assume !(1 == ~t6_pc~0); 16490#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 17890#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17653#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17654#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17805#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16805#L768-45 assume 1 == ~t7_pc~0; 16806#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16945#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17749#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17750#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17789#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17790#L787-45 assume 1 == ~t8_pc~0; 17958#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16951#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16952#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17368#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17369#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17677#L806-45 assume 1 == ~t9_pc~0; 18153#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16365#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17190#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17018#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16930#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16931#L825-45 assume 1 == ~t10_pc~0; 17542#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17455#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17560#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17561#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17713#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16573#L844-45 assume !(1 == ~t11_pc~0); 16574#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17096#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17097#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17113#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 17524#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16613#L863-45 assume 1 == ~t12_pc~0; 16614#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16214#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16215#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16730#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16731#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17530#L882-45 assume !(1 == ~t13_pc~0); 17060#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 16233#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16234#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16842#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18021#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17637#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17638#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17822#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16527#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16528#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16690#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17627#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17628#L1464-3 assume !(1 == ~T7_E~0); 18074#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18001#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18002#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18076#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17268#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17269#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17929#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17564#L1504-3 assume !(1 == ~E_1~0); 17565#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18010#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18050#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17191#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17192#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18097#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17492#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16946#L1544-3 assume !(1 == ~E_9~0); 16947#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17462#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16578#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16579#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17728#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17729#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16463#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17028#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17699#L1954 assume !(0 == start_simulation_~tmp~3#1); 17701#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17951#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16746#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17787#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17917#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17918#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18008#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18070#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 18168#L1935-2 [2021-12-19 19:16:59,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,937 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2021-12-19 19:16:59,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515416699] [2021-12-19 19:16:59,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515416699] [2021-12-19 19:16:59,966 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515416699] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,966 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,966 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040865546] [2021-12-19 19:16:59,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:16:59,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:16:59,967 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 4 times [2021-12-19 19:16:59,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:16:59,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770345936] [2021-12-19 19:16:59,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:16:59,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:16:59,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:16:59,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:16:59,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:16:59,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770345936] [2021-12-19 19:16:59,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770345936] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:16:59,998 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:16:59,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:16:59,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233772522] [2021-12-19 19:16:59,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:16:59,999 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:16:59,999 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:16:59,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:16:59,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,000 INFO L87 Difference]: Start difference. First operand 2021 states and 2989 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,026 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2021-12-19 19:17:00,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2988 transitions. [2021-12-19 19:17:00,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2988 transitions. [2021-12-19 19:17:00,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2988 transitions. [2021-12-19 19:17:00,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,070 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-12-19 19:17:00,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2988 transitions. [2021-12-19 19:17:00,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2988 transitions. [2021-12-19 19:17:00,097 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-12-19 19:17:00,097 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2021-12-19 19:17:00,097 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:00,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2988 transitions. [2021-12-19 19:17:00,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,106 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,106 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,106 INFO L791 eck$LassoCheckResult]: Stem: 21137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20869#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20870#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22260#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 22261#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21056#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21057#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21091#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21928#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21929#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22041#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22042#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20875#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20876#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22078#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21400#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21401#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21982#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22248#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 22138#L1286-2 assume !(0 == ~T1_E~0); 20784#L1291-1 assume !(0 == ~T2_E~0); 20785#L1296-1 assume !(0 == ~T3_E~0); 21490#L1301-1 assume !(0 == ~T4_E~0); 21491#L1306-1 assume !(0 == ~T5_E~0); 21991#L1311-1 assume !(0 == ~T6_E~0); 20744#L1316-1 assume !(0 == ~T7_E~0); 20745#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21510#L1326-1 assume !(0 == ~T9_E~0); 20559#L1331-1 assume !(0 == ~T10_E~0); 20265#L1336-1 assume !(0 == ~T11_E~0); 20266#L1341-1 assume !(0 == ~T12_E~0); 20317#L1346-1 assume !(0 == ~T13_E~0); 20318#L1351-1 assume !(0 == ~E_M~0); 20691#L1356-1 assume !(0 == ~E_1~0); 20692#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22211#L1366-1 assume !(0 == ~E_3~0); 20737#L1371-1 assume !(0 == ~E_4~0); 20738#L1376-1 assume !(0 == ~E_5~0); 21551#L1381-1 assume !(0 == ~E_6~0); 21552#L1386-1 assume !(0 == ~E_7~0); 22239#L1391-1 assume !(0 == ~E_8~0); 22252#L1396-1 assume !(0 == ~E_9~0); 21434#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21435#L1406-1 assume !(0 == ~E_11~0); 21737#L1411-1 assume !(0 == ~E_12~0); 21738#L1416-1 assume !(0 == ~E_13~0); 21358#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21196#L635 assume !(1 == ~m_pc~0); 20335#L635-2 is_master_triggered_~__retres1~0#1 := 0; 20336#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20686#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21322#L1598 assume !(0 != activate_threads_~tmp~1#1); 20514#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20515#L654 assume 1 == ~t1_pc~0; 21220#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21221#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22236#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21302#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 21303#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20562#L673 assume 1 == ~t2_pc~0; 20563#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21707#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21708#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22266#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 22273#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21381#L692 assume !(1 == ~t3_pc~0); 21198#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21199#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21058#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21026#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21027#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20587#L711 assume 1 == ~t4_pc~0; 20588#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21071#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21528#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20290#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 20291#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22259#L730 assume !(1 == ~t5_pc~0); 21641#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20469#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20470#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20597#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 20598#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20940#L749 assume 1 == ~t6_pc~0; 20714#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20474#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20906#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20907#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 21129#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20270#L768 assume !(1 == ~t7_pc~0); 20271#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21575#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20507#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20508#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 21594#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20746#L787 assume 1 == ~t8_pc~0; 20747#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21942#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22106#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22107#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 20315#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20316#L806 assume 1 == ~t9_pc~0; 21953#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20350#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20351#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20599#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 20600#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21936#L825 assume !(1 == ~t10_pc~0); 21937#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21542#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21543#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20687#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20688#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21271#L844 assume 1 == ~t11_pc~0; 20961#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20962#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21328#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21329#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 21924#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21925#L863 assume !(1 == ~t12_pc~0); 20450#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 20449#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20677#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22016#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 22017#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21395#L882 assume 1 == ~t13_pc~0; 21396#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21680#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22181#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21984#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 21667#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21668#L1434 assume !(1 == ~M_E~0); 22189#L1434-2 assume !(1 == ~T1_E~0); 22265#L1439-1 assume !(1 == ~T2_E~0); 20580#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20581#L1449-1 assume !(1 == ~T4_E~0); 21023#L1454-1 assume !(1 == ~T5_E~0); 21024#L1459-1 assume !(1 == ~T6_E~0); 21595#L1464-1 assume !(1 == ~T7_E~0); 21596#L1469-1 assume !(1 == ~T8_E~0); 21681#L1474-1 assume !(1 == ~T9_E~0); 21359#L1479-1 assume !(1 == ~T10_E~0); 21360#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21603#L1489-1 assume !(1 == ~T12_E~0); 21237#L1494-1 assume !(1 == ~T13_E~0); 21238#L1499-1 assume !(1 == ~E_M~0); 21419#L1504-1 assume !(1 == ~E_1~0); 21420#L1509-1 assume !(1 == ~E_2~0); 22033#L1514-1 assume !(1 == ~E_3~0); 21718#L1519-1 assume !(1 == ~E_4~0); 21719#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22223#L1529-1 assume !(1 == ~E_6~0); 22224#L1534-1 assume !(1 == ~E_7~0); 20370#L1539-1 assume !(1 == ~E_8~0); 20371#L1544-1 assume !(1 == ~E_9~0); 20801#L1549-1 assume !(1 == ~E_10~0); 22201#L1554-1 assume !(1 == ~E_11~0); 22199#L1559-1 assume !(1 == ~E_12~0); 22061#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22062#L1569-1 assume { :end_inline_reset_delta_events } true; 22217#L1935-2 [2021-12-19 19:17:00,107 INFO L793 eck$LassoCheckResult]: Loop: 22217#L1935-2 assume !false; 20379#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20380#L1261 assume !false; 21607#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21608#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20510#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20680#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20681#L1074 assume !(0 != eval_~tmp~0#1); 21038#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21636#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22037#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22093#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21812#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21813#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22249#L1301-3 assume !(0 == ~T4_E~0); 22207#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21315#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20614#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20615#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20720#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21456#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21721#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21722#L1341-3 assume !(0 == ~T12_E~0); 21016#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21007#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20951#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20952#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21532#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20305#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20306#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22048#L1381-3 assume !(0 == ~E_6~0); 21897#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21898#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22079#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22080#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20685#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20516#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20517#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21144#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20394#L635-45 assume 1 == ~m_pc~0; 20395#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21189#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21669#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21923#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20703#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20704#L654-45 assume 1 == ~t1_pc~0; 21524#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21872#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20357#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20358#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20383#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21210#L673-45 assume !(1 == ~t2_pc~0); 21211#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21535#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21536#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22161#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 21981#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20828#L692-45 assume !(1 == ~t3_pc~0); 20554#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 20555#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21599#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20882#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20883#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21195#L711-45 assume 1 == ~t4_pc~0; 21319#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21320#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21172#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21173#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21576#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20727#L730-45 assume 1 == ~t5_pc~0; 20565#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20566#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20975#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20976#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21727#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20538#L749-45 assume !(1 == ~t6_pc~0); 20539#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 21939#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21702#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21703#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21854#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20854#L768-45 assume 1 == ~t7_pc~0; 20855#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20994#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21798#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21799#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21838#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21839#L787-45 assume 1 == ~t8_pc~0; 22007#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21000#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21001#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21417#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21418#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21726#L806-45 assume 1 == ~t9_pc~0; 22202#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20414#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21239#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21067#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20979#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20980#L825-45 assume 1 == ~t10_pc~0; 21591#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21504#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21609#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21610#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21762#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20622#L844-45 assume 1 == ~t11_pc~0; 20624#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21145#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21146#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21162#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 21573#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20662#L863-45 assume 1 == ~t12_pc~0; 20663#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20263#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20264#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20779#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20780#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21579#L882-45 assume !(1 == ~t13_pc~0); 21109#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20282#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20283#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20891#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22070#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21686#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21687#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21871#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20576#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20577#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20739#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21676#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21677#L1464-3 assume !(1 == ~T7_E~0); 22123#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22050#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22051#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22125#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21317#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21318#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21978#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21613#L1504-3 assume !(1 == ~E_1~0); 21614#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22059#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22099#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21240#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21241#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22146#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21541#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20995#L1544-3 assume !(1 == ~E_9~0); 20996#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21511#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20627#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20628#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21777#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21778#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20512#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21077#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21748#L1954 assume !(0 == start_simulation_~tmp~3#1); 21750#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 22000#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21836#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21966#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21967#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22057#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22119#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 22217#L1935-2 [2021-12-19 19:17:00,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2021-12-19 19:17:00,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476793528] [2021-12-19 19:17:00,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,138 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476793528] [2021-12-19 19:17:00,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476793528] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,139 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021766899] [2021-12-19 19:17:00,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1797411554, now seen corresponding path program 1 times [2021-12-19 19:17:00,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102487100] [2021-12-19 19:17:00,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102487100] [2021-12-19 19:17:00,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102487100] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766413681] [2021-12-19 19:17:00,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,191 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,191 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,192 INFO L87 Difference]: Start difference. First operand 2021 states and 2988 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,219 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2021-12-19 19:17:00,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2987 transitions. [2021-12-19 19:17:00,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2987 transitions. [2021-12-19 19:17:00,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2987 transitions. [2021-12-19 19:17:00,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,241 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-12-19 19:17:00,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2987 transitions. [2021-12-19 19:17:00,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2987 transitions. [2021-12-19 19:17:00,269 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-12-19 19:17:00,269 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2021-12-19 19:17:00,269 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:00,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2987 transitions. [2021-12-19 19:17:00,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,276 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,276 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,276 INFO L791 eck$LassoCheckResult]: Stem: 25186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24918#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24919#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26309#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 26310#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25105#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25106#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25140#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25977#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25978#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26090#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26091#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24924#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24925#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26127#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25449#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25450#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26031#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26297#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 26187#L1286-2 assume !(0 == ~T1_E~0); 24833#L1291-1 assume !(0 == ~T2_E~0); 24834#L1296-1 assume !(0 == ~T3_E~0); 25539#L1301-1 assume !(0 == ~T4_E~0); 25540#L1306-1 assume !(0 == ~T5_E~0); 26040#L1311-1 assume !(0 == ~T6_E~0); 24793#L1316-1 assume !(0 == ~T7_E~0); 24794#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25559#L1326-1 assume !(0 == ~T9_E~0); 24608#L1331-1 assume !(0 == ~T10_E~0); 24314#L1336-1 assume !(0 == ~T11_E~0); 24315#L1341-1 assume !(0 == ~T12_E~0); 24366#L1346-1 assume !(0 == ~T13_E~0); 24367#L1351-1 assume !(0 == ~E_M~0); 24740#L1356-1 assume !(0 == ~E_1~0); 24741#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26260#L1366-1 assume !(0 == ~E_3~0); 24786#L1371-1 assume !(0 == ~E_4~0); 24787#L1376-1 assume !(0 == ~E_5~0); 25600#L1381-1 assume !(0 == ~E_6~0); 25601#L1386-1 assume !(0 == ~E_7~0); 26288#L1391-1 assume !(0 == ~E_8~0); 26301#L1396-1 assume !(0 == ~E_9~0); 25483#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25484#L1406-1 assume !(0 == ~E_11~0); 25786#L1411-1 assume !(0 == ~E_12~0); 25787#L1416-1 assume !(0 == ~E_13~0); 25407#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25245#L635 assume !(1 == ~m_pc~0); 24384#L635-2 is_master_triggered_~__retres1~0#1 := 0; 24385#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24735#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25371#L1598 assume !(0 != activate_threads_~tmp~1#1); 24563#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24564#L654 assume 1 == ~t1_pc~0; 25269#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25270#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26285#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25351#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 25352#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24611#L673 assume 1 == ~t2_pc~0; 24612#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25756#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25757#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26315#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 26322#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25430#L692 assume !(1 == ~t3_pc~0); 25247#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25248#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25107#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25075#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25076#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24636#L711 assume 1 == ~t4_pc~0; 24637#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25120#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25577#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24339#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 24340#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26308#L730 assume !(1 == ~t5_pc~0); 25690#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24518#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24519#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24646#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 24647#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24989#L749 assume 1 == ~t6_pc~0; 24763#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24523#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24955#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24956#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 25178#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24319#L768 assume !(1 == ~t7_pc~0); 24320#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25624#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24556#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24557#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 25643#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24795#L787 assume 1 == ~t8_pc~0; 24796#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25991#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26155#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26156#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 24364#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24365#L806 assume 1 == ~t9_pc~0; 26002#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24399#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24400#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24648#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 24649#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25985#L825 assume !(1 == ~t10_pc~0); 25986#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25591#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25592#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24736#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24737#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25320#L844 assume 1 == ~t11_pc~0; 25010#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25011#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25377#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 25973#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25974#L863 assume !(1 == ~t12_pc~0); 24499#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 24498#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24726#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26065#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 26066#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25444#L882 assume 1 == ~t13_pc~0; 25445#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25729#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26230#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26033#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 25716#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25717#L1434 assume !(1 == ~M_E~0); 26238#L1434-2 assume !(1 == ~T1_E~0); 26314#L1439-1 assume !(1 == ~T2_E~0); 24629#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24630#L1449-1 assume !(1 == ~T4_E~0); 25072#L1454-1 assume !(1 == ~T5_E~0); 25073#L1459-1 assume !(1 == ~T6_E~0); 25644#L1464-1 assume !(1 == ~T7_E~0); 25645#L1469-1 assume !(1 == ~T8_E~0); 25730#L1474-1 assume !(1 == ~T9_E~0); 25408#L1479-1 assume !(1 == ~T10_E~0); 25409#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25652#L1489-1 assume !(1 == ~T12_E~0); 25286#L1494-1 assume !(1 == ~T13_E~0); 25287#L1499-1 assume !(1 == ~E_M~0); 25468#L1504-1 assume !(1 == ~E_1~0); 25469#L1509-1 assume !(1 == ~E_2~0); 26082#L1514-1 assume !(1 == ~E_3~0); 25767#L1519-1 assume !(1 == ~E_4~0); 25768#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26272#L1529-1 assume !(1 == ~E_6~0); 26273#L1534-1 assume !(1 == ~E_7~0); 24419#L1539-1 assume !(1 == ~E_8~0); 24420#L1544-1 assume !(1 == ~E_9~0); 24850#L1549-1 assume !(1 == ~E_10~0); 26250#L1554-1 assume !(1 == ~E_11~0); 26248#L1559-1 assume !(1 == ~E_12~0); 26110#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26111#L1569-1 assume { :end_inline_reset_delta_events } true; 26266#L1935-2 [2021-12-19 19:17:00,277 INFO L793 eck$LassoCheckResult]: Loop: 26266#L1935-2 assume !false; 24428#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24429#L1261 assume !false; 25656#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25657#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24559#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24729#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24730#L1074 assume !(0 != eval_~tmp~0#1); 25087#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25685#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26086#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26142#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25861#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25862#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26298#L1301-3 assume !(0 == ~T4_E~0); 26256#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25364#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24663#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24664#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24769#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25505#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25770#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25771#L1341-3 assume !(0 == ~T12_E~0); 25065#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25056#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25000#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25001#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25581#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24354#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24355#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26097#L1381-3 assume !(0 == ~E_6~0); 25946#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25947#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26128#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26129#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24734#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24565#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24566#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25193#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24443#L635-45 assume 1 == ~m_pc~0; 24444#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25238#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25718#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25972#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24752#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24753#L654-45 assume 1 == ~t1_pc~0; 25573#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25921#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24406#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24407#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24432#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25259#L673-45 assume !(1 == ~t2_pc~0); 25260#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25584#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25585#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26210#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 26030#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24877#L692-45 assume !(1 == ~t3_pc~0); 24603#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 24604#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25648#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24931#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24932#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25244#L711-45 assume 1 == ~t4_pc~0; 25368#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25369#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25221#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25222#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25625#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24776#L730-45 assume 1 == ~t5_pc~0; 24614#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24615#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25024#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25025#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25776#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24587#L749-45 assume !(1 == ~t6_pc~0); 24588#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25988#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25751#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25752#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25903#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24903#L768-45 assume 1 == ~t7_pc~0; 24904#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25043#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25847#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25848#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25887#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25888#L787-45 assume 1 == ~t8_pc~0; 26056#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25049#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25050#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25466#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25467#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25775#L806-45 assume 1 == ~t9_pc~0; 26251#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24463#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25288#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25116#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25028#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25029#L825-45 assume !(1 == ~t10_pc~0); 25552#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 25553#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25658#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25659#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25811#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24671#L844-45 assume !(1 == ~t11_pc~0); 24672#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25194#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25195#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25211#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 25622#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24711#L863-45 assume 1 == ~t12_pc~0; 24712#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24312#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24313#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24828#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24829#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25628#L882-45 assume !(1 == ~t13_pc~0); 25158#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24331#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24332#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24940#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26119#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25735#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25736#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25920#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24625#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24626#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24788#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25725#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25726#L1464-3 assume !(1 == ~T7_E~0); 26172#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26099#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26100#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26174#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25366#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25367#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 26027#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25662#L1504-3 assume !(1 == ~E_1~0); 25663#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26108#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26148#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25289#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25290#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26195#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25590#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25044#L1544-3 assume !(1 == ~E_9~0); 25045#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25560#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24676#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24677#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25826#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25827#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24561#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25126#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25797#L1954 assume !(0 == start_simulation_~tmp~3#1); 25799#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26049#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24844#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25885#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 26015#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26016#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26106#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26168#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 26266#L1935-2 [2021-12-19 19:17:00,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,278 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2021-12-19 19:17:00,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205524268] [2021-12-19 19:17:00,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,278 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,302 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205524268] [2021-12-19 19:17:00,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205524268] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,302 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,302 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495782307] [2021-12-19 19:17:00,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,303 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,303 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 1 times [2021-12-19 19:17:00,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545210760] [2021-12-19 19:17:00,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545210760] [2021-12-19 19:17:00,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545210760] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,345 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102701574] [2021-12-19 19:17:00,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,346 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,346 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,347 INFO L87 Difference]: Start difference. First operand 2021 states and 2987 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,375 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2021-12-19 19:17:00,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2986 transitions. [2021-12-19 19:17:00,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2986 transitions. [2021-12-19 19:17:00,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2986 transitions. [2021-12-19 19:17:00,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,397 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-12-19 19:17:00,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2986 transitions. [2021-12-19 19:17:00,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2986 transitions. [2021-12-19 19:17:00,461 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-12-19 19:17:00,461 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2021-12-19 19:17:00,462 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:00,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2986 transitions. [2021-12-19 19:17:00,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,469 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,469 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,469 INFO L791 eck$LassoCheckResult]: Stem: 29235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28967#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28968#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30358#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 30359#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29154#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29155#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29189#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30026#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30027#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30139#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30140#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28973#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28974#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30176#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29498#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29499#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30080#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30346#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 30236#L1286-2 assume !(0 == ~T1_E~0); 28882#L1291-1 assume !(0 == ~T2_E~0); 28883#L1296-1 assume !(0 == ~T3_E~0); 29588#L1301-1 assume !(0 == ~T4_E~0); 29589#L1306-1 assume !(0 == ~T5_E~0); 30089#L1311-1 assume !(0 == ~T6_E~0); 28842#L1316-1 assume !(0 == ~T7_E~0); 28843#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29608#L1326-1 assume !(0 == ~T9_E~0); 28657#L1331-1 assume !(0 == ~T10_E~0); 28363#L1336-1 assume !(0 == ~T11_E~0); 28364#L1341-1 assume !(0 == ~T12_E~0); 28415#L1346-1 assume !(0 == ~T13_E~0); 28416#L1351-1 assume !(0 == ~E_M~0); 28789#L1356-1 assume !(0 == ~E_1~0); 28790#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30309#L1366-1 assume !(0 == ~E_3~0); 28835#L1371-1 assume !(0 == ~E_4~0); 28836#L1376-1 assume !(0 == ~E_5~0); 29649#L1381-1 assume !(0 == ~E_6~0); 29650#L1386-1 assume !(0 == ~E_7~0); 30337#L1391-1 assume !(0 == ~E_8~0); 30350#L1396-1 assume !(0 == ~E_9~0); 29532#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29533#L1406-1 assume !(0 == ~E_11~0); 29835#L1411-1 assume !(0 == ~E_12~0); 29836#L1416-1 assume !(0 == ~E_13~0); 29456#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29294#L635 assume !(1 == ~m_pc~0); 28433#L635-2 is_master_triggered_~__retres1~0#1 := 0; 28434#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28784#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29420#L1598 assume !(0 != activate_threads_~tmp~1#1); 28612#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28613#L654 assume 1 == ~t1_pc~0; 29318#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29319#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30334#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29400#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 29401#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28660#L673 assume 1 == ~t2_pc~0; 28661#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29805#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29806#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30364#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 30371#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29479#L692 assume !(1 == ~t3_pc~0); 29296#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29297#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29156#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29124#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29125#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28685#L711 assume 1 == ~t4_pc~0; 28686#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29169#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29626#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28388#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 28389#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30357#L730 assume !(1 == ~t5_pc~0); 29739#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28567#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28568#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28695#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 28696#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29038#L749 assume 1 == ~t6_pc~0; 28812#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28572#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29004#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29005#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 29227#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28368#L768 assume !(1 == ~t7_pc~0); 28369#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29673#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28605#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28606#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 29692#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28844#L787 assume 1 == ~t8_pc~0; 28845#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30040#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30204#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30205#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 28413#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28414#L806 assume 1 == ~t9_pc~0; 30051#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28448#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28449#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28697#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 28698#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30034#L825 assume !(1 == ~t10_pc~0); 30035#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29640#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29641#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28785#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28786#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29369#L844 assume 1 == ~t11_pc~0; 29059#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29060#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29426#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29427#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 30022#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30023#L863 assume !(1 == ~t12_pc~0); 28548#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 28547#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28775#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30114#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 30115#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29493#L882 assume 1 == ~t13_pc~0; 29494#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29778#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30279#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30082#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 29765#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29766#L1434 assume !(1 == ~M_E~0); 30287#L1434-2 assume !(1 == ~T1_E~0); 30363#L1439-1 assume !(1 == ~T2_E~0); 28678#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28679#L1449-1 assume !(1 == ~T4_E~0); 29121#L1454-1 assume !(1 == ~T5_E~0); 29122#L1459-1 assume !(1 == ~T6_E~0); 29693#L1464-1 assume !(1 == ~T7_E~0); 29694#L1469-1 assume !(1 == ~T8_E~0); 29779#L1474-1 assume !(1 == ~T9_E~0); 29457#L1479-1 assume !(1 == ~T10_E~0); 29458#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29701#L1489-1 assume !(1 == ~T12_E~0); 29335#L1494-1 assume !(1 == ~T13_E~0); 29336#L1499-1 assume !(1 == ~E_M~0); 29517#L1504-1 assume !(1 == ~E_1~0); 29518#L1509-1 assume !(1 == ~E_2~0); 30131#L1514-1 assume !(1 == ~E_3~0); 29816#L1519-1 assume !(1 == ~E_4~0); 29817#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30321#L1529-1 assume !(1 == ~E_6~0); 30322#L1534-1 assume !(1 == ~E_7~0); 28468#L1539-1 assume !(1 == ~E_8~0); 28469#L1544-1 assume !(1 == ~E_9~0); 28899#L1549-1 assume !(1 == ~E_10~0); 30299#L1554-1 assume !(1 == ~E_11~0); 30297#L1559-1 assume !(1 == ~E_12~0); 30159#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30160#L1569-1 assume { :end_inline_reset_delta_events } true; 30315#L1935-2 [2021-12-19 19:17:00,469 INFO L793 eck$LassoCheckResult]: Loop: 30315#L1935-2 assume !false; 28477#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28478#L1261 assume !false; 29705#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29706#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28608#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28778#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28779#L1074 assume !(0 != eval_~tmp~0#1); 29136#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29734#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30135#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30191#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29910#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29911#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30347#L1301-3 assume !(0 == ~T4_E~0); 30305#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29413#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28712#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28713#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28818#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29554#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29819#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29820#L1341-3 assume !(0 == ~T12_E~0); 29114#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29105#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29049#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29050#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29630#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28403#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28404#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30146#L1381-3 assume !(0 == ~E_6~0); 29995#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29996#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30177#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30178#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28783#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28614#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28615#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29242#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28492#L635-45 assume 1 == ~m_pc~0; 28493#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29287#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29767#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30021#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28801#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28802#L654-45 assume 1 == ~t1_pc~0; 29622#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29970#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28455#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28456#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28481#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29308#L673-45 assume !(1 == ~t2_pc~0); 29309#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29633#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29634#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30259#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 30079#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28926#L692-45 assume !(1 == ~t3_pc~0); 28652#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 28653#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29697#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28980#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28981#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29293#L711-45 assume 1 == ~t4_pc~0; 29417#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29418#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29270#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29271#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29674#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28825#L730-45 assume 1 == ~t5_pc~0; 28663#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28664#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29073#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29074#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29825#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L749-45 assume !(1 == ~t6_pc~0); 28637#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 30037#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29800#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29801#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29952#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28952#L768-45 assume 1 == ~t7_pc~0; 28953#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29092#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29896#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29897#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29936#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29937#L787-45 assume 1 == ~t8_pc~0; 30105#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29098#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29099#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29515#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29516#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29824#L806-45 assume 1 == ~t9_pc~0; 30300#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28512#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29337#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29165#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29077#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29078#L825-45 assume !(1 == ~t10_pc~0); 29601#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 29602#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29707#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29708#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29860#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28720#L844-45 assume !(1 == ~t11_pc~0); 28721#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29243#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29244#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29260#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 29671#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28760#L863-45 assume 1 == ~t12_pc~0; 28761#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28361#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28362#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28877#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28878#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29677#L882-45 assume !(1 == ~t13_pc~0); 29207#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28380#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28381#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 28989#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30168#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29784#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29785#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29969#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28674#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28675#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28837#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29774#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29775#L1464-3 assume !(1 == ~T7_E~0); 30221#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30148#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30149#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30223#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29415#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29416#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30076#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29711#L1504-3 assume !(1 == ~E_1~0); 29712#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30157#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30197#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29338#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29339#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30244#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29639#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29093#L1544-3 assume !(1 == ~E_9~0); 29094#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29609#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28725#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28726#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29875#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29876#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28610#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29175#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29846#L1954 assume !(0 == start_simulation_~tmp~3#1); 29848#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30098#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28893#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29934#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30064#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30065#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30155#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30217#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 30315#L1935-2 [2021-12-19 19:17:00,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2021-12-19 19:17:00,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476828021] [2021-12-19 19:17:00,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476828021] [2021-12-19 19:17:00,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476828021] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,495 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,495 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602177422] [2021-12-19 19:17:00,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,496 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,496 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 2 times [2021-12-19 19:17:00,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432466378] [2021-12-19 19:17:00,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,529 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432466378] [2021-12-19 19:17:00,532 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432466378] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,532 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,532 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,532 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751453138] [2021-12-19 19:17:00,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,533 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,533 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,534 INFO L87 Difference]: Start difference. First operand 2021 states and 2986 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,560 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2021-12-19 19:17:00,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2985 transitions. [2021-12-19 19:17:00,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2985 transitions. [2021-12-19 19:17:00,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2985 transitions. [2021-12-19 19:17:00,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,580 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-12-19 19:17:00,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2985 transitions. [2021-12-19 19:17:00,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2985 transitions. [2021-12-19 19:17:00,609 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-12-19 19:17:00,609 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2021-12-19 19:17:00,609 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:00,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2985 transitions. [2021-12-19 19:17:00,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,617 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,617 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,617 INFO L791 eck$LassoCheckResult]: Stem: 33284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33016#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33017#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34407#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 34408#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33203#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33204#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33238#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34075#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34076#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34188#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34189#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33022#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33023#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34225#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33547#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33548#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34129#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34395#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 34285#L1286-2 assume !(0 == ~T1_E~0); 32931#L1291-1 assume !(0 == ~T2_E~0); 32932#L1296-1 assume !(0 == ~T3_E~0); 33637#L1301-1 assume !(0 == ~T4_E~0); 33638#L1306-1 assume !(0 == ~T5_E~0); 34138#L1311-1 assume !(0 == ~T6_E~0); 32891#L1316-1 assume !(0 == ~T7_E~0); 32892#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33657#L1326-1 assume !(0 == ~T9_E~0); 32706#L1331-1 assume !(0 == ~T10_E~0); 32412#L1336-1 assume !(0 == ~T11_E~0); 32413#L1341-1 assume !(0 == ~T12_E~0); 32464#L1346-1 assume !(0 == ~T13_E~0); 32465#L1351-1 assume !(0 == ~E_M~0); 32838#L1356-1 assume !(0 == ~E_1~0); 32839#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 34358#L1366-1 assume !(0 == ~E_3~0); 32884#L1371-1 assume !(0 == ~E_4~0); 32885#L1376-1 assume !(0 == ~E_5~0); 33698#L1381-1 assume !(0 == ~E_6~0); 33699#L1386-1 assume !(0 == ~E_7~0); 34386#L1391-1 assume !(0 == ~E_8~0); 34399#L1396-1 assume !(0 == ~E_9~0); 33581#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33582#L1406-1 assume !(0 == ~E_11~0); 33884#L1411-1 assume !(0 == ~E_12~0); 33885#L1416-1 assume !(0 == ~E_13~0); 33505#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33343#L635 assume !(1 == ~m_pc~0); 32482#L635-2 is_master_triggered_~__retres1~0#1 := 0; 32483#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32833#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33469#L1598 assume !(0 != activate_threads_~tmp~1#1); 32661#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32662#L654 assume 1 == ~t1_pc~0; 33367#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33368#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34383#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33449#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 33450#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32709#L673 assume 1 == ~t2_pc~0; 32710#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33854#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33855#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34413#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 34420#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33528#L692 assume !(1 == ~t3_pc~0); 33345#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33346#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33205#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33173#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33174#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32734#L711 assume 1 == ~t4_pc~0; 32735#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33218#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33675#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32437#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 32438#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34406#L730 assume !(1 == ~t5_pc~0); 33788#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32616#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32617#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32744#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 32745#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33087#L749 assume 1 == ~t6_pc~0; 32861#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32621#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33053#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33054#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 33276#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32417#L768 assume !(1 == ~t7_pc~0); 32418#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33722#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32654#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32655#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 33741#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32893#L787 assume 1 == ~t8_pc~0; 32894#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34089#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34253#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34254#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 32462#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32463#L806 assume 1 == ~t9_pc~0; 34100#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32497#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32498#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32746#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34083#L825 assume !(1 == ~t10_pc~0); 34084#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33689#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33690#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32834#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32835#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33418#L844 assume 1 == ~t11_pc~0; 33108#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33109#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33475#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33476#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 34071#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34072#L863 assume !(1 == ~t12_pc~0); 32597#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 32596#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32824#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34163#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 34164#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33542#L882 assume 1 == ~t13_pc~0; 33543#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33827#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34328#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34131#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 33814#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33815#L1434 assume !(1 == ~M_E~0); 34336#L1434-2 assume !(1 == ~T1_E~0); 34412#L1439-1 assume !(1 == ~T2_E~0); 32727#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32728#L1449-1 assume !(1 == ~T4_E~0); 33170#L1454-1 assume !(1 == ~T5_E~0); 33171#L1459-1 assume !(1 == ~T6_E~0); 33742#L1464-1 assume !(1 == ~T7_E~0); 33743#L1469-1 assume !(1 == ~T8_E~0); 33828#L1474-1 assume !(1 == ~T9_E~0); 33506#L1479-1 assume !(1 == ~T10_E~0); 33507#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33750#L1489-1 assume !(1 == ~T12_E~0); 33384#L1494-1 assume !(1 == ~T13_E~0); 33385#L1499-1 assume !(1 == ~E_M~0); 33566#L1504-1 assume !(1 == ~E_1~0); 33567#L1509-1 assume !(1 == ~E_2~0); 34180#L1514-1 assume !(1 == ~E_3~0); 33865#L1519-1 assume !(1 == ~E_4~0); 33866#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34370#L1529-1 assume !(1 == ~E_6~0); 34371#L1534-1 assume !(1 == ~E_7~0); 32517#L1539-1 assume !(1 == ~E_8~0); 32518#L1544-1 assume !(1 == ~E_9~0); 32948#L1549-1 assume !(1 == ~E_10~0); 34348#L1554-1 assume !(1 == ~E_11~0); 34346#L1559-1 assume !(1 == ~E_12~0); 34208#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34209#L1569-1 assume { :end_inline_reset_delta_events } true; 34364#L1935-2 [2021-12-19 19:17:00,618 INFO L793 eck$LassoCheckResult]: Loop: 34364#L1935-2 assume !false; 32526#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32527#L1261 assume !false; 33754#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33755#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32657#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32827#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32828#L1074 assume !(0 != eval_~tmp~0#1); 33185#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33783#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34184#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34240#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33959#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33960#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34396#L1301-3 assume !(0 == ~T4_E~0); 34354#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33462#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32761#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32762#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32867#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33603#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33868#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33869#L1341-3 assume !(0 == ~T12_E~0); 33163#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33154#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33098#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33099#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33679#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32452#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32453#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34195#L1381-3 assume !(0 == ~E_6~0); 34044#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34045#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34226#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34227#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32832#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32663#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32664#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33291#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32541#L635-45 assume 1 == ~m_pc~0; 32542#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33336#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33816#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34070#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32850#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32851#L654-45 assume 1 == ~t1_pc~0; 33671#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34019#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32504#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32505#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32530#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33357#L673-45 assume !(1 == ~t2_pc~0); 33358#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33682#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33683#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34308#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 34128#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32975#L692-45 assume 1 == ~t3_pc~0; 32976#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32702#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33746#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33029#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33030#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33342#L711-45 assume 1 == ~t4_pc~0; 33466#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33467#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33319#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33320#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33723#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32874#L730-45 assume 1 == ~t5_pc~0; 32712#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32713#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33122#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33123#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33874#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32685#L749-45 assume !(1 == ~t6_pc~0); 32686#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 34086#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33849#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33850#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34001#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33001#L768-45 assume 1 == ~t7_pc~0; 33002#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33141#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33945#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33946#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33985#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33986#L787-45 assume 1 == ~t8_pc~0; 34154#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33147#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33148#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33564#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33565#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33873#L806-45 assume !(1 == ~t9_pc~0); 32560#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 32561#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33386#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33214#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33126#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33127#L825-45 assume !(1 == ~t10_pc~0); 33650#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 33651#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33756#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33757#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33909#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32769#L844-45 assume !(1 == ~t11_pc~0); 32770#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33292#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33293#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33309#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 33720#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32809#L863-45 assume 1 == ~t12_pc~0; 32810#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32410#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32411#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32926#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32927#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33726#L882-45 assume 1 == ~t13_pc~0; 34080#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32429#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32430#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33038#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34217#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33833#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33834#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34018#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32723#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32724#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32886#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33823#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33824#L1464-3 assume !(1 == ~T7_E~0); 34270#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34197#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34198#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34272#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33464#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33465#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34125#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33760#L1504-3 assume !(1 == ~E_1~0); 33761#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34206#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34246#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33387#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33388#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34293#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33688#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33142#L1544-3 assume !(1 == ~E_9~0); 33143#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33658#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32774#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32775#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33924#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33925#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32659#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33224#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33895#L1954 assume !(0 == start_simulation_~tmp~3#1); 33897#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34147#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32942#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33983#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34113#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34114#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34204#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34266#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 34364#L1935-2 [2021-12-19 19:17:00,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2021-12-19 19:17:00,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711625089] [2021-12-19 19:17:00,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,642 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711625089] [2021-12-19 19:17:00,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711625089] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,643 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,643 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425472860] [2021-12-19 19:17:00,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,644 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,644 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 1 times [2021-12-19 19:17:00,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583562578] [2021-12-19 19:17:00,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,674 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583562578] [2021-12-19 19:17:00,675 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583562578] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,675 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,675 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,675 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903507802] [2021-12-19 19:17:00,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,676 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,676 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,676 INFO L87 Difference]: Start difference. First operand 2021 states and 2985 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,701 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2021-12-19 19:17:00,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2984 transitions. [2021-12-19 19:17:00,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2984 transitions. [2021-12-19 19:17:00,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2984 transitions. [2021-12-19 19:17:00,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,726 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-12-19 19:17:00,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2984 transitions. [2021-12-19 19:17:00,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2984 transitions. [2021-12-19 19:17:00,764 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-12-19 19:17:00,764 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2021-12-19 19:17:00,765 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:00,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2984 transitions. [2021-12-19 19:17:00,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,772 INFO L791 eck$LassoCheckResult]: Stem: 37333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37065#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37066#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38456#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 38457#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37252#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37253#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37287#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38124#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38125#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38237#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38238#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37071#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37072#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38274#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37596#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37597#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38178#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38444#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 38334#L1286-2 assume !(0 == ~T1_E~0); 36980#L1291-1 assume !(0 == ~T2_E~0); 36981#L1296-1 assume !(0 == ~T3_E~0); 37686#L1301-1 assume !(0 == ~T4_E~0); 37687#L1306-1 assume !(0 == ~T5_E~0); 38187#L1311-1 assume !(0 == ~T6_E~0); 36940#L1316-1 assume !(0 == ~T7_E~0); 36941#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37706#L1326-1 assume !(0 == ~T9_E~0); 36755#L1331-1 assume !(0 == ~T10_E~0); 36461#L1336-1 assume !(0 == ~T11_E~0); 36462#L1341-1 assume !(0 == ~T12_E~0); 36513#L1346-1 assume !(0 == ~T13_E~0); 36514#L1351-1 assume !(0 == ~E_M~0); 36887#L1356-1 assume !(0 == ~E_1~0); 36888#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38407#L1366-1 assume !(0 == ~E_3~0); 36933#L1371-1 assume !(0 == ~E_4~0); 36934#L1376-1 assume !(0 == ~E_5~0); 37747#L1381-1 assume !(0 == ~E_6~0); 37748#L1386-1 assume !(0 == ~E_7~0); 38435#L1391-1 assume !(0 == ~E_8~0); 38448#L1396-1 assume !(0 == ~E_9~0); 37630#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37631#L1406-1 assume !(0 == ~E_11~0); 37933#L1411-1 assume !(0 == ~E_12~0); 37934#L1416-1 assume !(0 == ~E_13~0); 37554#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37392#L635 assume !(1 == ~m_pc~0); 36531#L635-2 is_master_triggered_~__retres1~0#1 := 0; 36532#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36882#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37518#L1598 assume !(0 != activate_threads_~tmp~1#1); 36710#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36711#L654 assume 1 == ~t1_pc~0; 37416#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37417#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38432#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37498#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 37499#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36758#L673 assume 1 == ~t2_pc~0; 36759#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37903#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37904#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38462#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 38469#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37577#L692 assume !(1 == ~t3_pc~0); 37394#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37395#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37254#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37222#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37223#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36783#L711 assume 1 == ~t4_pc~0; 36784#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37267#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37724#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36486#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 36487#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38455#L730 assume !(1 == ~t5_pc~0); 37837#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36665#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36666#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36793#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 36794#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37136#L749 assume 1 == ~t6_pc~0; 36910#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36670#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37102#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37103#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 37325#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36466#L768 assume !(1 == ~t7_pc~0); 36467#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37771#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36703#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36704#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 37790#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36942#L787 assume 1 == ~t8_pc~0; 36943#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38138#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38302#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38303#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 36511#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36512#L806 assume 1 == ~t9_pc~0; 38149#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36546#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36547#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36795#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 36796#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38132#L825 assume !(1 == ~t10_pc~0); 38133#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37738#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37739#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36883#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36884#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37467#L844 assume 1 == ~t11_pc~0; 37157#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37158#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37524#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37525#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 38120#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38121#L863 assume !(1 == ~t12_pc~0); 36646#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36645#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36873#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38212#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 38213#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37591#L882 assume 1 == ~t13_pc~0; 37592#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37876#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38377#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38180#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 37863#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37864#L1434 assume !(1 == ~M_E~0); 38385#L1434-2 assume !(1 == ~T1_E~0); 38461#L1439-1 assume !(1 == ~T2_E~0); 36776#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36777#L1449-1 assume !(1 == ~T4_E~0); 37219#L1454-1 assume !(1 == ~T5_E~0); 37220#L1459-1 assume !(1 == ~T6_E~0); 37791#L1464-1 assume !(1 == ~T7_E~0); 37792#L1469-1 assume !(1 == ~T8_E~0); 37877#L1474-1 assume !(1 == ~T9_E~0); 37555#L1479-1 assume !(1 == ~T10_E~0); 37556#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37799#L1489-1 assume !(1 == ~T12_E~0); 37433#L1494-1 assume !(1 == ~T13_E~0); 37434#L1499-1 assume !(1 == ~E_M~0); 37615#L1504-1 assume !(1 == ~E_1~0); 37616#L1509-1 assume !(1 == ~E_2~0); 38229#L1514-1 assume !(1 == ~E_3~0); 37914#L1519-1 assume !(1 == ~E_4~0); 37915#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38419#L1529-1 assume !(1 == ~E_6~0); 38420#L1534-1 assume !(1 == ~E_7~0); 36566#L1539-1 assume !(1 == ~E_8~0); 36567#L1544-1 assume !(1 == ~E_9~0); 36997#L1549-1 assume !(1 == ~E_10~0); 38397#L1554-1 assume !(1 == ~E_11~0); 38395#L1559-1 assume !(1 == ~E_12~0); 38257#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38258#L1569-1 assume { :end_inline_reset_delta_events } true; 38413#L1935-2 [2021-12-19 19:17:00,772 INFO L793 eck$LassoCheckResult]: Loop: 38413#L1935-2 assume !false; 36575#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36576#L1261 assume !false; 37803#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37804#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36706#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36876#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36877#L1074 assume !(0 != eval_~tmp~0#1); 37234#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37832#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38233#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38289#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38008#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38009#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38445#L1301-3 assume !(0 == ~T4_E~0); 38403#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37511#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36810#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36811#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36916#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37652#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37917#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37918#L1341-3 assume !(0 == ~T12_E~0); 37212#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37203#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37147#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37148#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37728#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36501#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36502#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38244#L1381-3 assume !(0 == ~E_6~0); 38093#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38094#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38275#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38276#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36881#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36712#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36713#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37340#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36590#L635-45 assume !(1 == ~m_pc~0); 36592#L635-47 is_master_triggered_~__retres1~0#1 := 0; 37385#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37865#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38119#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36899#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36900#L654-45 assume 1 == ~t1_pc~0; 37720#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38068#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36553#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36554#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36579#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37406#L673-45 assume 1 == ~t2_pc~0; 37408#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37731#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37732#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38357#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 38177#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37024#L692-45 assume 1 == ~t3_pc~0; 37025#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36751#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37795#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37078#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37079#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37391#L711-45 assume 1 == ~t4_pc~0; 37515#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37516#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37368#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37369#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37772#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36923#L730-45 assume 1 == ~t5_pc~0; 36761#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36762#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37171#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37172#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37923#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36734#L749-45 assume 1 == ~t6_pc~0; 36736#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38135#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37898#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37899#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38050#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37050#L768-45 assume 1 == ~t7_pc~0; 37051#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37190#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37994#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37995#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38034#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38035#L787-45 assume 1 == ~t8_pc~0; 38203#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37196#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37197#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37613#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37614#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37922#L806-45 assume !(1 == ~t9_pc~0); 36609#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36610#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37435#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37263#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37175#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37176#L825-45 assume !(1 == ~t10_pc~0); 37699#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 37700#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37805#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37806#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37958#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36818#L844-45 assume !(1 == ~t11_pc~0); 36819#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37341#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37342#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37358#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 37769#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36858#L863-45 assume 1 == ~t12_pc~0; 36859#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36459#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36460#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36975#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36976#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37775#L882-45 assume 1 == ~t13_pc~0; 38129#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 36478#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36479#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37087#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38266#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37882#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37883#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38067#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36772#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36773#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36935#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37872#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37873#L1464-3 assume !(1 == ~T7_E~0); 38319#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38246#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38247#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38321#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37513#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37514#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38174#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37809#L1504-3 assume !(1 == ~E_1~0); 37810#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38255#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38295#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37436#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37437#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38342#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37737#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37191#L1544-3 assume !(1 == ~E_9~0); 37192#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37707#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36823#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36824#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37973#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37974#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36708#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37273#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37944#L1954 assume !(0 == start_simulation_~tmp~3#1); 37946#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38196#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36991#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38032#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38162#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38253#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38315#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 38413#L1935-2 [2021-12-19 19:17:00,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2021-12-19 19:17:00,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608176398] [2021-12-19 19:17:00,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608176398] [2021-12-19 19:17:00,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608176398] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440747165] [2021-12-19 19:17:00,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,801 INFO L85 PathProgramCache]: Analyzing trace with hash -1698619550, now seen corresponding path program 1 times [2021-12-19 19:17:00,801 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527132521] [2021-12-19 19:17:00,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527132521] [2021-12-19 19:17:00,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527132521] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,833 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,833 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,833 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322623252] [2021-12-19 19:17:00,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,833 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:00,834 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:00,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:00,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:00,835 INFO L87 Difference]: Start difference. First operand 2021 states and 2984 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:00,859 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2021-12-19 19:17:00,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:00,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2983 transitions. [2021-12-19 19:17:00,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2983 transitions. [2021-12-19 19:17:00,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:00,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:00,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2983 transitions. [2021-12-19 19:17:00,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:00,874 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-12-19 19:17:00,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2983 transitions. [2021-12-19 19:17:00,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:00,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:00,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2983 transitions. [2021-12-19 19:17:00,931 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-12-19 19:17:00,931 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2021-12-19 19:17:00,931 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:00,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2983 transitions. [2021-12-19 19:17:00,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:00,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:00,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:00,937 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:00,938 INFO L791 eck$LassoCheckResult]: Stem: 41382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41114#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41115#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42505#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 42506#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41301#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41302#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41336#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42173#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42174#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42286#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42287#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41120#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41121#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42323#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41645#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41646#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42227#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42493#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 42383#L1286-2 assume !(0 == ~T1_E~0); 41029#L1291-1 assume !(0 == ~T2_E~0); 41030#L1296-1 assume !(0 == ~T3_E~0); 41735#L1301-1 assume !(0 == ~T4_E~0); 41736#L1306-1 assume !(0 == ~T5_E~0); 42236#L1311-1 assume !(0 == ~T6_E~0); 40989#L1316-1 assume !(0 == ~T7_E~0); 40990#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41755#L1326-1 assume !(0 == ~T9_E~0); 40804#L1331-1 assume !(0 == ~T10_E~0); 40510#L1336-1 assume !(0 == ~T11_E~0); 40511#L1341-1 assume !(0 == ~T12_E~0); 40562#L1346-1 assume !(0 == ~T13_E~0); 40563#L1351-1 assume !(0 == ~E_M~0); 40936#L1356-1 assume !(0 == ~E_1~0); 40937#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42456#L1366-1 assume !(0 == ~E_3~0); 40982#L1371-1 assume !(0 == ~E_4~0); 40983#L1376-1 assume !(0 == ~E_5~0); 41796#L1381-1 assume !(0 == ~E_6~0); 41797#L1386-1 assume !(0 == ~E_7~0); 42484#L1391-1 assume !(0 == ~E_8~0); 42497#L1396-1 assume !(0 == ~E_9~0); 41679#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 41680#L1406-1 assume !(0 == ~E_11~0); 41982#L1411-1 assume !(0 == ~E_12~0); 41983#L1416-1 assume !(0 == ~E_13~0); 41603#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41441#L635 assume !(1 == ~m_pc~0); 40580#L635-2 is_master_triggered_~__retres1~0#1 := 0; 40581#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40931#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41567#L1598 assume !(0 != activate_threads_~tmp~1#1); 40759#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40760#L654 assume 1 == ~t1_pc~0; 41465#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41466#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42481#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41547#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 41548#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40807#L673 assume 1 == ~t2_pc~0; 40808#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41952#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41953#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42511#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 42518#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41626#L692 assume !(1 == ~t3_pc~0); 41443#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41444#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41303#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41271#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41272#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40832#L711 assume 1 == ~t4_pc~0; 40833#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41316#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41773#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40535#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 40536#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42504#L730 assume !(1 == ~t5_pc~0); 41886#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40714#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40715#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40842#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 40843#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41185#L749 assume 1 == ~t6_pc~0; 40959#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40719#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41151#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41152#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 41374#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40515#L768 assume !(1 == ~t7_pc~0); 40516#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41820#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40752#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40753#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 41839#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40991#L787 assume 1 == ~t8_pc~0; 40992#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42187#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42351#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42352#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 40560#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40561#L806 assume 1 == ~t9_pc~0; 42198#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40595#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40596#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40844#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 40845#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42181#L825 assume !(1 == ~t10_pc~0); 42182#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41787#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41788#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40932#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40933#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41516#L844 assume 1 == ~t11_pc~0; 41206#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41207#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41573#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41574#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 42169#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42170#L863 assume !(1 == ~t12_pc~0); 40695#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40694#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40922#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42261#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 42262#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41640#L882 assume 1 == ~t13_pc~0; 41641#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41925#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42426#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42229#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 41912#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41913#L1434 assume !(1 == ~M_E~0); 42434#L1434-2 assume !(1 == ~T1_E~0); 42510#L1439-1 assume !(1 == ~T2_E~0); 40825#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40826#L1449-1 assume !(1 == ~T4_E~0); 41268#L1454-1 assume !(1 == ~T5_E~0); 41269#L1459-1 assume !(1 == ~T6_E~0); 41840#L1464-1 assume !(1 == ~T7_E~0); 41841#L1469-1 assume !(1 == ~T8_E~0); 41926#L1474-1 assume !(1 == ~T9_E~0); 41604#L1479-1 assume !(1 == ~T10_E~0); 41605#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41848#L1489-1 assume !(1 == ~T12_E~0); 41482#L1494-1 assume !(1 == ~T13_E~0); 41483#L1499-1 assume !(1 == ~E_M~0); 41664#L1504-1 assume !(1 == ~E_1~0); 41665#L1509-1 assume !(1 == ~E_2~0); 42278#L1514-1 assume !(1 == ~E_3~0); 41963#L1519-1 assume !(1 == ~E_4~0); 41964#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42468#L1529-1 assume !(1 == ~E_6~0); 42469#L1534-1 assume !(1 == ~E_7~0); 40615#L1539-1 assume !(1 == ~E_8~0); 40616#L1544-1 assume !(1 == ~E_9~0); 41046#L1549-1 assume !(1 == ~E_10~0); 42446#L1554-1 assume !(1 == ~E_11~0); 42444#L1559-1 assume !(1 == ~E_12~0); 42306#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42307#L1569-1 assume { :end_inline_reset_delta_events } true; 42462#L1935-2 [2021-12-19 19:17:00,938 INFO L793 eck$LassoCheckResult]: Loop: 42462#L1935-2 assume !false; 40624#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40625#L1261 assume !false; 41852#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41853#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40755#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40925#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40926#L1074 assume !(0 != eval_~tmp~0#1); 41283#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41881#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42282#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42338#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42057#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42058#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42494#L1301-3 assume !(0 == ~T4_E~0); 42452#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41560#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40859#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40860#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40965#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41701#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41966#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41967#L1341-3 assume !(0 == ~T12_E~0); 41261#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41252#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41196#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41197#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41777#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40550#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40551#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42293#L1381-3 assume !(0 == ~E_6~0); 42142#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42143#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42324#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42325#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40930#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40761#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40762#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41389#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40639#L635-45 assume 1 == ~m_pc~0; 40640#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41434#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41914#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42168#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40948#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40949#L654-45 assume 1 == ~t1_pc~0; 41769#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42117#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40602#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40603#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40628#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41455#L673-45 assume !(1 == ~t2_pc~0); 41456#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41780#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41781#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42406#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 42226#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41073#L692-45 assume 1 == ~t3_pc~0; 41074#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40800#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41844#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41127#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41128#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41440#L711-45 assume 1 == ~t4_pc~0; 41564#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41565#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41417#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41418#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41821#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40972#L730-45 assume 1 == ~t5_pc~0; 40810#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40811#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41220#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41221#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41972#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40783#L749-45 assume !(1 == ~t6_pc~0); 40784#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 42184#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41947#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41948#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42099#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41099#L768-45 assume 1 == ~t7_pc~0; 41100#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41239#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42043#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42044#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42083#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42084#L787-45 assume 1 == ~t8_pc~0; 42252#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41245#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41246#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41662#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41663#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41971#L806-45 assume !(1 == ~t9_pc~0); 40658#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 40659#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41484#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41312#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41224#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41225#L825-45 assume !(1 == ~t10_pc~0); 41748#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 41749#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41854#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41855#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42007#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40867#L844-45 assume !(1 == ~t11_pc~0); 40868#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41390#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41391#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41407#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 41818#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40907#L863-45 assume 1 == ~t12_pc~0; 40908#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40508#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40509#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41024#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41025#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41824#L882-45 assume 1 == ~t13_pc~0; 42178#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40527#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40528#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41136#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42315#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41931#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41932#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42116#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40821#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40822#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40984#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41921#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41922#L1464-3 assume !(1 == ~T7_E~0); 42368#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42295#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42296#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42370#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41562#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41563#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42223#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41858#L1504-3 assume !(1 == ~E_1~0); 41859#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42304#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42344#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41485#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41486#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42391#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41786#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41240#L1544-3 assume !(1 == ~E_9~0); 41241#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41756#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40872#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40873#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42022#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42023#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40757#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41322#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41993#L1954 assume !(0 == start_simulation_~tmp~3#1); 41995#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42245#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41040#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42081#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42211#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42212#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42302#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42364#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 42462#L1935-2 [2021-12-19 19:17:00,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,939 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2021-12-19 19:17:00,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422635263] [2021-12-19 19:17:00,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:00,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:00,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:00,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422635263] [2021-12-19 19:17:00,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422635263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:00,970 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:00,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:00,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418758183] [2021-12-19 19:17:00,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:00,970 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:00,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:00,971 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 2 times [2021-12-19 19:17:00,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:00,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163848663] [2021-12-19 19:17:00,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:00,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:00,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,000 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,001 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163848663] [2021-12-19 19:17:01,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163848663] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,001 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198440201] [2021-12-19 19:17:01,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,001 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:01,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:01,003 INFO L87 Difference]: Start difference. First operand 2021 states and 2983 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,025 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2021-12-19 19:17:01,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:01,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2982 transitions. [2021-12-19 19:17:01,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2982 transitions. [2021-12-19 19:17:01,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:01,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:01,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2982 transitions. [2021-12-19 19:17:01,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,041 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-12-19 19:17:01,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2982 transitions. [2021-12-19 19:17:01,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:01,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2982 transitions. [2021-12-19 19:17:01,063 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-12-19 19:17:01,063 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2021-12-19 19:17:01,063 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:01,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2982 transitions. [2021-12-19 19:17:01,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,069 INFO L791 eck$LassoCheckResult]: Stem: 45431#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45163#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45164#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46554#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 46555#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45350#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45351#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45385#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46222#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46223#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46335#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46336#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46372#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45694#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45695#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46276#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46542#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 46432#L1286-2 assume !(0 == ~T1_E~0); 45078#L1291-1 assume !(0 == ~T2_E~0); 45079#L1296-1 assume !(0 == ~T3_E~0); 45784#L1301-1 assume !(0 == ~T4_E~0); 45785#L1306-1 assume !(0 == ~T5_E~0); 46285#L1311-1 assume !(0 == ~T6_E~0); 45038#L1316-1 assume !(0 == ~T7_E~0); 45039#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45804#L1326-1 assume !(0 == ~T9_E~0); 44853#L1331-1 assume !(0 == ~T10_E~0); 44559#L1336-1 assume !(0 == ~T11_E~0); 44560#L1341-1 assume !(0 == ~T12_E~0); 44611#L1346-1 assume !(0 == ~T13_E~0); 44612#L1351-1 assume !(0 == ~E_M~0); 44985#L1356-1 assume !(0 == ~E_1~0); 44986#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46505#L1366-1 assume !(0 == ~E_3~0); 45031#L1371-1 assume !(0 == ~E_4~0); 45032#L1376-1 assume !(0 == ~E_5~0); 45845#L1381-1 assume !(0 == ~E_6~0); 45846#L1386-1 assume !(0 == ~E_7~0); 46533#L1391-1 assume !(0 == ~E_8~0); 46546#L1396-1 assume !(0 == ~E_9~0); 45728#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 45729#L1406-1 assume !(0 == ~E_11~0); 46031#L1411-1 assume !(0 == ~E_12~0); 46032#L1416-1 assume !(0 == ~E_13~0); 45652#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45490#L635 assume !(1 == ~m_pc~0); 44629#L635-2 is_master_triggered_~__retres1~0#1 := 0; 44630#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44980#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45616#L1598 assume !(0 != activate_threads_~tmp~1#1); 44808#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44809#L654 assume 1 == ~t1_pc~0; 45514#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45515#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46530#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45596#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 45597#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44856#L673 assume 1 == ~t2_pc~0; 44857#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46001#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46002#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46560#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 46567#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45675#L692 assume !(1 == ~t3_pc~0); 45492#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45493#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45352#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45320#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45321#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44881#L711 assume 1 == ~t4_pc~0; 44882#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45365#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45822#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44584#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 44585#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46553#L730 assume !(1 == ~t5_pc~0); 45935#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44763#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44764#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44891#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 44892#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45234#L749 assume 1 == ~t6_pc~0; 45008#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44768#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45200#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45201#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 45423#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44564#L768 assume !(1 == ~t7_pc~0); 44565#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45869#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44801#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44802#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 45888#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45040#L787 assume 1 == ~t8_pc~0; 45041#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46236#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46400#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46401#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 44609#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44610#L806 assume 1 == ~t9_pc~0; 46247#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44644#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44645#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44893#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 44894#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46230#L825 assume !(1 == ~t10_pc~0); 46231#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45836#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45837#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44981#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44982#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45565#L844 assume 1 == ~t11_pc~0; 45255#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45256#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45622#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45623#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 46218#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46219#L863 assume !(1 == ~t12_pc~0); 44744#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44743#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46310#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 46311#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45689#L882 assume 1 == ~t13_pc~0; 45690#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45974#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46475#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46278#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 45961#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45962#L1434 assume !(1 == ~M_E~0); 46483#L1434-2 assume !(1 == ~T1_E~0); 46559#L1439-1 assume !(1 == ~T2_E~0); 44874#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44875#L1449-1 assume !(1 == ~T4_E~0); 45317#L1454-1 assume !(1 == ~T5_E~0); 45318#L1459-1 assume !(1 == ~T6_E~0); 45889#L1464-1 assume !(1 == ~T7_E~0); 45890#L1469-1 assume !(1 == ~T8_E~0); 45975#L1474-1 assume !(1 == ~T9_E~0); 45653#L1479-1 assume !(1 == ~T10_E~0); 45654#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45897#L1489-1 assume !(1 == ~T12_E~0); 45531#L1494-1 assume !(1 == ~T13_E~0); 45532#L1499-1 assume !(1 == ~E_M~0); 45713#L1504-1 assume !(1 == ~E_1~0); 45714#L1509-1 assume !(1 == ~E_2~0); 46327#L1514-1 assume !(1 == ~E_3~0); 46012#L1519-1 assume !(1 == ~E_4~0); 46013#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46517#L1529-1 assume !(1 == ~E_6~0); 46518#L1534-1 assume !(1 == ~E_7~0); 44664#L1539-1 assume !(1 == ~E_8~0); 44665#L1544-1 assume !(1 == ~E_9~0); 45095#L1549-1 assume !(1 == ~E_10~0); 46495#L1554-1 assume !(1 == ~E_11~0); 46493#L1559-1 assume !(1 == ~E_12~0); 46355#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46356#L1569-1 assume { :end_inline_reset_delta_events } true; 46511#L1935-2 [2021-12-19 19:17:01,070 INFO L793 eck$LassoCheckResult]: Loop: 46511#L1935-2 assume !false; 44673#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44674#L1261 assume !false; 45901#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45902#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44804#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44974#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44975#L1074 assume !(0 != eval_~tmp~0#1); 45332#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45930#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46331#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46387#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46106#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46107#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46543#L1301-3 assume !(0 == ~T4_E~0); 46501#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45609#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44908#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44909#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45014#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45750#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46015#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46016#L1341-3 assume !(0 == ~T12_E~0); 45310#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45301#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45245#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45246#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45826#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44599#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44600#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46342#L1381-3 assume !(0 == ~E_6~0); 46191#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46192#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46373#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46374#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44979#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44810#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44811#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45438#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44688#L635-45 assume 1 == ~m_pc~0; 44689#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45483#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45963#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46217#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44997#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44998#L654-45 assume 1 == ~t1_pc~0; 45818#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46166#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44651#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44652#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44677#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45504#L673-45 assume !(1 == ~t2_pc~0); 45505#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45829#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45830#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46455#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 46275#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45122#L692-45 assume !(1 == ~t3_pc~0); 44848#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 44849#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45893#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45176#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45177#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45489#L711-45 assume 1 == ~t4_pc~0; 45613#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45614#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45466#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45467#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45870#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45021#L730-45 assume 1 == ~t5_pc~0; 44859#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44860#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45269#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45270#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46021#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44832#L749-45 assume !(1 == ~t6_pc~0); 44833#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 46233#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45996#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45997#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46148#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45148#L768-45 assume 1 == ~t7_pc~0; 45149#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45288#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46092#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46093#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46132#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46133#L787-45 assume 1 == ~t8_pc~0; 46301#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45294#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45295#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45711#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45712#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46020#L806-45 assume 1 == ~t9_pc~0; 46496#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44708#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45533#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45361#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45273#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45274#L825-45 assume !(1 == ~t10_pc~0); 45797#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 45798#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45903#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45904#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46056#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44916#L844-45 assume !(1 == ~t11_pc~0); 44917#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45439#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45440#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45456#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 45867#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44956#L863-45 assume 1 == ~t12_pc~0; 44957#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44557#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44558#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45073#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45074#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45873#L882-45 assume 1 == ~t13_pc~0; 46227#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44576#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44577#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45185#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46364#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45980#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45981#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46165#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44870#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44871#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45033#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45970#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45971#L1464-3 assume !(1 == ~T7_E~0); 46417#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46344#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46345#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46419#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45611#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45612#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46272#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45907#L1504-3 assume !(1 == ~E_1~0); 45908#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46353#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46393#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45534#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45535#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46440#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45835#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45289#L1544-3 assume !(1 == ~E_9~0); 45290#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45805#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44921#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44922#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46071#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46072#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44806#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45371#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46042#L1954 assume !(0 == start_simulation_~tmp~3#1); 46044#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46294#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45089#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46130#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46260#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46261#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46351#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46413#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 46511#L1935-2 [2021-12-19 19:17:01,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2021-12-19 19:17:01,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226147294] [2021-12-19 19:17:01,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,071 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226147294] [2021-12-19 19:17:01,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226147294] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,100 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063594191] [2021-12-19 19:17:01,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,101 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,102 INFO L85 PathProgramCache]: Analyzing trace with hash -1257801565, now seen corresponding path program 1 times [2021-12-19 19:17:01,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962164702] [2021-12-19 19:17:01,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962164702] [2021-12-19 19:17:01,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962164702] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,133 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,133 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,133 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888335646] [2021-12-19 19:17:01,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,133 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:01,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:01,134 INFO L87 Difference]: Start difference. First operand 2021 states and 2982 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,155 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2021-12-19 19:17:01,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:01,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2981 transitions. [2021-12-19 19:17:01,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2981 transitions. [2021-12-19 19:17:01,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:01,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:01,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2981 transitions. [2021-12-19 19:17:01,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,169 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-12-19 19:17:01,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2981 transitions. [2021-12-19 19:17:01,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:01,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2981 transitions. [2021-12-19 19:17:01,191 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-12-19 19:17:01,192 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2021-12-19 19:17:01,192 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:01,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2981 transitions. [2021-12-19 19:17:01,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,198 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,198 INFO L791 eck$LassoCheckResult]: Stem: 49480#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49212#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49213#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50603#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 50604#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49399#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49400#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49434#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50271#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50272#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50384#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50385#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49218#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49219#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50421#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49743#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49744#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50325#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50591#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 50481#L1286-2 assume !(0 == ~T1_E~0); 49127#L1291-1 assume !(0 == ~T2_E~0); 49128#L1296-1 assume !(0 == ~T3_E~0); 49833#L1301-1 assume !(0 == ~T4_E~0); 49834#L1306-1 assume !(0 == ~T5_E~0); 50334#L1311-1 assume !(0 == ~T6_E~0); 49087#L1316-1 assume !(0 == ~T7_E~0); 49088#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49853#L1326-1 assume !(0 == ~T9_E~0); 48902#L1331-1 assume !(0 == ~T10_E~0); 48608#L1336-1 assume !(0 == ~T11_E~0); 48609#L1341-1 assume !(0 == ~T12_E~0); 48660#L1346-1 assume !(0 == ~T13_E~0); 48661#L1351-1 assume !(0 == ~E_M~0); 49034#L1356-1 assume !(0 == ~E_1~0); 49035#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50554#L1366-1 assume !(0 == ~E_3~0); 49080#L1371-1 assume !(0 == ~E_4~0); 49081#L1376-1 assume !(0 == ~E_5~0); 49894#L1381-1 assume !(0 == ~E_6~0); 49895#L1386-1 assume !(0 == ~E_7~0); 50582#L1391-1 assume !(0 == ~E_8~0); 50595#L1396-1 assume !(0 == ~E_9~0); 49777#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 49778#L1406-1 assume !(0 == ~E_11~0); 50080#L1411-1 assume !(0 == ~E_12~0); 50081#L1416-1 assume !(0 == ~E_13~0); 49701#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49539#L635 assume !(1 == ~m_pc~0); 48678#L635-2 is_master_triggered_~__retres1~0#1 := 0; 48679#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49029#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49665#L1598 assume !(0 != activate_threads_~tmp~1#1); 48857#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48858#L654 assume 1 == ~t1_pc~0; 49563#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49564#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50579#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49645#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 49646#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48905#L673 assume 1 == ~t2_pc~0; 48906#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50050#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50051#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50609#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 50616#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49724#L692 assume !(1 == ~t3_pc~0); 49541#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49542#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49401#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49369#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49370#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48930#L711 assume 1 == ~t4_pc~0; 48931#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49414#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49871#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48633#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 48634#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50602#L730 assume !(1 == ~t5_pc~0); 49984#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48812#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48813#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48940#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 48941#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49283#L749 assume 1 == ~t6_pc~0; 49057#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48817#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49249#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49250#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 49472#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48613#L768 assume !(1 == ~t7_pc~0); 48614#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49918#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48850#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48851#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 49937#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49089#L787 assume 1 == ~t8_pc~0; 49090#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50285#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50449#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50450#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 48658#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48659#L806 assume 1 == ~t9_pc~0; 50296#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48693#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48694#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48942#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 48943#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50279#L825 assume !(1 == ~t10_pc~0); 50280#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49885#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49886#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49030#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49031#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49614#L844 assume 1 == ~t11_pc~0; 49304#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49305#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49671#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49672#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 50267#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50268#L863 assume !(1 == ~t12_pc~0); 48793#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 48792#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49020#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50359#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 50360#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49738#L882 assume 1 == ~t13_pc~0; 49739#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50023#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50524#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50327#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 50010#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50011#L1434 assume !(1 == ~M_E~0); 50532#L1434-2 assume !(1 == ~T1_E~0); 50608#L1439-1 assume !(1 == ~T2_E~0); 48923#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48924#L1449-1 assume !(1 == ~T4_E~0); 49366#L1454-1 assume !(1 == ~T5_E~0); 49367#L1459-1 assume !(1 == ~T6_E~0); 49938#L1464-1 assume !(1 == ~T7_E~0); 49939#L1469-1 assume !(1 == ~T8_E~0); 50024#L1474-1 assume !(1 == ~T9_E~0); 49702#L1479-1 assume !(1 == ~T10_E~0); 49703#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49946#L1489-1 assume !(1 == ~T12_E~0); 49580#L1494-1 assume !(1 == ~T13_E~0); 49581#L1499-1 assume !(1 == ~E_M~0); 49762#L1504-1 assume !(1 == ~E_1~0); 49763#L1509-1 assume !(1 == ~E_2~0); 50376#L1514-1 assume !(1 == ~E_3~0); 50061#L1519-1 assume !(1 == ~E_4~0); 50062#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50566#L1529-1 assume !(1 == ~E_6~0); 50567#L1534-1 assume !(1 == ~E_7~0); 48713#L1539-1 assume !(1 == ~E_8~0); 48714#L1544-1 assume !(1 == ~E_9~0); 49144#L1549-1 assume !(1 == ~E_10~0); 50544#L1554-1 assume !(1 == ~E_11~0); 50542#L1559-1 assume !(1 == ~E_12~0); 50404#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50405#L1569-1 assume { :end_inline_reset_delta_events } true; 50560#L1935-2 [2021-12-19 19:17:01,199 INFO L793 eck$LassoCheckResult]: Loop: 50560#L1935-2 assume !false; 48722#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48723#L1261 assume !false; 49950#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49951#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48853#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49023#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49024#L1074 assume !(0 != eval_~tmp~0#1); 49381#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49979#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50380#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50436#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50155#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50156#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50592#L1301-3 assume !(0 == ~T4_E~0); 50550#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49658#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48957#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48958#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49063#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49799#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50064#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50065#L1341-3 assume !(0 == ~T12_E~0); 49359#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49350#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49294#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49295#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49875#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48648#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48649#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50391#L1381-3 assume !(0 == ~E_6~0); 50240#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50241#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50422#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50423#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49028#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48859#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48860#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49487#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48737#L635-45 assume 1 == ~m_pc~0; 48738#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49532#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50012#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50266#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49046#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49047#L654-45 assume 1 == ~t1_pc~0; 49867#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50215#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48700#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48701#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48726#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49553#L673-45 assume !(1 == ~t2_pc~0); 49554#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49878#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49879#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50504#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 50324#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49171#L692-45 assume !(1 == ~t3_pc~0); 48897#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 48898#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49942#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49225#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49226#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49538#L711-45 assume !(1 == ~t4_pc~0); 49664#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 49663#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49515#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49516#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49919#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49070#L730-45 assume 1 == ~t5_pc~0; 48908#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48909#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49318#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49319#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50070#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48881#L749-45 assume !(1 == ~t6_pc~0); 48882#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 50282#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50045#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50046#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50197#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49197#L768-45 assume 1 == ~t7_pc~0; 49198#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49337#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50141#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50142#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50181#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50182#L787-45 assume 1 == ~t8_pc~0; 50350#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49343#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49344#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49760#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49761#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50069#L806-45 assume 1 == ~t9_pc~0; 50545#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48757#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49582#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49410#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49322#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49323#L825-45 assume !(1 == ~t10_pc~0); 49846#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 49847#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49952#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49953#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50105#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48965#L844-45 assume !(1 == ~t11_pc~0); 48966#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49488#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49489#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49505#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 49916#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49005#L863-45 assume 1 == ~t12_pc~0; 49006#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48606#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48607#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49122#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49123#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49922#L882-45 assume 1 == ~t13_pc~0; 50276#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 48625#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48626#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49234#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50413#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50029#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50030#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50214#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48919#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48920#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49082#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50019#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50020#L1464-3 assume !(1 == ~T7_E~0); 50466#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50393#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50394#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50468#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49660#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49661#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50321#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49956#L1504-3 assume !(1 == ~E_1~0); 49957#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50402#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50442#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49583#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49584#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50489#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49884#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49338#L1544-3 assume !(1 == ~E_9~0); 49339#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49854#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48970#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48971#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50120#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50121#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48855#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49420#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50091#L1954 assume !(0 == start_simulation_~tmp~3#1); 50093#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50343#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49138#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50179#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50309#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50310#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50400#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50462#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 50560#L1935-2 [2021-12-19 19:17:01,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,200 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2021-12-19 19:17:01,200 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,200 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656844399] [2021-12-19 19:17:01,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,223 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656844399] [2021-12-19 19:17:01,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656844399] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735835337] [2021-12-19 19:17:01,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,225 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,225 INFO L85 PathProgramCache]: Analyzing trace with hash 2007173988, now seen corresponding path program 1 times [2021-12-19 19:17:01,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857321090] [2021-12-19 19:17:01,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857321090] [2021-12-19 19:17:01,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857321090] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,252 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302909657] [2021-12-19 19:17:01,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,253 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,253 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:01,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:01,254 INFO L87 Difference]: Start difference. First operand 2021 states and 2981 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,274 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2021-12-19 19:17:01,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:01,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2980 transitions. [2021-12-19 19:17:01,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2980 transitions. [2021-12-19 19:17:01,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2021-12-19 19:17:01,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2021-12-19 19:17:01,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2980 transitions. [2021-12-19 19:17:01,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,328 INFO L681 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-12-19 19:17:01,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2980 transitions. [2021-12-19 19:17:01,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2021-12-19 19:17:01,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2980 transitions. [2021-12-19 19:17:01,353 INFO L704 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-12-19 19:17:01,353 INFO L587 BuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2021-12-19 19:17:01,353 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:01,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2980 transitions. [2021-12-19 19:17:01,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2021-12-19 19:17:01,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,359 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,359 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,360 INFO L791 eck$LassoCheckResult]: Stem: 53529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53261#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53262#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54652#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 54653#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53448#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53449#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53483#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54320#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54321#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54433#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54434#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53267#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53268#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54470#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53792#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53793#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54374#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54640#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 54530#L1286-2 assume !(0 == ~T1_E~0); 53176#L1291-1 assume !(0 == ~T2_E~0); 53177#L1296-1 assume !(0 == ~T3_E~0); 53882#L1301-1 assume !(0 == ~T4_E~0); 53883#L1306-1 assume !(0 == ~T5_E~0); 54383#L1311-1 assume !(0 == ~T6_E~0); 53136#L1316-1 assume !(0 == ~T7_E~0); 53137#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53902#L1326-1 assume !(0 == ~T9_E~0); 52951#L1331-1 assume !(0 == ~T10_E~0); 52657#L1336-1 assume !(0 == ~T11_E~0); 52658#L1341-1 assume !(0 == ~T12_E~0); 52709#L1346-1 assume !(0 == ~T13_E~0); 52710#L1351-1 assume !(0 == ~E_M~0); 53083#L1356-1 assume !(0 == ~E_1~0); 53084#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54603#L1366-1 assume !(0 == ~E_3~0); 53129#L1371-1 assume !(0 == ~E_4~0); 53130#L1376-1 assume !(0 == ~E_5~0); 53943#L1381-1 assume !(0 == ~E_6~0); 53944#L1386-1 assume !(0 == ~E_7~0); 54631#L1391-1 assume !(0 == ~E_8~0); 54644#L1396-1 assume !(0 == ~E_9~0); 53826#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 53827#L1406-1 assume !(0 == ~E_11~0); 54129#L1411-1 assume !(0 == ~E_12~0); 54130#L1416-1 assume !(0 == ~E_13~0); 53750#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53588#L635 assume !(1 == ~m_pc~0); 52727#L635-2 is_master_triggered_~__retres1~0#1 := 0; 52728#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53078#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53714#L1598 assume !(0 != activate_threads_~tmp~1#1); 52906#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52907#L654 assume 1 == ~t1_pc~0; 53612#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53613#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54628#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53694#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 53695#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52954#L673 assume 1 == ~t2_pc~0; 52955#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54099#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54100#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54658#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 54665#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53773#L692 assume !(1 == ~t3_pc~0); 53590#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53591#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53450#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53418#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53419#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52979#L711 assume 1 == ~t4_pc~0; 52980#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53463#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53920#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52682#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 52683#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54651#L730 assume !(1 == ~t5_pc~0); 54033#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52861#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52862#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52989#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 52990#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53332#L749 assume 1 == ~t6_pc~0; 53106#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52866#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53298#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53299#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 53521#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52662#L768 assume !(1 == ~t7_pc~0); 52663#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53967#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52899#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52900#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 53986#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53138#L787 assume 1 == ~t8_pc~0; 53139#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54334#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54498#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54499#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 52707#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52708#L806 assume 1 == ~t9_pc~0; 54345#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52742#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52743#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52991#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 52992#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54328#L825 assume !(1 == ~t10_pc~0); 54329#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53934#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53935#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53079#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53080#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53663#L844 assume 1 == ~t11_pc~0; 53353#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53354#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53720#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53721#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 54316#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54317#L863 assume !(1 == ~t12_pc~0); 52842#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52841#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53069#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54408#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 54409#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53787#L882 assume 1 == ~t13_pc~0; 53788#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54072#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54573#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54376#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 54059#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54060#L1434 assume !(1 == ~M_E~0); 54581#L1434-2 assume !(1 == ~T1_E~0); 54657#L1439-1 assume !(1 == ~T2_E~0); 52972#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52973#L1449-1 assume !(1 == ~T4_E~0); 53415#L1454-1 assume !(1 == ~T5_E~0); 53416#L1459-1 assume !(1 == ~T6_E~0); 53987#L1464-1 assume !(1 == ~T7_E~0); 53988#L1469-1 assume !(1 == ~T8_E~0); 54073#L1474-1 assume !(1 == ~T9_E~0); 53751#L1479-1 assume !(1 == ~T10_E~0); 53752#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53995#L1489-1 assume !(1 == ~T12_E~0); 53629#L1494-1 assume !(1 == ~T13_E~0); 53630#L1499-1 assume !(1 == ~E_M~0); 53811#L1504-1 assume !(1 == ~E_1~0); 53812#L1509-1 assume !(1 == ~E_2~0); 54425#L1514-1 assume !(1 == ~E_3~0); 54110#L1519-1 assume !(1 == ~E_4~0); 54111#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54615#L1529-1 assume !(1 == ~E_6~0); 54616#L1534-1 assume !(1 == ~E_7~0); 52762#L1539-1 assume !(1 == ~E_8~0); 52763#L1544-1 assume !(1 == ~E_9~0); 53193#L1549-1 assume !(1 == ~E_10~0); 54593#L1554-1 assume !(1 == ~E_11~0); 54591#L1559-1 assume !(1 == ~E_12~0); 54453#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54454#L1569-1 assume { :end_inline_reset_delta_events } true; 54609#L1935-2 [2021-12-19 19:17:01,360 INFO L793 eck$LassoCheckResult]: Loop: 54609#L1935-2 assume !false; 52771#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52772#L1261 assume !false; 53999#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54000#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52902#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53072#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53073#L1074 assume !(0 != eval_~tmp~0#1); 53430#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54028#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54429#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54485#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54204#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54205#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54641#L1301-3 assume !(0 == ~T4_E~0); 54599#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53707#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53006#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53007#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53112#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53848#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54113#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54114#L1341-3 assume !(0 == ~T12_E~0); 53408#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53399#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53343#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53344#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53924#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52697#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52698#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54440#L1381-3 assume !(0 == ~E_6~0); 54289#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54290#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54471#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54472#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53077#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52908#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52909#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53536#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52786#L635-45 assume 1 == ~m_pc~0; 52787#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53581#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54061#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54315#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53095#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53096#L654-45 assume 1 == ~t1_pc~0; 53916#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54264#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52749#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52750#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52775#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53602#L673-45 assume !(1 == ~t2_pc~0); 53603#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53927#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53928#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54553#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 54373#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53220#L692-45 assume !(1 == ~t3_pc~0); 52946#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 52947#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53991#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53274#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53275#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53587#L711-45 assume !(1 == ~t4_pc~0); 53713#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53712#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53564#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53565#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53968#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53119#L730-45 assume 1 == ~t5_pc~0; 52957#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52958#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53367#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53368#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54119#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52930#L749-45 assume !(1 == ~t6_pc~0); 52931#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54331#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54094#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54095#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54246#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53246#L768-45 assume !(1 == ~t7_pc~0); 53248#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53386#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54190#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54191#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54230#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54231#L787-45 assume !(1 == ~t8_pc~0); 54400#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 53392#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53393#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53809#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53810#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54118#L806-45 assume 1 == ~t9_pc~0; 54594#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52806#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53631#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53459#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53371#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53372#L825-45 assume !(1 == ~t10_pc~0); 53895#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 53896#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54001#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54002#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54154#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53014#L844-45 assume !(1 == ~t11_pc~0); 53015#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53537#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53538#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53554#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 53965#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53054#L863-45 assume !(1 == ~t12_pc~0); 53056#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 52655#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52656#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53171#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53172#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53971#L882-45 assume 1 == ~t13_pc~0; 54325#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 52674#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52675#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53283#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54462#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54078#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54079#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54263#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52968#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52969#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53131#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54068#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54069#L1464-3 assume !(1 == ~T7_E~0); 54515#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54442#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54443#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54517#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53709#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53710#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54370#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54005#L1504-3 assume !(1 == ~E_1~0); 54006#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54451#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54491#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53632#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53633#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54538#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53933#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53387#L1544-3 assume !(1 == ~E_9~0); 53388#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53903#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53019#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53020#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54169#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54170#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52904#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53469#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54140#L1954 assume !(0 == start_simulation_~tmp~3#1); 54142#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54392#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53187#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54228#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54358#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54359#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54449#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54511#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 54609#L1935-2 [2021-12-19 19:17:01,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,362 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2021-12-19 19:17:01,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564228741] [2021-12-19 19:17:01,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564228741] [2021-12-19 19:17:01,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564228741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,392 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:01,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688116784] [2021-12-19 19:17:01,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,394 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1509066009, now seen corresponding path program 1 times [2021-12-19 19:17:01,394 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464460996] [2021-12-19 19:17:01,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,425 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,425 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464460996] [2021-12-19 19:17:01,425 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464460996] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,425 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,425 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,425 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287912421] [2021-12-19 19:17:01,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,426 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,426 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:01,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:01,426 INFO L87 Difference]: Start difference. First operand 2021 states and 2980 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,474 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2021-12-19 19:17:01,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:01,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3767 states and 5538 transitions. [2021-12-19 19:17:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:01,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3767 states to 3767 states and 5538 transitions. [2021-12-19 19:17:01,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3767 [2021-12-19 19:17:01,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3767 [2021-12-19 19:17:01,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3767 states and 5538 transitions. [2021-12-19 19:17:01,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,498 INFO L681 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-12-19 19:17:01,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states and 5538 transitions. [2021-12-19 19:17:01,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3767. [2021-12-19 19:17:01,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5538 transitions. [2021-12-19 19:17:01,553 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-12-19 19:17:01,553 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2021-12-19 19:17:01,553 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:01,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5538 transitions. [2021-12-19 19:17:01,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:01,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,565 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,566 INFO L791 eck$LassoCheckResult]: Stem: 59327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 59056#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59057#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60502#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 60503#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59244#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59245#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59279#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60128#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60129#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60246#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60247#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59062#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59063#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60286#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59590#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59591#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60185#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60487#L1286 assume !(0 == ~M_E~0); 60350#L1286-2 assume !(0 == ~T1_E~0); 58971#L1291-1 assume !(0 == ~T2_E~0); 58972#L1296-1 assume !(0 == ~T3_E~0); 59682#L1301-1 assume !(0 == ~T4_E~0); 59683#L1306-1 assume !(0 == ~T5_E~0); 60194#L1311-1 assume !(0 == ~T6_E~0); 58931#L1316-1 assume !(0 == ~T7_E~0); 58932#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59702#L1326-1 assume !(0 == ~T9_E~0); 58746#L1331-1 assume !(0 == ~T10_E~0); 58452#L1336-1 assume !(0 == ~T11_E~0); 58453#L1341-1 assume !(0 == ~T12_E~0); 58504#L1346-1 assume !(0 == ~T13_E~0); 58505#L1351-1 assume !(0 == ~E_M~0); 58878#L1356-1 assume !(0 == ~E_1~0); 58879#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60437#L1366-1 assume !(0 == ~E_3~0); 58924#L1371-1 assume !(0 == ~E_4~0); 58925#L1376-1 assume !(0 == ~E_5~0); 59745#L1381-1 assume !(0 == ~E_6~0); 59746#L1386-1 assume !(0 == ~E_7~0); 60475#L1391-1 assume !(0 == ~E_8~0); 60493#L1396-1 assume !(0 == ~E_9~0); 59624#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59625#L1406-1 assume !(0 == ~E_11~0); 59933#L1411-1 assume !(0 == ~E_12~0); 59934#L1416-1 assume !(0 == ~E_13~0); 59548#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59386#L635 assume !(1 == ~m_pc~0); 58522#L635-2 is_master_triggered_~__retres1~0#1 := 0; 58523#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58875#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59512#L1598 assume !(0 != activate_threads_~tmp~1#1); 58701#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58702#L654 assume 1 == ~t1_pc~0; 59410#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59411#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60471#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59492#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 59493#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58752#L673 assume 1 == ~t2_pc~0; 58753#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59902#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59903#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60508#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 60516#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59571#L692 assume !(1 == ~t3_pc~0); 59388#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59389#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59248#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59213#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59214#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58774#L711 assume 1 == ~t4_pc~0; 58775#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59259#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59720#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58477#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 58478#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60501#L730 assume !(1 == ~t5_pc~0); 59836#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58656#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58657#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58784#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 58785#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59127#L749 assume 1 == ~t6_pc~0; 58901#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58664#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59093#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59094#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 59319#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58459#L768 assume !(1 == ~t7_pc~0); 58460#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59769#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58694#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58695#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 59788#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58933#L787 assume 1 == ~t8_pc~0; 58934#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60145#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60315#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60316#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 58502#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58503#L806 assume 1 == ~t9_pc~0; 60156#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58537#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58538#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58786#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 58787#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60139#L825 assume !(1 == ~t10_pc~0); 60140#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59735#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59736#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58876#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58877#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59461#L844 assume 1 == ~t11_pc~0; 59150#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59151#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59518#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59519#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 60124#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60125#L863 assume !(1 == ~t12_pc~0); 58639#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58638#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58864#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60221#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 60222#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59585#L882 assume 1 == ~t13_pc~0; 59586#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59875#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60397#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60187#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 59862#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59863#L1434 assume !(1 == ~M_E~0); 60410#L1434-2 assume !(1 == ~T1_E~0); 60507#L1439-1 assume !(1 == ~T2_E~0); 58767#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58768#L1449-1 assume !(1 == ~T4_E~0); 59211#L1454-1 assume !(1 == ~T5_E~0); 59212#L1459-1 assume !(1 == ~T6_E~0); 59789#L1464-1 assume !(1 == ~T7_E~0); 59790#L1469-1 assume !(1 == ~T8_E~0); 59876#L1474-1 assume !(1 == ~T9_E~0); 59549#L1479-1 assume !(1 == ~T10_E~0); 59550#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59797#L1489-1 assume !(1 == ~T12_E~0); 59427#L1494-1 assume !(1 == ~T13_E~0); 59428#L1499-1 assume !(1 == ~E_M~0); 59609#L1504-1 assume !(1 == ~E_1~0); 59610#L1509-1 assume !(1 == ~E_2~0); 60238#L1514-1 assume !(1 == ~E_3~0); 59913#L1519-1 assume !(1 == ~E_4~0); 59914#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60456#L1529-1 assume !(1 == ~E_6~0); 60457#L1534-1 assume !(1 == ~E_7~0); 58557#L1539-1 assume !(1 == ~E_8~0); 58558#L1544-1 assume !(1 == ~E_9~0); 58988#L1549-1 assume !(1 == ~E_10~0); 60425#L1554-1 assume !(1 == ~E_11~0); 60423#L1559-1 assume !(1 == ~E_12~0); 60269#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60270#L1569-1 assume { :end_inline_reset_delta_events } true; 60449#L1935-2 [2021-12-19 19:17:01,566 INFO L793 eck$LassoCheckResult]: Loop: 60449#L1935-2 assume !false; 60556#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60469#L1261 assume !false; 59804#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59805#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58697#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58868#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58869#L1074 assume !(0 != eval_~tmp~0#1); 59225#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59831#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60242#L1286-3 assume !(0 == ~M_E~0); 60303#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62201#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62200#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62199#L1301-3 assume !(0 == ~T4_E~0); 62198#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62197#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62196#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62195#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62194#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62193#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62192#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62191#L1341-3 assume !(0 == ~T12_E~0); 62190#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62189#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62188#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62187#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62186#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62185#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62184#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62183#L1381-3 assume !(0 == ~E_6~0); 62182#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62181#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62180#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62179#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62178#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62177#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62176#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62175#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62174#L635-45 assume 1 == ~m_pc~0; 62172#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62171#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62170#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62169#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62168#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62167#L654-45 assume !(1 == ~t1_pc~0); 62165#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 62164#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62163#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62161#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62160#L673-45 assume 1 == ~t2_pc~0; 62158#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62157#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62156#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62155#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 62154#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62153#L692-45 assume 1 == ~t3_pc~0; 62151#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62150#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62149#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62148#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62147#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62146#L711-45 assume 1 == ~t4_pc~0; 62144#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62143#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62142#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62141#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62140#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62139#L730-45 assume 1 == ~t5_pc~0; 62137#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62136#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62135#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62134#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62133#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62132#L749-45 assume !(1 == ~t6_pc~0); 62130#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62129#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62128#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62127#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62126#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62125#L768-45 assume 1 == ~t7_pc~0; 62123#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62122#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62121#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62120#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62119#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62118#L787-45 assume !(1 == ~t8_pc~0); 62116#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 62115#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62114#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62113#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62112#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62111#L806-45 assume 1 == ~t9_pc~0; 62109#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62108#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62107#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62106#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61679#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61678#L825-45 assume !(1 == ~t10_pc~0); 61676#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61675#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61674#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61673#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61672#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61671#L844-45 assume 1 == ~t11_pc~0; 61669#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61668#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61667#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61666#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 61665#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61664#L863-45 assume 1 == ~t12_pc~0; 61662#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61661#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61660#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61659#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61658#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61657#L882-45 assume !(1 == ~t13_pc~0); 61655#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 61654#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61653#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61652#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 61651#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59881#L1434-3 assume !(1 == ~M_E~0); 59882#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60069#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58763#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58764#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58926#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59871#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59872#L1464-3 assume !(1 == ~T7_E~0); 60335#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60255#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60256#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60337#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59507#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59508#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 60181#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59808#L1504-3 assume !(1 == ~E_1~0); 59809#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60265#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60307#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59430#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59431#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60358#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59731#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59182#L1544-3 assume !(1 == ~E_9~0); 59183#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59703#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58814#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58815#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60201#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61482#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61472#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61471#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61470#L1954 assume !(0 == start_simulation_~tmp~3#1); 61467#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60843#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60626#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60587#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60579#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60573#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60565#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 60449#L1935-2 [2021-12-19 19:17:01,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,567 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2021-12-19 19:17:01,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128297226] [2021-12-19 19:17:01,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128297226] [2021-12-19 19:17:01,596 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128297226] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,596 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478120475] [2021-12-19 19:17:01,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,596 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,597 INFO L85 PathProgramCache]: Analyzing trace with hash 627302755, now seen corresponding path program 1 times [2021-12-19 19:17:01,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842673392] [2021-12-19 19:17:01,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,623 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,623 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842673392] [2021-12-19 19:17:01,623 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842673392] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,624 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,624 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,624 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137993912] [2021-12-19 19:17:01,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,624 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,625 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:01,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:01,625 INFO L87 Difference]: Start difference. First operand 3767 states and 5538 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,712 INFO L93 Difference]: Finished difference Result 5505 states and 8078 transitions. [2021-12-19 19:17:01,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:01,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5505 states and 8078 transitions. [2021-12-19 19:17:01,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5310 [2021-12-19 19:17:01,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5505 states to 5505 states and 8078 transitions. [2021-12-19 19:17:01,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5505 [2021-12-19 19:17:01,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5505 [2021-12-19 19:17:01,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5505 states and 8078 transitions. [2021-12-19 19:17:01,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:01,797 INFO L681 BuchiCegarLoop]: Abstraction has 5505 states and 8078 transitions. [2021-12-19 19:17:01,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5505 states and 8078 transitions. [2021-12-19 19:17:01,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5505 to 3767. [2021-12-19 19:17:01,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.469338996548978) internal successors, (5535), 3766 states have internal predecessors, (5535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5535 transitions. [2021-12-19 19:17:01,853 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5535 transitions. [2021-12-19 19:17:01,853 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5535 transitions. [2021-12-19 19:17:01,853 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:01,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5535 transitions. [2021-12-19 19:17:01,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:01,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:01,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:01,863 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:01,864 INFO L791 eck$LassoCheckResult]: Stem: 68606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 68338#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68339#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69734#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 69735#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68525#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68526#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68560#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69397#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69398#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69512#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69513#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68344#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68345#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69549#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68869#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68870#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 69451#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69722#L1286 assume !(0 == ~M_E~0); 69609#L1286-2 assume !(0 == ~T1_E~0); 68253#L1291-1 assume !(0 == ~T2_E~0); 68254#L1296-1 assume !(0 == ~T3_E~0); 68960#L1301-1 assume !(0 == ~T4_E~0); 68961#L1306-1 assume !(0 == ~T5_E~0); 69460#L1311-1 assume !(0 == ~T6_E~0); 68213#L1316-1 assume !(0 == ~T7_E~0); 68214#L1321-1 assume !(0 == ~T8_E~0); 68979#L1326-1 assume !(0 == ~T9_E~0); 68028#L1331-1 assume !(0 == ~T10_E~0); 67734#L1336-1 assume !(0 == ~T11_E~0); 67735#L1341-1 assume !(0 == ~T12_E~0); 67786#L1346-1 assume !(0 == ~T13_E~0); 67787#L1351-1 assume !(0 == ~E_M~0); 68160#L1356-1 assume !(0 == ~E_1~0); 68161#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69685#L1366-1 assume !(0 == ~E_3~0); 68206#L1371-1 assume !(0 == ~E_4~0); 68207#L1376-1 assume !(0 == ~E_5~0); 69021#L1381-1 assume !(0 == ~E_6~0); 69022#L1386-1 assume !(0 == ~E_7~0); 69713#L1391-1 assume !(0 == ~E_8~0); 69726#L1396-1 assume !(0 == ~E_9~0); 68903#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 68904#L1406-1 assume !(0 == ~E_11~0); 69206#L1411-1 assume !(0 == ~E_12~0); 69207#L1416-1 assume !(0 == ~E_13~0); 68827#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68665#L635 assume !(1 == ~m_pc~0); 67806#L635-2 is_master_triggered_~__retres1~0#1 := 0; 67807#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68157#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68791#L1598 assume !(0 != activate_threads_~tmp~1#1); 67983#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67984#L654 assume 1 == ~t1_pc~0; 68689#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68690#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69710#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68771#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 68772#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68034#L673 assume 1 == ~t2_pc~0; 68035#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69176#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69177#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69740#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 69747#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68850#L692 assume !(1 == ~t3_pc~0); 68667#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68668#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68529#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68495#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68496#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68056#L711 assume 1 == ~t4_pc~0; 68057#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68540#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68997#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67759#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 67760#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69733#L730 assume !(1 == ~t5_pc~0); 69110#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 67938#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67939#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68066#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 68067#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68409#L749 assume 1 == ~t6_pc~0; 68183#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 67948#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68375#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68376#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 68598#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67741#L768 assume !(1 == ~t7_pc~0); 67742#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 69044#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67976#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67977#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 69063#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68215#L787 assume 1 == ~t8_pc~0; 68216#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69411#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69577#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69578#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 67784#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67785#L806 assume 1 == ~t9_pc~0; 69422#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 67819#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67820#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68068#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 68069#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69405#L825 assume !(1 == ~t10_pc~0); 69406#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 69011#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69012#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68158#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68159#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68740#L844 assume 1 == ~t11_pc~0; 68432#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68433#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68797#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68798#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 69393#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69394#L863 assume !(1 == ~t12_pc~0); 67923#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 67922#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68148#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69485#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 69486#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68864#L882 assume 1 == ~t13_pc~0; 68865#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69149#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69652#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69453#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 69136#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69137#L1434 assume !(1 == ~M_E~0); 69661#L1434-2 assume !(1 == ~T1_E~0); 69739#L1439-1 assume !(1 == ~T2_E~0); 68049#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68050#L1449-1 assume !(1 == ~T4_E~0); 68493#L1454-1 assume !(1 == ~T5_E~0); 68494#L1459-1 assume !(1 == ~T6_E~0); 69064#L1464-1 assume !(1 == ~T7_E~0); 69065#L1469-1 assume !(1 == ~T8_E~0); 69152#L1474-1 assume !(1 == ~T9_E~0); 68828#L1479-1 assume !(1 == ~T10_E~0); 68829#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69072#L1489-1 assume !(1 == ~T12_E~0); 68706#L1494-1 assume !(1 == ~T13_E~0); 68707#L1499-1 assume !(1 == ~E_M~0); 68888#L1504-1 assume !(1 == ~E_1~0); 68889#L1509-1 assume !(1 == ~E_2~0); 69502#L1514-1 assume !(1 == ~E_3~0); 69187#L1519-1 assume !(1 == ~E_4~0); 69188#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69697#L1529-1 assume !(1 == ~E_6~0); 69698#L1534-1 assume !(1 == ~E_7~0); 67841#L1539-1 assume !(1 == ~E_8~0); 67842#L1544-1 assume !(1 == ~E_9~0); 68270#L1549-1 assume !(1 == ~E_10~0); 69675#L1554-1 assume !(1 == ~E_11~0); 69673#L1559-1 assume !(1 == ~E_12~0); 69534#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 69535#L1569-1 assume { :end_inline_reset_delta_events } true; 69691#L1935-2 [2021-12-19 19:17:01,864 INFO L793 eck$LassoCheckResult]: Loop: 69691#L1935-2 assume !false; 67848#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67849#L1261 assume !false; 69078#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69079#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67979#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68149#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68150#L1074 assume !(0 != eval_~tmp~0#1); 68507#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69105#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69506#L1286-3 assume !(0 == ~M_E~0); 69566#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69282#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69283#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69723#L1301-3 assume !(0 == ~T4_E~0); 69681#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68784#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68083#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68084#L1321-3 assume !(0 == ~T8_E~0); 68189#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68925#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69190#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69191#L1341-3 assume !(0 == ~T12_E~0); 68485#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68476#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68420#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68421#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69001#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67774#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67775#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69519#L1381-3 assume !(0 == ~E_6~0); 69366#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69367#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69550#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69551#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68154#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67985#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 67986#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 68613#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67863#L635-45 assume !(1 == ~m_pc~0); 67865#L635-47 is_master_triggered_~__retres1~0#1 := 0; 68658#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69138#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69392#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68172#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68173#L654-45 assume 1 == ~t1_pc~0; 68993#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69341#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67826#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67827#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67852#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68679#L673-45 assume 1 == ~t2_pc~0; 68681#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69004#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69005#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69632#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 69450#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68297#L692-45 assume 1 == ~t3_pc~0; 68298#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68027#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69068#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68351#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68352#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68664#L711-45 assume 1 == ~t4_pc~0; 68788#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68789#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68642#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68643#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69046#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68196#L730-45 assume !(1 == ~t5_pc~0); 68033#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 68032#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68444#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68445#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69196#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68007#L749-45 assume 1 == ~t6_pc~0; 68009#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69408#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69171#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69172#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69323#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68323#L768-45 assume !(1 == ~t7_pc~0); 68325#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 68467#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69267#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69268#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69307#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69308#L787-45 assume !(1 == ~t8_pc~0); 69477#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68469#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68470#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68886#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68887#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69195#L806-45 assume !(1 == ~t9_pc~0); 67885#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 67886#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68708#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68536#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68448#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68449#L825-45 assume 1 == ~t10_pc~0; 69060#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68973#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69076#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69077#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69229#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68087#L844-45 assume 1 == ~t11_pc~0; 68089#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68614#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68615#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68631#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 69041#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68128#L863-45 assume 1 == ~t12_pc~0; 68129#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 67732#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67733#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68245#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68246#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69047#L882-45 assume !(1 == ~t13_pc~0); 68578#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 67751#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 67752#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 68360#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69541#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69155#L1434-3 assume !(1 == ~M_E~0); 69156#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69340#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68045#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68046#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68208#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69145#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69146#L1464-3 assume !(1 == ~T7_E~0); 69594#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69521#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69522#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69596#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68786#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68787#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 69447#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69080#L1504-3 assume !(1 == ~E_1~0); 69081#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69530#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69570#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68709#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68710#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69617#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69007#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68463#L1544-3 assume !(1 == ~E_9~0); 68464#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68980#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68096#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68097#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69246#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69247#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67981#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68546#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69217#L1954 assume !(0 == start_simulation_~tmp~3#1); 69219#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69469#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68264#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69305#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 69435#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69436#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69528#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69590#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 69691#L1935-2 [2021-12-19 19:17:01,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2021-12-19 19:17:01,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130650585] [2021-12-19 19:17:01,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130650585] [2021-12-19 19:17:01,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130650585] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:01,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610189776] [2021-12-19 19:17:01,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,894 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:01,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:01,895 INFO L85 PathProgramCache]: Analyzing trace with hash 771221602, now seen corresponding path program 1 times [2021-12-19 19:17:01,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:01,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804286491] [2021-12-19 19:17:01,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:01,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:01,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:01,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:01,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:01,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804286491] [2021-12-19 19:17:01,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804286491] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:01,928 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:01,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:01,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77587530] [2021-12-19 19:17:01,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:01,929 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:01,930 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:01,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:01,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:01,931 INFO L87 Difference]: Start difference. First operand 3767 states and 5535 transitions. cyclomatic complexity: 1769 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:01,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:01,987 INFO L93 Difference]: Finished difference Result 3767 states and 5497 transitions. [2021-12-19 19:17:01,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:01,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3767 states and 5497 transitions. [2021-12-19 19:17:01,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:02,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3767 states to 3767 states and 5497 transitions. [2021-12-19 19:17:02,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3767 [2021-12-19 19:17:02,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3767 [2021-12-19 19:17:02,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3767 states and 5497 transitions. [2021-12-19 19:17:02,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:02,013 INFO L681 BuchiCegarLoop]: Abstraction has 3767 states and 5497 transitions. [2021-12-19 19:17:02,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states and 5497 transitions. [2021-12-19 19:17:02,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3767. [2021-12-19 19:17:02,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.459251393681975) internal successors, (5497), 3766 states have internal predecessors, (5497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5497 transitions. [2021-12-19 19:17:02,060 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5497 transitions. [2021-12-19 19:17:02,060 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5497 transitions. [2021-12-19 19:17:02,061 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:02,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5497 transitions. [2021-12-19 19:17:02,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:02,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,071 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,072 INFO L791 eck$LassoCheckResult]: Stem: 76146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 75879#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75880#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77345#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 77346#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76065#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76066#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76100#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76957#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76958#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77077#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77078#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75885#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75886#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77119#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76411#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76412#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 77014#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77322#L1286 assume !(0 == ~M_E~0); 77181#L1286-2 assume !(0 == ~T1_E~0); 75794#L1291-1 assume !(0 == ~T2_E~0); 75795#L1296-1 assume !(0 == ~T3_E~0); 76505#L1301-1 assume !(0 == ~T4_E~0); 76506#L1306-1 assume !(0 == ~T5_E~0); 77023#L1311-1 assume !(0 == ~T6_E~0); 75754#L1316-1 assume !(0 == ~T7_E~0); 75755#L1321-1 assume !(0 == ~T8_E~0); 76524#L1326-1 assume !(0 == ~T9_E~0); 75569#L1331-1 assume !(0 == ~T10_E~0); 75275#L1336-1 assume !(0 == ~T11_E~0); 75276#L1341-1 assume !(0 == ~T12_E~0); 75327#L1346-1 assume !(0 == ~T13_E~0); 75328#L1351-1 assume !(0 == ~E_M~0); 75701#L1356-1 assume !(0 == ~E_1~0); 75702#L1361-1 assume !(0 == ~E_2~0); 77277#L1366-1 assume !(0 == ~E_3~0); 75747#L1371-1 assume !(0 == ~E_4~0); 75748#L1376-1 assume !(0 == ~E_5~0); 76566#L1381-1 assume !(0 == ~E_6~0); 76567#L1386-1 assume !(0 == ~E_7~0); 77312#L1391-1 assume !(0 == ~E_8~0); 77333#L1396-1 assume !(0 == ~E_9~0); 76445#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 76446#L1406-1 assume !(0 == ~E_11~0); 76752#L1411-1 assume !(0 == ~E_12~0); 76753#L1416-1 assume !(0 == ~E_13~0); 76369#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76207#L635 assume !(1 == ~m_pc~0); 75347#L635-2 is_master_triggered_~__retres1~0#1 := 0; 75348#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75698#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76333#L1598 assume !(0 != activate_threads_~tmp~1#1); 75524#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75525#L654 assume 1 == ~t1_pc~0; 76230#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76231#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77309#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76313#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 76314#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75575#L673 assume !(1 == ~t2_pc~0); 75577#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76721#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76722#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77355#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 77364#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76392#L692 assume !(1 == ~t3_pc~0); 76209#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76210#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76069#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76035#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76036#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75597#L711 assume 1 == ~t4_pc~0; 75598#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76080#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76542#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75300#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 75301#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77343#L730 assume !(1 == ~t5_pc~0); 76655#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75479#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75480#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75607#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 75608#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75949#L749 assume 1 == ~t6_pc~0; 75724#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75489#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75915#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75916#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 76138#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75282#L768 assume !(1 == ~t7_pc~0); 75283#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76589#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75517#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75518#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 76608#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75756#L787 assume 1 == ~t8_pc~0; 75757#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76974#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77148#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77149#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 75325#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75326#L806 assume 1 == ~t9_pc~0; 76985#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75360#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75361#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75609#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 75610#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76968#L825 assume !(1 == ~t10_pc~0); 76969#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76556#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76557#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75699#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75700#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76281#L844 assume 1 == ~t11_pc~0; 75972#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75973#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76339#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76340#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 76953#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76954#L863 assume !(1 == ~t12_pc~0); 75464#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 75463#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75688#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77051#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 77052#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76406#L882 assume 1 == ~t13_pc~0; 76407#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76694#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 77231#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77016#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 76681#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76682#L1434 assume !(1 == ~M_E~0); 77243#L1434-2 assume !(1 == ~T1_E~0); 77354#L1439-1 assume !(1 == ~T2_E~0); 75590#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75591#L1449-1 assume !(1 == ~T4_E~0); 76033#L1454-1 assume !(1 == ~T5_E~0); 76034#L1459-1 assume !(1 == ~T6_E~0); 76609#L1464-1 assume !(1 == ~T7_E~0); 76610#L1469-1 assume !(1 == ~T8_E~0); 76697#L1474-1 assume !(1 == ~T9_E~0); 76370#L1479-1 assume !(1 == ~T10_E~0); 76371#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76617#L1489-1 assume !(1 == ~T12_E~0); 76247#L1494-1 assume !(1 == ~T13_E~0); 76248#L1499-1 assume !(1 == ~E_M~0); 76430#L1504-1 assume !(1 == ~E_1~0); 76431#L1509-1 assume !(1 == ~E_2~0); 77069#L1514-1 assume !(1 == ~E_3~0); 76732#L1519-1 assume !(1 == ~E_4~0); 76733#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77293#L1529-1 assume !(1 == ~E_6~0); 77294#L1534-1 assume !(1 == ~E_7~0); 75380#L1539-1 assume !(1 == ~E_8~0); 75381#L1544-1 assume !(1 == ~E_9~0); 75811#L1549-1 assume !(1 == ~E_10~0); 77259#L1554-1 assume !(1 == ~E_11~0); 77257#L1559-1 assume !(1 == ~E_12~0); 77103#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 77104#L1569-1 assume { :end_inline_reset_delta_events } true; 77284#L1935-2 [2021-12-19 19:17:02,072 INFO L793 eck$LassoCheckResult]: Loop: 77284#L1935-2 assume !false; 77404#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77307#L1261 assume !false; 76623#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76624#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75520#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75691#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 75692#L1074 assume !(0 != eval_~tmp~0#1); 76047#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76650#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77073#L1286-3 assume !(0 == ~M_E~0); 77137#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76829#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76830#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77326#L1301-3 assume !(0 == ~T4_E~0); 77270#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76326#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75624#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75625#L1321-3 assume !(0 == ~T8_E~0); 75737#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76469#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 76735#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76736#L1341-3 assume !(0 == ~T12_E~0); 76025#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76016#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 75960#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75961#L1361-3 assume !(0 == ~E_2~0); 76546#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75315#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 75316#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77084#L1381-3 assume !(0 == ~E_6~0); 76923#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76924#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77121#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77122#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 75695#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75526#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 75527#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76153#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75404#L635-45 assume 1 == ~m_pc~0; 75405#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76200#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76683#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76952#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75713#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75714#L654-45 assume !(1 == ~t1_pc~0); 76539#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 76897#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75367#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75368#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75393#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76220#L673-45 assume !(1 == ~t2_pc~0); 76221#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 76549#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76550#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77205#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 77013#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75838#L692-45 assume !(1 == ~t3_pc~0); 75564#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 75565#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76613#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75892#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75893#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76206#L711-45 assume 1 == ~t4_pc~0; 76330#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76331#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76181#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76182#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76590#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75736#L730-45 assume 1 == ~t5_pc~0; 75572#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75573#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75984#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75985#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76741#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75548#L749-45 assume !(1 == ~t6_pc~0); 75549#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 76971#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76715#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76716#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76875#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75864#L768-45 assume 1 == ~t7_pc~0; 75865#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76003#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76814#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76815#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76858#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76859#L787-45 assume !(1 == ~t8_pc~0); 77041#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 76009#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76010#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78536#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78535#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78534#L806-45 assume !(1 == ~t9_pc~0); 75423#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 75424#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76249#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76076#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 75988#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75989#L825-45 assume !(1 == ~t10_pc~0); 76517#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 76518#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76621#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76622#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76777#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75632#L844-45 assume !(1 == ~t11_pc~0); 75633#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 76154#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76155#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76171#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 76587#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75671#L863-45 assume !(1 == ~t12_pc~0); 75673#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 75273#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75274#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75789#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75790#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76593#L882-45 assume 1 == ~t13_pc~0; 76964#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75292#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75293#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75900#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77110#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76700#L1434-3 assume !(1 == ~M_E~0); 76701#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76895#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75586#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75587#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75749#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78573#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78572#L1464-3 assume !(1 == ~T7_E~0); 78571#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78570#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77274#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77167#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76328#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76329#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77010#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76627#L1504-3 assume !(1 == ~E_1~0); 76628#L1509-3 assume !(1 == ~E_2~0); 77095#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77141#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76250#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76251#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77190#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78559#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78558#L1544-3 assume !(1 == ~E_9~0); 78557#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78556#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78555#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78554#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 76793#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76794#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75522#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 76086#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 76763#L1954 assume !(0 == start_simulation_~tmp~3#1); 76765#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77693#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77681#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77475#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77435#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77427#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77421#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77413#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 77284#L1935-2 [2021-12-19 19:17:02,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,073 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2021-12-19 19:17:02,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002843200] [2021-12-19 19:17:02,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,105 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002843200] [2021-12-19 19:17:02,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002843200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,105 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,106 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332537748] [2021-12-19 19:17:02,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,106 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,106 INFO L85 PathProgramCache]: Analyzing trace with hash -1670511899, now seen corresponding path program 1 times [2021-12-19 19:17:02,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199793977] [2021-12-19 19:17:02,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,107 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,133 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199793977] [2021-12-19 19:17:02,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199793977] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,134 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340551645] [2021-12-19 19:17:02,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,134 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:02,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:02,135 INFO L87 Difference]: Start difference. First operand 3767 states and 5497 transitions. cyclomatic complexity: 1731 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:02,254 INFO L93 Difference]: Finished difference Result 5390 states and 7848 transitions. [2021-12-19 19:17:02,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:02,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5390 states and 7848 transitions. [2021-12-19 19:17:02,274 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5210 [2021-12-19 19:17:02,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5390 states to 5390 states and 7848 transitions. [2021-12-19 19:17:02,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5390 [2021-12-19 19:17:02,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5390 [2021-12-19 19:17:02,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5390 states and 7848 transitions. [2021-12-19 19:17:02,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:02,295 INFO L681 BuchiCegarLoop]: Abstraction has 5390 states and 7848 transitions. [2021-12-19 19:17:02,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5390 states and 7848 transitions. [2021-12-19 19:17:02,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5390 to 3767. [2021-12-19 19:17:02,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.4584550039819486) internal successors, (5494), 3766 states have internal predecessors, (5494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5494 transitions. [2021-12-19 19:17:02,346 INFO L704 BuchiCegarLoop]: Abstraction has 3767 states and 5494 transitions. [2021-12-19 19:17:02,346 INFO L587 BuchiCegarLoop]: Abstraction has 3767 states and 5494 transitions. [2021-12-19 19:17:02,346 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:02,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5494 transitions. [2021-12-19 19:17:02,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2021-12-19 19:17:02,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,356 INFO L791 eck$LassoCheckResult]: Stem: 85312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85045#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85046#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86453#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 86454#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85231#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85232#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85266#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86105#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86106#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86220#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86221#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85051#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85052#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86259#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85574#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85575#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86159#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86440#L1286 assume !(0 == ~M_E~0); 86321#L1286-2 assume !(0 == ~T1_E~0); 84960#L1291-1 assume !(0 == ~T2_E~0); 84961#L1296-1 assume !(0 == ~T3_E~0); 85665#L1301-1 assume !(0 == ~T4_E~0); 85666#L1306-1 assume !(0 == ~T5_E~0); 86168#L1311-1 assume !(0 == ~T6_E~0); 84920#L1316-1 assume !(0 == ~T7_E~0); 84921#L1321-1 assume !(0 == ~T8_E~0); 85684#L1326-1 assume !(0 == ~T9_E~0); 84736#L1331-1 assume !(0 == ~T10_E~0); 84442#L1336-1 assume !(0 == ~T11_E~0); 84443#L1341-1 assume !(0 == ~T12_E~0); 84494#L1346-1 assume !(0 == ~T13_E~0); 84495#L1351-1 assume !(0 == ~E_M~0); 84867#L1356-1 assume !(0 == ~E_1~0); 84868#L1361-1 assume !(0 == ~E_2~0); 86398#L1366-1 assume !(0 == ~E_3~0); 84913#L1371-1 assume !(0 == ~E_4~0); 84914#L1376-1 assume !(0 == ~E_5~0); 85726#L1381-1 assume !(0 == ~E_6~0); 85727#L1386-1 assume !(0 == ~E_7~0); 86430#L1391-1 assume !(0 == ~E_8~0); 86444#L1396-1 assume !(0 == ~E_9~0); 85608#L1401-1 assume !(0 == ~E_10~0); 85609#L1406-1 assume !(0 == ~E_11~0); 85912#L1411-1 assume !(0 == ~E_12~0); 85913#L1416-1 assume !(0 == ~E_13~0); 85532#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85371#L635 assume !(1 == ~m_pc~0); 84514#L635-2 is_master_triggered_~__retres1~0#1 := 0; 84515#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84864#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85496#L1598 assume !(0 != activate_threads_~tmp~1#1); 84691#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84692#L654 assume 1 == ~t1_pc~0; 85394#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85395#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86427#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85476#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 85477#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84742#L673 assume !(1 == ~t2_pc~0); 84744#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85881#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85882#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86459#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 86466#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85555#L692 assume !(1 == ~t3_pc~0); 85373#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85374#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85235#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85201#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85202#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84764#L711 assume 1 == ~t4_pc~0; 84765#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85246#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85702#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84467#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 84468#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86452#L730 assume !(1 == ~t5_pc~0); 85815#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84646#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84647#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84774#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 84775#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85115#L749 assume 1 == ~t6_pc~0; 84890#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84656#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85081#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85082#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 85304#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84449#L768 assume !(1 == ~t7_pc~0); 84450#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85749#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84684#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84685#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 85768#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84922#L787 assume 1 == ~t8_pc~0; 84923#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86119#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86289#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86290#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 84492#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84493#L806 assume 1 == ~t9_pc~0; 86130#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84527#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84528#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84776#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 84777#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86113#L825 assume !(1 == ~t10_pc~0); 86114#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85716#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85717#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84865#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84866#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85445#L844 assume 1 == ~t11_pc~0; 85138#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85139#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85502#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85503#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 86101#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86102#L863 assume !(1 == ~t12_pc~0); 84631#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 84630#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84855#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86193#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 86194#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85569#L882 assume 1 == ~t13_pc~0; 85570#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85854#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86366#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86161#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 85841#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85842#L1434 assume !(1 == ~M_E~0); 86375#L1434-2 assume !(1 == ~T1_E~0); 86458#L1439-1 assume !(1 == ~T2_E~0); 84757#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84758#L1449-1 assume !(1 == ~T4_E~0); 85199#L1454-1 assume !(1 == ~T5_E~0); 85200#L1459-1 assume !(1 == ~T6_E~0); 85769#L1464-1 assume !(1 == ~T7_E~0); 85770#L1469-1 assume !(1 == ~T8_E~0); 85857#L1474-1 assume !(1 == ~T9_E~0); 85533#L1479-1 assume !(1 == ~T10_E~0); 85534#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85777#L1489-1 assume !(1 == ~T12_E~0); 85411#L1494-1 assume !(1 == ~T13_E~0); 85412#L1499-1 assume !(1 == ~E_M~0); 85593#L1504-1 assume !(1 == ~E_1~0); 85594#L1509-1 assume !(1 == ~E_2~0); 86211#L1514-1 assume !(1 == ~E_3~0); 85892#L1519-1 assume !(1 == ~E_4~0); 85893#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86413#L1529-1 assume !(1 == ~E_6~0); 86414#L1534-1 assume !(1 == ~E_7~0); 84549#L1539-1 assume !(1 == ~E_8~0); 84550#L1544-1 assume !(1 == ~E_9~0); 84977#L1549-1 assume !(1 == ~E_10~0); 86388#L1554-1 assume !(1 == ~E_11~0); 86386#L1559-1 assume !(1 == ~E_12~0); 86244#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86245#L1569-1 assume { :end_inline_reset_delta_events } true; 86407#L1935-2 [2021-12-19 19:17:02,357 INFO L793 eck$LassoCheckResult]: Loop: 86407#L1935-2 assume !false; 84556#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84557#L1261 assume !false; 85783#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85784#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84687#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84856#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 84857#L1074 assume !(0 != eval_~tmp~0#1); 85213#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85810#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86216#L1286-3 assume !(0 == ~M_E~0); 86278#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85988#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85989#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86441#L1301-3 assume !(0 == ~T4_E~0); 86394#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85489#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84791#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84792#L1321-3 assume !(0 == ~T8_E~0); 84896#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 85630#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85897#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85898#L1341-3 assume !(0 == ~T12_E~0); 85191#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85182#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85126#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85127#L1361-3 assume !(0 == ~E_2~0); 85706#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84484#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 84485#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86229#L1381-3 assume !(0 == ~E_6~0); 86074#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86075#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86261#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86262#L1401-3 assume !(0 == ~E_10~0); 84861#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 84693#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 84694#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 85319#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84571#L635-45 assume !(1 == ~m_pc~0); 84573#L635-47 is_master_triggered_~__retres1~0#1 := 0; 85364#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85843#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86100#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84879#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84880#L654-45 assume !(1 == ~t1_pc~0); 85699#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 86049#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84534#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84535#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84560#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85384#L673-45 assume !(1 == ~t2_pc~0); 85385#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 85709#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85710#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86346#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 86158#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85004#L692-45 assume 1 == ~t3_pc~0; 85005#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84735#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85773#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85058#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85059#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85370#L711-45 assume 1 == ~t4_pc~0; 85493#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85494#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85348#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85349#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85751#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84903#L730-45 assume 1 == ~t5_pc~0; 84739#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84740#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85150#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85151#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85902#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84715#L749-45 assume 1 == ~t6_pc~0; 84717#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86116#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85876#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85877#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86031#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85030#L768-45 assume 1 == ~t7_pc~0; 85031#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85173#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85973#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85974#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86014#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86015#L787-45 assume !(1 == ~t8_pc~0); 86185#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 85175#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85176#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85590#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85591#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85901#L806-45 assume 1 == ~t9_pc~0; 86389#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84591#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85413#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85242#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85154#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85155#L825-45 assume 1 == ~t10_pc~0; 85765#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 85678#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85781#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85782#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85937#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84798#L844-45 assume 1 == ~t11_pc~0; 84800#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85320#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85321#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85337#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 85746#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84838#L863-45 assume 1 == ~t12_pc~0; 84839#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84440#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84441#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84952#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 84953#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85752#L882-45 assume !(1 == ~t13_pc~0); 85284#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 84459#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 84460#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 85066#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86251#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85860#L1434-3 assume !(1 == ~M_E~0); 85861#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86048#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84753#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84754#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84915#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85850#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85851#L1464-3 assume !(1 == ~T7_E~0); 86306#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86231#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86232#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86308#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85491#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85492#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 86155#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85785#L1504-3 assume !(1 == ~E_1~0); 85786#L1509-3 assume !(1 == ~E_2~0); 86240#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86282#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85414#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85415#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86331#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85712#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85169#L1544-3 assume !(1 == ~E_9~0); 85170#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 85685#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 84804#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 84805#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 85951#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85952#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84689#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85252#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85923#L1954 assume !(0 == start_simulation_~tmp~3#1); 85925#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86177#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84971#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86012#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86143#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86144#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86238#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86302#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 86407#L1935-2 [2021-12-19 19:17:02,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2021-12-19 19:17:02,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352358667] [2021-12-19 19:17:02,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,379 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352358667] [2021-12-19 19:17:02,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352358667] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,380 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,380 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:02,380 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362621043] [2021-12-19 19:17:02,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,381 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,381 INFO L85 PathProgramCache]: Analyzing trace with hash -1769844833, now seen corresponding path program 1 times [2021-12-19 19:17:02,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24335240] [2021-12-19 19:17:02,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,408 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24335240] [2021-12-19 19:17:02,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24335240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,408 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127976383] [2021-12-19 19:17:02,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,409 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,409 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:02,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:02,410 INFO L87 Difference]: Start difference. First operand 3767 states and 5494 transitions. cyclomatic complexity: 1728 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:02,493 INFO L93 Difference]: Finished difference Result 7125 states and 10338 transitions. [2021-12-19 19:17:02,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:02,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7125 states and 10338 transitions. [2021-12-19 19:17:02,514 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6949 [2021-12-19 19:17:02,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7125 states to 7125 states and 10338 transitions. [2021-12-19 19:17:02,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7125 [2021-12-19 19:17:02,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7125 [2021-12-19 19:17:02,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7125 states and 10338 transitions. [2021-12-19 19:17:02,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:02,587 INFO L681 BuchiCegarLoop]: Abstraction has 7125 states and 10338 transitions. [2021-12-19 19:17:02,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7125 states and 10338 transitions. [2021-12-19 19:17:02,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7125 to 7121. [2021-12-19 19:17:02,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7121 states, 7121 states have (on average 1.4512006740626318) internal successors, (10334), 7120 states have internal predecessors, (10334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:02,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7121 states to 7121 states and 10334 transitions. [2021-12-19 19:17:02,679 INFO L704 BuchiCegarLoop]: Abstraction has 7121 states and 10334 transitions. [2021-12-19 19:17:02,679 INFO L587 BuchiCegarLoop]: Abstraction has 7121 states and 10334 transitions. [2021-12-19 19:17:02,679 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:02,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7121 states and 10334 transitions. [2021-12-19 19:17:02,693 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6945 [2021-12-19 19:17:02,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:02,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:02,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:02,695 INFO L791 eck$LassoCheckResult]: Stem: 96216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 95945#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95946#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97447#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 97448#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96134#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96135#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96170#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97044#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97045#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97171#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97172#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95951#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95952#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97212#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96484#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96485#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97108#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97428#L1286 assume !(0 == ~M_E~0); 97285#L1286-2 assume !(0 == ~T1_E~0); 95860#L1291-1 assume !(0 == ~T2_E~0); 95861#L1296-1 assume !(0 == ~T3_E~0); 96579#L1301-1 assume !(0 == ~T4_E~0); 96580#L1306-1 assume !(0 == ~T5_E~0); 97117#L1311-1 assume !(0 == ~T6_E~0); 95820#L1316-1 assume !(0 == ~T7_E~0); 95821#L1321-1 assume !(0 == ~T8_E~0); 96600#L1326-1 assume !(0 == ~T9_E~0); 95635#L1331-1 assume !(0 == ~T10_E~0); 95341#L1336-1 assume !(0 == ~T11_E~0); 95342#L1341-1 assume !(0 == ~T12_E~0); 95393#L1346-1 assume !(0 == ~T13_E~0); 95394#L1351-1 assume !(0 == ~E_M~0); 95765#L1356-1 assume !(0 == ~E_1~0); 95766#L1361-1 assume !(0 == ~E_2~0); 97373#L1366-1 assume !(0 == ~E_3~0); 95812#L1371-1 assume !(0 == ~E_4~0); 95813#L1376-1 assume !(0 == ~E_5~0); 96643#L1381-1 assume !(0 == ~E_6~0); 96644#L1386-1 assume !(0 == ~E_7~0); 97411#L1391-1 assume !(0 == ~E_8~0); 97434#L1396-1 assume !(0 == ~E_9~0); 96518#L1401-1 assume !(0 == ~E_10~0); 96519#L1406-1 assume !(0 == ~E_11~0); 96839#L1411-1 assume !(0 == ~E_12~0); 96840#L1416-1 assume !(0 == ~E_13~0); 96441#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96277#L635 assume !(1 == ~m_pc~0); 95411#L635-2 is_master_triggered_~__retres1~0#1 := 0; 95412#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95760#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96404#L1598 assume !(0 != activate_threads_~tmp~1#1); 95590#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95591#L654 assume !(1 == ~t1_pc~0); 96381#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97214#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97408#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96379#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 96380#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95638#L673 assume !(1 == ~t2_pc~0); 95640#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96807#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96808#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97457#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 97466#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96465#L692 assume !(1 == ~t3_pc~0); 96279#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96280#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96136#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96105#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 96106#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95663#L711 assume 1 == ~t4_pc~0; 95664#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 96150#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96619#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95366#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 95367#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97446#L730 assume !(1 == ~t5_pc~0); 96737#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95545#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95546#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95673#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 95674#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96017#L749 assume 1 == ~t6_pc~0; 95789#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95550#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95981#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95982#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 96208#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95346#L768 assume !(1 == ~t7_pc~0); 95347#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96668#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95583#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95584#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 96690#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95822#L787 assume 1 == ~t8_pc~0; 95823#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 97061#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97246#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97247#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 95391#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95392#L806 assume 1 == ~t9_pc~0; 97073#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95426#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95427#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95675#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 95676#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97052#L825 assume !(1 == ~t10_pc~0); 97053#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96633#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96634#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95761#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 95762#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96348#L844 assume 1 == ~t11_pc~0; 96038#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96039#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96410#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 96411#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 97038#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97039#L863 assume !(1 == ~t12_pc~0); 95526#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 95525#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95751#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 97143#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 97144#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96479#L882 assume 1 == ~t13_pc~0; 96480#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 96776#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97338#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97110#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 96763#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96764#L1434 assume !(1 == ~M_E~0); 97347#L1434-2 assume !(1 == ~T1_E~0); 97455#L1439-1 assume !(1 == ~T2_E~0); 95656#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95657#L1449-1 assume !(1 == ~T4_E~0); 96102#L1454-1 assume !(1 == ~T5_E~0); 96103#L1459-1 assume !(1 == ~T6_E~0); 96691#L1464-1 assume !(1 == ~T7_E~0); 96692#L1469-1 assume !(1 == ~T8_E~0); 96777#L1474-1 assume !(1 == ~T9_E~0); 96442#L1479-1 assume !(1 == ~T10_E~0); 96443#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 96699#L1489-1 assume !(1 == ~T12_E~0); 96314#L1494-1 assume !(1 == ~T13_E~0); 96315#L1499-1 assume !(1 == ~E_M~0); 96503#L1504-1 assume !(1 == ~E_1~0); 96504#L1509-1 assume !(1 == ~E_2~0); 97160#L1514-1 assume !(1 == ~E_3~0); 96820#L1519-1 assume !(1 == ~E_4~0); 96821#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 97387#L1529-1 assume !(1 == ~E_6~0); 97388#L1534-1 assume !(1 == ~E_7~0); 95446#L1539-1 assume !(1 == ~E_8~0); 95447#L1544-1 assume !(1 == ~E_9~0); 95877#L1549-1 assume !(1 == ~E_10~0); 97363#L1554-1 assume !(1 == ~E_11~0); 97361#L1559-1 assume !(1 == ~E_12~0); 97194#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 97195#L1569-1 assume { :end_inline_reset_delta_events } true; 97380#L1935-2 [2021-12-19 19:17:02,695 INFO L793 eck$LassoCheckResult]: Loop: 97380#L1935-2 assume !false; 95455#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95456#L1261 assume !false; 100512#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100424#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100415#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 95754#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 95755#L1074 assume !(0 != eval_~tmp~0#1); 96116#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96732#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97167#L1286-3 assume !(0 == ~M_E~0); 97233#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96918#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96919#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97430#L1301-3 assume !(0 == ~T4_E~0); 97368#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96394#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95690#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95691#L1321-3 assume !(0 == ~T8_E~0); 95795#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 96541#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 96823#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96824#L1341-3 assume !(0 == ~T12_E~0); 96095#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96086#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 96028#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96029#L1361-3 assume !(0 == ~E_2~0); 96623#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95381#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95382#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97181#L1381-3 assume !(0 == ~E_6~0); 97009#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 97010#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 97215#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 97216#L1401-3 assume !(0 == ~E_10~0); 95759#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 95592#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 95593#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 96223#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95470#L635-45 assume !(1 == ~m_pc~0); 95472#L635-47 is_master_triggered_~__retres1~0#1 := 0; 96270#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96765#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97037#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95777#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95778#L654-45 assume !(1 == ~t1_pc~0); 96616#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 96983#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95433#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95434#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95459#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96290#L673-45 assume !(1 == ~t2_pc~0); 96291#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 96626#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96627#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97314#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 97107#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95904#L692-45 assume 1 == ~t3_pc~0; 95905#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95631#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96695#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95958#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95959#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96276#L711-45 assume 1 == ~t4_pc~0; 96401#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 96402#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96251#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96252#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96669#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95802#L730-45 assume 1 == ~t5_pc~0; 95641#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95642#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96052#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96053#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 96829#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95614#L749-45 assume 1 == ~t6_pc~0; 95616#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97055#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96801#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96802#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96963#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95931#L768-45 assume !(1 == ~t7_pc~0); 95933#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 96071#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96904#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96905#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 96945#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96946#L787-45 assume !(1 == ~t8_pc~0); 97135#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 96079#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96080#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96501#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96502#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96828#L806-45 assume !(1 == ~t9_pc~0); 95489#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 95490#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96316#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96145#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 96056#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96057#L825-45 assume !(1 == ~t10_pc~0); 96593#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 96594#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96705#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96706#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101788#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101787#L844-45 assume !(1 == ~t11_pc~0); 97317#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 96224#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96225#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 96241#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 96666#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 95737#L863-45 assume !(1 == ~t12_pc~0); 95739#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 95339#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95340#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 95855#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 95856#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96674#L882-45 assume 1 == ~t13_pc~0; 97049#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 95358#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95359#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 95966#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 97204#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96782#L1434-3 assume !(1 == ~M_E~0); 96783#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101743#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101741#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101739#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101737#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101735#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101733#L1464-3 assume !(1 == ~T7_E~0); 101730#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101728#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101726#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 101724#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 101722#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 101720#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 101717#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101715#L1504-3 assume !(1 == ~E_1~0); 101714#L1509-3 assume !(1 == ~E_2~0); 101713#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101712#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101711#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101710#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101709#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101708#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101707#L1544-3 assume !(1 == ~E_9~0); 101706#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101705#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101704#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 101703#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 101702#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101696#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101687#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97041#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 96850#L1954 assume !(0 == start_simulation_~tmp~3#1); 96852#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97126#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 95871#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96943#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 97086#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97087#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97190#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 97263#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 97380#L1935-2 [2021-12-19 19:17:02,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,696 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2021-12-19 19:17:02,696 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018715222] [2021-12-19 19:17:02,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,696 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,730 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018715222] [2021-12-19 19:17:02,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018715222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:02,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375098803] [2021-12-19 19:17:02,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,732 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:02,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:02,733 INFO L85 PathProgramCache]: Analyzing trace with hash 135629219, now seen corresponding path program 1 times [2021-12-19 19:17:02,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:02,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070109500] [2021-12-19 19:17:02,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:02,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:02,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:02,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:02,761 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:02,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070109500] [2021-12-19 19:17:02,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070109500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:02,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:02,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:02,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862548324] [2021-12-19 19:17:02,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:02,763 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:02,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:02,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:02,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:02,764 INFO L87 Difference]: Start difference. First operand 7121 states and 10334 transitions. cyclomatic complexity: 3215 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:03,022 INFO L93 Difference]: Finished difference Result 19447 states and 28232 transitions. [2021-12-19 19:17:03,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:03,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19447 states and 28232 transitions. [2021-12-19 19:17:03,095 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 19064 [2021-12-19 19:17:03,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19447 states to 19447 states and 28232 transitions. [2021-12-19 19:17:03,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19447 [2021-12-19 19:17:03,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19447 [2021-12-19 19:17:03,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19447 states and 28232 transitions. [2021-12-19 19:17:03,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:03,186 INFO L681 BuchiCegarLoop]: Abstraction has 19447 states and 28232 transitions. [2021-12-19 19:17:03,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19447 states and 28232 transitions. [2021-12-19 19:17:03,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19447 to 7304. [2021-12-19 19:17:03,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7304 states, 7304 states have (on average 1.439895947426068) internal successors, (10517), 7303 states have internal predecessors, (10517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7304 states to 7304 states and 10517 transitions. [2021-12-19 19:17:03,348 INFO L704 BuchiCegarLoop]: Abstraction has 7304 states and 10517 transitions. [2021-12-19 19:17:03,348 INFO L587 BuchiCegarLoop]: Abstraction has 7304 states and 10517 transitions. [2021-12-19 19:17:03,348 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:03,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7304 states and 10517 transitions. [2021-12-19 19:17:03,414 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7125 [2021-12-19 19:17:03,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:03,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:03,416 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:03,416 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:03,417 INFO L791 eck$LassoCheckResult]: Stem: 122809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 122810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 122532#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122533#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124289#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 124290#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122725#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122726#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122761#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123726#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123727#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123896#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123897#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122538#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122539#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123944#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 123082#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 123083#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 123809#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124258#L1286 assume !(0 == ~M_E~0); 124038#L1286-2 assume !(0 == ~T1_E~0); 122447#L1291-1 assume !(0 == ~T2_E~0); 122448#L1296-1 assume !(0 == ~T3_E~0); 123184#L1301-1 assume !(0 == ~T4_E~0); 123185#L1306-1 assume !(0 == ~T5_E~0); 123820#L1311-1 assume !(0 == ~T6_E~0); 122405#L1316-1 assume !(0 == ~T7_E~0); 122406#L1321-1 assume !(0 == ~T8_E~0); 123207#L1326-1 assume !(0 == ~T9_E~0); 122220#L1331-1 assume !(0 == ~T10_E~0); 121922#L1336-1 assume !(0 == ~T11_E~0); 121923#L1341-1 assume !(0 == ~T12_E~0); 121974#L1346-1 assume !(0 == ~T13_E~0); 121975#L1351-1 assume !(0 == ~E_M~0); 122352#L1356-1 assume !(0 == ~E_1~0); 122353#L1361-1 assume !(0 == ~E_2~0); 124182#L1366-1 assume !(0 == ~E_3~0); 122398#L1371-1 assume !(0 == ~E_4~0); 122399#L1376-1 assume !(0 == ~E_5~0); 123256#L1381-1 assume !(0 == ~E_6~0); 123257#L1386-1 assume !(0 == ~E_7~0); 124237#L1391-1 assume !(0 == ~E_8~0); 124273#L1396-1 assume !(0 == ~E_9~0); 123122#L1401-1 assume !(0 == ~E_10~0); 123123#L1406-1 assume !(0 == ~E_11~0); 123475#L1411-1 assume !(0 == ~E_12~0); 123476#L1416-1 assume !(0 == ~E_13~0); 123038#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122872#L635 assume !(1 == ~m_pc~0); 121992#L635-2 is_master_triggered_~__retres1~0#1 := 0; 121993#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122347#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123002#L1598 assume !(0 != activate_threads_~tmp~1#1); 122174#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122175#L654 assume !(1 == ~t1_pc~0); 122982#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123946#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124229#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122980#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 122981#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122223#L673 assume !(1 == ~t2_pc~0); 122225#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123435#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123436#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124307#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 124321#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123063#L692 assume !(1 == ~t3_pc~0); 122874#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122875#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124267#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122691#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 122692#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122248#L711 assume 1 == ~t4_pc~0; 122249#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 122741#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123226#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121947#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 121948#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124288#L730 assume !(1 == ~t5_pc~0); 123364#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122128#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122129#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122258#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 122259#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122602#L749 assume 1 == ~t6_pc~0; 122375#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 122133#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122568#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122569#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 122801#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121927#L768 assume !(1 == ~t7_pc~0); 121928#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 123283#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122167#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122168#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 123305#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122407#L787 assume 1 == ~t8_pc~0; 122408#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 123748#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123986#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123987#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 121972#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121973#L806 assume 1 == ~t9_pc~0; 123763#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122007#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122008#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122260#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 122261#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123736#L825 assume !(1 == ~t10_pc~0); 123737#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 123245#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123246#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122348#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122349#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122944#L844 assume 1 == ~t11_pc~0; 122623#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122624#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123008#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 123009#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 123719#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 123720#L863 assume !(1 == ~t12_pc~0); 122107#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 122106#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 122337#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 123856#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 123857#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123077#L882 assume 1 == ~t13_pc~0; 123078#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 123407#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 124116#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 123811#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 123393#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123394#L1434 assume !(1 == ~M_E~0); 124133#L1434-2 assume !(1 == ~T1_E~0); 124306#L1439-1 assume !(1 == ~T2_E~0); 122241#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122242#L1449-1 assume !(1 == ~T4_E~0); 122687#L1454-1 assume !(1 == ~T5_E~0); 122688#L1459-1 assume !(1 == ~T6_E~0); 123306#L1464-1 assume !(1 == ~T7_E~0); 123307#L1469-1 assume !(1 == ~T8_E~0); 123408#L1474-1 assume !(1 == ~T9_E~0); 123039#L1479-1 assume !(1 == ~T10_E~0); 123040#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123321#L1489-1 assume !(1 == ~T12_E~0); 122910#L1494-1 assume !(1 == ~T13_E~0); 122911#L1499-1 assume !(1 == ~E_M~0); 123103#L1504-1 assume !(1 == ~E_1~0); 123104#L1509-1 assume !(1 == ~E_2~0); 123882#L1514-1 assume !(1 == ~E_3~0); 123448#L1519-1 assume !(1 == ~E_4~0); 123449#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 124207#L1529-1 assume !(1 == ~E_6~0); 124208#L1534-1 assume !(1 == ~E_7~0); 122027#L1539-1 assume !(1 == ~E_8~0); 122028#L1544-1 assume !(1 == ~E_9~0); 122464#L1549-1 assume !(1 == ~E_10~0); 124156#L1554-1 assume !(1 == ~E_11~0); 124153#L1559-1 assume !(1 == ~E_12~0); 123925#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 123926#L1569-1 assume { :end_inline_reset_delta_events } true; 124195#L1935-2 [2021-12-19 19:17:03,417 INFO L793 eck$LassoCheckResult]: Loop: 124195#L1935-2 assume !false; 125215#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 125206#L1261 assume !false; 125196#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124736#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 124726#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 124723#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 124721#L1074 assume !(0 != eval_~tmp~0#1); 124722#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129221#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129220#L1286-3 assume !(0 == ~M_E~0); 129219#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123567#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 123568#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129218#L1301-3 assume !(0 == ~T4_E~0); 129217#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 129216#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129215#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129214#L1321-3 assume !(0 == ~T8_E~0); 129190#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 129189#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 129188#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 129187#L1341-3 assume !(0 == ~T12_E~0); 129186#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 129185#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 129184#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123230#L1361-3 assume !(0 == ~E_2~0); 123231#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121962#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 121963#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123907#L1381-3 assume !(0 == ~E_6~0); 129161#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129159#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 129157#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 129155#L1401-3 assume !(0 == ~E_10~0); 129152#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 122176#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 122177#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 122816#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122817#L635-45 assume !(1 == ~m_pc~0); 122865#L635-47 is_master_triggered_~__retres1~0#1 := 0; 122864#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124015#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124016#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 122364#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122365#L654-45 assume !(1 == ~t1_pc~0); 129148#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 129147#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129146#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129145#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129144#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129143#L673-45 assume !(1 == ~t2_pc~0); 129141#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 129140#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129139#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 129138#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 129137#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129136#L692-45 assume !(1 == ~t3_pc~0); 129135#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 129133#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129131#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129129#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 129126#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129124#L711-45 assume !(1 == ~t4_pc~0); 129121#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 129119#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129114#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129113#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 129112#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129111#L730-45 assume 1 == ~t5_pc~0; 129109#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 129108#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129107#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 129106#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 129105#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129052#L749-45 assume !(1 == ~t6_pc~0); 129049#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 129047#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 129044#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 129042#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 129040#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129038#L768-45 assume 1 == ~t7_pc~0; 129035#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 129033#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 129030#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129029#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 129028#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 129027#L787-45 assume !(1 == ~t8_pc~0); 129025#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 129024#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 129023#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129022#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 129021#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129020#L806-45 assume !(1 == ~t9_pc~0); 129019#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 129017#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129016#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122737#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 122641#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122642#L825-45 assume !(1 == ~t10_pc~0); 123200#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 123201#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124296#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 123504#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 123505#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122283#L844-45 assume 1 == ~t11_pc~0; 122285#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122818#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 122819#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 122836#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 123281#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 122323#L863-45 assume !(1 == ~t12_pc~0); 122325#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 121920#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121921#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122442#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 122443#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123289#L882-45 assume 1 == ~t13_pc~0; 123732#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 121939#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 121940#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 122553#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 123936#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123413#L1434-3 assume !(1 == ~M_E~0); 123414#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126993#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126990#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126988#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126986#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 126984#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 126982#L1464-3 assume !(1 == ~T7_E~0); 126980#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 126977#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 126975#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 126973#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 126971#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126969#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 126966#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 126964#L1504-3 assume !(1 == ~E_1~0); 126962#L1509-3 assume !(1 == ~E_2~0); 126961#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 126960#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 126959#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 126958#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 126957#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 126956#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 126955#L1544-3 assume !(1 == ~E_9~0); 125720#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 125719#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 125718#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 125717#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 125716#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 125710#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 125701#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125700#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 123488#L1954 assume !(0 == start_simulation_~tmp~3#1); 123490#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 125315#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 125295#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125285#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 125275#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 125263#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 125252#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 125238#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 124195#L1935-2 [2021-12-19 19:17:03,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:03,418 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2021-12-19 19:17:03,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:03,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275850595] [2021-12-19 19:17:03,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:03,418 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:03,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:03,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:03,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:03,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275850595] [2021-12-19 19:17:03,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275850595] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:03,447 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:03,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:03,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393495680] [2021-12-19 19:17:03,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:03,449 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:03,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:03,450 INFO L85 PathProgramCache]: Analyzing trace with hash -511897562, now seen corresponding path program 1 times [2021-12-19 19:17:03,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:03,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569769847] [2021-12-19 19:17:03,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:03,450 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:03,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:03,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:03,476 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:03,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569769847] [2021-12-19 19:17:03,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569769847] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:03,476 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:03,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:03,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142616569] [2021-12-19 19:17:03,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:03,477 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:03,477 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:03,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:03,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:03,478 INFO L87 Difference]: Start difference. First operand 7304 states and 10517 transitions. cyclomatic complexity: 3215 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:03,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:03,666 INFO L93 Difference]: Finished difference Result 17449 states and 24972 transitions. [2021-12-19 19:17:03,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:03,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17449 states and 24972 transitions. [2021-12-19 19:17:03,736 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17255 [2021-12-19 19:17:03,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17449 states to 17449 states and 24972 transitions. [2021-12-19 19:17:03,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17449 [2021-12-19 19:17:03,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17449 [2021-12-19 19:17:03,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17449 states and 24972 transitions. [2021-12-19 19:17:03,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:03,819 INFO L681 BuchiCegarLoop]: Abstraction has 17449 states and 24972 transitions. [2021-12-19 19:17:03,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17449 states and 24972 transitions. [2021-12-19 19:17:03,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17449 to 13952. [2021-12-19 19:17:03,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13952 states, 13952 states have (on average 1.4341313073394495) internal successors, (20009), 13951 states have internal predecessors, (20009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:04,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13952 states to 13952 states and 20009 transitions. [2021-12-19 19:17:04,006 INFO L704 BuchiCegarLoop]: Abstraction has 13952 states and 20009 transitions. [2021-12-19 19:17:04,006 INFO L587 BuchiCegarLoop]: Abstraction has 13952 states and 20009 transitions. [2021-12-19 19:17:04,006 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:04,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13952 states and 20009 transitions. [2021-12-19 19:17:04,045 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 13772 [2021-12-19 19:17:04,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:04,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:04,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:04,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:04,048 INFO L791 eck$LassoCheckResult]: Stem: 147559#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 147560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 147288#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 147289#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148864#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 148865#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 147478#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 147479#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 147513#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148414#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 148415#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 148554#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 148555#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 147294#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 147295#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 148603#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 147832#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 147833#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 148486#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148837#L1286 assume !(0 == ~M_E~0); 148678#L1286-2 assume !(0 == ~T1_E~0); 147203#L1291-1 assume !(0 == ~T2_E~0); 147204#L1296-1 assume !(0 == ~T3_E~0); 147934#L1301-1 assume !(0 == ~T4_E~0); 147935#L1306-1 assume !(0 == ~T5_E~0); 148495#L1311-1 assume !(0 == ~T6_E~0); 147163#L1316-1 assume !(0 == ~T7_E~0); 147164#L1321-1 assume !(0 == ~T8_E~0); 147955#L1326-1 assume !(0 == ~T9_E~0); 146978#L1331-1 assume !(0 == ~T10_E~0); 146685#L1336-1 assume !(0 == ~T11_E~0); 146686#L1341-1 assume !(0 == ~T12_E~0); 146737#L1346-1 assume !(0 == ~T13_E~0); 146738#L1351-1 assume !(0 == ~E_M~0); 147107#L1356-1 assume !(0 == ~E_1~0); 147108#L1361-1 assume !(0 == ~E_2~0); 148782#L1366-1 assume !(0 == ~E_3~0); 147156#L1371-1 assume !(0 == ~E_4~0); 147157#L1376-1 assume !(0 == ~E_5~0); 148005#L1381-1 assume !(0 == ~E_6~0); 148006#L1386-1 assume !(0 == ~E_7~0); 148820#L1391-1 assume !(0 == ~E_8~0); 148843#L1396-1 assume !(0 == ~E_9~0); 147868#L1401-1 assume !(0 == ~E_10~0); 147869#L1406-1 assume !(0 == ~E_11~0); 148203#L1411-1 assume !(0 == ~E_12~0); 148204#L1416-1 assume !(0 == ~E_13~0); 147786#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147620#L635 assume !(1 == ~m_pc~0); 146757#L635-2 is_master_triggered_~__retres1~0#1 := 0; 146758#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147104#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147749#L1598 assume !(0 != activate_threads_~tmp~1#1); 146933#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146934#L654 assume !(1 == ~t1_pc~0); 147729#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 148606#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148814#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147725#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 147726#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146984#L673 assume !(1 == ~t2_pc~0); 146986#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 148171#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148172#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 148875#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 148884#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147811#L692 assume !(1 == ~t3_pc~0); 147622#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 147623#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148840#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147449#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 147450#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147006#L711 assume !(1 == ~t4_pc~0); 147007#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 148595#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147978#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 146710#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 146711#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148863#L730 assume !(1 == ~t5_pc~0); 148100#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 146889#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 146890#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147015#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 147016#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147361#L749 assume 1 == ~t6_pc~0; 147131#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 146899#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147327#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 147328#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 147551#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146692#L768 assume !(1 == ~t7_pc~0); 146693#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 148028#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 146926#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 146927#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 148050#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 147165#L787 assume 1 == ~t8_pc~0; 147166#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148435#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 148637#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 148638#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 146735#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 146736#L806 assume 1 == ~t9_pc~0; 148449#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146770#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146771#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147017#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 147018#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 148422#L825 assume !(1 == ~t10_pc~0); 148423#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 147993#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147994#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 147105#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147106#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147691#L844 assume 1 == ~t11_pc~0; 147384#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 147385#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147755#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147756#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 148410#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 148411#L863 assume !(1 == ~t12_pc~0); 146874#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 146873#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 147095#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 148527#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 148528#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 147827#L882 assume 1 == ~t13_pc~0; 147828#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 148143#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 148732#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 148488#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 148130#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148131#L1434 assume !(1 == ~M_E~0); 148747#L1434-2 assume !(1 == ~T1_E~0); 148874#L1439-1 assume !(1 == ~T2_E~0); 146999#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147000#L1449-1 assume !(1 == ~T4_E~0); 147447#L1454-1 assume !(1 == ~T5_E~0); 147448#L1459-1 assume !(1 == ~T6_E~0); 148051#L1464-1 assume !(1 == ~T7_E~0); 148052#L1469-1 assume !(1 == ~T8_E~0); 148146#L1474-1 assume !(1 == ~T9_E~0); 147787#L1479-1 assume !(1 == ~T10_E~0); 147788#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 148061#L1489-1 assume !(1 == ~T12_E~0); 147657#L1494-1 assume !(1 == ~T13_E~0); 147658#L1499-1 assume !(1 == ~E_M~0); 147851#L1504-1 assume !(1 == ~E_1~0); 147852#L1509-1 assume !(1 == ~E_2~0); 148546#L1514-1 assume !(1 == ~E_3~0); 148184#L1519-1 assume !(1 == ~E_4~0); 148185#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 148795#L1529-1 assume !(1 == ~E_6~0); 148796#L1534-1 assume !(1 == ~E_7~0); 146792#L1539-1 assume !(1 == ~E_8~0); 146793#L1544-1 assume !(1 == ~E_9~0); 147221#L1549-1 assume !(1 == ~E_10~0); 148767#L1554-1 assume !(1 == ~E_11~0); 148765#L1559-1 assume !(1 == ~E_12~0); 148583#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 148584#L1569-1 assume { :end_inline_reset_delta_events } true; 148789#L1935-2 [2021-12-19 19:17:04,048 INFO L793 eck$LassoCheckResult]: Loop: 148789#L1935-2 assume !false; 146799#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146800#L1261 assume !false; 148068#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148069#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146929#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 147097#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 147098#L1074 assume !(0 != eval_~tmp~0#1); 147460#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148095#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148550#L1286-3 assume !(0 == ~M_E~0); 148626#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 160442#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 160441#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148839#L1301-3 assume !(0 == ~T4_E~0); 148774#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 147739#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147740#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 160438#L1321-3 assume !(0 == ~T8_E~0); 160437#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 148759#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 148760#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 160414#L1341-3 assume !(0 == ~T12_E~0); 160412#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 160410#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 160408#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 147982#L1361-3 assume !(0 == ~E_2~0); 147983#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146725#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 146726#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 148564#L1381-3 assume !(0 == ~E_6~0); 148382#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 148383#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 148607#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 148608#L1401-3 assume !(0 == ~E_10~0); 147101#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 146935#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 146936#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 147566#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146815#L635-45 assume 1 == ~m_pc~0; 146816#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 147610#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148132#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148409#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147119#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147120#L654-45 assume !(1 == ~t1_pc~0); 147970#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 148355#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146777#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 146778#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146803#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 147633#L673-45 assume !(1 == ~t2_pc~0); 147634#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 147986#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 147987#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 148709#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 148485#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147248#L692-45 assume 1 == ~t3_pc~0; 147249#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 148835#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148056#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 148057#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147303#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147619#L711-45 assume !(1 == ~t4_pc~0); 147821#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 147822#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147594#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147595#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148029#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147146#L730-45 assume !(1 == ~t5_pc~0); 146983#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 146982#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147396#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147397#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 148193#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 146957#L749-45 assume !(1 == ~t6_pc~0); 146958#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 148425#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 148165#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 148166#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 148334#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147274#L768-45 assume 1 == ~t7_pc~0; 147275#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 147415#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 148269#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 148270#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 148312#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 148313#L787-45 assume 1 == ~t8_pc~0; 148516#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 147423#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147424#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147849#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 147850#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 148192#L806-45 assume 1 == ~t9_pc~0; 148769#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146834#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 147659#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147490#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147400#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147401#L825-45 assume 1 == ~t10_pc~0; 148047#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 147949#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 148066#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148067#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 148229#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147040#L844-45 assume 1 == ~t11_pc~0; 147042#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 147567#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147568#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 147584#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 148026#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 147079#L863-45 assume 1 == ~t12_pc~0; 147080#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 146683#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 146684#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 147198#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 147199#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 148031#L882-45 assume 1 == ~t13_pc~0; 148419#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 146702#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 146703#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 147312#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 148594#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148149#L1434-3 assume !(1 == ~M_E~0); 148150#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 148354#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146995#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146996#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147158#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 148139#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 148140#L1464-3 assume !(1 == ~T7_E~0); 148659#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 148566#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 148567#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 148662#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147744#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 147745#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 148482#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 148072#L1504-3 assume !(1 == ~E_1~0); 148073#L1509-3 assume !(1 == ~E_2~0); 148577#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 148630#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147660#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147661#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 148689#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147992#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 147416#L1544-3 assume !(1 == ~E_9~0); 147417#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 147956#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 147045#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 147046#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 148245#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148246#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146931#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 147500#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 148217#L1954 assume !(0 == start_simulation_~tmp~3#1); 148219#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148506#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 147215#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148310#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 148461#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148462#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148575#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 148652#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 148789#L1935-2 [2021-12-19 19:17:04,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:04,049 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2021-12-19 19:17:04,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:04,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333171942] [2021-12-19 19:17:04,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:04,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:04,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:04,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:04,079 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:04,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333171942] [2021-12-19 19:17:04,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1333171942] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:04,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:04,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:04,080 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486412690] [2021-12-19 19:17:04,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:04,080 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:04,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:04,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1201619743, now seen corresponding path program 1 times [2021-12-19 19:17:04,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:04,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239408577] [2021-12-19 19:17:04,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:04,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:04,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:04,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:04,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:04,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239408577] [2021-12-19 19:17:04,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239408577] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:04,116 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:04,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:04,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565636113] [2021-12-19 19:17:04,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:04,117 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:04,117 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:04,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:04,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:04,118 INFO L87 Difference]: Start difference. First operand 13952 states and 20009 transitions. cyclomatic complexity: 6059 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:04,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:04,427 INFO L93 Difference]: Finished difference Result 33428 states and 47673 transitions. [2021-12-19 19:17:04,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:04,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33428 states and 47673 transitions. [2021-12-19 19:17:04,567 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 33217 [2021-12-19 19:17:04,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33428 states to 33428 states and 47673 transitions. [2021-12-19 19:17:04,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33428 [2021-12-19 19:17:04,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33428 [2021-12-19 19:17:04,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33428 states and 47673 transitions. [2021-12-19 19:17:04,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:04,715 INFO L681 BuchiCegarLoop]: Abstraction has 33428 states and 47673 transitions. [2021-12-19 19:17:04,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33428 states and 47673 transitions. [2021-12-19 19:17:05,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33428 to 26779. [2021-12-19 19:17:05,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26779 states, 26779 states have (on average 1.4289555248515629) internal successors, (38266), 26778 states have internal predecessors, (38266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:05,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26779 states to 26779 states and 38266 transitions. [2021-12-19 19:17:05,274 INFO L704 BuchiCegarLoop]: Abstraction has 26779 states and 38266 transitions. [2021-12-19 19:17:05,274 INFO L587 BuchiCegarLoop]: Abstraction has 26779 states and 38266 transitions. [2021-12-19 19:17:05,274 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:05,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26779 states and 38266 transitions. [2021-12-19 19:17:05,356 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26596 [2021-12-19 19:17:05,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:05,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:05,359 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:05,359 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:05,360 INFO L791 eck$LassoCheckResult]: Stem: 194939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 194940#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 194674#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 194675#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196220#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 196221#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194860#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194861#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194894#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 195792#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 195793#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 195928#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 195929#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 194680#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 194681#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 195974#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 195212#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 195213#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 195855#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196195#L1286 assume !(0 == ~M_E~0); 196046#L1286-2 assume !(0 == ~T1_E~0); 194590#L1291-1 assume !(0 == ~T2_E~0); 194591#L1296-1 assume !(0 == ~T3_E~0); 195310#L1301-1 assume !(0 == ~T4_E~0); 195311#L1306-1 assume !(0 == ~T5_E~0); 195864#L1311-1 assume !(0 == ~T6_E~0); 194550#L1316-1 assume !(0 == ~T7_E~0); 194551#L1321-1 assume !(0 == ~T8_E~0); 195330#L1326-1 assume !(0 == ~T9_E~0); 194367#L1331-1 assume !(0 == ~T10_E~0); 194075#L1336-1 assume !(0 == ~T11_E~0); 194076#L1341-1 assume !(0 == ~T12_E~0); 194127#L1346-1 assume !(0 == ~T13_E~0); 194128#L1351-1 assume !(0 == ~E_M~0); 194496#L1356-1 assume !(0 == ~E_1~0); 194497#L1361-1 assume !(0 == ~E_2~0); 196144#L1366-1 assume !(0 == ~E_3~0); 194543#L1371-1 assume !(0 == ~E_4~0); 194544#L1376-1 assume !(0 == ~E_5~0); 195373#L1381-1 assume !(0 == ~E_6~0); 195374#L1386-1 assume !(0 == ~E_7~0); 196179#L1391-1 assume !(0 == ~E_8~0); 196204#L1396-1 assume !(0 == ~E_9~0); 195249#L1401-1 assume !(0 == ~E_10~0); 195250#L1406-1 assume !(0 == ~E_11~0); 195572#L1411-1 assume !(0 == ~E_12~0); 195573#L1416-1 assume !(0 == ~E_13~0); 195167#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195002#L635 assume !(1 == ~m_pc~0); 194145#L635-2 is_master_triggered_~__retres1~0#1 := 0; 194146#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194491#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 195131#L1598 assume !(0 != activate_threads_~tmp~1#1); 194323#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194324#L654 assume !(1 == ~t1_pc~0); 195112#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 195976#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196175#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 195110#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 195111#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194370#L673 assume !(1 == ~t2_pc~0); 194372#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 195537#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 195538#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 196234#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 196246#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195191#L692 assume !(1 == ~t3_pc~0); 195004#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 195005#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196198#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 194829#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 194830#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194395#L711 assume !(1 == ~t4_pc~0); 194396#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 195966#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195349#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 194100#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 194101#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196219#L730 assume !(1 == ~t5_pc~0); 195471#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 194279#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194280#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 194404#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 194405#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194743#L749 assume !(1 == ~t6_pc~0); 194283#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 194284#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194711#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 194712#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 194931#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194080#L768 assume !(1 == ~t7_pc~0); 194081#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 195398#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194316#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 194317#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 195420#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 194552#L787 assume 1 == ~t8_pc~0; 194553#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 195809#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 196005#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 196006#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 194125#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 194126#L806 assume 1 == ~t9_pc~0; 195820#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 194160#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 194161#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 194406#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 194407#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 195800#L825 assume !(1 == ~t10_pc~0); 195801#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 195363#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 195364#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 194492#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 194493#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 195075#L844 assume 1 == ~t11_pc~0; 194764#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 194765#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 195137#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 195138#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 195787#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 195788#L863 assume !(1 == ~t12_pc~0); 194260#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 194259#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 194482#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 195895#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 195896#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 195207#L882 assume 1 == ~t13_pc~0; 195208#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 195510#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 196099#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 195857#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 195497#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 195498#L1434 assume !(1 == ~M_E~0); 196113#L1434-2 assume !(1 == ~T1_E~0); 196233#L1439-1 assume !(1 == ~T2_E~0); 194388#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194389#L1449-1 assume !(1 == ~T4_E~0); 194826#L1454-1 assume !(1 == ~T5_E~0); 194827#L1459-1 assume !(1 == ~T6_E~0); 195421#L1464-1 assume !(1 == ~T7_E~0); 195422#L1469-1 assume !(1 == ~T8_E~0); 195511#L1474-1 assume !(1 == ~T9_E~0); 195168#L1479-1 assume !(1 == ~T10_E~0); 195169#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 195430#L1489-1 assume !(1 == ~T12_E~0); 195040#L1494-1 assume !(1 == ~T13_E~0); 195041#L1499-1 assume !(1 == ~E_M~0); 195232#L1504-1 assume !(1 == ~E_1~0); 195233#L1509-1 assume !(1 == ~E_2~0); 195913#L1514-1 assume !(1 == ~E_3~0); 195551#L1519-1 assume !(1 == ~E_4~0); 195552#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 196158#L1529-1 assume !(1 == ~E_6~0); 196159#L1534-1 assume !(1 == ~E_7~0); 194180#L1539-1 assume !(1 == ~E_8~0); 194181#L1544-1 assume !(1 == ~E_9~0); 194607#L1549-1 assume !(1 == ~E_10~0); 196131#L1554-1 assume !(1 == ~E_11~0); 196129#L1559-1 assume !(1 == ~E_12~0); 195951#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 195952#L1569-1 assume { :end_inline_reset_delta_events } true; 196152#L1935-2 [2021-12-19 19:17:05,360 INFO L793 eck$LassoCheckResult]: Loop: 196152#L1935-2 assume !false; 194189#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 194190#L1261 assume !false; 195435#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 195436#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 194319#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 194485#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 194486#L1074 assume !(0 != eval_~tmp~0#1); 194842#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 195920#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195921#L1286-3 assume !(0 == ~M_E~0); 195992#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220488#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220487#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220486#L1301-3 assume !(0 == ~T4_E~0); 220485#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220484#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220482#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220479#L1321-3 assume !(0 == ~T8_E~0); 220477#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220475#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 220473#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 220472#L1341-3 assume !(0 == ~T12_E~0); 220471#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 220469#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220467#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220465#L1361-3 assume !(0 == ~E_2~0); 220463#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 220461#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 220459#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220456#L1381-3 assume !(0 == ~E_6~0); 220454#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220452#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 220450#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 220449#L1401-3 assume !(0 == ~E_10~0); 220448#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 220447#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 220446#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 220445#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220443#L635-45 assume !(1 == ~m_pc~0); 220417#L635-47 is_master_triggered_~__retres1~0#1 := 0; 220414#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196030#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 195786#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 194508#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194509#L654-45 assume !(1 == ~t1_pc~0); 195346#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 195727#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194167#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 194168#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 194193#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 195015#L673-45 assume !(1 == ~t2_pc~0); 195016#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 195356#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 195357#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 196074#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 195853#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195854#L692-45 assume !(1 == ~t3_pc~0); 220801#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 220803#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220802#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220797#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 220795#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220794#L711-45 assume !(1 == ~t4_pc~0); 219136#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 220793#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220792#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220791#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220790#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220789#L730-45 assume 1 == ~t5_pc~0; 220787#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 220786#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220785#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 220784#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 220783#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220782#L749-45 assume !(1 == ~t6_pc~0); 205764#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 220781#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220780#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220779#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220778#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220777#L768-45 assume 1 == ~t7_pc~0; 220775#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 220774#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220773#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 220772#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 220771#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220770#L787-45 assume 1 == ~t8_pc~0; 220769#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 220767#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220766#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 220765#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 220764#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220763#L806-45 assume !(1 == ~t9_pc~0); 220762#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 220760#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 220757#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 220756#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 220755#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 220754#L825-45 assume 1 == ~t10_pc~0; 220753#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 220147#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 195437#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 195438#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 195599#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 194429#L844-45 assume !(1 == ~t11_pc~0); 194430#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 194947#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 194948#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 194964#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 195396#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 194468#L863-45 assume !(1 == ~t12_pc~0); 194470#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 194073#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 194074#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 194585#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 194586#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 195405#L882-45 assume !(1 == ~t13_pc~0); 194912#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 194092#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 194093#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 194695#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 195965#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 195516#L1434-3 assume !(1 == ~M_E~0); 195517#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 195725#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 194384#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194385#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 194545#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 195506#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 195507#L1464-3 assume !(1 == ~T7_E~0); 196031#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 195938#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 195939#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 196033#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 195126#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 195127#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 219119#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 219118#L1504-3 assume !(1 == ~E_1~0); 219117#L1509-3 assume !(1 == ~E_2~0); 219116#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 219112#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 219111#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 219110#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 219108#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 218821#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 218767#L1544-3 assume !(1 == ~E_9~0); 218762#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 218757#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 218752#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 218749#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 218747#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 218685#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 218654#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 218646#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 195587#L1954 assume !(0 == start_simulation_~tmp~3#1); 195589#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 195875#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 194601#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 195682#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 195833#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 195834#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 195946#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 196023#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 196152#L1935-2 [2021-12-19 19:17:05,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:05,360 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2021-12-19 19:17:05,361 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:05,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452920300] [2021-12-19 19:17:05,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:05,361 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:05,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:05,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:05,390 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:05,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452920300] [2021-12-19 19:17:05,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452920300] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:05,391 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:05,391 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:05,391 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119372453] [2021-12-19 19:17:05,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:05,392 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:05,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:05,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1971999578, now seen corresponding path program 1 times [2021-12-19 19:17:05,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:05,393 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800185521] [2021-12-19 19:17:05,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:05,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:05,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:05,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:05,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:05,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800185521] [2021-12-19 19:17:05,428 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800185521] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:05,428 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:05,428 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:05,428 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796573260] [2021-12-19 19:17:05,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:05,429 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:05,429 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:05,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:05,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:05,429 INFO L87 Difference]: Start difference. First operand 26779 states and 38266 transitions. cyclomatic complexity: 11489 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:05,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:05,874 INFO L93 Difference]: Finished difference Result 64114 states and 91135 transitions. [2021-12-19 19:17:05,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:05,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64114 states and 91135 transitions. [2021-12-19 19:17:06,297 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 63868 [2021-12-19 19:17:06,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64114 states to 64114 states and 91135 transitions. [2021-12-19 19:17:06,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64114 [2021-12-19 19:17:06,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64114 [2021-12-19 19:17:06,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64114 states and 91135 transitions. [2021-12-19 19:17:06,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:06,574 INFO L681 BuchiCegarLoop]: Abstraction has 64114 states and 91135 transitions. [2021-12-19 19:17:06,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64114 states and 91135 transitions. [2021-12-19 19:17:07,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64114 to 51502. [2021-12-19 19:17:07,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51502 states, 51502 states have (on average 1.424158285115141) internal successors, (73347), 51501 states have internal predecessors, (73347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:07,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51502 states to 51502 states and 73347 transitions. [2021-12-19 19:17:07,459 INFO L704 BuchiCegarLoop]: Abstraction has 51502 states and 73347 transitions. [2021-12-19 19:17:07,459 INFO L587 BuchiCegarLoop]: Abstraction has 51502 states and 73347 transitions. [2021-12-19 19:17:07,459 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:07,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51502 states and 73347 transitions. [2021-12-19 19:17:07,698 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51312 [2021-12-19 19:17:07,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:07,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:07,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:07,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:07,731 INFO L791 eck$LassoCheckResult]: Stem: 285842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 285843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 285579#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285580#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 287154#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 287155#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285763#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 285764#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 285797#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 286703#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 286704#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 286835#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 286836#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 285585#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 285586#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 286888#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 286119#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 286120#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 286762#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 287126#L1286 assume !(0 == ~M_E~0); 286962#L1286-2 assume !(0 == ~T1_E~0); 285495#L1291-1 assume !(0 == ~T2_E~0); 285496#L1296-1 assume !(0 == ~T3_E~0); 286219#L1301-1 assume !(0 == ~T4_E~0); 286220#L1306-1 assume !(0 == ~T5_E~0); 286775#L1311-1 assume !(0 == ~T6_E~0); 285455#L1316-1 assume !(0 == ~T7_E~0); 285456#L1321-1 assume !(0 == ~T8_E~0); 286238#L1326-1 assume !(0 == ~T9_E~0); 285270#L1331-1 assume !(0 == ~T10_E~0); 284978#L1336-1 assume !(0 == ~T11_E~0); 284979#L1341-1 assume !(0 == ~T12_E~0); 285030#L1346-1 assume !(0 == ~T13_E~0); 285031#L1351-1 assume !(0 == ~E_M~0); 285400#L1356-1 assume !(0 == ~E_1~0); 285401#L1361-1 assume !(0 == ~E_2~0); 287072#L1366-1 assume !(0 == ~E_3~0); 285448#L1371-1 assume !(0 == ~E_4~0); 285449#L1376-1 assume !(0 == ~E_5~0); 286283#L1381-1 assume !(0 == ~E_6~0); 286284#L1386-1 assume !(0 == ~E_7~0); 287112#L1391-1 assume !(0 == ~E_8~0); 287137#L1396-1 assume !(0 == ~E_9~0); 286155#L1401-1 assume !(0 == ~E_10~0); 286156#L1406-1 assume !(0 == ~E_11~0); 286482#L1411-1 assume !(0 == ~E_12~0); 286483#L1416-1 assume !(0 == ~E_13~0); 286074#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285906#L635 assume !(1 == ~m_pc~0); 285050#L635-2 is_master_triggered_~__retres1~0#1 := 0; 285051#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285397#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 286037#L1598 assume !(0 != activate_threads_~tmp~1#1); 285226#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 285227#L654 assume !(1 == ~t1_pc~0); 286019#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 286890#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 287104#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 286015#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 286016#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285276#L673 assume !(1 == ~t2_pc~0); 285278#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 286447#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286448#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 287167#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 287184#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286098#L692 assume !(1 == ~t3_pc~0); 285908#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 285909#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 287130#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 285731#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 285732#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 285298#L711 assume !(1 == ~t4_pc~0); 285299#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 286880#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 286258#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 285003#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 285004#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 287153#L730 assume !(1 == ~t5_pc~0); 286380#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 285183#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285184#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 285307#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 285308#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285647#L749 assume !(1 == ~t6_pc~0); 285191#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 285192#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 285614#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 285615#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 285834#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 284985#L768 assume !(1 == ~t7_pc~0); 284986#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 286307#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 285219#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 285220#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 286329#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 285457#L787 assume !(1 == ~t8_pc~0); 285458#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 286973#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 286919#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 286920#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 285028#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 285029#L806 assume 1 == ~t9_pc~0; 286733#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 285063#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 285064#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 285309#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 285310#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 286711#L825 assume !(1 == ~t10_pc~0); 286712#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 286272#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 286273#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 285398#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 285399#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 285980#L844 assume 1 == ~t11_pc~0; 285670#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 285671#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 286043#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 286044#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 286699#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 286700#L863 assume !(1 == ~t12_pc~0); 285168#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 285167#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 285388#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 286805#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 286806#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 286114#L882 assume 1 == ~t13_pc~0; 286115#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 286419#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 287021#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 286764#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 286406#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 286407#L1434 assume !(1 == ~M_E~0); 287036#L1434-2 assume !(1 == ~T1_E~0); 287166#L1439-1 assume !(1 == ~T2_E~0); 285291#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 285292#L1449-1 assume !(1 == ~T4_E~0); 285729#L1454-1 assume !(1 == ~T5_E~0); 285730#L1459-1 assume !(1 == ~T6_E~0); 286330#L1464-1 assume !(1 == ~T7_E~0); 286331#L1469-1 assume !(1 == ~T8_E~0); 286422#L1474-1 assume !(1 == ~T9_E~0); 286075#L1479-1 assume !(1 == ~T10_E~0); 286076#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 286340#L1489-1 assume !(1 == ~T12_E~0); 285944#L1494-1 assume !(1 == ~T13_E~0); 285945#L1499-1 assume !(1 == ~E_M~0); 286138#L1504-1 assume !(1 == ~E_1~0); 286139#L1509-1 assume !(1 == ~E_2~0); 286824#L1514-1 assume !(1 == ~E_3~0); 286460#L1519-1 assume !(1 == ~E_4~0); 286461#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 287087#L1529-1 assume !(1 == ~E_6~0); 287088#L1534-1 assume !(1 == ~E_7~0); 285085#L1539-1 assume !(1 == ~E_8~0); 285086#L1544-1 assume !(1 == ~E_9~0); 285513#L1549-1 assume !(1 == ~E_10~0); 287052#L1554-1 assume !(1 == ~E_11~0); 287050#L1559-1 assume !(1 == ~E_12~0); 286868#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 286869#L1569-1 assume { :end_inline_reset_delta_events } true; 287081#L1935-2 [2021-12-19 19:17:07,732 INFO L793 eck$LassoCheckResult]: Loop: 287081#L1935-2 assume !false; 285092#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 285093#L1261 assume !false; 286346#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 286347#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 285222#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 285390#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 285391#L1074 assume !(0 != eval_~tmp~0#1); 285744#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286375#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 286828#L1286-3 assume !(0 == ~M_E~0); 286908#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 286568#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 286569#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 287128#L1301-3 assume !(0 == ~T4_E~0); 287062#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 287063#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 334648#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 334647#L1321-3 assume !(0 == ~T8_E~0); 334646#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 287046#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 287047#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 333334#L1341-3 assume !(0 == ~T12_E~0); 333332#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 333330#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 333328#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 333325#L1361-3 assume !(0 == ~E_2~0); 333323#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 333321#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 333319#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 333317#L1381-3 assume !(0 == ~E_6~0); 333315#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 333313#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 333311#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 333309#L1401-3 assume !(0 == ~E_10~0); 333307#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 333305#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 333302#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 333300#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333299#L635-45 assume 1 == ~m_pc~0; 333297#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 333296#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333295#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 333280#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 333278#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333276#L654-45 assume !(1 == ~t1_pc~0); 333274#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 333272#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333042#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 333041#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 333040#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333039#L673-45 assume !(1 == ~t2_pc~0); 333037#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 333036#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333035#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 333034#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 333033#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333032#L692-45 assume 1 == ~t3_pc~0; 333031#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 333029#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333027#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 333024#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 333023#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 287215#L711-45 assume !(1 == ~t4_pc~0); 286109#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 286110#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 285880#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 285881#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 286308#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285438#L730-45 assume 1 == ~t5_pc~0; 285273#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 285274#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285681#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 285682#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 286472#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285250#L749-45 assume !(1 == ~t6_pc~0); 285251#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 336025#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336022#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336020#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 336018#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336016#L768-45 assume !(1 == ~t7_pc~0); 336011#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 336008#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336006#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 336004#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 336002#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 336000#L787-45 assume !(1 == ~t8_pc~0); 294126#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 335996#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 335994#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 335992#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 286470#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 286471#L806-45 assume !(1 == ~t9_pc~0); 285125#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 285126#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 285946#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 285775#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 285685#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 285686#L825-45 assume 1 == ~t10_pc~0; 286326#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 286232#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 286344#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 286345#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 286509#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 285333#L844-45 assume !(1 == ~t11_pc~0); 285334#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 285850#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285851#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 285869#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 286305#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 285372#L863-45 assume 1 == ~t12_pc~0; 285373#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 284976#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 284977#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 285490#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 285491#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 286311#L882-45 assume 1 == ~t13_pc~0; 286708#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 284995#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 284996#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 285600#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 286879#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 286425#L1434-3 assume !(1 == ~M_E~0); 286426#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 286636#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 285287#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 285288#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 285450#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 335627#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 335450#L1464-3 assume !(1 == ~T7_E~0); 334862#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 334861#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 334860#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 334859#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 334858#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 334857#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 334856#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 334754#L1504-3 assume !(1 == ~E_1~0); 286861#L1509-3 assume !(1 == ~E_2~0); 286862#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 286912#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 285947#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 285948#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 286971#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 286271#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 285700#L1544-3 assume !(1 == ~E_9~0); 285701#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 286239#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 285338#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 285339#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 286525#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 286526#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 285224#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 285784#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 286497#L1954 assume !(0 == start_simulation_~tmp~3#1); 286499#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 286784#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 285507#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 286592#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 286745#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 286746#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 286854#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 286939#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 287081#L1935-2 [2021-12-19 19:17:07,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:07,732 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2021-12-19 19:17:07,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:07,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992084211] [2021-12-19 19:17:07,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:07,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:07,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:07,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:07,775 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:07,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992084211] [2021-12-19 19:17:07,775 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992084211] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:07,775 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:07,775 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:07,775 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281247827] [2021-12-19 19:17:07,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:07,776 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:07,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:07,776 INFO L85 PathProgramCache]: Analyzing trace with hash -605450014, now seen corresponding path program 1 times [2021-12-19 19:17:07,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:07,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759257798] [2021-12-19 19:17:07,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:07,777 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:07,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:07,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:07,800 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:07,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [759257798] [2021-12-19 19:17:07,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [759257798] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:07,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:07,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:07,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280987276] [2021-12-19 19:17:07,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:07,801 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:07,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:07,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:07,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:07,802 INFO L87 Difference]: Start difference. First operand 51502 states and 73347 transitions. cyclomatic complexity: 21847 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:08,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:08,370 INFO L93 Difference]: Finished difference Result 123185 states and 174556 transitions. [2021-12-19 19:17:08,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:08,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123185 states and 174556 transitions. [2021-12-19 19:17:09,057 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 122868 [2021-12-19 19:17:09,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123185 states to 123185 states and 174556 transitions. [2021-12-19 19:17:09,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123185 [2021-12-19 19:17:09,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123185 [2021-12-19 19:17:09,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123185 states and 174556 transitions. [2021-12-19 19:17:09,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:09,579 INFO L681 BuchiCegarLoop]: Abstraction has 123185 states and 174556 transitions. [2021-12-19 19:17:09,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123185 states and 174556 transitions. [2021-12-19 19:17:10,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123185 to 99101. [2021-12-19 19:17:10,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99101 states, 99101 states have (on average 1.419642586855834) internal successors, (140688), 99100 states have internal predecessors, (140688), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:11,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99101 states to 99101 states and 140688 transitions. [2021-12-19 19:17:11,125 INFO L704 BuchiCegarLoop]: Abstraction has 99101 states and 140688 transitions. [2021-12-19 19:17:11,125 INFO L587 BuchiCegarLoop]: Abstraction has 99101 states and 140688 transitions. [2021-12-19 19:17:11,125 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:17:11,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99101 states and 140688 transitions. [2021-12-19 19:17:11,378 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 98896 [2021-12-19 19:17:11,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:11,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:11,386 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:11,386 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:11,386 INFO L791 eck$LassoCheckResult]: Stem: 460546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 460547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 460277#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 460278#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 461909#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 461910#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 460463#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 460464#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 460500#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 461409#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 461410#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 461565#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 461566#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 460283#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 460284#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 461622#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 460823#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 460824#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 461477#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 461878#L1286 assume !(0 == ~M_E~0); 461702#L1286-2 assume !(0 == ~T1_E~0); 460191#L1291-1 assume !(0 == ~T2_E~0); 460192#L1296-1 assume !(0 == ~T3_E~0); 460921#L1301-1 assume !(0 == ~T4_E~0); 460922#L1306-1 assume !(0 == ~T5_E~0); 461491#L1311-1 assume !(0 == ~T6_E~0); 460152#L1316-1 assume !(0 == ~T7_E~0); 460153#L1321-1 assume !(0 == ~T8_E~0); 460941#L1326-1 assume !(0 == ~T9_E~0); 459966#L1331-1 assume !(0 == ~T10_E~0); 459675#L1336-1 assume !(0 == ~T11_E~0); 459676#L1341-1 assume !(0 == ~T12_E~0); 459727#L1346-1 assume !(0 == ~T13_E~0); 459728#L1351-1 assume !(0 == ~E_M~0); 460098#L1356-1 assume !(0 == ~E_1~0); 460099#L1361-1 assume !(0 == ~E_2~0); 461816#L1366-1 assume !(0 == ~E_3~0); 460144#L1371-1 assume !(0 == ~E_4~0); 460145#L1376-1 assume !(0 == ~E_5~0); 460987#L1381-1 assume !(0 == ~E_6~0); 460988#L1386-1 assume !(0 == ~E_7~0); 461859#L1391-1 assume !(0 == ~E_8~0); 461890#L1396-1 assume !(0 == ~E_9~0); 460859#L1401-1 assume !(0 == ~E_10~0); 460860#L1406-1 assume !(0 == ~E_11~0); 461186#L1411-1 assume !(0 == ~E_12~0); 461187#L1416-1 assume !(0 == ~E_13~0); 460777#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 460609#L635 assume !(1 == ~m_pc~0); 459745#L635-2 is_master_triggered_~__retres1~0#1 := 0; 459746#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 460091#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 460740#L1598 assume !(0 != activate_threads_~tmp~1#1); 459922#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459923#L654 assume !(1 == ~t1_pc~0); 460719#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 461624#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 461856#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 460717#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 460718#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 459969#L673 assume !(1 == ~t2_pc~0); 459971#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 461152#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 461153#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 461921#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 461937#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 460801#L692 assume !(1 == ~t3_pc~0); 460611#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 460612#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 461886#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 460432#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 460433#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 459994#L711 assume !(1 == ~t4_pc~0); 459995#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 461613#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 460962#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 459700#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 459701#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 461907#L730 assume !(1 == ~t5_pc~0); 461085#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 459879#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 459880#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 460003#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 460004#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 460345#L749 assume !(1 == ~t6_pc~0); 459883#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 459884#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 460313#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 460314#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 460538#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 459680#L768 assume !(1 == ~t7_pc~0); 459681#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 461014#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 459915#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 459916#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 461033#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 460154#L787 assume !(1 == ~t8_pc~0); 460155#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 461713#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461658#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 461659#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 459725#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 459726#L806 assume !(1 == ~t9_pc~0); 460513#L806-2 is_transmit9_triggered_~__retres1~9#1 := 0; 459760#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 459761#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 460005#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 460006#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 461417#L825 assume !(1 == ~t10_pc~0); 461418#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 460976#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 460977#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 460092#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 460093#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 460682#L844 assume 1 == ~t11_pc~0; 460367#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 460368#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460746#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 460747#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 461405#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 461406#L863 assume !(1 == ~t12_pc~0); 459860#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 459859#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 460082#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 461526#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 461527#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 460818#L882 assume 1 == ~t13_pc~0; 460819#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 461124#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 461769#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 461479#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 461111#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 461112#L1434 assume !(1 == ~M_E~0); 461781#L1434-2 assume !(1 == ~T1_E~0); 461920#L1439-1 assume !(1 == ~T2_E~0); 459987#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 459988#L1449-1 assume !(1 == ~T4_E~0); 460429#L1454-1 assume !(1 == ~T5_E~0); 460430#L1459-1 assume !(1 == ~T6_E~0); 461034#L1464-1 assume !(1 == ~T7_E~0); 461035#L1469-1 assume !(1 == ~T8_E~0); 461125#L1474-1 assume !(1 == ~T9_E~0); 460778#L1479-1 assume !(1 == ~T10_E~0); 460779#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 461043#L1489-1 assume !(1 == ~T12_E~0); 460646#L1494-1 assume !(1 == ~T13_E~0); 460647#L1499-1 assume !(1 == ~E_M~0); 460843#L1504-1 assume !(1 == ~E_1~0); 460844#L1509-1 assume !(1 == ~E_2~0); 461550#L1514-1 assume !(1 == ~E_3~0); 461166#L1519-1 assume !(1 == ~E_4~0); 461167#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 461832#L1529-1 assume !(1 == ~E_6~0); 461833#L1534-1 assume !(1 == ~E_7~0); 459780#L1539-1 assume !(1 == ~E_8~0); 459781#L1544-1 assume !(1 == ~E_9~0); 460210#L1549-1 assume !(1 == ~E_10~0); 461798#L1554-1 assume !(1 == ~E_11~0); 461796#L1559-1 assume !(1 == ~E_12~0); 461597#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 461598#L1569-1 assume { :end_inline_reset_delta_events } true; 461825#L1935-2 [2021-12-19 19:17:11,387 INFO L793 eck$LassoCheckResult]: Loop: 461825#L1935-2 assume !false; 459789#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 459790#L1261 assume !false; 461048#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 461049#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 459918#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 460085#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 460086#L1074 assume !(0 != eval_~tmp~0#1); 460445#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 461079#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 461558#L1286-3 assume !(0 == ~M_E~0); 461641#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 461272#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 461273#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 461883#L1301-3 assume !(0 == ~T4_E~0); 461809#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 460732#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 460021#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 460022#L1321-3 assume !(0 == ~T8_E~0); 460129#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 460883#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 461169#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 461170#L1341-3 assume !(0 == ~T12_E~0); 460422#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 460413#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 460356#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 460357#L1361-3 assume !(0 == ~E_2~0); 460966#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 459715#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 459716#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 461575#L1381-3 assume !(0 == ~E_6~0); 461376#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 461377#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 461625#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 461626#L1401-3 assume !(0 == ~E_10~0); 460090#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 459924#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 459925#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 460553#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 459804#L635-45 assume !(1 == ~m_pc~0); 459806#L635-47 is_master_triggered_~__retres1~0#1 := 0; 460599#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 461113#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 461404#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 460110#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 460111#L654-45 assume !(1 == ~t1_pc~0); 460959#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 461344#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 459767#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 459768#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 459793#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 460622#L673-45 assume !(1 == ~t2_pc~0); 460623#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 460969#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 460970#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 461739#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 461476#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 460237#L692-45 assume !(1 == ~t3_pc~0); 460239#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 557686#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 461039#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 460290#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 460291#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 460608#L711-45 assume !(1 == ~t4_pc~0); 461965#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 552463#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 552462#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 550076#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 550074#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 550073#L730-45 assume !(1 == ~t5_pc~0); 550072#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 550068#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 550066#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 550064#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 550062#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 459946#L749-45 assume !(1 == ~t6_pc~0); 459947#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 461510#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 461146#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 461147#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 461323#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 460263#L768-45 assume !(1 == ~t7_pc~0); 460265#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 460398#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 461255#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 461256#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 461302#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 461303#L787-45 assume !(1 == ~t8_pc~0); 461943#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 460405#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 460406#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 460841#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 460842#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 461174#L806-45 assume !(1 == ~t9_pc~0); 459822#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 459823#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 460648#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 460478#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 460384#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 460385#L825-45 assume 1 == ~t10_pc~0; 461030#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 460935#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 461050#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 461051#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 461213#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 460029#L844-45 assume 1 == ~t11_pc~0; 460031#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 460554#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460555#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 460572#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 461012#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 460068#L863-45 assume !(1 == ~t12_pc~0); 460070#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 459673#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 459674#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 460186#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 460187#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 461018#L882-45 assume !(1 == ~t13_pc~0); 460518#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 459692#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 459693#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 460299#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 461612#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 461130#L1434-3 assume !(1 == ~M_E~0); 461131#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 461342#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 459983#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 459984#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 460146#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 461120#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 461121#L1464-3 assume !(1 == ~T7_E~0); 461681#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 461577#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 461578#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 461685#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 460735#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 460736#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 461474#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 461054#L1504-3 assume !(1 == ~E_1~0); 461055#L1509-3 assume !(1 == ~E_2~0); 461594#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 461648#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 460649#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 460650#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 461712#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 460975#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 460399#L1544-3 assume !(1 == ~E_9~0); 460400#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 460942#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 460034#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 460035#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 461229#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 461230#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 459920#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 460487#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 461200#L1954 assume !(0 == start_simulation_~tmp~3#1); 461202#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 461502#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 460203#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 461299#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 461456#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 461457#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 461585#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 461674#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 461825#L1935-2 [2021-12-19 19:17:11,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:11,387 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2021-12-19 19:17:11,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:11,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720129169] [2021-12-19 19:17:11,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:11,388 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:11,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:11,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:11,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:11,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720129169] [2021-12-19 19:17:11,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720129169] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:11,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:11,417 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:11,417 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886969508] [2021-12-19 19:17:11,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:11,417 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:11,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:11,418 INFO L85 PathProgramCache]: Analyzing trace with hash -15239448, now seen corresponding path program 1 times [2021-12-19 19:17:11,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:11,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473237703] [2021-12-19 19:17:11,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:11,418 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:11,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:11,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:11,449 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:11,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473237703] [2021-12-19 19:17:11,449 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473237703] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:11,449 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:11,449 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:11,449 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414433992] [2021-12-19 19:17:11,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:11,450 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:11,450 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:11,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:11,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:11,451 INFO L87 Difference]: Start difference. First operand 99101 states and 140688 transitions. cyclomatic complexity: 41589 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:12,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:12,450 INFO L93 Difference]: Finished difference Result 230838 states and 330351 transitions. [2021-12-19 19:17:12,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:12,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230838 states and 330351 transitions. [2021-12-19 19:17:13,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 230464 [2021-12-19 19:17:14,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230838 states to 230838 states and 330351 transitions. [2021-12-19 19:17:14,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230838 [2021-12-19 19:17:14,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230838 [2021-12-19 19:17:14,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230838 states and 330351 transitions. [2021-12-19 19:17:14,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:14,797 INFO L681 BuchiCegarLoop]: Abstraction has 230838 states and 330351 transitions. [2021-12-19 19:17:14,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230838 states and 330351 transitions. [2021-12-19 19:17:16,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230838 to 101600. [2021-12-19 19:17:16,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101600 states, 101600 states have (on average 1.4093208661417322) internal successors, (143187), 101599 states have internal predecessors, (143187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:16,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101600 states to 101600 states and 143187 transitions. [2021-12-19 19:17:16,341 INFO L704 BuchiCegarLoop]: Abstraction has 101600 states and 143187 transitions. [2021-12-19 19:17:16,341 INFO L587 BuchiCegarLoop]: Abstraction has 101600 states and 143187 transitions. [2021-12-19 19:17:16,341 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:17:16,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101600 states and 143187 transitions. [2021-12-19 19:17:16,977 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 101392 [2021-12-19 19:17:16,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:16,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:16,989 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:16,989 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:16,989 INFO L791 eck$LassoCheckResult]: Stem: 790498#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 790499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 790227#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 790228#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 791884#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 791885#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 790410#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 790411#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 790450#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 791381#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 791382#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 791526#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 791527#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 790233#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 790234#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 791580#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 790774#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 790775#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 791439#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 791853#L1286 assume !(0 == ~M_E~0); 791659#L1286-2 assume !(0 == ~T1_E~0); 790143#L1291-1 assume !(0 == ~T2_E~0); 790144#L1296-1 assume !(0 == ~T3_E~0); 790875#L1301-1 assume !(0 == ~T4_E~0); 790876#L1306-1 assume !(0 == ~T5_E~0); 791452#L1311-1 assume !(0 == ~T6_E~0); 790104#L1316-1 assume !(0 == ~T7_E~0); 790105#L1321-1 assume !(0 == ~T8_E~0); 790895#L1326-1 assume !(0 == ~T9_E~0); 789917#L1331-1 assume !(0 == ~T10_E~0); 789627#L1336-1 assume !(0 == ~T11_E~0); 789628#L1341-1 assume !(0 == ~T12_E~0); 789679#L1346-1 assume !(0 == ~T13_E~0); 789680#L1351-1 assume !(0 == ~E_M~0); 790050#L1356-1 assume !(0 == ~E_1~0); 790051#L1361-1 assume !(0 == ~E_2~0); 791781#L1366-1 assume !(0 == ~E_3~0); 790097#L1371-1 assume !(0 == ~E_4~0); 790098#L1376-1 assume !(0 == ~E_5~0); 790941#L1381-1 assume !(0 == ~E_6~0); 790942#L1386-1 assume !(0 == ~E_7~0); 791832#L1391-1 assume !(0 == ~E_8~0); 791867#L1396-1 assume !(0 == ~E_9~0); 790809#L1401-1 assume !(0 == ~E_10~0); 790810#L1406-1 assume !(0 == ~E_11~0); 791148#L1411-1 assume !(0 == ~E_12~0); 791149#L1416-1 assume !(0 == ~E_13~0); 790727#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 790560#L635 assume !(1 == ~m_pc~0); 789697#L635-2 is_master_triggered_~__retres1~0#1 := 0; 789698#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 790043#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 790690#L1598 assume !(0 != activate_threads_~tmp~1#1); 789873#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 789874#L654 assume !(1 == ~t1_pc~0); 790668#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 791582#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 791826#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 790666#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 790667#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 789920#L673 assume !(1 == ~t2_pc~0); 789922#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 791112#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 791113#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 791894#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 791910#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 790753#L692 assume !(1 == ~t3_pc~0); 790562#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 790563#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 791950#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 790381#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 790382#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 789945#L711 assume !(1 == ~t4_pc~0); 789946#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 791572#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 790917#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 789652#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 789653#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 791883#L730 assume !(1 == ~t5_pc~0); 791043#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 789830#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 789831#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 789954#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 789955#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 790295#L749 assume !(1 == ~t6_pc~0); 789834#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 789835#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 790263#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 790264#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 790490#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 789632#L768 assume !(1 == ~t7_pc~0); 789633#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 790967#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 789866#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 789867#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 790987#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 790106#L787 assume !(1 == ~t8_pc~0); 790107#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 791669#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 791615#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 791616#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 789677#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 789678#L806 assume !(1 == ~t9_pc~0); 790463#L806-2 is_transmit9_triggered_~__retres1~9#1 := 0; 789712#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 789713#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 789956#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 789957#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 791389#L825 assume !(1 == ~t10_pc~0); 791390#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 790932#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 790933#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 790044#L1678 assume !(0 != activate_threads_~tmp___9~0#1); 790045#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 790633#L844 assume 1 == ~t11_pc~0; 790316#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 790317#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 790696#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 790697#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 791376#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 791377#L863 assume !(1 == ~t12_pc~0); 789811#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 789810#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 790034#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 791489#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 791490#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 790769#L882 assume 1 == ~t13_pc~0; 790770#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 791085#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 791721#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 791441#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 791070#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 791071#L1434 assume !(1 == ~M_E~0); 791739#L1434-2 assume !(1 == ~T1_E~0); 791893#L1439-1 assume !(1 == ~T2_E~0); 789938#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 789939#L1449-1 assume !(1 == ~T4_E~0); 790378#L1454-1 assume !(1 == ~T5_E~0); 790379#L1459-1 assume !(1 == ~T6_E~0); 790988#L1464-1 assume !(1 == ~T7_E~0); 790989#L1469-1 assume !(1 == ~T8_E~0); 791086#L1474-1 assume !(1 == ~T9_E~0); 790728#L1479-1 assume !(1 == ~T10_E~0); 790729#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 790998#L1489-1 assume !(1 == ~T12_E~0); 790599#L1494-1 assume !(1 == ~T13_E~0); 790600#L1499-1 assume !(1 == ~E_M~0); 790792#L1504-1 assume !(1 == ~E_1~0); 790793#L1509-1 assume !(1 == ~E_2~0); 791514#L1514-1 assume !(1 == ~E_3~0); 791126#L1519-1 assume !(1 == ~E_4~0); 791127#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 791802#L1529-1 assume !(1 == ~E_6~0); 791803#L1534-1 assume !(1 == ~E_7~0); 789732#L1539-1 assume !(1 == ~E_8~0); 789733#L1544-1 assume !(1 == ~E_9~0); 790161#L1549-1 assume !(1 == ~E_10~0); 791755#L1554-1 assume !(1 == ~E_11~0); 791753#L1559-1 assume !(1 == ~E_12~0); 791558#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 791559#L1569-1 assume { :end_inline_reset_delta_events } true; 791793#L1935-2 [2021-12-19 19:17:16,989 INFO L793 eck$LassoCheckResult]: Loop: 791793#L1935-2 assume !false; 862363#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 862358#L1261 assume !false; 862357#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 862350#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 862342#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 862341#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 862340#L1074 assume !(0 != eval_~tmp~0#1); 791036#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 791037#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 791519#L1286-3 assume !(0 == ~M_E~0); 791600#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 791235#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 791236#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 791856#L1301-3 assume !(0 == ~T4_E~0); 791775#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 790682#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 789968#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 789969#L1321-3 assume !(0 == ~T8_E~0); 790081#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 790834#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 791129#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 791130#L1341-3 assume !(0 == ~T12_E~0); 790371#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 790362#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 790306#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 790307#L1361-3 assume !(0 == ~E_2~0); 790921#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 789667#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 789668#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 791534#L1381-3 assume !(0 == ~E_6~0); 791345#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 791346#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 791583#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 791584#L1401-3 assume !(0 == ~E_10~0); 790042#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 789875#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 789876#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 790507#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 789756#L635-45 assume 1 == ~m_pc~0; 789757#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 790551#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 791072#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 890854#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 890853#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890852#L654-45 assume !(1 == ~t1_pc~0); 890370#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 890367#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 890365#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 890364#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 890362#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 890361#L673-45 assume !(1 == ~t2_pc~0); 890359#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 890358#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 890356#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 890355#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 888356#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 888355#L692-45 assume !(1 == ~t3_pc~0); 888353#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 888351#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 888349#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 888348#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 888346#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 888345#L711-45 assume !(1 == ~t4_pc~0); 872888#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 888323#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 888321#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 888319#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 888316#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 888297#L730-45 assume !(1 == ~t5_pc~0); 888295#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 888292#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 888290#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888288#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 888286#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 888282#L749-45 assume !(1 == ~t6_pc~0); 880785#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 888278#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 888275#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 887459#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 886894#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 886890#L768-45 assume !(1 == ~t7_pc~0); 886885#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 886881#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 886879#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 886877#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 886875#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 869273#L787-45 assume !(1 == ~t8_pc~0); 869267#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 869261#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 869255#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 869249#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 869243#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 854378#L806-45 assume !(1 == ~t9_pc~0); 854377#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 854376#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 854375#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 854374#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 854373#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 854372#L825-45 assume !(1 == ~t10_pc~0); 854371#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 854369#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 854367#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 854365#L1678-45 assume !(0 != activate_threads_~tmp___9~0#1); 854362#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 854360#L844-45 assume 1 == ~t11_pc~0; 854357#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 854354#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 854352#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 854350#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 854348#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 854346#L863-45 assume !(1 == ~t12_pc~0); 854344#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 854340#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 854338#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 854336#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 847938#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 847936#L882-45 assume !(1 == ~t13_pc~0); 847933#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 847930#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 847928#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 847926#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 847924#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 847922#L1434-3 assume !(1 == ~M_E~0); 847918#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847915#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 847913#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 847911#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 847909#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 847907#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 847905#L1464-3 assume !(1 == ~T7_E~0); 847902#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 847900#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 847898#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 847896#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 847894#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 847892#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 847891#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 847889#L1504-3 assume !(1 == ~E_1~0); 847887#L1509-3 assume !(1 == ~E_2~0); 847885#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 847883#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 847881#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 847879#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 847877#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 847875#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 847873#L1544-3 assume !(1 == ~E_9~0); 847871#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 847869#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 847867#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 847865#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 847863#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 847830#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 847820#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 847818#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 847814#L1954 assume !(0 == start_simulation_~tmp~3#1); 847815#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 862391#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 862382#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 862378#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 862376#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 862374#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 862373#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 862368#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 791793#L1935-2 [2021-12-19 19:17:16,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:16,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2021-12-19 19:17:16,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:16,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131451016] [2021-12-19 19:17:16,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:16,991 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:16,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:17,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:17,018 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:17,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131451016] [2021-12-19 19:17:17,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131451016] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:17,018 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:17,018 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:17,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586575418] [2021-12-19 19:17:17,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:17,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:17,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:17,019 INFO L85 PathProgramCache]: Analyzing trace with hash -191531158, now seen corresponding path program 1 times [2021-12-19 19:17:17,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:17,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039003875] [2021-12-19 19:17:17,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:17,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:17,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:17,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:17,043 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:17,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039003875] [2021-12-19 19:17:17,043 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039003875] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:17,043 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:17,043 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:17,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964666216] [2021-12-19 19:17:17,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:17,044 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:17,044 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:17,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:17,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:17,045 INFO L87 Difference]: Start difference. First operand 101600 states and 143187 transitions. cyclomatic complexity: 41589 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:17,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:17,962 INFO L93 Difference]: Finished difference Result 241999 states and 339456 transitions. [2021-12-19 19:17:17,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:17,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 241999 states and 339456 transitions. [2021-12-19 19:17:19,426 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 241536 [2021-12-19 19:17:20,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 241999 states to 241999 states and 339456 transitions. [2021-12-19 19:17:20,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 241999 [2021-12-19 19:17:20,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 241999 [2021-12-19 19:17:20,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 241999 states and 339456 transitions. [2021-12-19 19:17:20,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:20,686 INFO L681 BuchiCegarLoop]: Abstraction has 241999 states and 339456 transitions. [2021-12-19 19:17:20,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241999 states and 339456 transitions. [2021-12-19 19:17:22,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241999 to 195439. [2021-12-19 19:17:22,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195439 states, 195439 states have (on average 1.4051647828734286) internal successors, (274624), 195438 states have internal predecessors, (274624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:23,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195439 states to 195439 states and 274624 transitions. [2021-12-19 19:17:23,115 INFO L704 BuchiCegarLoop]: Abstraction has 195439 states and 274624 transitions. [2021-12-19 19:17:23,115 INFO L587 BuchiCegarLoop]: Abstraction has 195439 states and 274624 transitions. [2021-12-19 19:17:23,115 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:17:23,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195439 states and 274624 transitions. [2021-12-19 19:17:23,664 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195200 [2021-12-19 19:17:23,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:23,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:23,680 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:23,680 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:23,681 INFO L791 eck$LassoCheckResult]: Stem: 1134104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1134105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1133836#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1133837#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1135545#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 1135546#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1134017#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1134018#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1134055#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1135000#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1135001#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1135143#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1135144#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1133842#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1133843#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1135196#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1134382#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1134383#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1135063#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1135509#L1286 assume !(0 == ~M_E~0); 1135294#L1286-2 assume !(0 == ~T1_E~0); 1133752#L1291-1 assume !(0 == ~T2_E~0); 1133753#L1296-1 assume !(0 == ~T3_E~0); 1134485#L1301-1 assume !(0 == ~T4_E~0); 1134486#L1306-1 assume !(0 == ~T5_E~0); 1135074#L1311-1 assume !(0 == ~T6_E~0); 1133712#L1316-1 assume !(0 == ~T7_E~0); 1133713#L1321-1 assume !(0 == ~T8_E~0); 1134505#L1326-1 assume !(0 == ~T9_E~0); 1133527#L1331-1 assume !(0 == ~T10_E~0); 1133236#L1336-1 assume !(0 == ~T11_E~0); 1133237#L1341-1 assume !(0 == ~T12_E~0); 1133288#L1346-1 assume !(0 == ~T13_E~0); 1133289#L1351-1 assume !(0 == ~E_M~0); 1133657#L1356-1 assume !(0 == ~E_1~0); 1133658#L1361-1 assume !(0 == ~E_2~0); 1135435#L1366-1 assume !(0 == ~E_3~0); 1133705#L1371-1 assume !(0 == ~E_4~0); 1133706#L1376-1 assume !(0 == ~E_5~0); 1134556#L1381-1 assume !(0 == ~E_6~0); 1134557#L1386-1 assume !(0 == ~E_7~0); 1135484#L1391-1 assume !(0 == ~E_8~0); 1135527#L1396-1 assume !(0 == ~E_9~0); 1134420#L1401-1 assume !(0 == ~E_10~0); 1134421#L1406-1 assume !(0 == ~E_11~0); 1134766#L1411-1 assume !(0 == ~E_12~0); 1134767#L1416-1 assume !(0 == ~E_13~0); 1134340#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1134169#L635 assume !(1 == ~m_pc~0); 1133308#L635-2 is_master_triggered_~__retres1~0#1 := 0; 1133309#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133654#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1134301#L1598 assume !(0 != activate_threads_~tmp~1#1); 1133482#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133483#L654 assume !(1 == ~t1_pc~0); 1134283#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1135198#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1135476#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1134279#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 1134280#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133533#L673 assume !(1 == ~t2_pc~0); 1133535#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1134731#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134732#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135557#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 1135578#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1134363#L692 assume !(1 == ~t3_pc~0); 1134171#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1134172#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135640#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1133988#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 1133989#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1133555#L711 assume !(1 == ~t4_pc~0); 1133556#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1135188#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1134529#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1133261#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 1133262#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135544#L730 assume !(1 == ~t5_pc~0); 1134659#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1133440#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133441#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1133564#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 1133565#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133904#L749 assume !(1 == ~t6_pc~0); 1133448#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1133449#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133873#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1133874#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 1134096#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1133243#L768 assume !(1 == ~t7_pc~0); 1133244#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1134582#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1133475#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1133476#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 1134605#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1133714#L787 assume !(1 == ~t8_pc~0); 1133715#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1135307#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1135233#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1135234#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 1133286#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1133287#L806 assume !(1 == ~t9_pc~0); 1134069#L806-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1133321#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1133322#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1133566#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 1133567#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1135008#L825 assume !(1 == ~t10_pc~0); 1135009#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1134545#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1134546#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1133655#L1678 assume !(0 != activate_threads_~tmp___9~0#1); 1133656#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1134242#L844 assume !(1 == ~t11_pc~0); 1134243#L844-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1134487#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1134307#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1134308#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 1134996#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1134997#L863 assume !(1 == ~t12_pc~0); 1133425#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1133424#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1133645#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1135107#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 1135108#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1134377#L882 assume 1 == ~t13_pc~0; 1134378#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1134702#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1135371#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1135065#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 1134687#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134688#L1434 assume !(1 == ~M_E~0); 1135392#L1434-2 assume !(1 == ~T1_E~0); 1135556#L1439-1 assume !(1 == ~T2_E~0); 1133548#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133549#L1449-1 assume !(1 == ~T4_E~0); 1133986#L1454-1 assume !(1 == ~T5_E~0); 1133987#L1459-1 assume !(1 == ~T6_E~0); 1134606#L1464-1 assume !(1 == ~T7_E~0); 1134607#L1469-1 assume !(1 == ~T8_E~0); 1134705#L1474-1 assume !(1 == ~T9_E~0); 1134341#L1479-1 assume !(1 == ~T10_E~0); 1134342#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1134617#L1489-1 assume !(1 == ~T12_E~0); 1134208#L1494-1 assume !(1 == ~T13_E~0); 1134209#L1499-1 assume !(1 == ~E_M~0); 1134403#L1504-1 assume !(1 == ~E_1~0); 1134404#L1509-1 assume !(1 == ~E_2~0); 1135129#L1514-1 assume !(1 == ~E_3~0); 1134745#L1519-1 assume !(1 == ~E_4~0); 1134746#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1135452#L1529-1 assume !(1 == ~E_6~0); 1135453#L1534-1 assume !(1 == ~E_7~0); 1133343#L1539-1 assume !(1 == ~E_8~0); 1133344#L1544-1 assume !(1 == ~E_9~0); 1133770#L1549-1 assume !(1 == ~E_10~0); 1135414#L1554-1 assume !(1 == ~E_11~0); 1135412#L1559-1 assume !(1 == ~E_12~0); 1135176#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1135177#L1569-1 assume { :end_inline_reset_delta_events } true; 1135445#L1935-2 [2021-12-19 19:17:23,681 INFO L793 eck$LassoCheckResult]: Loop: 1135445#L1935-2 assume !false; 1268839#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1268834#L1261 assume !false; 1268833#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1268820#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1268811#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1268808#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1268804#L1074 assume !(0 != eval_~tmp~0#1); 1268805#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1327632#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1327628#L1286-3 assume !(0 == ~M_E~0); 1327625#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1327622#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1327619#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1327611#L1301-3 assume !(0 == ~T4_E~0); 1327607#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1327602#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1327598#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1327597#L1321-3 assume !(0 == ~T8_E~0); 1327596#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1327594#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1327592#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1327590#L1341-3 assume !(0 == ~T12_E~0); 1327588#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1327586#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1327584#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1327582#L1361-3 assume !(0 == ~E_2~0); 1327581#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1327580#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1327579#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1327577#L1381-3 assume !(0 == ~E_6~0); 1327574#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1327572#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1327570#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1327568#L1401-3 assume !(0 == ~E_10~0); 1327566#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1327564#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1327562#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1327560#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1327558#L635-45 assume 1 == ~m_pc~0; 1327554#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1327552#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1327550#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1327526#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1327518#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1327510#L654-45 assume !(1 == ~t1_pc~0); 1327503#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1327498#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1327478#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1327477#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1327476#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1327461#L673-45 assume !(1 == ~t2_pc~0); 1327459#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1327457#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327456#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1327455#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 1327454#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1327453#L692-45 assume 1 == ~t3_pc~0; 1327452#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1327450#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1327448#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1327445#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1327444#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135629#L711-45 assume !(1 == ~t4_pc~0); 1135630#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1318921#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1318919#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1318917#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1318915#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1318913#L730-45 assume 1 == ~t5_pc~0; 1318910#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1318908#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1318906#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1318905#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1318902#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1318900#L749-45 assume !(1 == ~t6_pc~0); 1266989#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1318897#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1318895#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1318893#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1318889#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1318887#L768-45 assume 1 == ~t7_pc~0; 1318884#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1318882#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1318879#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1318877#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1318874#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1318119#L787-45 assume !(1 == ~t8_pc~0); 1309406#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1318115#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1318113#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1318111#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1317975#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1269259#L806-45 assume !(1 == ~t9_pc~0); 1269257#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1269255#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1269253#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1269250#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1269248#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1269246#L825-45 assume !(1 == ~t10_pc~0); 1269243#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 1269241#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1269239#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1269237#L1678-45 assume !(0 != activate_threads_~tmp___9~0#1); 1269234#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1269232#L844-45 assume !(1 == ~t11_pc~0); 1238570#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1269228#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1269226#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1269224#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 1269222#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1269220#L863-45 assume !(1 == ~t12_pc~0); 1269217#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1269214#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1269212#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1269210#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1269208#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1269205#L882-45 assume 1 == ~t13_pc~0; 1269203#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1269200#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1269198#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1269196#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1269194#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269192#L1434-3 assume !(1 == ~M_E~0); 1269188#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1269186#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1269184#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1269182#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1269180#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1269178#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1269176#L1464-3 assume !(1 == ~T7_E~0); 1269174#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1269172#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1269170#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1269168#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1269166#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1269164#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1269162#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1269160#L1504-3 assume !(1 == ~E_1~0); 1269158#L1509-3 assume !(1 == ~E_2~0); 1269156#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1269154#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1269152#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1269150#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1269148#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1269147#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1269146#L1544-3 assume !(1 == ~E_9~0); 1269145#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1269144#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1269143#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1269142#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1269141#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1269126#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1269116#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1269114#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1269111#L1954 assume !(0 == start_simulation_~tmp~3#1); 1269108#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1268875#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1268862#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1268858#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1268854#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1268849#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1268848#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1268844#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 1135445#L1935-2 [2021-12-19 19:17:23,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:23,682 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2021-12-19 19:17:23,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:23,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780769691] [2021-12-19 19:17:23,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:23,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:23,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:23,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:23,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:23,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780769691] [2021-12-19 19:17:23,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780769691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:23,751 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:23,751 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:23,751 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181602734] [2021-12-19 19:17:23,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:23,751 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:23,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:23,752 INFO L85 PathProgramCache]: Analyzing trace with hash -1434830619, now seen corresponding path program 1 times [2021-12-19 19:17:23,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:23,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950384446] [2021-12-19 19:17:23,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:23,752 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:23,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:23,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:23,777 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:23,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950384446] [2021-12-19 19:17:23,777 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950384446] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:23,777 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:23,777 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:23,778 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37012873] [2021-12-19 19:17:23,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:23,778 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:23,778 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:23,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:23,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:23,779 INFO L87 Difference]: Start difference. First operand 195439 states and 274624 transitions. cyclomatic complexity: 79187 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:25,882 INFO L93 Difference]: Finished difference Result 463294 states and 648045 transitions. [2021-12-19 19:17:25,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:25,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463294 states and 648045 transitions. [2021-12-19 19:17:28,528 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 462544 [2021-12-19 19:17:30,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463294 states to 463294 states and 648045 transitions. [2021-12-19 19:17:30,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463294 [2021-12-19 19:17:30,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463294 [2021-12-19 19:17:30,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463294 states and 648045 transitions. [2021-12-19 19:17:30,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,398 INFO L681 BuchiCegarLoop]: Abstraction has 463294 states and 648045 transitions. [2021-12-19 19:17:30,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463294 states and 648045 transitions. [2021-12-19 19:17:34,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463294 to 375662. [2021-12-19 19:17:34,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 375662 states, 375662 states have (on average 1.4012516570747109) internal successors, (526397), 375661 states have internal predecessors, (526397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 375662 states to 375662 states and 526397 transitions. [2021-12-19 19:17:35,558 INFO L704 BuchiCegarLoop]: Abstraction has 375662 states and 526397 transitions. [2021-12-19 19:17:35,558 INFO L587 BuchiCegarLoop]: Abstraction has 375662 states and 526397 transitions. [2021-12-19 19:17:35,558 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:17:35,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 375662 states and 526397 transitions. [2021-12-19 19:17:37,311 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 375360 [2021-12-19 19:17:37,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,373 INFO L791 eck$LassoCheckResult]: Stem: 1792845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1792846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1792580#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1792581#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1794281#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 1794282#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1792761#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1792762#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1792797#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1793745#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1793746#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1793894#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1793895#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1792586#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1792587#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1793948#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1793121#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1793122#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1793811#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1794240#L1286 assume !(0 == ~M_E~0); 1794035#L1286-2 assume !(0 == ~T1_E~0); 1792496#L1291-1 assume !(0 == ~T2_E~0); 1792497#L1296-1 assume !(0 == ~T3_E~0); 1793224#L1301-1 assume !(0 == ~T4_E~0); 1793225#L1306-1 assume !(0 == ~T5_E~0); 1793824#L1311-1 assume !(0 == ~T6_E~0); 1792456#L1316-1 assume !(0 == ~T7_E~0); 1792457#L1321-1 assume !(0 == ~T8_E~0); 1793246#L1326-1 assume !(0 == ~T9_E~0); 1792269#L1331-1 assume !(0 == ~T10_E~0); 1791979#L1336-1 assume !(0 == ~T11_E~0); 1791980#L1341-1 assume !(0 == ~T12_E~0); 1792032#L1346-1 assume !(0 == ~T13_E~0); 1792033#L1351-1 assume !(0 == ~E_M~0); 1792401#L1356-1 assume !(0 == ~E_1~0); 1792402#L1361-1 assume !(0 == ~E_2~0); 1794176#L1366-1 assume !(0 == ~E_3~0); 1792448#L1371-1 assume !(0 == ~E_4~0); 1792449#L1376-1 assume !(0 == ~E_5~0); 1793297#L1381-1 assume !(0 == ~E_6~0); 1793298#L1386-1 assume !(0 == ~E_7~0); 1794224#L1391-1 assume !(0 == ~E_8~0); 1794255#L1396-1 assume !(0 == ~E_9~0); 1793158#L1401-1 assume !(0 == ~E_10~0); 1793159#L1406-1 assume !(0 == ~E_11~0); 1793503#L1411-1 assume !(0 == ~E_12~0); 1793504#L1416-1 assume !(0 == ~E_13~0); 1793078#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1792906#L635 assume !(1 == ~m_pc~0); 1792051#L635-2 is_master_triggered_~__retres1~0#1 := 0; 1792052#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1792394#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1793039#L1598 assume !(0 != activate_threads_~tmp~1#1); 1792226#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1792227#L654 assume !(1 == ~t1_pc~0); 1793017#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1793950#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1794220#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1793015#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 1793016#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1792271#L673 assume !(1 == ~t2_pc~0); 1792273#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1793469#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1793470#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1794295#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 1794312#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1793101#L692 assume !(1 == ~t3_pc~0); 1792908#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1792909#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1794359#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1792729#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 1792730#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1792296#L711 assume !(1 == ~t4_pc~0); 1792297#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1793940#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1793269#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1792004#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 1792005#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1794280#L730 assume !(1 == ~t5_pc~0); 1793398#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1792184#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1792185#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1792307#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 1792308#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1792646#L749 assume !(1 == ~t6_pc~0); 1792188#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1792189#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1792615#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1792616#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 1792837#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1791984#L768 assume !(1 == ~t7_pc~0); 1791985#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1793321#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1792219#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1792220#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 1793343#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1792458#L787 assume !(1 == ~t8_pc~0); 1792459#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1794048#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1793989#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1793990#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 1792030#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1792031#L806 assume !(1 == ~t9_pc~0); 1792810#L806-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1792066#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1792067#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1792305#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 1792306#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1793755#L825 assume !(1 == ~t10_pc~0); 1793756#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1793286#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1793287#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1792395#L1678 assume !(0 != activate_threads_~tmp___9~0#1); 1792396#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1792979#L844 assume !(1 == ~t11_pc~0); 1792980#L844-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1793227#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1793045#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1793046#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 1793740#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1793741#L863 assume !(1 == ~t12_pc~0); 1792165#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1792164#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1792385#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1793858#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 1793859#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1793117#L882 assume !(1 == ~t13_pc~0); 1793118#L882-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1793442#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1794117#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1793813#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 1793426#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1793427#L1434 assume !(1 == ~M_E~0); 1794132#L1434-2 assume !(1 == ~T1_E~0); 1794294#L1439-1 assume !(1 == ~T2_E~0); 1792289#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1792290#L1449-1 assume !(1 == ~T4_E~0); 1792726#L1454-1 assume !(1 == ~T5_E~0); 1792727#L1459-1 assume !(1 == ~T6_E~0); 1793344#L1464-1 assume !(1 == ~T7_E~0); 1793345#L1469-1 assume !(1 == ~T8_E~0); 1793443#L1474-1 assume !(1 == ~T9_E~0); 1793079#L1479-1 assume !(1 == ~T10_E~0); 1793080#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1793353#L1489-1 assume !(1 == ~T12_E~0); 1792945#L1494-1 assume !(1 == ~T13_E~0); 1792946#L1499-1 assume !(1 == ~E_M~0); 1793141#L1504-1 assume !(1 == ~E_1~0); 1793142#L1509-1 assume !(1 == ~E_2~0); 1793879#L1514-1 assume !(1 == ~E_3~0); 1793483#L1519-1 assume !(1 == ~E_4~0); 1793484#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1794197#L1529-1 assume !(1 == ~E_6~0); 1794198#L1534-1 assume !(1 == ~E_7~0); 1792086#L1539-1 assume !(1 == ~E_8~0); 1792087#L1544-1 assume !(1 == ~E_9~0); 1792514#L1549-1 assume !(1 == ~E_10~0); 1794151#L1554-1 assume !(1 == ~E_11~0); 1794149#L1559-1 assume !(1 == ~E_12~0); 1793926#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1793927#L1569-1 assume { :end_inline_reset_delta_events } true; 1794188#L1935-2 [2021-12-19 19:17:37,373 INFO L793 eck$LassoCheckResult]: Loop: 1794188#L1935-2 assume !false; 2083498#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2083494#L1261 assume !false; 2083493#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2083480#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2083470#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2083468#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2083465#L1074 assume !(0 != eval_~tmp~0#1); 2083466#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2161752#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2161751#L1286-3 assume !(0 == ~M_E~0); 2161750#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2161749#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2161748#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2161747#L1301-3 assume !(0 == ~T4_E~0); 2161746#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2161745#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2161744#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2161743#L1321-3 assume !(0 == ~T8_E~0); 2161742#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2161741#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2161740#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2161739#L1341-3 assume !(0 == ~T12_E~0); 2161738#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2161737#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2161736#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2161735#L1361-3 assume !(0 == ~E_2~0); 2161734#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2161733#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2161732#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2161731#L1381-3 assume !(0 == ~E_6~0); 2161730#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2161729#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2161728#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2161727#L1401-3 assume !(0 == ~E_10~0); 2161726#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2161725#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 2161724#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2161723#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2161722#L635-45 assume 1 == ~m_pc~0; 2161720#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2161719#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2161718#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2161717#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2161716#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2161715#L654-45 assume !(1 == ~t1_pc~0); 2161714#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 2161713#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2161712#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2161711#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2161710#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2161709#L673-45 assume !(1 == ~t2_pc~0); 2161707#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 2161706#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2161705#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2161704#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 2161703#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2161702#L692-45 assume !(1 == ~t3_pc~0); 2161699#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 2161698#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2161697#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2161696#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 2161694#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2161693#L711-45 assume !(1 == ~t4_pc~0); 2158022#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 2161692#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2161691#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2161690#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2161686#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2161684#L730-45 assume 1 == ~t5_pc~0; 2160139#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2160140#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2161668#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2160134#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2160132#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2157825#L749-45 assume !(1 == ~t6_pc~0); 2157823#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 2157821#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2157818#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2157816#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2157814#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2157812#L768-45 assume 1 == ~t7_pc~0; 2157809#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2157807#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2157806#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2157804#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2157802#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1794316#L787-45 assume !(1 == ~t8_pc~0); 1794317#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1792702#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1792703#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1793139#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1793140#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1793491#L806-45 assume !(1 == ~t9_pc~0); 2113856#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 2113849#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2113841#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2113833#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2113823#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2113814#L825-45 assume !(1 == ~t10_pc~0); 2113806#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 2113796#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2113787#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2113723#L1678-45 assume !(0 != activate_threads_~tmp___9~0#1); 2113437#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2083794#L844-45 assume !(1 == ~t11_pc~0); 2083790#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 2083788#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2083786#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2083785#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 2083784#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2083783#L863-45 assume !(1 == ~t12_pc~0); 2083782#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 2083780#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2083779#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2083778#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2083777#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2083776#L882-45 assume !(1 == ~t13_pc~0); 1902859#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 2083774#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2083772#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 2083770#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2083768#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2083766#L1434-3 assume !(1 == ~M_E~0); 2082683#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2083763#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2083761#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2083759#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2083757#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2083755#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2083753#L1464-3 assume !(1 == ~T7_E~0); 2083751#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2083749#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2083747#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2083745#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2083743#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2083741#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2083739#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2083737#L1504-3 assume !(1 == ~E_1~0); 2083735#L1509-3 assume !(1 == ~E_2~0); 2083733#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2083731#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2083729#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2083727#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2083725#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2083724#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2083723#L1544-3 assume !(1 == ~E_9~0); 2083722#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2083721#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2083720#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2083719#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2083718#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2083711#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2083700#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2083698#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 2083696#L1954 assume !(0 == start_simulation_~tmp~3#1); 2083693#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2083532#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2083519#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2083516#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 2083513#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2083508#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2083507#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 2083503#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 1794188#L1935-2 [2021-12-19 19:17:37,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1787790413, now seen corresponding path program 1 times [2021-12-19 19:17:37,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781793432] [2021-12-19 19:17:37,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781793432] [2021-12-19 19:17:37,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781793432] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,436 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010201045] [2021-12-19 19:17:37,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,439 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,439 INFO L85 PathProgramCache]: Analyzing trace with hash 304362217, now seen corresponding path program 1 times [2021-12-19 19:17:37,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453368656] [2021-12-19 19:17:37,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453368656] [2021-12-19 19:17:37,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453368656] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933370568] [2021-12-19 19:17:37,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:37,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:37,484 INFO L87 Difference]: Start difference. First operand 375662 states and 526397 transitions. cyclomatic complexity: 150737 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)