./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:22,273 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:22,278 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:22,311 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:22,312 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:22,314 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:22,315 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:22,317 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:22,318 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:22,321 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:22,321 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:22,322 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:22,322 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:22,324 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:22,326 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:22,330 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:22,330 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:22,331 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:22,332 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:22,336 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:22,337 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:22,338 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:22,343 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:22,344 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:22,348 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:22,348 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:22,349 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:22,350 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:22,350 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:22,351 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:22,351 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:22,351 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:22,352 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:22,353 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:22,354 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:22,354 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:22,355 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:22,355 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:22,355 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:22,356 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:22,357 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:22,358 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:22,383 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:22,383 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:22,384 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:22,384 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:22,385 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:22,385 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:22,385 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:22,385 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:22,385 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:22,386 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:22,386 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:22,386 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:22,386 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:22,387 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:22,387 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:22,388 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:22,389 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:22,389 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:22,389 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:22,389 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:22,389 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:22,390 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:22,390 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:22,391 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2021-12-19 19:17:22,552 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:22,565 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:22,567 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:22,568 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:22,568 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:22,569 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-12-19 19:17:22,620 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ce142139/379bf18f39ea4045b134861315059abb/FLAG8498185a8 [2021-12-19 19:17:22,963 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:22,968 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-12-19 19:17:22,977 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ce142139/379bf18f39ea4045b134861315059abb/FLAG8498185a8 [2021-12-19 19:17:22,995 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ce142139/379bf18f39ea4045b134861315059abb [2021-12-19 19:17:22,998 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:22,999 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:23,002 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:23,003 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:23,005 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:23,005 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:22" (1/1) ... [2021-12-19 19:17:23,006 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@12cf26dd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23, skipping insertion in model container [2021-12-19 19:17:23,006 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:22" (1/1) ... [2021-12-19 19:17:23,011 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:23,045 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:23,160 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2021-12-19 19:17:23,199 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:23,204 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:23,213 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2021-12-19 19:17:23,233 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:23,243 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:23,244 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23 WrapperNode [2021-12-19 19:17:23,244 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:23,245 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:23,245 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:23,245 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:23,249 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,255 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,288 INFO L137 Inliner]: procedures = 36, calls = 42, calls flagged for inlining = 37, calls inlined = 70, statements flattened = 966 [2021-12-19 19:17:23,288 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:23,289 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:23,289 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:23,289 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:23,294 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,295 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,307 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,307 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,315 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,321 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,333 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,336 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:23,337 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:23,337 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:23,337 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:23,338 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (1/1) ... [2021-12-19 19:17:23,354 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:23,360 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:23,369 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:23,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:23,389 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:23,389 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:23,390 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:23,390 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:23,482 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:23,484 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:24,025 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:24,040 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:24,040 INFO L301 CfgBuilder]: Removed 8 assume(true) statements. [2021-12-19 19:17:24,042 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:24 BoogieIcfgContainer [2021-12-19 19:17:24,042 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:24,042 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:24,042 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:24,046 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:24,047 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:24,047 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:22" (1/3) ... [2021-12-19 19:17:24,048 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@36be6a22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:24, skipping insertion in model container [2021-12-19 19:17:24,048 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:24,048 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:23" (2/3) ... [2021-12-19 19:17:24,048 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@36be6a22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:24, skipping insertion in model container [2021-12-19 19:17:24,048 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:24,048 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:24" (3/3) ... [2021-12-19 19:17:24,049 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2021-12-19 19:17:24,078 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:24,079 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:24,079 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:24,079 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:24,079 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:24,079 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:24,079 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:24,079 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:24,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2021-12-19 19:17:24,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,160 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,160 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,160 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:24,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2021-12-19 19:17:24,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,177 INFO L791 eck$LassoCheckResult]: Stem: 381#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 327#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 191#L739true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29#L334true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 364#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 24#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 83#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 18#L507-1true assume !(0 == ~T2_E~0); 56#L512-1true assume !(0 == ~T3_E~0); 314#L517-1true assume !(0 == ~T4_E~0); 12#L522-1true assume !(0 == ~E_1~0); 277#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 358#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115#L238true assume 1 == ~m_pc~0; 320#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 195#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159#L250true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 200#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89#L257true assume 1 == ~t1_pc~0; 323#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 112#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#L269true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193#L623true assume !(0 != activate_threads_~tmp___0~0#1); 25#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192#L276true assume !(1 == ~t2_pc~0); 279#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 337#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214#L288true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 340#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99#L295true assume 1 == ~t3_pc~0; 38#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 92#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149#L307true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L639true assume !(0 != activate_threads_~tmp___2~0#1); 318#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372#L314true assume !(1 == ~t4_pc~0); 345#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 142#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321#L326true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88#L647true assume !(0 != activate_threads_~tmp___3~0#1); 273#L647-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386#L555true assume !(1 == ~M_E~0); 40#L555-2true assume !(1 == ~T1_E~0); 366#L560-1true assume !(1 == ~T2_E~0); 13#L565-1true assume !(1 == ~T3_E~0); 94#L570-1true assume !(1 == ~T4_E~0); 222#L575-1true assume !(1 == ~E_1~0); 292#L580-1true assume !(1 == ~E_2~0); 130#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 31#L590-1true assume !(1 == ~E_4~0); 28#L595-1true assume { :end_inline_reset_delta_events } true; 179#L776-2true [2021-12-19 19:17:24,181 INFO L793 eck$LassoCheckResult]: Loop: 179#L776-2true assume !false; 20#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118#L477true assume !true; 379#L492true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124#L334-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75#L502-3true assume !(0 == ~M_E~0); 300#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 312#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 53#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 50#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 90#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 140#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 264#L537-3true assume !(0 == ~E_4~0); 59#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84#L238-15true assume !(1 == ~m_pc~0); 113#L238-17true is_master_triggered_~__retres1~0#1 := 0; 309#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163#L250-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 230#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210#L257-15true assume !(1 == ~t1_pc~0); 72#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 334#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362#L269-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 305#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367#L276-15true assume 1 == ~t2_pc~0; 253#L277-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 188#L288-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 288#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26#L295-15true assume 1 == ~t3_pc~0; 304#L296-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 331#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155#L307-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 165#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164#L314-15true assume 1 == ~t4_pc~0; 282#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 186#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#L326-5true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 317#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119#L647-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 196#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 43#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 306#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 346#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 289#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 194#L580-3true assume !(1 == ~E_2~0); 390#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 236#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 271#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 166#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 71#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 100#L402-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 98#L795true assume !(0 == start_simulation_~tmp~3#1); 319#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 266#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 248#L402-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 171#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272#L758true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 276#L808true assume !(0 != start_simulation_~tmp___0~1#1); 179#L776-2true [2021-12-19 19:17:24,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2021-12-19 19:17:24,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307842334] [2021-12-19 19:17:24,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,196 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,349 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307842334] [2021-12-19 19:17:24,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307842334] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,352 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501938417] [2021-12-19 19:17:24,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,357 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:24,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1190976846, now seen corresponding path program 1 times [2021-12-19 19:17:24,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524315060] [2021-12-19 19:17:24,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524315060] [2021-12-19 19:17:24,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524315060] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,394 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:24,395 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1500740797] [2021-12-19 19:17:24,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,396 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:24,397 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:24,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:24,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:24,431 INFO L87 Difference]: Start difference. First operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:24,472 INFO L93 Difference]: Finished difference Result 390 states and 581 transitions. [2021-12-19 19:17:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:24,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 581 transitions. [2021-12-19 19:17:24,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 384 states and 575 transitions. [2021-12-19 19:17:24,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-19 19:17:24,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-19 19:17:24,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 575 transitions. [2021-12-19 19:17:24,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,489 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-19 19:17:24,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 575 transitions. [2021-12-19 19:17:24,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-19 19:17:24,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 575 transitions. [2021-12-19 19:17:24,529 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-19 19:17:24,529 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-19 19:17:24,529 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:24,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 575 transitions. [2021-12-19 19:17:24,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,536 INFO L791 eck$LassoCheckResult]: Stem: 1171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 790#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 791#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 915#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1021#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 875#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 887#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 888#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 933#L502 assume !(0 == ~M_E~0); 934#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L507-1 assume !(0 == ~T2_E~0); 863#L512-1 assume !(0 == ~T3_E~0); 1023#L517-1 assume !(0 == ~T4_E~0); 844#L522-1 assume !(0 == ~E_1~0); 845#L527-1 assume !(0 == ~E_2~0); 1040#L532-1 assume !(0 == ~E_3~0); 1134#L537-1 assume !(0 == ~E_4~0); 1148#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1124#L238 assume 1 == ~m_pc~0; 1125#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 803#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1104#L615 assume !(0 != activate_threads_~tmp~1#1); 826#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 827#L257 assume 1 == ~t1_pc~0; 1082#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 977#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 797#L623 assume !(0 != activate_threads_~tmp___0~0#1); 798#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792#L276 assume !(1 == ~t2_pc~0); 793#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1051#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 889#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 890#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1159#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1103#L295 assume 1 == ~t3_pc~0; 953#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 908#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1135#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1128#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1129#L314 assume !(1 == ~t4_pc~0); 945#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 944#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1130#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1080#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1034#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1035#L555 assume !(1 == ~M_E~0); 958#L555-2 assume !(1 == ~T1_E~0); 959#L560-1 assume !(1 == ~T2_E~0); 846#L565-1 assume !(1 == ~T3_E~0); 847#L570-1 assume !(1 == ~T4_E~0); 918#L575-1 assume !(1 == ~E_1~0); 919#L580-1 assume !(1 == ~E_2~0); 1081#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 920#L590-1 assume !(1 == ~E_4~0); 909#L595-1 assume { :end_inline_reset_delta_events } true; 910#L776-2 [2021-12-19 19:17:24,536 INFO L793 eck$LassoCheckResult]: Loop: 910#L776-2 assume !false; 878#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879#L477 assume !false; 969#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 970#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 811#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 812#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 850#L416 assume !(0 != eval_~tmp~0#1); 852#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1138#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065#L502-3 assume !(0 == ~M_E~0); 1066#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1092#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1000#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1001#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1083#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1017#L537-3 assume !(0 == ~E_4~0); 1018#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1027#L238-15 assume 1 == ~m_pc~0; 828#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 829#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1113#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 939#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 940#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869#L257-15 assume !(1 == ~t1_pc~0); 870#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1061#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1152#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1105#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119#L276-15 assume 1 == ~t2_pc~0; 997#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 984#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1173#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1074#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904#L295-15 assume !(1 == ~t3_pc~0); 905#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1102#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1146#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1136#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137#L314-15 assume 1 == ~t4_pc~0; 1056#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1057#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 996#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1123#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1073#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 805#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 806#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 974#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1108#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1075#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 799#L580-3 assume !(1 == ~E_2~0); 800#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 956#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1032#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 883#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1059#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1098#L795 assume !(0 == start_simulation_~tmp~3#1); 1100#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1120#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 986#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 987#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 966#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1033#L808 assume !(0 != start_simulation_~tmp___0~1#1); 910#L776-2 [2021-12-19 19:17:24,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2021-12-19 19:17:24,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210548550] [2021-12-19 19:17:24,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210548550] [2021-12-19 19:17:24,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210548550] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,562 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,562 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288865239] [2021-12-19 19:17:24,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,562 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:24,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,563 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 1 times [2021-12-19 19:17:24,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240601223] [2021-12-19 19:17:24,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,621 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240601223] [2021-12-19 19:17:24,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240601223] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,621 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,621 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6887384] [2021-12-19 19:17:24,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:24,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:24,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:24,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:24,622 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:24,634 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2021-12-19 19:17:24,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:24,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 574 transitions. [2021-12-19 19:17:24,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 574 transitions. [2021-12-19 19:17:24,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-19 19:17:24,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-19 19:17:24,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 574 transitions. [2021-12-19 19:17:24,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,641 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-19 19:17:24,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 574 transitions. [2021-12-19 19:17:24,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-19 19:17:24,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 574 transitions. [2021-12-19 19:17:24,651 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-19 19:17:24,651 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-19 19:17:24,652 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:24,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 574 transitions. [2021-12-19 19:17:24,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,654 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,654 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,654 INFO L791 eck$LassoCheckResult]: Stem: 1946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1565#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1566#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1688#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1794#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1649#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1650#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1662#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1663#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1708#L502 assume !(0 == ~M_E~0); 1709#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1637#L507-1 assume !(0 == ~T2_E~0); 1638#L512-1 assume !(0 == ~T3_E~0); 1797#L517-1 assume !(0 == ~T4_E~0); 1610#L522-1 assume !(0 == ~E_1~0); 1611#L527-1 assume !(0 == ~E_2~0); 1815#L532-1 assume !(0 == ~E_3~0); 1909#L537-1 assume !(0 == ~E_4~0); 1923#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1899#L238 assume 1 == ~m_pc~0; 1900#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1578#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1579#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1879#L615 assume !(0 != activate_threads_~tmp~1#1); 1597#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1598#L257 assume 1 == ~t1_pc~0; 1857#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1717#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1752#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1572#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1573#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L276 assume !(1 == ~t2_pc~0); 1568#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1825#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1664#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1665#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1933#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1876#L295 assume 1 == ~t3_pc~0; 1728#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1683#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1863#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1910#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1902#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1903#L314 assume !(1 == ~t4_pc~0); 1720#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1719#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1905#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1855#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1809#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1810#L555 assume !(1 == ~M_E~0); 1733#L555-2 assume !(1 == ~T1_E~0); 1734#L560-1 assume !(1 == ~T2_E~0); 1612#L565-1 assume !(1 == ~T3_E~0); 1613#L570-1 assume !(1 == ~T4_E~0); 1693#L575-1 assume !(1 == ~E_1~0); 1694#L580-1 assume !(1 == ~E_2~0); 1856#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1695#L590-1 assume !(1 == ~E_4~0); 1684#L595-1 assume { :end_inline_reset_delta_events } true; 1685#L776-2 [2021-12-19 19:17:24,655 INFO L793 eck$LassoCheckResult]: Loop: 1685#L776-2 assume !false; 1653#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1654#L477 assume !false; 1744#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1745#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1586#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1587#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1625#L416 assume !(0 != eval_~tmp~0#1); 1627#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1913#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1840#L502-3 assume !(0 == ~M_E~0); 1841#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1866#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1789#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1790#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1775#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1776#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1858#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1792#L537-3 assume !(0 == ~E_4~0); 1793#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1802#L238-15 assume 1 == ~m_pc~0; 1603#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1604#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1889#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1714#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1715#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1644#L257-15 assume !(1 == ~t1_pc~0); 1645#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1836#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1927#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1880#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1881#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1894#L276-15 assume 1 == ~t2_pc~0; 1772#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1759#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1760#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1948#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1849#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1679#L295-15 assume !(1 == ~t3_pc~0); 1680#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1878#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1921#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1942#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1911#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1912#L314-15 assume 1 == ~t4_pc~0; 1831#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1832#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1770#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1771#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1898#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1848#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1580#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1581#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1749#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1883#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1850#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1574#L580-3 assume !(1 == ~E_2~0); 1575#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1731#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1732#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1807#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1658#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1835#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1873#L795 assume !(0 == start_simulation_~tmp~3#1); 1875#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1895#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1620#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1761#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1762#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1742#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1743#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1808#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1685#L776-2 [2021-12-19 19:17:24,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,655 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2021-12-19 19:17:24,655 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859740613] [2021-12-19 19:17:24,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,655 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859740613] [2021-12-19 19:17:24,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859740613] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144622224] [2021-12-19 19:17:24,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,692 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:24,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,692 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 2 times [2021-12-19 19:17:24,692 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,692 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271891616] [2021-12-19 19:17:24,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,693 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,748 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,748 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271891616] [2021-12-19 19:17:24,748 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271891616] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,749 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,749 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,749 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176302088] [2021-12-19 19:17:24,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,750 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:24,751 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:24,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:24,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:24,751 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:24,759 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2021-12-19 19:17:24,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:24,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 573 transitions. [2021-12-19 19:17:24,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 573 transitions. [2021-12-19 19:17:24,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-19 19:17:24,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-19 19:17:24,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 573 transitions. [2021-12-19 19:17:24,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,779 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-19 19:17:24,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 573 transitions. [2021-12-19 19:17:24,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-19 19:17:24,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 573 transitions. [2021-12-19 19:17:24,788 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-19 19:17:24,788 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-19 19:17:24,788 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:24,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 573 transitions. [2021-12-19 19:17:24,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,790 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,790 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,790 INFO L791 eck$LassoCheckResult]: Stem: 2721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2340#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2341#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2465#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2571#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2424#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2425#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2437#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2438#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2483#L502 assume !(0 == ~M_E~0); 2484#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2415#L507-1 assume !(0 == ~T2_E~0); 2416#L512-1 assume !(0 == ~T3_E~0); 2573#L517-1 assume !(0 == ~T4_E~0); 2394#L522-1 assume !(0 == ~E_1~0); 2395#L527-1 assume !(0 == ~E_2~0); 2590#L532-1 assume !(0 == ~E_3~0); 2684#L537-1 assume !(0 == ~E_4~0); 2698#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2674#L238 assume 1 == ~m_pc~0; 2675#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2353#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2354#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2654#L615 assume !(0 != activate_threads_~tmp~1#1); 2376#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2377#L257 assume 1 == ~t1_pc~0; 2632#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2492#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2527#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2347#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2348#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2342#L276 assume !(1 == ~t2_pc~0); 2343#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2603#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2439#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2440#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2709#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2653#L295 assume 1 == ~t3_pc~0; 2503#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2458#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2638#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2685#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2678#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2679#L314 assume !(1 == ~t4_pc~0); 2495#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2494#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2680#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2630#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2584#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2585#L555 assume !(1 == ~M_E~0); 2508#L555-2 assume !(1 == ~T1_E~0); 2509#L560-1 assume !(1 == ~T2_E~0); 2396#L565-1 assume !(1 == ~T3_E~0); 2397#L570-1 assume !(1 == ~T4_E~0); 2468#L575-1 assume !(1 == ~E_1~0); 2469#L580-1 assume !(1 == ~E_2~0); 2631#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2470#L590-1 assume !(1 == ~E_4~0); 2459#L595-1 assume { :end_inline_reset_delta_events } true; 2460#L776-2 [2021-12-19 19:17:24,790 INFO L793 eck$LassoCheckResult]: Loop: 2460#L776-2 assume !false; 2428#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2429#L477 assume !false; 2519#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2520#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2361#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2362#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2400#L416 assume !(0 != eval_~tmp~0#1); 2402#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2688#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2615#L502-3 assume !(0 == ~M_E~0); 2616#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2642#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2564#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2565#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2551#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2633#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2567#L537-3 assume !(0 == ~E_4~0); 2568#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2577#L238-15 assume 1 == ~m_pc~0; 2378#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2379#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2663#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2489#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2490#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2419#L257-15 assume !(1 == ~t1_pc~0); 2420#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2611#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2655#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2656#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2669#L276-15 assume 1 == ~t2_pc~0; 2547#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2534#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2535#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2723#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2624#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2454#L295-15 assume !(1 == ~t3_pc~0); 2455#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2652#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2696#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2717#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2686#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2687#L314-15 assume !(1 == ~t4_pc~0); 2608#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 2607#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2545#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2546#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2673#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2623#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2355#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2356#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2625#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2349#L580-3 assume !(1 == ~E_2~0); 2350#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2506#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2507#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2582#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2433#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2609#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2648#L795 assume !(0 == start_simulation_~tmp~3#1); 2650#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2670#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2391#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2536#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2537#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2515#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2516#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2583#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2460#L776-2 [2021-12-19 19:17:24,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,791 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2021-12-19 19:17:24,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511694438] [2021-12-19 19:17:24,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,822 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511694438] [2021-12-19 19:17:24,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511694438] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,822 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045552843] [2021-12-19 19:17:24,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,823 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:24,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,823 INFO L85 PathProgramCache]: Analyzing trace with hash -2012547652, now seen corresponding path program 1 times [2021-12-19 19:17:24,823 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806693854] [2021-12-19 19:17:24,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,848 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806693854] [2021-12-19 19:17:24,849 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806693854] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,849 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,849 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109765064] [2021-12-19 19:17:24,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,849 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:24,849 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:24,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:24,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:24,850 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:24,856 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2021-12-19 19:17:24,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:24,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 572 transitions. [2021-12-19 19:17:24,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 572 transitions. [2021-12-19 19:17:24,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-19 19:17:24,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-19 19:17:24,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 572 transitions. [2021-12-19 19:17:24,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,862 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-19 19:17:24,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 572 transitions. [2021-12-19 19:17:24,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-19 19:17:24,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 572 transitions. [2021-12-19 19:17:24,868 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-19 19:17:24,868 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-19 19:17:24,868 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:24,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 572 transitions. [2021-12-19 19:17:24,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-19 19:17:24,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:24,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:24,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,871 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:24,871 INFO L791 eck$LassoCheckResult]: Stem: 3496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3115#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3116#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3238#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3346#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3199#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3200#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3212#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3213#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3258#L502 assume !(0 == ~M_E~0); 3259#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3187#L507-1 assume !(0 == ~T2_E~0); 3188#L512-1 assume !(0 == ~T3_E~0); 3347#L517-1 assume !(0 == ~T4_E~0); 3162#L522-1 assume !(0 == ~E_1~0); 3163#L527-1 assume !(0 == ~E_2~0); 3365#L532-1 assume !(0 == ~E_3~0); 3459#L537-1 assume !(0 == ~E_4~0); 3473#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L238 assume 1 == ~m_pc~0; 3450#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3128#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3129#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3429#L615 assume !(0 != activate_threads_~tmp~1#1); 3147#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3148#L257 assume 1 == ~t1_pc~0; 3407#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3267#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3302#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3122#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3123#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3117#L276 assume !(1 == ~t2_pc~0); 3118#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3375#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3214#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3215#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3483#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3426#L295 assume 1 == ~t3_pc~0; 3278#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3233#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3413#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3460#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3452#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3453#L314 assume !(1 == ~t4_pc~0); 3270#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3269#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3455#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3405#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3359#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3360#L555 assume !(1 == ~M_E~0); 3283#L555-2 assume !(1 == ~T1_E~0); 3284#L560-1 assume !(1 == ~T2_E~0); 3164#L565-1 assume !(1 == ~T3_E~0); 3165#L570-1 assume !(1 == ~T4_E~0); 3243#L575-1 assume !(1 == ~E_1~0); 3244#L580-1 assume !(1 == ~E_2~0); 3406#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3245#L590-1 assume !(1 == ~E_4~0); 3234#L595-1 assume { :end_inline_reset_delta_events } true; 3235#L776-2 [2021-12-19 19:17:24,871 INFO L793 eck$LassoCheckResult]: Loop: 3235#L776-2 assume !false; 3203#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3204#L477 assume !false; 3294#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3295#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3136#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3137#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3175#L416 assume !(0 != eval_~tmp~0#1); 3177#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3463#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3390#L502-3 assume !(0 == ~M_E~0); 3391#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3416#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3339#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3340#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3325#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3326#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3408#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3342#L537-3 assume !(0 == ~E_4~0); 3343#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3352#L238-15 assume 1 == ~m_pc~0; 3153#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3154#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3439#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3264#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3265#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3194#L257-15 assume !(1 == ~t1_pc~0); 3195#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3386#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3477#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3430#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3431#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3444#L276-15 assume 1 == ~t2_pc~0; 3322#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3309#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3310#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3498#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3399#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3229#L295-15 assume !(1 == ~t3_pc~0); 3230#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3428#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3471#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3492#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3461#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3462#L314-15 assume 1 == ~t4_pc~0; 3381#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3382#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3321#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3448#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3398#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3130#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3299#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3400#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3124#L580-3 assume !(1 == ~E_2~0); 3125#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3281#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3282#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3358#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3208#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3385#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3423#L795 assume !(0 == start_simulation_~tmp~3#1); 3425#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3445#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3172#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3311#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3312#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3290#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3291#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3356#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3235#L776-2 [2021-12-19 19:17:24,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2021-12-19 19:17:24,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447233738] [2021-12-19 19:17:24,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,896 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447233738] [2021-12-19 19:17:24,897 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447233738] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,897 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,897 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,897 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209886541] [2021-12-19 19:17:24,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,897 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:24,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:24,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 3 times [2021-12-19 19:17:24,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:24,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245101226] [2021-12-19 19:17:24,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:24,898 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:24,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:24,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:24,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:24,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245101226] [2021-12-19 19:17:24,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245101226] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:24,922 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:24,922 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:24,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501886547] [2021-12-19 19:17:24,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:24,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:24,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:24,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:24,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:24,923 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. cyclomatic complexity: 189 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:24,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:24,986 INFO L93 Difference]: Finished difference Result 666 states and 987 transitions. [2021-12-19 19:17:24,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:24,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 666 states and 987 transitions. [2021-12-19 19:17:24,990 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 592 [2021-12-19 19:17:24,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 666 states to 666 states and 987 transitions. [2021-12-19 19:17:24,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 666 [2021-12-19 19:17:24,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 666 [2021-12-19 19:17:24,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 666 states and 987 transitions. [2021-12-19 19:17:24,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:24,995 INFO L681 BuchiCegarLoop]: Abstraction has 666 states and 987 transitions. [2021-12-19 19:17:24,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states and 987 transitions. [2021-12-19 19:17:25,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 666. [2021-12-19 19:17:25,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 666 states, 666 states have (on average 1.481981981981982) internal successors, (987), 665 states have internal predecessors, (987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 666 states to 666 states and 987 transitions. [2021-12-19 19:17:25,016 INFO L704 BuchiCegarLoop]: Abstraction has 666 states and 987 transitions. [2021-12-19 19:17:25,016 INFO L587 BuchiCegarLoop]: Abstraction has 666 states and 987 transitions. [2021-12-19 19:17:25,016 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:25,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 666 states and 987 transitions. [2021-12-19 19:17:25,018 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 592 [2021-12-19 19:17:25,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:25,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:25,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,020 INFO L791 eck$LassoCheckResult]: Stem: 4591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4175#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4176#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4299#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4411#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4260#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4261#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4273#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4274#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4319#L502 assume !(0 == ~M_E~0); 4320#L502-2 assume !(0 == ~T1_E~0); 4248#L507-1 assume !(0 == ~T2_E~0); 4249#L512-1 assume !(0 == ~T3_E~0); 4412#L517-1 assume !(0 == ~T4_E~0); 4226#L522-1 assume !(0 == ~E_1~0); 4227#L527-1 assume !(0 == ~E_2~0); 4431#L532-1 assume !(0 == ~E_3~0); 4541#L537-1 assume !(0 == ~E_4~0); 4558#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4529#L238 assume 1 == ~m_pc~0; 4530#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4188#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4189#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4503#L615 assume !(0 != activate_threads_~tmp~1#1); 4208#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4209#L257 assume 1 == ~t1_pc~0; 4476#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4328#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4364#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4182#L623 assume !(0 != activate_threads_~tmp___0~0#1); 4183#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4177#L276 assume !(1 == ~t2_pc~0); 4178#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4442#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4275#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4276#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4571#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4497#L295 assume 1 == ~t3_pc~0; 4339#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4294#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4482#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4542#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4533#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4534#L314 assume !(1 == ~t4_pc~0); 4331#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4330#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4535#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4474#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4425#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4426#L555 assume 1 == ~M_E~0;~M_E~0 := 2; 4598#L555-2 assume !(1 == ~T1_E~0); 4345#L560-1 assume !(1 == ~T2_E~0); 4647#L565-1 assume !(1 == ~T3_E~0); 4645#L570-1 assume !(1 == ~T4_E~0); 4304#L575-1 assume !(1 == ~E_1~0); 4305#L580-1 assume !(1 == ~E_2~0); 4475#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4306#L590-1 assume !(1 == ~E_4~0); 4295#L595-1 assume { :end_inline_reset_delta_events } true; 4296#L776-2 [2021-12-19 19:17:25,020 INFO L793 eck$LassoCheckResult]: Loop: 4296#L776-2 assume !false; 4264#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4265#L477 assume !false; 4609#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4606#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4603#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4405#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4236#L416 assume !(0 != eval_~tmp~0#1); 4238#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4589#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4599#L502-3 assume !(0 == ~M_E~0); 4600#L502-5 assume !(0 == ~T1_E~0); 4805#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4804#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4803#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4802#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4801#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4800#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4799#L537-3 assume !(0 == ~E_4~0); 4798#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4797#L238-15 assume 1 == ~m_pc~0; 4795#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4794#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4793#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4792#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4791#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4790#L257-15 assume 1 == ~t1_pc~0; 4788#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4787#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4786#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4785#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4784#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4783#L276-15 assume 1 == ~t2_pc~0; 4781#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4780#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4779#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4778#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4777#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4776#L295-15 assume 1 == ~t3_pc~0; 4500#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4502#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4555#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4583#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4544#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4545#L314-15 assume 1 == ~t4_pc~0; 4448#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4449#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4597#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4527#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4528#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4690#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4466#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4191#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4507#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4508#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4468#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4184#L580-3 assume !(1 == ~E_2~0); 4185#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4342#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4343#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4424#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4269#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4452#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4494#L795 assume !(0 == start_simulation_~tmp~3#1); 4496#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4521#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4223#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4373#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4374#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4352#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4353#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4422#L808 assume !(0 != start_simulation_~tmp___0~1#1); 4296#L776-2 [2021-12-19 19:17:25,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1411348912, now seen corresponding path program 1 times [2021-12-19 19:17:25,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476330861] [2021-12-19 19:17:25,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,021 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476330861] [2021-12-19 19:17:25,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476330861] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,054 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:25,054 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210618547] [2021-12-19 19:17:25,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,055 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:25,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1100846239, now seen corresponding path program 1 times [2021-12-19 19:17:25,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676161050] [2021-12-19 19:17:25,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,097 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676161050] [2021-12-19 19:17:25,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676161050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,100 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:25,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221137028] [2021-12-19 19:17:25,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:25,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:25,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:25,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:25,102 INFO L87 Difference]: Start difference. First operand 666 states and 987 transitions. cyclomatic complexity: 323 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:25,135 INFO L93 Difference]: Finished difference Result 1244 states and 1820 transitions. [2021-12-19 19:17:25,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:25,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1244 states and 1820 transitions. [2021-12-19 19:17:25,142 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1167 [2021-12-19 19:17:25,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1244 states to 1244 states and 1820 transitions. [2021-12-19 19:17:25,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1244 [2021-12-19 19:17:25,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1244 [2021-12-19 19:17:25,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1244 states and 1820 transitions. [2021-12-19 19:17:25,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:25,148 INFO L681 BuchiCegarLoop]: Abstraction has 1244 states and 1820 transitions. [2021-12-19 19:17:25,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1244 states and 1820 transitions. [2021-12-19 19:17:25,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1244 to 1172. [2021-12-19 19:17:25,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1172 states, 1172 states have (on average 1.469283276450512) internal successors, (1722), 1171 states have internal predecessors, (1722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1172 states to 1172 states and 1722 transitions. [2021-12-19 19:17:25,164 INFO L704 BuchiCegarLoop]: Abstraction has 1172 states and 1722 transitions. [2021-12-19 19:17:25,164 INFO L587 BuchiCegarLoop]: Abstraction has 1172 states and 1722 transitions. [2021-12-19 19:17:25,164 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:25,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1172 states and 1722 transitions. [2021-12-19 19:17:25,168 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1095 [2021-12-19 19:17:25,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:25,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:25,170 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,170 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,170 INFO L791 eck$LassoCheckResult]: Stem: 6536#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6092#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6093#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6213#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 6329#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6176#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6177#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6189#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6190#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6237#L502 assume !(0 == ~M_E~0); 6238#L502-2 assume !(0 == ~T1_E~0); 6164#L507-1 assume !(0 == ~T2_E~0); 6165#L512-1 assume !(0 == ~T3_E~0); 6332#L517-1 assume !(0 == ~T4_E~0); 6137#L522-1 assume !(0 == ~E_1~0); 6138#L527-1 assume !(0 == ~E_2~0); 6357#L532-1 assume !(0 == ~E_3~0); 6463#L537-1 assume !(0 == ~E_4~0); 6489#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6453#L238 assume !(1 == ~m_pc~0); 6454#L238-2 is_master_triggered_~__retres1~0#1 := 0; 6103#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6104#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6431#L615 assume !(0 != activate_threads_~tmp~1#1); 6124#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6125#L257 assume 1 == ~t1_pc~0; 6403#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6246#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6284#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6097#L623 assume !(0 != activate_threads_~tmp___0~0#1); 6098#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6094#L276 assume !(1 == ~t2_pc~0); 6095#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6368#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6191#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6192#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6505#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6428#L295 assume 1 == ~t3_pc~0; 6259#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6210#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6409#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6464#L639 assume !(0 != activate_threads_~tmp___2~0#1); 6455#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6456#L314 assume !(1 == ~t4_pc~0); 6249#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6248#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6459#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6401#L647 assume !(0 != activate_threads_~tmp___3~0#1); 6349#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6350#L555 assume 1 == ~M_E~0;~M_E~0 := 2; 6545#L555-2 assume !(1 == ~T1_E~0); 6265#L560-1 assume !(1 == ~T2_E~0); 7075#L565-1 assume !(1 == ~T3_E~0); 6414#L570-1 assume !(1 == ~T4_E~0); 6220#L575-1 assume !(1 == ~E_1~0); 6221#L580-1 assume !(1 == ~E_2~0); 6402#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7071#L590-1 assume !(1 == ~E_4~0); 6211#L595-1 assume { :end_inline_reset_delta_events } true; 6212#L776-2 [2021-12-19 19:17:25,171 INFO L793 eck$LassoCheckResult]: Loop: 6212#L776-2 assume !false; 6180#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6181#L477 assume !false; 6276#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6277#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6111#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6112#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6152#L416 assume !(0 != eval_~tmp~0#1); 6154#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6534#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7031#L502-3 assume !(0 == ~M_E~0); 6416#L502-5 assume !(0 == ~T1_E~0); 6417#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6322#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6323#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6309#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6310#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6404#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6327#L537-3 assume !(0 == ~E_4~0); 6328#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6340#L238-15 assume !(1 == ~m_pc~0); 6397#L238-17 is_master_triggered_~__retres1~0#1 := 0; 6440#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6441#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6243#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6244#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6171#L257-15 assume !(1 == ~t1_pc~0); 6172#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 6380#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6493#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6432#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6433#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6447#L276-15 assume 1 == ~t2_pc~0; 6305#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6292#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6293#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6542#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6394#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6206#L295-15 assume 1 == ~t3_pc~0; 6208#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6430#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6487#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6518#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6466#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6467#L314-15 assume 1 == ~t4_pc~0; 6374#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6375#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6303#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6304#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6452#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6393#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6107#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6108#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6281#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6435#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6395#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6101#L580-3 assume !(1 == ~E_2~0); 6102#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6262#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6263#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6346#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6185#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6377#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 6425#L795 assume !(0 == start_simulation_~tmp~3#1); 6427#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6458#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6335#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6336#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7073#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6272#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6273#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 6356#L808 assume !(0 != start_simulation_~tmp___0~1#1); 6212#L776-2 [2021-12-19 19:17:25,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1011357713, now seen corresponding path program 1 times [2021-12-19 19:17:25,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335811607] [2021-12-19 19:17:25,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,220 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335811607] [2021-12-19 19:17:25,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335811607] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,221 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,221 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:25,221 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428810061] [2021-12-19 19:17:25,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,221 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:25,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1184548063, now seen corresponding path program 1 times [2021-12-19 19:17:25,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856671238] [2021-12-19 19:17:25,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856671238] [2021-12-19 19:17:25,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856671238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,245 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:25,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742845683] [2021-12-19 19:17:25,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,246 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:25,246 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:25,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:25,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:25,247 INFO L87 Difference]: Start difference. First operand 1172 states and 1722 transitions. cyclomatic complexity: 554 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:25,285 INFO L93 Difference]: Finished difference Result 2100 states and 3064 transitions. [2021-12-19 19:17:25,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:25,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2100 states and 3064 transitions. [2021-12-19 19:17:25,296 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2016 [2021-12-19 19:17:25,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2100 states to 2100 states and 3064 transitions. [2021-12-19 19:17:25,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2100 [2021-12-19 19:17:25,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2100 [2021-12-19 19:17:25,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2100 states and 3064 transitions. [2021-12-19 19:17:25,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:25,308 INFO L681 BuchiCegarLoop]: Abstraction has 2100 states and 3064 transitions. [2021-12-19 19:17:25,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2100 states and 3064 transitions. [2021-12-19 19:17:25,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2100 to 2092. [2021-12-19 19:17:25,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2092 states, 2092 states have (on average 1.4608030592734225) internal successors, (3056), 2091 states have internal predecessors, (3056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2092 states to 2092 states and 3056 transitions. [2021-12-19 19:17:25,337 INFO L704 BuchiCegarLoop]: Abstraction has 2092 states and 3056 transitions. [2021-12-19 19:17:25,337 INFO L587 BuchiCegarLoop]: Abstraction has 2092 states and 3056 transitions. [2021-12-19 19:17:25,337 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:25,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2092 states and 3056 transitions. [2021-12-19 19:17:25,344 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2008 [2021-12-19 19:17:25,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:25,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:25,346 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,346 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,347 INFO L791 eck$LassoCheckResult]: Stem: 9810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9371#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9372#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9495#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 9610#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9454#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9455#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9467#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9468#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9514#L502 assume !(0 == ~M_E~0); 9515#L502-2 assume !(0 == ~T1_E~0); 9446#L507-1 assume !(0 == ~T2_E~0); 9447#L512-1 assume !(0 == ~T3_E~0); 9613#L517-1 assume !(0 == ~T4_E~0); 9425#L522-1 assume !(0 == ~E_1~0); 9426#L527-1 assume !(0 == ~E_2~0); 9633#L532-1 assume !(0 == ~E_3~0); 9742#L537-1 assume !(0 == ~E_4~0); 9765#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9731#L238 assume !(1 == ~m_pc~0); 9732#L238-2 is_master_triggered_~__retres1~0#1 := 0; 9384#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9385#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9711#L615 assume !(0 != activate_threads_~tmp~1#1); 9407#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9408#L257 assume !(1 == ~t1_pc~0); 9522#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9523#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9560#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9378#L623 assume !(0 != activate_threads_~tmp___0~0#1); 9379#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9373#L276 assume !(1 == ~t2_pc~0); 9374#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9646#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9469#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9470#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9779#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9708#L295 assume 1 == ~t3_pc~0; 9535#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9488#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9691#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9744#L639 assume !(0 != activate_threads_~tmp___2~0#1); 9734#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9735#L314 assume !(1 == ~t4_pc~0); 9527#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9526#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9737#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9680#L647 assume !(0 != activate_threads_~tmp___3~0#1); 9627#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9628#L555 assume 1 == ~M_E~0;~M_E~0 := 2; 9820#L555-2 assume !(1 == ~T1_E~0); 9541#L560-1 assume !(1 == ~T2_E~0); 9803#L565-1 assume !(1 == ~T3_E~0); 9693#L570-1 assume !(1 == ~T4_E~0); 9498#L575-1 assume !(1 == ~E_1~0); 9499#L580-1 assume !(1 == ~E_2~0); 9757#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9758#L590-1 assume !(1 == ~E_4~0); 9489#L595-1 assume { :end_inline_reset_delta_events } true; 9490#L776-2 [2021-12-19 19:17:25,347 INFO L793 eck$LassoCheckResult]: Loop: 9490#L776-2 assume !false; 10986#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10982#L477 assume !false; 9552#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9553#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10967#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10964#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9431#L416 assume !(0 != eval_~tmp~0#1); 9433#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9747#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9663#L502-3 assume !(0 == ~M_E~0); 9664#L502-5 assume !(0 == ~T1_E~0); 9697#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9602#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9603#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9588#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9589#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9683#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9606#L537-3 assume !(0 == ~E_4~0); 9607#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9620#L238-15 assume !(1 == ~m_pc~0); 9675#L238-17 is_master_triggered_~__retres1~0#1 := 0; 11162#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11161#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11160#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11159#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9450#L257-15 assume !(1 == ~t1_pc~0); 9451#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 9654#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9769#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9712#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9713#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9727#L276-15 assume 1 == ~t2_pc~0; 9584#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9566#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9567#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9817#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9672#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9482#L295-15 assume !(1 == ~t3_pc~0); 9483#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 9707#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9760#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9794#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9745#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9746#L314-15 assume 1 == ~t4_pc~0; 9649#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9650#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9582#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9583#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9730#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9739#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10755#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10754#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10753#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10752#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10751#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10750#L580-3 assume !(1 == ~E_2~0); 10749#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10748#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10747#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10744#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10741#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10740#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9704#L795 assume !(0 == start_simulation_~tmp~3#1); 9706#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9725#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9418#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9570#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9571#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9548#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9549#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9625#L808 assume !(0 != start_simulation_~tmp___0~1#1); 9490#L776-2 [2021-12-19 19:17:25,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1654959310, now seen corresponding path program 1 times [2021-12-19 19:17:25,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653728177] [2021-12-19 19:17:25,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,381 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653728177] [2021-12-19 19:17:25,381 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653728177] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,382 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,382 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:25,382 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413439762] [2021-12-19 19:17:25,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,383 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:25,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,383 INFO L85 PathProgramCache]: Analyzing trace with hash -444102210, now seen corresponding path program 1 times [2021-12-19 19:17:25,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235687611] [2021-12-19 19:17:25,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,386 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,433 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235687611] [2021-12-19 19:17:25,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1235687611] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,433 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,433 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:25,433 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269019229] [2021-12-19 19:17:25,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,434 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:25,434 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:25,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:25,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:25,434 INFO L87 Difference]: Start difference. First operand 2092 states and 3056 transitions. cyclomatic complexity: 972 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:25,552 INFO L93 Difference]: Finished difference Result 5403 states and 7901 transitions. [2021-12-19 19:17:25,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:25,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5403 states and 7901 transitions. [2021-12-19 19:17:25,579 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5224 [2021-12-19 19:17:25,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5403 states to 5403 states and 7901 transitions. [2021-12-19 19:17:25,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5403 [2021-12-19 19:17:25,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5403 [2021-12-19 19:17:25,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5403 states and 7901 transitions. [2021-12-19 19:17:25,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:25,639 INFO L681 BuchiCegarLoop]: Abstraction has 5403 states and 7901 transitions. [2021-12-19 19:17:25,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5403 states and 7901 transitions. [2021-12-19 19:17:25,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5403 to 2203. [2021-12-19 19:17:25,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2203 states, 2203 states have (on average 1.4375851112119837) internal successors, (3167), 2202 states have internal predecessors, (3167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2203 states to 2203 states and 3167 transitions. [2021-12-19 19:17:25,677 INFO L704 BuchiCegarLoop]: Abstraction has 2203 states and 3167 transitions. [2021-12-19 19:17:25,677 INFO L587 BuchiCegarLoop]: Abstraction has 2203 states and 3167 transitions. [2021-12-19 19:17:25,678 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:25,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2203 states and 3167 transitions. [2021-12-19 19:17:25,684 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2116 [2021-12-19 19:17:25,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:25,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:25,686 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,686 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,687 INFO L791 eck$LassoCheckResult]: Stem: 17370#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 17286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16879#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16880#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17003#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 17123#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16964#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16965#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16977#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16978#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17023#L502 assume !(0 == ~M_E~0); 17024#L502-2 assume !(0 == ~T1_E~0); 16953#L507-1 assume !(0 == ~T2_E~0); 16954#L512-1 assume !(0 == ~T3_E~0); 17124#L517-1 assume !(0 == ~T4_E~0); 16931#L522-1 assume !(0 == ~E_1~0); 16932#L527-1 assume !(0 == ~E_2~0); 17149#L532-1 assume !(0 == ~E_3~0); 17276#L537-1 assume !(0 == ~E_4~0); 17299#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17264#L238 assume !(1 == ~m_pc~0); 17265#L238-2 is_master_triggered_~__retres1~0#1 := 0; 16892#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16893#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17238#L615 assume !(0 != activate_threads_~tmp~1#1); 16912#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16913#L257 assume !(1 == ~t1_pc~0); 17031#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17032#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17071#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16886#L623 assume !(0 != activate_threads_~tmp___0~0#1); 16887#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16881#L276 assume !(1 == ~t2_pc~0); 16882#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17161#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17308#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17316#L631 assume !(0 != activate_threads_~tmp___1~0#1); 17317#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17233#L295 assume 1 == ~t3_pc~0; 17045#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16998#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17216#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17277#L639 assume !(0 != activate_threads_~tmp___2~0#1); 17268#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17269#L314 assume !(1 == ~t4_pc~0); 17035#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17034#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17270#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17205#L647 assume !(0 != activate_threads_~tmp___3~0#1); 17139#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17140#L555 assume 1 == ~M_E~0;~M_E~0 := 2; 17050#L555-2 assume !(1 == ~T1_E~0); 17051#L560-1 assume !(1 == ~T2_E~0); 16933#L565-1 assume !(1 == ~T3_E~0); 16934#L570-1 assume !(1 == ~T4_E~0); 17008#L575-1 assume !(1 == ~E_1~0); 17009#L580-1 assume !(1 == ~E_2~0); 17206#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 17010#L590-1 assume !(1 == ~E_4~0); 16999#L595-1 assume { :end_inline_reset_delta_events } true; 17000#L776-2 [2021-12-19 19:17:25,687 INFO L793 eck$LassoCheckResult]: Loop: 17000#L776-2 assume !false; 18369#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18365#L477 assume !false; 18364#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18361#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18358#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18357#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18355#L416 assume !(0 != eval_~tmp~0#1); 18354#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18353#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18351#L502-3 assume !(0 == ~M_E~0); 18349#L502-5 assume !(0 == ~T1_E~0); 18347#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18345#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18343#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18341#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18339#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18337#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18335#L537-3 assume !(0 == ~E_4~0); 18333#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18332#L238-15 assume !(1 == ~m_pc~0); 18331#L238-17 is_master_triggered_~__retres1~0#1 := 0; 18330#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18329#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18328#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18327#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18326#L257-15 assume !(1 == ~t1_pc~0); 18325#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 18324#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18323#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18322#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18321#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18320#L276-15 assume 1 == ~t2_pc~0; 18318#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18316#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18314#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18312#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18289#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18287#L295-15 assume !(1 == ~t3_pc~0); 18284#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 18281#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18279#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18277#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18275#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18273#L314-15 assume 1 == ~t4_pc~0; 18270#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18267#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18265#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18263#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18261#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18259#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18257#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18255#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18253#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18251#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18249#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18247#L580-3 assume !(1 == ~E_2~0); 18243#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18242#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18241#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18238#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17172#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17173#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17230#L795 assume !(0 == start_simulation_~tmp~3#1); 17232#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18409#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18404#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18401#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 18396#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18395#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18387#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 18381#L808 assume !(0 != start_simulation_~tmp___0~1#1); 17000#L776-2 [2021-12-19 19:17:25,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1520945804, now seen corresponding path program 1 times [2021-12-19 19:17:25,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347805686] [2021-12-19 19:17:25,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,706 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347805686] [2021-12-19 19:17:25,706 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347805686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,707 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,707 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:25,707 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390691763] [2021-12-19 19:17:25,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,707 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:25,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,707 INFO L85 PathProgramCache]: Analyzing trace with hash -444102210, now seen corresponding path program 2 times [2021-12-19 19:17:25,708 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568832257] [2021-12-19 19:17:25,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,733 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568832257] [2021-12-19 19:17:25,733 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568832257] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,733 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,734 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:25,734 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101341012] [2021-12-19 19:17:25,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,734 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:25,734 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:25,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:25,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:25,735 INFO L87 Difference]: Start difference. First operand 2203 states and 3167 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:25,773 INFO L93 Difference]: Finished difference Result 3982 states and 5704 transitions. [2021-12-19 19:17:25,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:25,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3982 states and 5704 transitions. [2021-12-19 19:17:25,789 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3868 [2021-12-19 19:17:25,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3982 states to 3982 states and 5704 transitions. [2021-12-19 19:17:25,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3982 [2021-12-19 19:17:25,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3982 [2021-12-19 19:17:25,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3982 states and 5704 transitions. [2021-12-19 19:17:25,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:25,809 INFO L681 BuchiCegarLoop]: Abstraction has 3982 states and 5704 transitions. [2021-12-19 19:17:25,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3982 states and 5704 transitions. [2021-12-19 19:17:25,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3982 to 3966. [2021-12-19 19:17:25,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3966 states, 3966 states have (on average 1.4341906202723147) internal successors, (5688), 3965 states have internal predecessors, (5688), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:25,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3966 states to 3966 states and 5688 transitions. [2021-12-19 19:17:25,887 INFO L704 BuchiCegarLoop]: Abstraction has 3966 states and 5688 transitions. [2021-12-19 19:17:25,887 INFO L587 BuchiCegarLoop]: Abstraction has 3966 states and 5688 transitions. [2021-12-19 19:17:25,887 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:25,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3966 states and 5688 transitions. [2021-12-19 19:17:25,903 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3852 [2021-12-19 19:17:25,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:25,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:25,904 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,904 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:25,904 INFO L791 eck$LassoCheckResult]: Stem: 23527#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 23456#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23071#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23072#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23192#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 23309#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23155#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23156#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23168#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23169#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23214#L502 assume !(0 == ~M_E~0); 23215#L502-2 assume !(0 == ~T1_E~0); 23143#L507-1 assume !(0 == ~T2_E~0); 23144#L512-1 assume !(0 == ~T3_E~0); 23312#L517-1 assume !(0 == ~T4_E~0); 23116#L522-1 assume !(0 == ~E_1~0); 23117#L527-1 assume !(0 == ~E_2~0); 23335#L532-1 assume !(0 == ~E_3~0); 23447#L537-1 assume !(0 == ~E_4~0); 23468#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23436#L238 assume !(1 == ~m_pc~0); 23437#L238-2 is_master_triggered_~__retres1~0#1 := 0; 23082#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23083#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23410#L615 assume !(0 != activate_threads_~tmp~1#1); 23103#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23104#L257 assume !(1 == ~t1_pc~0); 23222#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23223#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23260#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23076#L623 assume !(0 != activate_threads_~tmp___0~0#1); 23077#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23073#L276 assume !(1 == ~t2_pc~0); 23074#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23345#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23170#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23171#L631 assume !(0 != activate_threads_~tmp___1~0#1); 23487#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23408#L295 assume !(1 == ~t3_pc~0); 23188#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23189#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23390#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23448#L639 assume !(0 != activate_threads_~tmp___2~0#1); 23438#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23439#L314 assume !(1 == ~t4_pc~0); 23228#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23227#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23441#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23382#L647 assume !(0 != activate_threads_~tmp___3~0#1); 23327#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23328#L555 assume 1 == ~M_E~0;~M_E~0 := 2; 23541#L555-2 assume !(1 == ~T1_E~0); 23242#L560-1 assume !(1 == ~T2_E~0); 25409#L565-1 assume !(1 == ~T3_E~0); 25408#L570-1 assume !(1 == ~T4_E~0); 25407#L575-1 assume !(1 == ~E_1~0); 25406#L580-1 assume !(1 == ~E_2~0); 25404#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25399#L590-1 assume !(1 == ~E_4~0); 25387#L595-1 assume { :end_inline_reset_delta_events } true; 25386#L776-2 [2021-12-19 19:17:25,905 INFO L793 eck$LassoCheckResult]: Loop: 25386#L776-2 assume !false; 24724#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24721#L477 assume !false; 24714#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24715#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24699#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24700#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24691#L416 assume !(0 != eval_~tmp~0#1); 24693#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25809#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25808#L502-3 assume !(0 == ~M_E~0); 25806#L502-5 assume !(0 == ~T1_E~0); 25804#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25802#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25800#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25798#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25796#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25793#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25790#L537-3 assume !(0 == ~E_4~0); 25787#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25784#L238-15 assume !(1 == ~m_pc~0); 25781#L238-17 is_master_triggered_~__retres1~0#1 := 0; 25778#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25775#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25772#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25769#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25766#L257-15 assume !(1 == ~t1_pc~0); 25763#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 25760#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25758#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25756#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25753#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25750#L276-15 assume 1 == ~t2_pc~0; 25747#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25745#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25742#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25737#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25732#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25727#L295-15 assume !(1 == ~t3_pc~0); 25723#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 25719#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25716#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25713#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25710#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25707#L314-15 assume 1 == ~t4_pc~0; 25703#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25700#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25696#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25693#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25689#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25686#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25683#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25680#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25677#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25674#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25671#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25668#L580-3 assume !(1 == ~E_2~0); 25665#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25663#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25661#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25655#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25645#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25642#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 25639#L795 assume !(0 == start_simulation_~tmp~3#1); 25635#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25396#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25393#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25392#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 25391#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25390#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25389#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 25388#L808 assume !(0 != start_simulation_~tmp___0~1#1); 25386#L776-2 [2021-12-19 19:17:25,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1407559147, now seen corresponding path program 1 times [2021-12-19 19:17:25,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318837303] [2021-12-19 19:17:25,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318837303] [2021-12-19 19:17:25,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318837303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:25,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102980305] [2021-12-19 19:17:25,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,930 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:25,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:25,930 INFO L85 PathProgramCache]: Analyzing trace with hash -444102210, now seen corresponding path program 3 times [2021-12-19 19:17:25,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:25,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934779874] [2021-12-19 19:17:25,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:25,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:25,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:25,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:25,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:25,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934779874] [2021-12-19 19:17:25,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934779874] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:25,953 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:25,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:25,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424616247] [2021-12-19 19:17:25,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:25,954 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:25,954 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:25,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:25,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:25,955 INFO L87 Difference]: Start difference. First operand 3966 states and 5688 transitions. cyclomatic complexity: 1738 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:26,008 INFO L93 Difference]: Finished difference Result 5793 states and 8285 transitions. [2021-12-19 19:17:26,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:26,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5793 states and 8285 transitions. [2021-12-19 19:17:26,025 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5660 [2021-12-19 19:17:26,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5793 states to 5793 states and 8285 transitions. [2021-12-19 19:17:26,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5793 [2021-12-19 19:17:26,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5793 [2021-12-19 19:17:26,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5793 states and 8285 transitions. [2021-12-19 19:17:26,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:26,054 INFO L681 BuchiCegarLoop]: Abstraction has 5793 states and 8285 transitions. [2021-12-19 19:17:26,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5793 states and 8285 transitions. [2021-12-19 19:17:26,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5793 to 4029. [2021-12-19 19:17:26,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4029 states, 4029 states have (on average 1.435095557210226) internal successors, (5782), 4028 states have internal predecessors, (5782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4029 states to 4029 states and 5782 transitions. [2021-12-19 19:17:26,141 INFO L704 BuchiCegarLoop]: Abstraction has 4029 states and 5782 transitions. [2021-12-19 19:17:26,141 INFO L587 BuchiCegarLoop]: Abstraction has 4029 states and 5782 transitions. [2021-12-19 19:17:26,141 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:26,141 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4029 states and 5782 transitions. [2021-12-19 19:17:26,150 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3924 [2021-12-19 19:17:26,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:26,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:26,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,152 INFO L791 eck$LassoCheckResult]: Stem: 33262#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 33205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32837#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32838#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32955#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 33068#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32919#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32920#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32932#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32933#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32977#L502 assume !(0 == ~M_E~0); 32978#L502-2 assume !(0 == ~T1_E~0); 32909#L507-1 assume !(0 == ~T2_E~0); 32910#L512-1 assume !(0 == ~T3_E~0); 33071#L517-1 assume !(0 == ~T4_E~0); 32881#L522-1 assume !(0 == ~E_1~0); 32882#L527-1 assume !(0 == ~E_2~0); 33093#L532-1 assume !(0 == ~E_3~0); 33199#L537-1 assume !(0 == ~E_4~0); 33217#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33189#L238 assume !(1 == ~m_pc~0); 33190#L238-2 is_master_triggered_~__retres1~0#1 := 0; 32848#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32849#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33167#L615 assume !(0 != activate_threads_~tmp~1#1); 32869#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32870#L257 assume !(1 == ~t1_pc~0); 32985#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32986#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33020#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32842#L623 assume !(0 != activate_threads_~tmp___0~0#1); 32843#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32839#L276 assume !(1 == ~t2_pc~0); 32840#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33103#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32934#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32935#L631 assume !(0 != activate_threads_~tmp___1~0#1); 33231#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33163#L295 assume !(1 == ~t3_pc~0); 32951#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32952#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33148#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33200#L639 assume !(0 != activate_threads_~tmp___2~0#1); 33191#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33192#L314 assume !(1 == ~t4_pc~0); 32990#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32989#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33195#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33140#L647 assume !(0 != activate_threads_~tmp___3~0#1); 33085#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33086#L555 assume !(1 == ~M_E~0); 33002#L555-2 assume !(1 == ~T1_E~0); 33003#L560-1 assume !(1 == ~T2_E~0); 32883#L565-1 assume !(1 == ~T3_E~0); 32884#L570-1 assume !(1 == ~T4_E~0); 32962#L575-1 assume !(1 == ~E_1~0); 32963#L580-1 assume !(1 == ~E_2~0); 33141#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 32964#L590-1 assume !(1 == ~E_4~0); 32953#L595-1 assume { :end_inline_reset_delta_events } true; 32954#L776-2 [2021-12-19 19:17:26,152 INFO L793 eck$LassoCheckResult]: Loop: 32954#L776-2 assume !false; 34088#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34084#L477 assume !false; 34081#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34077#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34073#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34071#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34068#L416 assume !(0 != eval_~tmp~0#1); 34069#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36848#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36846#L502-3 assume !(0 == ~M_E~0); 36845#L502-5 assume !(0 == ~T1_E~0); 36844#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36843#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36842#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36841#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36840#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36839#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36838#L537-3 assume !(0 == ~E_4~0); 36836#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36834#L238-15 assume !(1 == ~m_pc~0); 36833#L238-17 is_master_triggered_~__retres1~0#1 := 0; 36832#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36831#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 36830#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36829#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36828#L257-15 assume !(1 == ~t1_pc~0); 36827#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 36826#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36825#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36823#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36744#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33256#L276-15 assume 1 == ~t2_pc~0; 33043#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33044#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36741#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36740#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33131#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32949#L295-15 assume !(1 == ~t3_pc~0); 32950#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 33213#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33214#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33246#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33201#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33202#L314-15 assume 1 == ~t4_pc~0; 33107#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33108#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33041#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33042#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33188#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33129#L555-3 assume !(1 == ~M_E~0); 32852#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32853#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33017#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33171#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33132#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32846#L580-3 assume !(1 == ~E_2~0); 32847#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33000#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33001#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 33082#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 32928#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 33112#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 33160#L795 assume !(0 == start_simulation_~tmp~3#1); 33162#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34110#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34105#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34103#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 34101#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34099#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34096#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 34093#L808 assume !(0 != start_simulation_~tmp___0~1#1); 32954#L776-2 [2021-12-19 19:17:26,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2021-12-19 19:17:26,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490358519] [2021-12-19 19:17:26,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:26,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:26,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:26,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490358519] [2021-12-19 19:17:26,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490358519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:26,180 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:26,180 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:26,180 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955572061] [2021-12-19 19:17:26,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:26,181 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:26,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,181 INFO L85 PathProgramCache]: Analyzing trace with hash -225247492, now seen corresponding path program 1 times [2021-12-19 19:17:26,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111833701] [2021-12-19 19:17:26,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:26,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:26,198 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:26,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111833701] [2021-12-19 19:17:26,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111833701] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:26,199 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:26,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:26,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320322009] [2021-12-19 19:17:26,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:26,199 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:26,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:26,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:26,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:26,200 INFO L87 Difference]: Start difference. First operand 4029 states and 5782 transitions. cyclomatic complexity: 1761 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:26,321 INFO L93 Difference]: Finished difference Result 6380 states and 9066 transitions. [2021-12-19 19:17:26,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:26,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6380 states and 9066 transitions. [2021-12-19 19:17:26,347 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6200 [2021-12-19 19:17:26,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6380 states to 6380 states and 9066 transitions. [2021-12-19 19:17:26,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6380 [2021-12-19 19:17:26,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6380 [2021-12-19 19:17:26,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6380 states and 9066 transitions. [2021-12-19 19:17:26,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:26,385 INFO L681 BuchiCegarLoop]: Abstraction has 6380 states and 9066 transitions. [2021-12-19 19:17:26,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6380 states and 9066 transitions. [2021-12-19 19:17:26,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6380 to 4818. [2021-12-19 19:17:26,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4818 states, 4818 states have (on average 1.4219593192195932) internal successors, (6851), 4817 states have internal predecessors, (6851), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4818 states to 4818 states and 6851 transitions. [2021-12-19 19:17:26,461 INFO L704 BuchiCegarLoop]: Abstraction has 4818 states and 6851 transitions. [2021-12-19 19:17:26,462 INFO L587 BuchiCegarLoop]: Abstraction has 4818 states and 6851 transitions. [2021-12-19 19:17:26,462 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:26,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4818 states and 6851 transitions. [2021-12-19 19:17:26,474 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4668 [2021-12-19 19:17:26,474 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:26,474 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:26,475 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,475 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,476 INFO L791 eck$LassoCheckResult]: Stem: 43711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 43632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43256#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43257#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43375#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 43484#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43337#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43338#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43350#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43351#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43397#L502 assume !(0 == ~M_E~0); 43398#L502-2 assume !(0 == ~T1_E~0); 43327#L507-1 assume !(0 == ~T2_E~0); 43328#L512-1 assume !(0 == ~T3_E~0); 43487#L517-1 assume !(0 == ~T4_E~0); 43300#L522-1 assume !(0 == ~E_1~0); 43301#L527-1 assume !(0 == ~E_2~0); 43507#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43623#L537-1 assume !(0 == ~E_4~0); 43689#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43612#L238 assume !(1 == ~m_pc~0); 43613#L238-2 is_master_triggered_~__retres1~0#1 := 0; 43267#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43268#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43589#L615 assume !(0 != activate_threads_~tmp~1#1); 43590#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43557#L257 assume !(1 == ~t1_pc~0); 43558#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43609#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43610#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43731#L623 assume !(0 != activate_threads_~tmp___0~0#1); 43359#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43360#L276 assume !(1 == ~t2_pc~0); 43518#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43519#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43352#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43353#L631 assume !(0 != activate_threads_~tmp___1~0#1); 43686#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43687#L295 assume !(1 == ~t3_pc~0); 43371#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43372#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43673#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43674#L639 assume !(0 != activate_threads_~tmp___2~0#1); 43614#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43615#L314 assume !(1 == ~t4_pc~0); 43410#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43409#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43618#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43619#L647 assume !(0 != activate_threads_~tmp___3~0#1); 43500#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43501#L555 assume !(1 == ~M_E~0); 43422#L555-2 assume !(1 == ~T1_E~0); 43423#L560-1 assume !(1 == ~T2_E~0); 43302#L565-1 assume !(1 == ~T3_E~0); 43303#L570-1 assume !(1 == ~T4_E~0); 43730#L575-1 assume !(1 == ~E_1~0); 43555#L580-1 assume !(1 == ~E_2~0); 43556#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 43384#L590-1 assume !(1 == ~E_4~0); 43373#L595-1 assume { :end_inline_reset_delta_events } true; 43374#L776-2 [2021-12-19 19:17:26,476 INFO L793 eck$LassoCheckResult]: Loop: 43374#L776-2 assume !false; 44637#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44634#L477 assume !false; 44633#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44630#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44627#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44626#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44624#L416 assume !(0 != eval_~tmp~0#1); 44625#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47928#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47927#L502-3 assume !(0 == ~M_E~0); 47925#L502-5 assume !(0 == ~T1_E~0); 47924#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47923#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47922#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47921#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47920#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43659#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43482#L537-3 assume !(0 == ~E_4~0); 43483#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43492#L238-15 assume !(1 == ~m_pc~0); 43547#L238-17 is_master_triggered_~__retres1~0#1 := 0; 43598#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43599#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43403#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43404#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43333#L257-15 assume !(1 == ~t1_pc~0); 43334#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 43530#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43654#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43591#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43592#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43605#L276-15 assume 1 == ~t2_pc~0; 43462#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43463#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48030#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48029#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43544#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43369#L295-15 assume !(1 == ~t3_pc~0); 43370#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 43646#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43647#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43684#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43627#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43628#L314-15 assume 1 == ~t4_pc~0; 43523#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43524#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43460#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43461#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43611#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43543#L555-3 assume !(1 == ~M_E~0); 43271#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43272#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43437#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43594#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43545#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43265#L580-3 assume !(1 == ~E_2~0); 43266#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43420#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43421#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43498#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43346#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43528#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 43581#L795 assume !(0 == start_simulation_~tmp~3#1); 43583#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44650#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44647#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44646#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 44645#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44644#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44642#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 44640#L808 assume !(0 != start_simulation_~tmp___0~1#1); 43374#L776-2 [2021-12-19 19:17:26,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,476 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2021-12-19 19:17:26,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800443745] [2021-12-19 19:17:26,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:26,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:26,500 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:26,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800443745] [2021-12-19 19:17:26,500 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800443745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:26,502 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:26,502 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:26,503 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423621401] [2021-12-19 19:17:26,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:26,504 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:26,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,504 INFO L85 PathProgramCache]: Analyzing trace with hash -225247492, now seen corresponding path program 2 times [2021-12-19 19:17:26,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879339757] [2021-12-19 19:17:26,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:26,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:26,544 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:26,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879339757] [2021-12-19 19:17:26,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879339757] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:26,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:26,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:26,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142275972] [2021-12-19 19:17:26,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:26,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:26,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:26,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:26,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:26,547 INFO L87 Difference]: Start difference. First operand 4818 states and 6851 transitions. cyclomatic complexity: 2041 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:26,617 INFO L93 Difference]: Finished difference Result 5485 states and 7772 transitions. [2021-12-19 19:17:26,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:26,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5485 states and 7772 transitions. [2021-12-19 19:17:26,663 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5352 [2021-12-19 19:17:26,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5485 states to 5485 states and 7772 transitions. [2021-12-19 19:17:26,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5485 [2021-12-19 19:17:26,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5485 [2021-12-19 19:17:26,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5485 states and 7772 transitions. [2021-12-19 19:17:26,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:26,685 INFO L681 BuchiCegarLoop]: Abstraction has 5485 states and 7772 transitions. [2021-12-19 19:17:26,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5485 states and 7772 transitions. [2021-12-19 19:17:26,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5485 to 4029. [2021-12-19 19:17:26,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4029 states, 4029 states have (on average 1.4157359146190123) internal successors, (5704), 4028 states have internal predecessors, (5704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4029 states to 4029 states and 5704 transitions. [2021-12-19 19:17:26,749 INFO L704 BuchiCegarLoop]: Abstraction has 4029 states and 5704 transitions. [2021-12-19 19:17:26,749 INFO L587 BuchiCegarLoop]: Abstraction has 4029 states and 5704 transitions. [2021-12-19 19:17:26,749 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:26,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4029 states and 5704 transitions. [2021-12-19 19:17:26,758 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3924 [2021-12-19 19:17:26,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:26,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:26,759 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:26,759 INFO L791 eck$LassoCheckResult]: Stem: 53984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 53933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53569#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53570#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53691#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 53804#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53650#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53651#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53663#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53664#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53708#L502 assume !(0 == ~M_E~0); 53709#L502-2 assume !(0 == ~T1_E~0); 53642#L507-1 assume !(0 == ~T2_E~0); 53643#L512-1 assume !(0 == ~T3_E~0); 53806#L517-1 assume !(0 == ~T4_E~0); 53622#L522-1 assume !(0 == ~E_1~0); 53623#L527-1 assume !(0 == ~E_2~0); 53824#L532-1 assume !(0 == ~E_3~0); 53924#L537-1 assume !(0 == ~E_4~0); 53946#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53913#L238 assume !(1 == ~m_pc~0); 53914#L238-2 is_master_triggered_~__retres1~0#1 := 0; 53582#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53583#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53893#L615 assume !(0 != activate_threads_~tmp~1#1); 53605#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53606#L257 assume !(1 == ~t1_pc~0); 53716#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53717#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53754#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53576#L623 assume !(0 != activate_threads_~tmp___0~0#1); 53577#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53571#L276 assume !(1 == ~t2_pc~0); 53572#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53837#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53665#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53666#L631 assume !(0 != activate_threads_~tmp___1~0#1); 53960#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53892#L295 assume !(1 == ~t3_pc~0); 53683#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53684#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53877#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53925#L639 assume !(0 != activate_threads_~tmp___2~0#1); 53917#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53918#L314 assume !(1 == ~t4_pc~0); 53721#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53720#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53919#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53868#L647 assume !(0 != activate_threads_~tmp___3~0#1); 53817#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53818#L555 assume !(1 == ~M_E~0); 53733#L555-2 assume !(1 == ~T1_E~0); 53734#L560-1 assume !(1 == ~T2_E~0); 53624#L565-1 assume !(1 == ~T3_E~0); 53625#L570-1 assume !(1 == ~T4_E~0); 53694#L575-1 assume !(1 == ~E_1~0); 53695#L580-1 assume !(1 == ~E_2~0); 53869#L585-1 assume !(1 == ~E_3~0); 53696#L590-1 assume !(1 == ~E_4~0); 53685#L595-1 assume { :end_inline_reset_delta_events } true; 53686#L776-2 [2021-12-19 19:17:26,760 INFO L793 eck$LassoCheckResult]: Loop: 53686#L776-2 assume !false; 54795#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54790#L477 assume !false; 54787#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54773#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54768#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54759#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54755#L416 assume !(0 != eval_~tmp~0#1); 54749#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54707#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54701#L502-3 assume !(0 == ~M_E~0); 54693#L502-5 assume !(0 == ~T1_E~0); 54686#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54680#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54674#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54672#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54670#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54664#L532-3 assume !(0 == ~E_3~0); 54662#L537-3 assume !(0 == ~E_4~0); 54660#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54657#L238-15 assume !(1 == ~m_pc~0); 54655#L238-17 is_master_triggered_~__retres1~0#1 := 0; 54653#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54651#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 54649#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54647#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54645#L257-15 assume !(1 == ~t1_pc~0); 54643#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 54641#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54639#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 54637#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54635#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54633#L276-15 assume 1 == ~t2_pc~0; 54630#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54627#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54624#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54621#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54619#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54617#L295-15 assume !(1 == ~t3_pc~0); 54615#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 54612#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54610#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54608#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54606#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54604#L314-15 assume 1 == ~t4_pc~0; 54601#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54598#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54595#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54592#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54589#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54587#L555-3 assume !(1 == ~M_E~0); 54480#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54584#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54582#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54580#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54578#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54576#L580-3 assume !(1 == ~E_2~0); 54574#L585-3 assume !(1 == ~E_3~0); 54571#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54569#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54117#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54109#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54090#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 54082#L795 assume !(0 == start_simulation_~tmp~3#1); 54083#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54862#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54857#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54855#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54853#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54813#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54809#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 54805#L808 assume !(0 != start_simulation_~tmp___0~1#1); 53686#L776-2 [2021-12-19 19:17:26,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2021-12-19 19:17:26,761 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817536066] [2021-12-19 19:17:26,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:26,768 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:26,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:26,791 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:26,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:26,791 INFO L85 PathProgramCache]: Analyzing trace with hash -118325760, now seen corresponding path program 1 times [2021-12-19 19:17:26,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:26,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17691836] [2021-12-19 19:17:26,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:26,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:26,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:26,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:26,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:26,806 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17691836] [2021-12-19 19:17:26,806 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17691836] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:26,806 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:26,806 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:26,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374710603] [2021-12-19 19:17:26,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:26,807 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:26,807 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:26,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:26,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:26,808 INFO L87 Difference]: Start difference. First operand 4029 states and 5704 transitions. cyclomatic complexity: 1683 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:26,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:26,853 INFO L93 Difference]: Finished difference Result 6955 states and 9765 transitions. [2021-12-19 19:17:26,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:26,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6955 states and 9765 transitions. [2021-12-19 19:17:26,875 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6768 [2021-12-19 19:17:26,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6955 states to 6955 states and 9765 transitions. [2021-12-19 19:17:26,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6955 [2021-12-19 19:17:26,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6955 [2021-12-19 19:17:26,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6955 states and 9765 transitions. [2021-12-19 19:17:26,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:26,901 INFO L681 BuchiCegarLoop]: Abstraction has 6955 states and 9765 transitions. [2021-12-19 19:17:26,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6955 states and 9765 transitions. [2021-12-19 19:17:26,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6955 to 6947. [2021-12-19 19:17:26,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6947 states, 6947 states have (on average 1.4044911472578092) internal successors, (9757), 6946 states have internal predecessors, (9757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6947 states to 6947 states and 9757 transitions. [2021-12-19 19:17:27,001 INFO L704 BuchiCegarLoop]: Abstraction has 6947 states and 9757 transitions. [2021-12-19 19:17:27,001 INFO L587 BuchiCegarLoop]: Abstraction has 6947 states and 9757 transitions. [2021-12-19 19:17:27,001 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:27,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6947 states and 9757 transitions. [2021-12-19 19:17:27,018 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6760 [2021-12-19 19:17:27,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,019 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,019 INFO L791 eck$LassoCheckResult]: Stem: 65021#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 64941#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64559#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64560#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64676#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 64790#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64641#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64642#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64654#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64655#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64697#L502 assume !(0 == ~M_E~0); 64698#L502-2 assume !(0 == ~T1_E~0); 64630#L507-1 assume !(0 == ~T2_E~0); 64631#L512-1 assume !(0 == ~T3_E~0); 64793#L517-1 assume !(0 == ~T4_E~0); 64603#L522-1 assume !(0 == ~E_1~0); 64604#L527-1 assume 0 == ~E_2~0;~E_2~0 := 1; 64813#L532-1 assume !(0 == ~E_3~0); 64934#L537-1 assume !(0 == ~E_4~0); 65060#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65058#L238 assume !(1 == ~m_pc~0); 65001#L238-2 is_master_triggered_~__retres1~0#1 := 0; 64570#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64571#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 65053#L615 assume !(0 != activate_threads_~tmp~1#1); 64591#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64592#L257 assume !(1 == ~t1_pc~0); 64705#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64706#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64743#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 64564#L623 assume !(0 != activate_threads_~tmp___0~0#1); 64565#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64561#L276 assume !(1 == ~t2_pc~0); 64562#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 64962#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64656#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64657#L631 assume !(0 != activate_threads_~tmp___1~0#1); 64994#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64894#L295 assume !(1 == ~t3_pc~0); 64672#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64673#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64876#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65054#L639 assume !(0 != activate_threads_~tmp___2~0#1); 65052#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65011#L314 assume !(1 == ~t4_pc~0); 65012#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64967#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64928#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64929#L647 assume !(0 != activate_threads_~tmp___3~0#1); 64806#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64807#L555 assume !(1 == ~M_E~0); 64725#L555-2 assume !(1 == ~T1_E~0); 64726#L560-1 assume !(1 == ~T2_E~0); 64605#L565-1 assume !(1 == ~T3_E~0); 64606#L570-1 assume !(1 == ~T4_E~0); 64683#L575-1 assume !(1 == ~E_1~0); 64684#L580-1 assume 1 == ~E_2~0;~E_2~0 := 2; 64867#L585-1 assume !(1 == ~E_3~0); 64685#L590-1 assume !(1 == ~E_4~0); 64674#L595-1 assume { :end_inline_reset_delta_events } true; 64675#L776-2 [2021-12-19 19:17:27,020 INFO L793 eck$LassoCheckResult]: Loop: 64675#L776-2 assume !false; 69417#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69413#L477 assume !false; 69411#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69399#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69395#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69393#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69391#L416 assume !(0 != eval_~tmp~0#1); 69392#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69598#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69592#L502-3 assume !(0 == ~M_E~0); 69590#L502-5 assume !(0 == ~T1_E~0); 69588#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69587#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69586#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69585#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69559#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69557#L532-3 assume !(0 == ~E_3~0); 69556#L537-3 assume !(0 == ~E_4~0); 69555#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69554#L238-15 assume !(1 == ~m_pc~0); 69552#L238-17 is_master_triggered_~__retres1~0#1 := 0; 69550#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69548#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 69546#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69544#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69542#L257-15 assume !(1 == ~t1_pc~0); 69540#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 69538#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69536#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69534#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69530#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69527#L276-15 assume !(1 == ~t2_pc~0); 69525#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 69523#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69521#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69519#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 69516#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69514#L295-15 assume !(1 == ~t3_pc~0); 69512#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 69510#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69508#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69506#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69504#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69501#L314-15 assume !(1 == ~t4_pc~0); 69499#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 69496#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69494#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69492#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69489#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69487#L555-3 assume !(1 == ~M_E~0); 69483#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69481#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69479#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69477#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69474#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69472#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69469#L585-3 assume !(1 == ~E_3~0); 69468#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69467#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69461#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69457#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69455#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 69453#L795 assume !(0 == start_simulation_~tmp~3#1); 69450#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69443#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69439#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69438#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 69435#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69433#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69431#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 69429#L808 assume !(0 != start_simulation_~tmp___0~1#1); 64675#L776-2 [2021-12-19 19:17:27,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,020 INFO L85 PathProgramCache]: Analyzing trace with hash -1231104977, now seen corresponding path program 1 times [2021-12-19 19:17:27,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498691715] [2021-12-19 19:17:27,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,021 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,033 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498691715] [2021-12-19 19:17:27,033 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498691715] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,033 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,033 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:27,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42630080] [2021-12-19 19:17:27,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,034 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:27,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,034 INFO L85 PathProgramCache]: Analyzing trace with hash 599927998, now seen corresponding path program 1 times [2021-12-19 19:17:27,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367781815] [2021-12-19 19:17:27,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,055 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367781815] [2021-12-19 19:17:27,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367781815] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:27,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118189530] [2021-12-19 19:17:27,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,056 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,056 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:27,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:27,056 INFO L87 Difference]: Start difference. First operand 6947 states and 9757 transitions. cyclomatic complexity: 2818 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,083 INFO L93 Difference]: Finished difference Result 3858 states and 5361 transitions. [2021-12-19 19:17:27,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:27,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3858 states and 5361 transitions. [2021-12-19 19:17:27,096 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3756 [2021-12-19 19:17:27,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3858 states to 3858 states and 5361 transitions. [2021-12-19 19:17:27,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3858 [2021-12-19 19:17:27,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3858 [2021-12-19 19:17:27,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3858 states and 5361 transitions. [2021-12-19 19:17:27,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,111 INFO L681 BuchiCegarLoop]: Abstraction has 3858 states and 5361 transitions. [2021-12-19 19:17:27,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3858 states and 5361 transitions. [2021-12-19 19:17:27,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3858 to 3858. [2021-12-19 19:17:27,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3858 states, 3858 states have (on average 1.3895800933125972) internal successors, (5361), 3857 states have internal predecessors, (5361), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3858 states to 3858 states and 5361 transitions. [2021-12-19 19:17:27,213 INFO L704 BuchiCegarLoop]: Abstraction has 3858 states and 5361 transitions. [2021-12-19 19:17:27,213 INFO L587 BuchiCegarLoop]: Abstraction has 3858 states and 5361 transitions. [2021-12-19 19:17:27,213 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:27,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3858 states and 5361 transitions. [2021-12-19 19:17:27,219 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3756 [2021-12-19 19:17:27,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,220 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,221 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,221 INFO L791 eck$LassoCheckResult]: Stem: 75789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 75736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 75373#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75374#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75495#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 75605#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75456#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75457#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75469#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75470#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75512#L502 assume !(0 == ~M_E~0); 75513#L502-2 assume !(0 == ~T1_E~0); 75448#L507-1 assume !(0 == ~T2_E~0); 75449#L512-1 assume !(0 == ~T3_E~0); 75609#L517-1 assume !(0 == ~T4_E~0); 75424#L522-1 assume !(0 == ~E_1~0); 75425#L527-1 assume !(0 == ~E_2~0); 75627#L532-1 assume !(0 == ~E_3~0); 75730#L537-1 assume !(0 == ~E_4~0); 75746#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75719#L238 assume !(1 == ~m_pc~0); 75720#L238-2 is_master_triggered_~__retres1~0#1 := 0; 75386#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75387#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 75698#L615 assume !(0 != activate_threads_~tmp~1#1); 75409#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75410#L257 assume !(1 == ~t1_pc~0); 75520#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75521#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75555#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 75380#L623 assume !(0 != activate_threads_~tmp___0~0#1); 75381#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75375#L276 assume !(1 == ~t2_pc~0); 75376#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75640#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75471#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75472#L631 assume !(0 != activate_threads_~tmp___1~0#1); 75759#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75697#L295 assume !(1 == ~t3_pc~0); 75487#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75488#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75679#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75731#L639 assume !(0 != activate_threads_~tmp___2~0#1); 75722#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75723#L314 assume !(1 == ~t4_pc~0); 75525#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75524#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75725#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75671#L647 assume !(0 != activate_threads_~tmp___3~0#1); 75620#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75621#L555 assume !(1 == ~M_E~0); 75537#L555-2 assume !(1 == ~T1_E~0); 75538#L560-1 assume !(1 == ~T2_E~0); 75426#L565-1 assume !(1 == ~T3_E~0); 75427#L570-1 assume !(1 == ~T4_E~0); 75498#L575-1 assume !(1 == ~E_1~0); 75499#L580-1 assume !(1 == ~E_2~0); 75672#L585-1 assume !(1 == ~E_3~0); 75500#L590-1 assume !(1 == ~E_4~0); 75489#L595-1 assume { :end_inline_reset_delta_events } true; 75490#L776-2 [2021-12-19 19:17:27,221 INFO L793 eck$LassoCheckResult]: Loop: 75490#L776-2 assume !false; 77233#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77229#L477 assume !false; 77228#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77225#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77222#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77220#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77218#L416 assume !(0 != eval_~tmp~0#1); 77217#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77216#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77215#L502-3 assume !(0 == ~M_E~0); 77214#L502-5 assume !(0 == ~T1_E~0); 77212#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77210#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77209#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77207#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77204#L527-3 assume !(0 == ~E_2~0); 77202#L532-3 assume !(0 == ~E_3~0); 77200#L537-3 assume !(0 == ~E_4~0); 77198#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77196#L238-15 assume !(1 == ~m_pc~0); 77194#L238-17 is_master_triggered_~__retres1~0#1 := 0; 77192#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77190#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 77188#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77186#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77184#L257-15 assume !(1 == ~t1_pc~0); 77181#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 77179#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77177#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77175#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77173#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77171#L276-15 assume !(1 == ~t2_pc~0); 77168#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 77166#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77164#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77162#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 77160#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77158#L295-15 assume !(1 == ~t3_pc~0); 77156#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 77153#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77151#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77149#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77147#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77145#L314-15 assume !(1 == ~t4_pc~0); 77141#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 77138#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77136#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77135#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77134#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77133#L555-3 assume !(1 == ~M_E~0); 77036#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77132#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77131#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77130#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77129#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77128#L580-3 assume !(1 == ~E_2~0); 77127#L585-3 assume !(1 == ~E_3~0); 77126#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77125#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77118#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77114#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77112#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 77109#L795 assume !(0 == start_simulation_~tmp~3#1); 77110#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77256#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77250#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77245#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 77241#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77240#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77239#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 77237#L808 assume !(0 != start_simulation_~tmp___0~1#1); 75490#L776-2 [2021-12-19 19:17:27,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2021-12-19 19:17:27,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723355913] [2021-12-19 19:17:27,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,227 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:27,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,252 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:27,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,252 INFO L85 PathProgramCache]: Analyzing trace with hash -380465606, now seen corresponding path program 1 times [2021-12-19 19:17:27,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618505320] [2021-12-19 19:17:27,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,253 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618505320] [2021-12-19 19:17:27,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618505320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,274 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,274 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:27,274 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498064526] [2021-12-19 19:17:27,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,275 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,275 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:27,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:27,275 INFO L87 Difference]: Start difference. First operand 3858 states and 5361 transitions. cyclomatic complexity: 1511 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,338 INFO L93 Difference]: Finished difference Result 6702 states and 9173 transitions. [2021-12-19 19:17:27,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:17:27,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6702 states and 9173 transitions. [2021-12-19 19:17:27,357 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6560 [2021-12-19 19:17:27,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6702 states to 6702 states and 9173 transitions. [2021-12-19 19:17:27,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6702 [2021-12-19 19:17:27,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6702 [2021-12-19 19:17:27,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6702 states and 9173 transitions. [2021-12-19 19:17:27,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,379 INFO L681 BuchiCegarLoop]: Abstraction has 6702 states and 9173 transitions. [2021-12-19 19:17:27,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6702 states and 9173 transitions. [2021-12-19 19:17:27,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6702 to 3906. [2021-12-19 19:17:27,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3906 states, 3906 states have (on average 1.3847926267281105) internal successors, (5409), 3905 states have internal predecessors, (5409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3906 states to 3906 states and 5409 transitions. [2021-12-19 19:17:27,449 INFO L704 BuchiCegarLoop]: Abstraction has 3906 states and 5409 transitions. [2021-12-19 19:17:27,449 INFO L587 BuchiCegarLoop]: Abstraction has 3906 states and 5409 transitions. [2021-12-19 19:17:27,449 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:27,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3906 states and 5409 transitions. [2021-12-19 19:17:27,455 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3804 [2021-12-19 19:17:27,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,456 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,456 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,457 INFO L791 eck$LassoCheckResult]: Stem: 86394#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 86325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 85949#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85950#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86070#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 86182#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86031#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86032#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86044#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86045#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86087#L502 assume !(0 == ~M_E~0); 86088#L502-2 assume !(0 == ~T1_E~0); 86022#L507-1 assume !(0 == ~T2_E~0); 86023#L512-1 assume !(0 == ~T3_E~0); 86184#L517-1 assume !(0 == ~T4_E~0); 86003#L522-1 assume !(0 == ~E_1~0); 86004#L527-1 assume !(0 == ~E_2~0); 86203#L532-1 assume !(0 == ~E_3~0); 86318#L537-1 assume !(0 == ~E_4~0); 86337#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86303#L238 assume !(1 == ~m_pc~0); 86304#L238-2 is_master_triggered_~__retres1~0#1 := 0; 85962#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85963#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 86277#L615 assume !(0 != activate_threads_~tmp~1#1); 85985#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85986#L257 assume !(1 == ~t1_pc~0); 86095#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86096#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86130#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 85956#L623 assume !(0 != activate_threads_~tmp___0~0#1); 85957#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85951#L276 assume !(1 == ~t2_pc~0); 85952#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86217#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86046#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 86047#L631 assume !(0 != activate_threads_~tmp___1~0#1); 86352#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86275#L295 assume !(1 == ~t3_pc~0); 86062#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86063#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86259#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86319#L639 assume !(0 != activate_threads_~tmp___2~0#1); 86309#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86310#L314 assume !(1 == ~t4_pc~0); 86100#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86099#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86312#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86251#L647 assume !(0 != activate_threads_~tmp___3~0#1); 86195#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86196#L555 assume !(1 == ~M_E~0); 86112#L555-2 assume !(1 == ~T1_E~0); 86113#L560-1 assume !(1 == ~T2_E~0); 86005#L565-1 assume !(1 == ~T3_E~0); 86006#L570-1 assume !(1 == ~T4_E~0); 86073#L575-1 assume !(1 == ~E_1~0); 86074#L580-1 assume !(1 == ~E_2~0); 86252#L585-1 assume !(1 == ~E_3~0); 86075#L590-1 assume !(1 == ~E_4~0); 86064#L595-1 assume { :end_inline_reset_delta_events } true; 86065#L776-2 [2021-12-19 19:17:27,463 INFO L793 eck$LassoCheckResult]: Loop: 86065#L776-2 assume !false; 88287#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88281#L477 assume !false; 88009#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87998#L374 assume !(0 == ~m_st~0); 87999#L378 assume !(0 == ~t1_st~0); 88001#L382 assume !(0 == ~t2_st~0); 87996#L386 assume !(0 == ~t3_st~0); 87997#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 88000#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87212#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 87213#L416 assume !(0 != eval_~tmp~0#1); 87993#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87992#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87991#L502-3 assume !(0 == ~M_E~0); 87990#L502-5 assume !(0 == ~T1_E~0); 87989#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87988#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87987#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87986#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87985#L527-3 assume !(0 == ~E_2~0); 87984#L532-3 assume !(0 == ~E_3~0); 87983#L537-3 assume !(0 == ~E_4~0); 87982#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87981#L238-15 assume !(1 == ~m_pc~0); 87980#L238-17 is_master_triggered_~__retres1~0#1 := 0; 87979#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87978#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 87977#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87976#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87975#L257-15 assume !(1 == ~t1_pc~0); 87974#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 87973#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87972#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 87971#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87970#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87969#L276-15 assume !(1 == ~t2_pc~0); 87967#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 87966#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87965#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 87964#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 87963#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87962#L295-15 assume !(1 == ~t3_pc~0); 87961#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 87960#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87959#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87958#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87957#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87956#L314-15 assume !(1 == ~t4_pc~0); 87955#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 87953#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87952#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87951#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87950#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87949#L555-3 assume !(1 == ~M_E~0); 87647#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87948#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87947#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87946#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87945#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87944#L580-3 assume !(1 == ~E_2~0); 87943#L585-3 assume !(1 == ~E_3~0); 87942#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87941#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87938#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87934#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87932#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 87929#L795 assume !(0 == start_simulation_~tmp~3#1); 87930#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 88300#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 88297#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 88296#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 88295#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88294#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88292#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 88290#L808 assume !(0 != start_simulation_~tmp___0~1#1); 86065#L776-2 [2021-12-19 19:17:27,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2021-12-19 19:17:27,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242160048] [2021-12-19 19:17:27,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,471 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:27,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:27,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,487 INFO L85 PathProgramCache]: Analyzing trace with hash 1670976558, now seen corresponding path program 1 times [2021-12-19 19:17:27,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119045513] [2021-12-19 19:17:27,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,537 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119045513] [2021-12-19 19:17:27,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119045513] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:27,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035544346] [2021-12-19 19:17:27,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,538 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,539 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:27,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:27,539 INFO L87 Difference]: Start difference. First operand 3906 states and 5409 transitions. cyclomatic complexity: 1511 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,642 INFO L93 Difference]: Finished difference Result 6790 states and 9426 transitions. [2021-12-19 19:17:27,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:27,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6790 states and 9426 transitions. [2021-12-19 19:17:27,663 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6664 [2021-12-19 19:17:27,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6790 states to 6790 states and 9426 transitions. [2021-12-19 19:17:27,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6790 [2021-12-19 19:17:27,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6790 [2021-12-19 19:17:27,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6790 states and 9426 transitions. [2021-12-19 19:17:27,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,688 INFO L681 BuchiCegarLoop]: Abstraction has 6790 states and 9426 transitions. [2021-12-19 19:17:27,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6790 states and 9426 transitions. [2021-12-19 19:17:27,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6790 to 3966. [2021-12-19 19:17:27,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3966 states, 3966 states have (on average 1.367624810892587) internal successors, (5424), 3965 states have internal predecessors, (5424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3966 states to 3966 states and 5424 transitions. [2021-12-19 19:17:27,740 INFO L704 BuchiCegarLoop]: Abstraction has 3966 states and 5424 transitions. [2021-12-19 19:17:27,740 INFO L587 BuchiCegarLoop]: Abstraction has 3966 states and 5424 transitions. [2021-12-19 19:17:27,740 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:27,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3966 states and 5424 transitions. [2021-12-19 19:17:27,746 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3864 [2021-12-19 19:17:27,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,748 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,748 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,748 INFO L791 eck$LassoCheckResult]: Stem: 97104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 97036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 96658#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96659#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96774#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 96892#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96738#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96739#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96751#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96752#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96795#L502 assume !(0 == ~M_E~0); 96796#L502-2 assume !(0 == ~T1_E~0); 96728#L507-1 assume !(0 == ~T2_E~0); 96729#L512-1 assume !(0 == ~T3_E~0); 96895#L517-1 assume !(0 == ~T4_E~0); 96702#L522-1 assume !(0 == ~E_1~0); 96703#L527-1 assume !(0 == ~E_2~0); 96918#L532-1 assume !(0 == ~E_3~0); 97028#L537-1 assume !(0 == ~E_4~0); 97050#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97016#L238 assume !(1 == ~m_pc~0); 97017#L238-2 is_master_triggered_~__retres1~0#1 := 0; 96669#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96670#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 96992#L615 assume !(0 != activate_threads_~tmp~1#1); 96690#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96691#L257 assume !(1 == ~t1_pc~0); 96803#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96804#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96839#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 96663#L623 assume !(0 != activate_threads_~tmp___0~0#1); 96664#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96660#L276 assume !(1 == ~t2_pc~0); 96661#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96928#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96753#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 96754#L631 assume !(0 != activate_threads_~tmp___1~0#1); 97063#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96990#L295 assume !(1 == ~t3_pc~0); 96770#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96771#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96973#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 97029#L639 assume !(0 != activate_threads_~tmp___2~0#1); 97018#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97019#L314 assume !(1 == ~t4_pc~0); 96808#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96807#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97022#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96966#L647 assume !(0 != activate_threads_~tmp___3~0#1); 96910#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96911#L555 assume !(1 == ~M_E~0); 96820#L555-2 assume !(1 == ~T1_E~0); 96821#L560-1 assume !(1 == ~T2_E~0); 96704#L565-1 assume !(1 == ~T3_E~0); 96705#L570-1 assume !(1 == ~T4_E~0); 96781#L575-1 assume !(1 == ~E_1~0); 96782#L580-1 assume !(1 == ~E_2~0); 96967#L585-1 assume !(1 == ~E_3~0); 96783#L590-1 assume !(1 == ~E_4~0); 96772#L595-1 assume { :end_inline_reset_delta_events } true; 96773#L776-2 [2021-12-19 19:17:27,748 INFO L793 eck$LassoCheckResult]: Loop: 96773#L776-2 assume !false; 98912#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98909#L477 assume !false; 98908#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98904#L374 assume !(0 == ~m_st~0); 98905#L378 assume !(0 == ~t1_st~0); 98907#L382 assume !(0 == ~t2_st~0); 98902#L386 assume !(0 == ~t3_st~0); 98903#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 98906#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98736#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98737#L416 assume !(0 != eval_~tmp~0#1); 99595#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99594#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99593#L502-3 assume !(0 == ~M_E~0); 99592#L502-5 assume !(0 == ~T1_E~0); 99591#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 99590#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99589#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99588#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99587#L527-3 assume !(0 == ~E_2~0); 99586#L532-3 assume !(0 == ~E_3~0); 99585#L537-3 assume !(0 == ~E_4~0); 96901#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96902#L238-15 assume !(1 == ~m_pc~0); 99087#L238-17 is_master_triggered_~__retres1~0#1 := 0; 99084#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99080#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 99077#L615-15 assume !(0 != activate_threads_~tmp~1#1); 99074#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99071#L257-15 assume !(1 == ~t1_pc~0); 99068#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 99065#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99062#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 99059#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99056#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99052#L276-15 assume !(1 == ~t2_pc~0); 99048#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 99045#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99042#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 99038#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 99034#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99030#L295-15 assume !(1 == ~t3_pc~0); 99026#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 99022#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99017#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99013#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99009#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99004#L314-15 assume !(1 == ~t4_pc~0); 99001#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 98998#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98996#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98994#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98992#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98991#L555-3 assume !(1 == ~M_E~0); 98988#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98986#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98984#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98982#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98980#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98978#L580-3 assume !(1 == ~E_2~0); 98976#L585-3 assume !(1 == ~E_3~0); 98974#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98973#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98947#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98932#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98818#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 98819#L795 assume !(0 == start_simulation_~tmp~3#1); 98928#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98925#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98922#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98921#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 98920#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98919#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98917#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 98915#L808 assume !(0 != start_simulation_~tmp___0~1#1); 96773#L776-2 [2021-12-19 19:17:27,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,749 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2021-12-19 19:17:27,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914917986] [2021-12-19 19:17:27,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,754 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:27,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,762 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:27,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,763 INFO L85 PathProgramCache]: Analyzing trace with hash -684828692, now seen corresponding path program 1 times [2021-12-19 19:17:27,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025892524] [2021-12-19 19:17:27,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025892524] [2021-12-19 19:17:27,780 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025892524] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,780 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,780 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,780 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155037255] [2021-12-19 19:17:27,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,781 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,781 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:27,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:27,781 INFO L87 Difference]: Start difference. First operand 3966 states and 5424 transitions. cyclomatic complexity: 1466 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,812 INFO L93 Difference]: Finished difference Result 5890 states and 7933 transitions. [2021-12-19 19:17:27,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:27,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5890 states and 7933 transitions. [2021-12-19 19:17:27,826 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5776 [2021-12-19 19:17:27,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5890 states to 5890 states and 7933 transitions. [2021-12-19 19:17:27,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5890 [2021-12-19 19:17:27,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5890 [2021-12-19 19:17:27,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5890 states and 7933 transitions. [2021-12-19 19:17:27,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,840 INFO L681 BuchiCegarLoop]: Abstraction has 5890 states and 7933 transitions. [2021-12-19 19:17:27,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5890 states and 7933 transitions. [2021-12-19 19:17:27,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5890 to 5766. [2021-12-19 19:17:27,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5766 states, 5766 states have (on average 1.3491155046826222) internal successors, (7779), 5765 states have internal predecessors, (7779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5766 states to 5766 states and 7779 transitions. [2021-12-19 19:17:27,929 INFO L704 BuchiCegarLoop]: Abstraction has 5766 states and 7779 transitions. [2021-12-19 19:17:27,929 INFO L587 BuchiCegarLoop]: Abstraction has 5766 states and 7779 transitions. [2021-12-19 19:17:27,929 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:27,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5766 states and 7779 transitions. [2021-12-19 19:17:27,938 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5652 [2021-12-19 19:17:27,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,939 INFO L791 eck$LassoCheckResult]: Stem: 106953#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 106892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 106520#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106521#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106636#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 106752#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106601#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106602#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106614#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106615#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106657#L502 assume !(0 == ~M_E~0); 106658#L502-2 assume !(0 == ~T1_E~0); 106591#L507-1 assume !(0 == ~T2_E~0); 106592#L512-1 assume !(0 == ~T3_E~0); 106755#L517-1 assume !(0 == ~T4_E~0); 106564#L522-1 assume !(0 == ~E_1~0); 106565#L527-1 assume !(0 == ~E_2~0); 106781#L532-1 assume !(0 == ~E_3~0); 106883#L537-1 assume !(0 == ~E_4~0); 106902#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106873#L238 assume !(1 == ~m_pc~0); 106874#L238-2 is_master_triggered_~__retres1~0#1 := 0; 106531#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106532#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 106852#L615 assume !(0 != activate_threads_~tmp~1#1); 106552#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106553#L257 assume !(1 == ~t1_pc~0); 106665#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 106666#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106700#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 106525#L623 assume !(0 != activate_threads_~tmp___0~0#1); 106526#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106522#L276 assume !(1 == ~t2_pc~0); 106523#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 106791#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106616#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 106617#L631 assume !(0 != activate_threads_~tmp___1~0#1); 106917#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106848#L295 assume !(1 == ~t3_pc~0); 106632#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106633#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106832#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106884#L639 assume !(0 != activate_threads_~tmp___2~0#1); 106876#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106877#L314 assume !(1 == ~t4_pc~0); 106670#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 106669#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106879#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106825#L647 assume !(0 != activate_threads_~tmp___3~0#1); 106771#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106772#L555 assume !(1 == ~M_E~0); 106682#L555-2 assume !(1 == ~T1_E~0); 106683#L560-1 assume !(1 == ~T2_E~0); 106566#L565-1 assume !(1 == ~T3_E~0); 106567#L570-1 assume !(1 == ~T4_E~0); 106643#L575-1 assume !(1 == ~E_1~0); 106644#L580-1 assume !(1 == ~E_2~0); 106826#L585-1 assume !(1 == ~E_3~0); 106645#L590-1 assume !(1 == ~E_4~0); 106634#L595-1 assume { :end_inline_reset_delta_events } true; 106635#L776-2 assume !false; 111930#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111926#L477 [2021-12-19 19:17:27,939 INFO L793 eck$LassoCheckResult]: Loop: 111926#L477 assume !false; 111923#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 111916#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 111911#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 111909#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 111907#L416 assume 0 != eval_~tmp~0#1; 111906#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 106945#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 106947#L421 assume !(0 == ~t1_st~0); 109764#L435 assume !(0 == ~t2_st~0); 110174#L449 assume !(0 == ~t3_st~0); 110172#L463 assume !(0 == ~t4_st~0); 111926#L477 [2021-12-19 19:17:27,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,940 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2021-12-19 19:17:27,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268415701] [2021-12-19 19:17:27,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,945 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:27,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,958 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:27,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,958 INFO L85 PathProgramCache]: Analyzing trace with hash 839567500, now seen corresponding path program 1 times [2021-12-19 19:17:27,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426676560] [2021-12-19 19:17:27,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,962 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:27,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:27,965 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:27,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,965 INFO L85 PathProgramCache]: Analyzing trace with hash -1729123880, now seen corresponding path program 1 times [2021-12-19 19:17:27,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771369503] [2021-12-19 19:17:27,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,966 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771369503] [2021-12-19 19:17:27,982 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771369503] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,982 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,982 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,982 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960570121] [2021-12-19 19:17:27,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,042 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,042 INFO L87 Difference]: Start difference. First operand 5766 states and 7779 transitions. cyclomatic complexity: 2025 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,105 INFO L93 Difference]: Finished difference Result 10626 states and 14157 transitions. [2021-12-19 19:17:28,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10626 states and 14157 transitions. [2021-12-19 19:17:28,135 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9481 [2021-12-19 19:17:28,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10626 states to 10626 states and 14157 transitions. [2021-12-19 19:17:28,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10626 [2021-12-19 19:17:28,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10626 [2021-12-19 19:17:28,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10626 states and 14157 transitions. [2021-12-19 19:17:28,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,162 INFO L681 BuchiCegarLoop]: Abstraction has 10626 states and 14157 transitions. [2021-12-19 19:17:28,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10626 states and 14157 transitions. [2021-12-19 19:17:28,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10626 to 10241. [2021-12-19 19:17:28,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10241 states, 10241 states have (on average 1.3359046968069523) internal successors, (13681), 10240 states have internal predecessors, (13681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10241 states to 10241 states and 13681 transitions. [2021-12-19 19:17:28,252 INFO L704 BuchiCegarLoop]: Abstraction has 10241 states and 13681 transitions. [2021-12-19 19:17:28,252 INFO L587 BuchiCegarLoop]: Abstraction has 10241 states and 13681 transitions. [2021-12-19 19:17:28,252 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:28,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10241 states and 13681 transitions. [2021-12-19 19:17:28,270 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9096 [2021-12-19 19:17:28,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,271 INFO L791 eck$LassoCheckResult]: Stem: 123362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 123299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 122920#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122921#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123039#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 123153#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 123348#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128985#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128984#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128983#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 128982#L502 assume !(0 == ~M_E~0); 128981#L502-2 assume !(0 == ~T1_E~0); 128980#L507-1 assume !(0 == ~T2_E~0); 128979#L512-1 assume !(0 == ~T3_E~0); 128978#L517-1 assume !(0 == ~T4_E~0); 128977#L522-1 assume !(0 == ~E_1~0); 128976#L527-1 assume !(0 == ~E_2~0); 128975#L532-1 assume !(0 == ~E_3~0); 128974#L537-1 assume !(0 == ~E_4~0); 128973#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128972#L238 assume !(1 == ~m_pc~0); 128971#L238-2 is_master_triggered_~__retres1~0#1 := 0; 128970#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128969#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 128968#L615 assume !(0 != activate_threads_~tmp~1#1); 128967#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128966#L257 assume !(1 == ~t1_pc~0); 128965#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 128964#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128963#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 128962#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 122928#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122922#L276 assume !(1 == ~t2_pc~0); 122923#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123191#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123016#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123017#L631 assume !(0 != activate_threads_~tmp___1~0#1); 123324#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123251#L295 assume !(1 == ~t3_pc~0); 123031#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 123032#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123235#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123291#L639 assume !(0 != activate_threads_~tmp___2~0#1); 123283#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123284#L314 assume !(1 == ~t4_pc~0); 123070#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123069#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123285#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123226#L647 assume !(0 != activate_threads_~tmp___3~0#1); 123170#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123171#L555 assume !(1 == ~M_E~0); 123082#L555-2 assume !(1 == ~T1_E~0); 123083#L560-1 assume !(1 == ~T2_E~0); 122976#L565-1 assume !(1 == ~T3_E~0); 122977#L570-1 assume !(1 == ~T4_E~0); 123042#L575-1 assume !(1 == ~E_1~0); 123043#L580-1 assume !(1 == ~E_2~0); 123227#L585-1 assume !(1 == ~E_3~0); 123044#L590-1 assume !(1 == ~E_4~0); 123045#L595-1 assume { :end_inline_reset_delta_events } true; 128924#L776-2 assume !false; 128901#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128896#L477 [2021-12-19 19:17:28,271 INFO L793 eck$LassoCheckResult]: Loop: 128896#L477 assume !false; 128894#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 128891#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128889#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 128887#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 128885#L416 assume 0 != eval_~tmp~0#1; 128883#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 128880#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 128881#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 128929#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 128928#L435 assume !(0 == ~t2_st~0); 128923#L449 assume !(0 == ~t3_st~0); 128900#L463 assume !(0 == ~t4_st~0); 128896#L477 [2021-12-19 19:17:28,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,272 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2021-12-19 19:17:28,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637779536] [2021-12-19 19:17:28,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,283 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637779536] [2021-12-19 19:17:28,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637779536] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,284 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716713178] [2021-12-19 19:17:28,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,285 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,285 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 1 times [2021-12-19 19:17:28,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644669914] [2021-12-19 19:17:28,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,286 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,290 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:28,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,292 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:28,358 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,358 INFO L87 Difference]: Start difference. First operand 10241 states and 13681 transitions. cyclomatic complexity: 3464 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,374 INFO L93 Difference]: Finished difference Result 6046 states and 8082 transitions. [2021-12-19 19:17:28,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6046 states and 8082 transitions. [2021-12-19 19:17:28,389 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5853 [2021-12-19 19:17:28,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6046 states to 6046 states and 8082 transitions. [2021-12-19 19:17:28,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6046 [2021-12-19 19:17:28,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6046 [2021-12-19 19:17:28,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6046 states and 8082 transitions. [2021-12-19 19:17:28,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,406 INFO L681 BuchiCegarLoop]: Abstraction has 6046 states and 8082 transitions. [2021-12-19 19:17:28,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6046 states and 8082 transitions. [2021-12-19 19:17:28,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6046 to 6046. [2021-12-19 19:17:28,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6046 states, 6046 states have (on average 1.3367515712868012) internal successors, (8082), 6045 states have internal predecessors, (8082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6046 states to 6046 states and 8082 transitions. [2021-12-19 19:17:28,549 INFO L704 BuchiCegarLoop]: Abstraction has 6046 states and 8082 transitions. [2021-12-19 19:17:28,549 INFO L587 BuchiCegarLoop]: Abstraction has 6046 states and 8082 transitions. [2021-12-19 19:17:28,549 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:28,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6046 states and 8082 transitions. [2021-12-19 19:17:28,559 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5853 [2021-12-19 19:17:28,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,560 INFO L791 eck$LassoCheckResult]: Stem: 139641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 139577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 139213#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 139214#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139329#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 139442#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 139295#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 139296#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 139308#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 139309#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 139350#L502 assume !(0 == ~M_E~0); 139351#L502-2 assume !(0 == ~T1_E~0); 139283#L507-1 assume !(0 == ~T2_E~0); 139284#L512-1 assume !(0 == ~T3_E~0); 139445#L517-1 assume !(0 == ~T4_E~0); 139257#L522-1 assume !(0 == ~E_1~0); 139258#L527-1 assume !(0 == ~E_2~0); 139466#L532-1 assume !(0 == ~E_3~0); 139570#L537-1 assume !(0 == ~E_4~0); 139595#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139561#L238 assume !(1 == ~m_pc~0); 139562#L238-2 is_master_triggered_~__retres1~0#1 := 0; 139224#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139225#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 139539#L615 assume !(0 != activate_threads_~tmp~1#1); 139245#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139246#L257 assume !(1 == ~t1_pc~0); 139358#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 139359#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139396#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 139218#L623 assume !(0 != activate_threads_~tmp___0~0#1); 139219#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139215#L276 assume !(1 == ~t2_pc~0); 139216#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139476#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139310#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 139311#L631 assume !(0 != activate_threads_~tmp___1~0#1); 139608#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139536#L295 assume !(1 == ~t3_pc~0); 139325#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 139326#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139521#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139571#L639 assume !(0 != activate_threads_~tmp___2~0#1); 139563#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139564#L314 assume !(1 == ~t4_pc~0); 139363#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139362#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139566#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 139514#L647 assume !(0 != activate_threads_~tmp___3~0#1); 139459#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139460#L555 assume !(1 == ~M_E~0); 139378#L555-2 assume !(1 == ~T1_E~0); 139379#L560-1 assume !(1 == ~T2_E~0); 139259#L565-1 assume !(1 == ~T3_E~0); 139260#L570-1 assume !(1 == ~T4_E~0); 139337#L575-1 assume !(1 == ~E_1~0); 139338#L580-1 assume !(1 == ~E_2~0); 139515#L585-1 assume !(1 == ~E_3~0); 139336#L590-1 assume !(1 == ~E_4~0); 139327#L595-1 assume { :end_inline_reset_delta_events } true; 139328#L776-2 assume !false; 140995#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140990#L477 [2021-12-19 19:17:28,560 INFO L793 eck$LassoCheckResult]: Loop: 140990#L477 assume !false; 140989#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 140982#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 140980#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 140978#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 140976#L416 assume 0 != eval_~tmp~0#1; 140975#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 140974#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 140972#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 140969#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 140970#L435 assume !(0 == ~t2_st~0); 141073#L449 assume !(0 == ~t3_st~0); 140994#L463 assume !(0 == ~t4_st~0); 140990#L477 [2021-12-19 19:17:28,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,560 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2021-12-19 19:17:28,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538757357] [2021-12-19 19:17:28,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,565 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:28,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:28,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,580 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 2 times [2021-12-19 19:17:28,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671752114] [2021-12-19 19:17:28,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,583 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:28,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,585 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:28,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,585 INFO L85 PathProgramCache]: Analyzing trace with hash 2084563792, now seen corresponding path program 1 times [2021-12-19 19:17:28,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053902273] [2021-12-19 19:17:28,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053902273] [2021-12-19 19:17:28,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053902273] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574533742] [2021-12-19 19:17:28,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,664 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,665 INFO L87 Difference]: Start difference. First operand 6046 states and 8082 transitions. cyclomatic complexity: 2048 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,695 INFO L93 Difference]: Finished difference Result 9417 states and 12512 transitions. [2021-12-19 19:17:28,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9417 states and 12512 transitions. [2021-12-19 19:17:28,728 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9095 [2021-12-19 19:17:28,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9417 states to 9417 states and 12512 transitions. [2021-12-19 19:17:28,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9417 [2021-12-19 19:17:28,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9417 [2021-12-19 19:17:28,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9417 states and 12512 transitions. [2021-12-19 19:17:28,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,758 INFO L681 BuchiCegarLoop]: Abstraction has 9417 states and 12512 transitions. [2021-12-19 19:17:28,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9417 states and 12512 transitions. [2021-12-19 19:17:28,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9417 to 9417. [2021-12-19 19:17:28,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9417 states, 9417 states have (on average 1.3286609323563767) internal successors, (12512), 9416 states have internal predecessors, (12512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9417 states to 9417 states and 12512 transitions. [2021-12-19 19:17:28,836 INFO L704 BuchiCegarLoop]: Abstraction has 9417 states and 12512 transitions. [2021-12-19 19:17:28,836 INFO L587 BuchiCegarLoop]: Abstraction has 9417 states and 12512 transitions. [2021-12-19 19:17:28,836 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:28,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9417 states and 12512 transitions. [2021-12-19 19:17:28,854 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9095 [2021-12-19 19:17:28,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,855 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,855 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,855 INFO L791 eck$LassoCheckResult]: Stem: 155124#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 155055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 154684#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154685#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154805#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 154917#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154766#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154767#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154779#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154780#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154822#L502 assume !(0 == ~M_E~0); 154823#L502-2 assume !(0 == ~T1_E~0); 154757#L507-1 assume !(0 == ~T2_E~0); 154758#L512-1 assume !(0 == ~T3_E~0); 154920#L517-1 assume !(0 == ~T4_E~0); 154737#L522-1 assume !(0 == ~E_1~0); 154738#L527-1 assume !(0 == ~E_2~0); 154943#L532-1 assume !(0 == ~E_3~0); 155047#L537-1 assume !(0 == ~E_4~0); 155067#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155037#L238 assume !(1 == ~m_pc~0); 155038#L238-2 is_master_triggered_~__retres1~0#1 := 0; 154697#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154698#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 155012#L615 assume !(0 != activate_threads_~tmp~1#1); 154720#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154721#L257 assume !(1 == ~t1_pc~0); 154830#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154831#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154866#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 154691#L623 assume !(0 != activate_threads_~tmp___0~0#1); 154692#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154686#L276 assume !(1 == ~t2_pc~0); 154687#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154956#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154781#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 154782#L631 assume !(0 != activate_threads_~tmp___1~0#1); 155082#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155010#L295 assume !(1 == ~t3_pc~0); 154797#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154798#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154996#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 155048#L639 assume !(0 != activate_threads_~tmp___2~0#1); 155041#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155042#L314 assume !(1 == ~t4_pc~0); 154835#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 154834#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155043#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 154988#L647 assume !(0 != activate_threads_~tmp___3~0#1); 154936#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154937#L555 assume !(1 == ~M_E~0); 154847#L555-2 assume !(1 == ~T1_E~0); 154848#L560-1 assume !(1 == ~T2_E~0); 154739#L565-1 assume !(1 == ~T3_E~0); 154740#L570-1 assume !(1 == ~T4_E~0); 154809#L575-1 assume !(1 == ~E_1~0); 154810#L580-1 assume !(1 == ~E_2~0); 154989#L585-1 assume !(1 == ~E_3~0); 154808#L590-1 assume !(1 == ~E_4~0); 154799#L595-1 assume { :end_inline_reset_delta_events } true; 154800#L776-2 assume !false; 157318#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157313#L477 [2021-12-19 19:17:28,855 INFO L793 eck$LassoCheckResult]: Loop: 157313#L477 assume !false; 157311#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 157309#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 157306#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 157304#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 157302#L416 assume 0 != eval_~tmp~0#1; 157300#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 157297#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 157295#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 157292#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 157290#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 157227#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 157288#L449 assume !(0 == ~t3_st~0); 157317#L463 assume !(0 == ~t4_st~0); 157313#L477 [2021-12-19 19:17:28,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,856 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2021-12-19 19:17:28,856 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813235689] [2021-12-19 19:17:28,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,856 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,861 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:28,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,868 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:28,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,869 INFO L85 PathProgramCache]: Analyzing trace with hash -901553796, now seen corresponding path program 1 times [2021-12-19 19:17:28,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353088463] [2021-12-19 19:17:28,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,869 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,871 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:28,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:28,873 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:28,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,873 INFO L85 PathProgramCache]: Analyzing trace with hash 192225224, now seen corresponding path program 1 times [2021-12-19 19:17:28,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410431796] [2021-12-19 19:17:28,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410431796] [2021-12-19 19:17:28,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410431796] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,889 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725309991] [2021-12-19 19:17:28,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,960 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,961 INFO L87 Difference]: Start difference. First operand 9417 states and 12512 transitions. cyclomatic complexity: 3107 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,004 INFO L93 Difference]: Finished difference Result 10755 states and 14186 transitions. [2021-12-19 19:17:29,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:29,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10755 states and 14186 transitions. [2021-12-19 19:17:29,037 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10213 [2021-12-19 19:17:29,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10755 states to 10755 states and 14186 transitions. [2021-12-19 19:17:29,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10755 [2021-12-19 19:17:29,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10755 [2021-12-19 19:17:29,175 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10755 states and 14186 transitions. [2021-12-19 19:17:29,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,182 INFO L681 BuchiCegarLoop]: Abstraction has 10755 states and 14186 transitions. [2021-12-19 19:17:29,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10755 states and 14186 transitions. [2021-12-19 19:17:29,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10755 to 10381. [2021-12-19 19:17:29,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10381 states, 10381 states have (on average 1.3206820152201137) internal successors, (13710), 10380 states have internal predecessors, (13710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10381 states to 10381 states and 13710 transitions. [2021-12-19 19:17:29,266 INFO L704 BuchiCegarLoop]: Abstraction has 10381 states and 13710 transitions. [2021-12-19 19:17:29,266 INFO L587 BuchiCegarLoop]: Abstraction has 10381 states and 13710 transitions. [2021-12-19 19:17:29,266 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:29,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10381 states and 13710 transitions. [2021-12-19 19:17:29,288 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9839 [2021-12-19 19:17:29,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,289 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,290 INFO L791 eck$LassoCheckResult]: Stem: 175307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 175233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 174864#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174865#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174979#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 175089#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174944#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174945#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174957#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174958#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 175000#L502 assume !(0 == ~M_E~0); 175001#L502-2 assume !(0 == ~T1_E~0); 174933#L507-1 assume !(0 == ~T2_E~0); 174934#L512-1 assume !(0 == ~T3_E~0); 175092#L517-1 assume !(0 == ~T4_E~0); 174908#L522-1 assume !(0 == ~E_1~0); 174909#L527-1 assume !(0 == ~E_2~0); 175117#L532-1 assume !(0 == ~E_3~0); 175226#L537-1 assume !(0 == ~E_4~0); 175250#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 175215#L238 assume !(1 == ~m_pc~0); 175216#L238-2 is_master_triggered_~__retres1~0#1 := 0; 174875#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174876#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 175192#L615 assume !(0 != activate_threads_~tmp~1#1); 174896#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174897#L257 assume !(1 == ~t1_pc~0); 175008#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175009#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 175043#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174869#L623 assume !(0 != activate_threads_~tmp___0~0#1); 174870#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174866#L276 assume !(1 == ~t2_pc~0); 174867#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 175127#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174959#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174960#L631 assume !(0 != activate_threads_~tmp___1~0#1); 175266#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175190#L295 assume !(1 == ~t3_pc~0); 174975#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174976#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175171#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 175227#L639 assume !(0 != activate_threads_~tmp___2~0#1); 175217#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175218#L314 assume !(1 == ~t4_pc~0); 175013#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 175012#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175222#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 175163#L647 assume !(0 != activate_threads_~tmp___3~0#1); 175108#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175109#L555 assume !(1 == ~M_E~0); 175025#L555-2 assume !(1 == ~T1_E~0); 175026#L560-1 assume !(1 == ~T2_E~0); 174910#L565-1 assume !(1 == ~T3_E~0); 174911#L570-1 assume !(1 == ~T4_E~0); 174986#L575-1 assume !(1 == ~E_1~0); 174987#L580-1 assume !(1 == ~E_2~0); 175164#L585-1 assume !(1 == ~E_3~0); 174988#L590-1 assume !(1 == ~E_4~0); 174977#L595-1 assume { :end_inline_reset_delta_events } true; 174978#L776-2 assume !false; 179926#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179921#L477 [2021-12-19 19:17:29,290 INFO L793 eck$LassoCheckResult]: Loop: 179921#L477 assume !false; 179919#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 179916#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 179914#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 179912#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 179910#L416 assume 0 != eval_~tmp~0#1; 179907#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 179904#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 179902#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 179899#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 179897#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 179820#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 179896#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 179932#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 179925#L463 assume !(0 == ~t4_st~0); 179921#L477 [2021-12-19 19:17:29,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,290 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2021-12-19 19:17:29,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923922989] [2021-12-19 19:17:29,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,291 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,295 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:29,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,302 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:29,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,303 INFO L85 PathProgramCache]: Analyzing trace with hash 2116454956, now seen corresponding path program 1 times [2021-12-19 19:17:29,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628703499] [2021-12-19 19:17:29,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,306 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:29,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,307 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:29,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1663866208, now seen corresponding path program 1 times [2021-12-19 19:17:29,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685723853] [2021-12-19 19:17:29,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,325 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,325 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685723853] [2021-12-19 19:17:29,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685723853] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,325 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,326 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:29,326 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834800433] [2021-12-19 19:17:29,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,420 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:29,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:29,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:29,421 INFO L87 Difference]: Start difference. First operand 10381 states and 13710 transitions. cyclomatic complexity: 3341 Second operand has 3 states, 2 states have (on average 38.5) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,477 INFO L93 Difference]: Finished difference Result 19770 states and 26006 transitions. [2021-12-19 19:17:29,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:29,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19770 states and 26006 transitions. [2021-12-19 19:17:29,547 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18750 [2021-12-19 19:17:29,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19770 states to 19770 states and 26006 transitions. [2021-12-19 19:17:29,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19770 [2021-12-19 19:17:29,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19770 [2021-12-19 19:17:29,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19770 states and 26006 transitions. [2021-12-19 19:17:29,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,629 INFO L681 BuchiCegarLoop]: Abstraction has 19770 states and 26006 transitions. [2021-12-19 19:17:29,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19770 states and 26006 transitions. [2021-12-19 19:17:29,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19770 to 19770. [2021-12-19 19:17:29,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19770 states, 19770 states have (on average 1.3154274152756702) internal successors, (26006), 19769 states have internal predecessors, (26006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19770 states to 19770 states and 26006 transitions. [2021-12-19 19:17:29,904 INFO L704 BuchiCegarLoop]: Abstraction has 19770 states and 26006 transitions. [2021-12-19 19:17:29,905 INFO L587 BuchiCegarLoop]: Abstraction has 19770 states and 26006 transitions. [2021-12-19 19:17:29,905 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:29,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19770 states and 26006 transitions. [2021-12-19 19:17:29,955 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18750 [2021-12-19 19:17:29,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,957 INFO L791 eck$LassoCheckResult]: Stem: 205478#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 205397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 205023#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 205024#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205140#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 205252#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205103#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205104#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205116#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205117#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205159#L502 assume !(0 == ~M_E~0); 205160#L502-2 assume !(0 == ~T1_E~0); 205094#L507-1 assume !(0 == ~T2_E~0); 205095#L512-1 assume !(0 == ~T3_E~0); 205256#L517-1 assume !(0 == ~T4_E~0); 205073#L522-1 assume !(0 == ~E_1~0); 205074#L527-1 assume !(0 == ~E_2~0); 205277#L532-1 assume !(0 == ~E_3~0); 205385#L537-1 assume !(0 == ~E_4~0); 205413#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205373#L238 assume !(1 == ~m_pc~0); 205374#L238-2 is_master_triggered_~__retres1~0#1 := 0; 205036#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205037#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 205347#L615 assume !(0 != activate_threads_~tmp~1#1); 205059#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205060#L257 assume !(1 == ~t1_pc~0); 205167#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 205168#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205205#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205028#L623 assume !(0 != activate_threads_~tmp___0~0#1); 205029#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 205025#L276 assume !(1 == ~t2_pc~0); 205026#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205293#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205118#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205119#L631 assume !(0 != activate_threads_~tmp___1~0#1); 205428#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 205346#L295 assume !(1 == ~t3_pc~0); 205134#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 205135#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 205332#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205388#L639 assume !(0 != activate_threads_~tmp___2~0#1); 205377#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205378#L314 assume !(1 == ~t4_pc~0); 205173#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 205172#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 205379#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205325#L647 assume !(0 != activate_threads_~tmp___3~0#1); 205270#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205271#L555 assume !(1 == ~M_E~0); 205186#L555-2 assume !(1 == ~T1_E~0); 205187#L560-1 assume !(1 == ~T2_E~0); 205075#L565-1 assume !(1 == ~T3_E~0); 205076#L570-1 assume !(1 == ~T4_E~0); 205145#L575-1 assume !(1 == ~E_1~0); 205146#L580-1 assume !(1 == ~E_2~0); 205326#L585-1 assume !(1 == ~E_3~0); 205147#L590-1 assume !(1 == ~E_4~0); 205136#L595-1 assume { :end_inline_reset_delta_events } true; 205137#L776-2 assume !false; 212674#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212670#L477 [2021-12-19 19:17:29,957 INFO L793 eck$LassoCheckResult]: Loop: 212670#L477 assume !false; 212668#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 212665#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 212663#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 212661#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 212659#L416 assume 0 != eval_~tmp~0#1; 212656#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 212653#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 212651#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 212647#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 212645#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 212607#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 212643#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 213047#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 212678#L463 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 212672#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 212670#L477 [2021-12-19 19:17:29,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,957 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2021-12-19 19:17:29,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487168565] [2021-12-19 19:17:29,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,963 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:29,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,971 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:29,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1185593964, now seen corresponding path program 1 times [2021-12-19 19:17:29,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921134645] [2021-12-19 19:17:29,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,974 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:29,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,976 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:29,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,977 INFO L85 PathProgramCache]: Analyzing trace with hash 40244664, now seen corresponding path program 1 times [2021-12-19 19:17:29,977 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812092496] [2021-12-19 19:17:29,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,982 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:29,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:29,993 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:30,882 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.12 07:17:30 BoogieIcfgContainer [2021-12-19 19:17:30,882 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-19 19:17:30,882 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-19 19:17:30,883 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-19 19:17:30,883 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-19 19:17:30,883 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:24" (3/4) ... [2021-12-19 19:17:30,885 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-19 19:17:30,921 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-19 19:17:30,921 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-19 19:17:30,922 INFO L158 Benchmark]: Toolchain (without parser) took 7922.32ms. Allocated memory was 98.6MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 69.7MB in the beginning and 1.1GB in the end (delta: -995.9MB). Peak memory consumption was 514.6MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,922 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 98.6MB. Free memory was 55.6MB in the beginning and 55.5MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-19 19:17:30,922 INFO L158 Benchmark]: CACSL2BoogieTranslator took 241.90ms. Allocated memory is still 98.6MB. Free memory was 69.5MB in the beginning and 70.5MB in the end (delta: -1.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,922 INFO L158 Benchmark]: Boogie Procedure Inliner took 43.40ms. Allocated memory is still 98.6MB. Free memory was 70.5MB in the beginning and 66.7MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,922 INFO L158 Benchmark]: Boogie Preprocessor took 47.33ms. Allocated memory is still 98.6MB. Free memory was 66.7MB in the beginning and 63.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,922 INFO L158 Benchmark]: RCFGBuilder took 705.14ms. Allocated memory was 98.6MB in the beginning and 121.6MB in the end (delta: 23.1MB). Free memory was 63.3MB in the beginning and 80.4MB in the end (delta: -17.1MB). Peak memory consumption was 25.6MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,923 INFO L158 Benchmark]: BuchiAutomizer took 6839.76ms. Allocated memory was 121.6MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 80.4MB in the beginning and 1.1GB in the end (delta: -989.5MB). Peak memory consumption was 498.1MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,923 INFO L158 Benchmark]: Witness Printer took 38.71ms. Allocated memory is still 1.6GB. Free memory was 1.1GB in the beginning and 1.1GB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-19 19:17:30,924 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 98.6MB. Free memory was 55.6MB in the beginning and 55.5MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 241.90ms. Allocated memory is still 98.6MB. Free memory was 69.5MB in the beginning and 70.5MB in the end (delta: -1.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 43.40ms. Allocated memory is still 98.6MB. Free memory was 70.5MB in the beginning and 66.7MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 47.33ms. Allocated memory is still 98.6MB. Free memory was 66.7MB in the beginning and 63.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 705.14ms. Allocated memory was 98.6MB in the beginning and 121.6MB in the end (delta: 23.1MB). Free memory was 63.3MB in the beginning and 80.4MB in the end (delta: -17.1MB). Peak memory consumption was 25.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 6839.76ms. Allocated memory was 121.6MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 80.4MB in the beginning and 1.1GB in the end (delta: -989.5MB). Peak memory consumption was 498.1MB. Max. memory is 16.1GB. * Witness Printer took 38.71ms. Allocated memory is still 1.6GB. Free memory was 1.1GB in the beginning and 1.1GB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 19770 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.7s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.4s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 1.5s AutomataMinimizationTime, 22 MinimizatonAttempts, 14589 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had 19770 states and ocurred in iteration 22. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 14690 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 14690 mSDsluCounter, 25378 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 11837 mSDsCounter, 239 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 626 IncrementalHoareTripleChecker+Invalid, 865 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 239 mSolverCounterUnsat, 13541 mSDtfsCounter, 626 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e9d52d1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c91fb4f=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ff002a7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@694b085c=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55c98530=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50d1d6a3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@109547bb=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e1b68e7=0, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7698101=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d5ce06c=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2661d30d=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5dfd918=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@328ed14e=0, t1_st=0, __retres1=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) [L507] COND FALSE !(T1_E == 0) [L512] COND FALSE !(T2_E == 0) [L517] COND FALSE !(T3_E == 0) [L522] COND FALSE !(T4_E == 0) [L527] COND FALSE !(E_1 == 0) [L532] COND FALSE !(E_2 == 0) [L537] COND FALSE !(E_3 == 0) [L542] COND FALSE !(E_4 == 0) [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; [L238] COND FALSE !(m_pc == 1) [L248] __retres1 = 0 [L250] return (__retres1); [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; [L257] COND FALSE !(t1_pc == 1) [L267] __retres1 = 0 [L269] return (__retres1); [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; [L276] COND FALSE !(t2_pc == 1) [L286] __retres1 = 0 [L288] return (__retres1); [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; [L295] COND FALSE !(t3_pc == 1) [L305] __retres1 = 0 [L307] return (__retres1); [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; [L314] COND FALSE !(t4_pc == 1) [L324] __retres1 = 0 [L326] return (__retres1); [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) [L560] COND FALSE !(T1_E == 1) [L565] COND FALSE !(T2_E == 1) [L570] COND FALSE !(T3_E == 1) [L575] COND FALSE !(T4_E == 1) [L580] COND FALSE !(E_1 == 1) [L585] COND FALSE !(E_2 == 1) [L590] COND FALSE !(E_3 == 1) [L595] COND FALSE !(E_4 == 1) [L773] RET reset_delta_events() [L776] COND TRUE 1 [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-19 19:17:30,967 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)