./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:24,733 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:24,742 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:24,770 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:24,770 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:24,773 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:24,775 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:24,779 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:24,781 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:24,784 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:24,785 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:24,786 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:24,786 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:24,788 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:24,789 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:24,790 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:24,790 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:24,791 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:24,794 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:24,798 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:24,799 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:24,800 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:24,801 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:24,802 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:24,806 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:24,807 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:24,807 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:24,808 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:24,809 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:24,809 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:24,809 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:24,810 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:24,811 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:24,812 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:24,812 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:24,813 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:24,813 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:24,813 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:24,813 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:24,814 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:24,814 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:24,815 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:24,840 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:24,840 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:24,841 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:24,841 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:24,842 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:24,842 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:24,842 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:24,842 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:24,842 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:24,842 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:24,843 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:24,843 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:24,843 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:24,843 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:24,844 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:24,845 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:24,845 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:24,845 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:24,846 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:24,846 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:24,846 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:24,846 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:24,846 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:24,846 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:24,847 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:24,847 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:24,848 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:24,848 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2021-12-19 19:17:25,058 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:25,076 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:25,078 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:25,079 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:25,080 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:25,081 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-12-19 19:17:25,140 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f0327c86d/817c0653cff24bcc9529c82ed74f2a49/FLAG0080ea75f [2021-12-19 19:17:25,484 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:25,485 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-12-19 19:17:25,498 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f0327c86d/817c0653cff24bcc9529c82ed74f2a49/FLAG0080ea75f [2021-12-19 19:17:25,901 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f0327c86d/817c0653cff24bcc9529c82ed74f2a49 [2021-12-19 19:17:25,903 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:25,904 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:25,906 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:25,907 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:25,909 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:25,909 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:25" (1/1) ... [2021-12-19 19:17:25,910 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@20a81271 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:25, skipping insertion in model container [2021-12-19 19:17:25,910 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:25" (1/1) ... [2021-12-19 19:17:25,914 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:25,953 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:26,072 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2021-12-19 19:17:26,121 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:26,127 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:26,137 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2021-12-19 19:17:26,168 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:26,179 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:26,180 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26 WrapperNode [2021-12-19 19:17:26,180 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:26,181 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:26,181 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:26,181 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:26,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,193 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,236 INFO L137 Inliner]: procedures = 40, calls = 48, calls flagged for inlining = 43, calls inlined = 104, statements flattened = 1522 [2021-12-19 19:17:26,239 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:26,239 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:26,240 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:26,240 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:26,245 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,245 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,250 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,251 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,263 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,274 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,286 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,291 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:26,292 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:26,292 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:26,292 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:26,293 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (1/1) ... [2021-12-19 19:17:26,305 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:26,322 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:26,332 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:26,354 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:26,378 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:26,378 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:26,378 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:26,378 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:26,491 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:26,492 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:27,198 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:27,207 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:27,208 INFO L301 CfgBuilder]: Removed 10 assume(true) statements. [2021-12-19 19:17:27,210 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:27 BoogieIcfgContainer [2021-12-19 19:17:27,210 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:27,210 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:27,211 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:27,225 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:27,226 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:27,226 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:25" (1/3) ... [2021-12-19 19:17:27,227 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1567d391 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:27, skipping insertion in model container [2021-12-19 19:17:27,227 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:27,227 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:26" (2/3) ... [2021-12-19 19:17:27,227 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1567d391 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:27, skipping insertion in model container [2021-12-19 19:17:27,228 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:27,228 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:27" (3/3) ... [2021-12-19 19:17:27,229 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2021-12-19 19:17:27,262 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:27,262 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:27,262 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:27,262 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:27,262 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:27,262 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:27,263 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:27,263 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:27,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2021-12-19 19:17:27,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,334 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,334 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,335 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:27,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2021-12-19 19:17:27,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,347 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,352 INFO L791 eck$LassoCheckResult]: Stem: 625#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 513#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 414#L987true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5#L454true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 340#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 555#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 610#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 45#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 272#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 130#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 54#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 525#L670true assume !(0 == ~M_E~0); 301#L670-2true assume !(0 == ~T1_E~0); 251#L675-1true assume !(0 == ~T2_E~0); 338#L680-1true assume !(0 == ~T3_E~0); 432#L685-1true assume !(0 == ~T4_E~0); 306#L690-1true assume !(0 == ~T5_E~0); 609#L695-1true assume !(0 == ~T6_E~0); 384#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L705-1true assume !(0 == ~E_2~0); 547#L710-1true assume !(0 == ~E_3~0); 249#L715-1true assume !(0 == ~E_4~0); 192#L720-1true assume !(0 == ~E_5~0); 234#L725-1true assume !(0 == ~E_6~0); 275#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405#L320true assume 1 == ~m_pc~0; 222#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 153#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 498#L332true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131#L825true assume !(0 != activate_threads_~tmp~1#1); 447#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L339true assume !(1 == ~t1_pc~0); 420#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 121#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 388#L351true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57#L833true assume !(0 != activate_threads_~tmp___0~0#1); 537#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14#L358true assume 1 == ~t2_pc~0; 588#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 303#L370true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 238#L841true assume !(0 != activate_threads_~tmp___1~0#1); 128#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452#L377true assume !(1 == ~t3_pc~0); 320#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 330#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317#L389true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133#L849true assume !(0 != activate_threads_~tmp___2~0#1); 335#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L396true assume 1 == ~t4_pc~0; 443#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607#L408true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263#L857true assume !(0 != activate_threads_~tmp___3~0#1); 85#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122#L415true assume 1 == ~t5_pc~0; 324#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 276#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583#L427true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423#L865true assume !(0 != activate_threads_~tmp___4~0#1); 35#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 321#L434true assume !(1 == ~t6_pc~0); 214#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 351#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 604#L446true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 352#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 139#L873-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 535#L743true assume !(1 == ~M_E~0); 80#L743-2true assume !(1 == ~T1_E~0); 484#L748-1true assume !(1 == ~T2_E~0); 268#L753-1true assume !(1 == ~T3_E~0); 389#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 458#L763-1true assume !(1 == ~T5_E~0); 552#L768-1true assume !(1 == ~T6_E~0); 136#L773-1true assume !(1 == ~E_1~0); 623#L778-1true assume !(1 == ~E_2~0); 126#L783-1true assume !(1 == ~E_3~0); 597#L788-1true assume !(1 == ~E_4~0); 336#L793-1true assume !(1 == ~E_5~0); 293#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 65#L803-1true assume { :end_inline_reset_delta_events } true; 243#L1024-2true [2021-12-19 19:17:27,354 INFO L793 eck$LassoCheckResult]: Loop: 243#L1024-2true assume !false; 471#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 459#L645true assume false; 589#L660true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 367#L454-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 228#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 150#L675-3true assume !(0 == ~T2_E~0); 426#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 333#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 603#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 558#L695-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 346#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 632#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 93#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 379#L715-3true assume !(0 == ~E_4~0); 240#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 307#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 495#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L320-21true assume 1 == ~m_pc~0; 456#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 530#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185#L332-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 473#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 441#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99#L339-21true assume !(1 == ~t1_pc~0); 265#L339-23true is_transmit1_triggered_~__retres1~1#1 := 0; 620#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86#L351-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 580#L358-21true assume !(1 == ~t2_pc~0); 104#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 66#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#L370-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 395#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464#L377-21true assume 1 == ~t3_pc~0; 561#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 262#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357#L389-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 167#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294#L396-21true assume !(1 == ~t4_pc~0); 184#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 223#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165#L408-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18#L857-21true assume !(0 != activate_threads_~tmp___3~0#1); 297#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151#L415-21true assume 1 == ~t5_pc~0; 507#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 425#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77#L427-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 219#L865-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 195#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L434-21true assume !(1 == ~t6_pc~0); 30#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 419#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431#L446-7true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 147#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256#L873-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 491#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 554#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 257#L753-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 209#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 161#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 522#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 465#L773-3true assume !(1 == ~E_1~0); 112#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 260#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 571#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 516#L793-3true assume 1 == ~E_5~0;~E_5~0 := 2; 529#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 299#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 391#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 203#L542-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 434#L1043true assume !(0 == start_simulation_~tmp~3#1); 429#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 258#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 323#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 236#L542-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 226#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 140#L1006true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 218#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 243#L1024-2true [2021-12-19 19:17:27,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2021-12-19 19:17:27,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500464321] [2021-12-19 19:17:27,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500464321] [2021-12-19 19:17:27,508 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500464321] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,508 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,508 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,509 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851924118] [2021-12-19 19:17:27,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:27,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,514 INFO L85 PathProgramCache]: Analyzing trace with hash -243567112, now seen corresponding path program 1 times [2021-12-19 19:17:27,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535939745] [2021-12-19 19:17:27,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535939745] [2021-12-19 19:17:27,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535939745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:27,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737904015] [2021-12-19 19:17:27,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,540 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:27,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:27,562 INFO L87 Difference]: Start difference. First operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,605 INFO L93 Difference]: Finished difference Result 632 states and 943 transitions. [2021-12-19 19:17:27,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:27,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 632 states and 943 transitions. [2021-12-19 19:17:27,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 632 states to 626 states and 937 transitions. [2021-12-19 19:17:27,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:27,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:27,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 937 transitions. [2021-12-19 19:17:27,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,630 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-19 19:17:27,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 937 transitions. [2021-12-19 19:17:27,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:27,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 937 transitions. [2021-12-19 19:17:27,668 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-19 19:17:27,668 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-19 19:17:27,668 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:27,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 937 transitions. [2021-12-19 19:17:27,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,673 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,673 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,674 INFO L791 eck$LassoCheckResult]: Stem: 1899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1834#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1278#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1274#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1275#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1893#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1370#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1371#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1523#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1387#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1388#L670 assume !(0 == ~M_E~0); 1758#L670-2 assume !(0 == ~T1_E~0); 1706#L675-1 assume !(0 == ~T2_E~0); 1707#L680-1 assume !(0 == ~T3_E~0); 1788#L685-1 assume !(0 == ~T4_E~0); 1761#L690-1 assume !(0 == ~T5_E~0); 1762#L695-1 assume !(0 == ~T6_E~0); 1820#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1812#L705-1 assume !(0 == ~E_2~0); 1813#L710-1 assume !(0 == ~E_3~0); 1705#L715-1 assume !(0 == ~E_4~0); 1629#L720-1 assume !(0 == ~E_5~0); 1630#L725-1 assume !(0 == ~E_6~0); 1683#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1730#L320 assume 1 == ~m_pc~0; 1671#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1565#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1566#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1524#L825 assume !(0 != activate_threads_~tmp~1#1); 1525#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1530#L339 assume !(1 == ~t1_pc~0); 1531#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1508#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1509#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1390#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1391#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1299#L358 assume 1 == ~t2_pc~0; 1300#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1808#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1759#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1687#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1521#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1522#L377 assume !(1 == ~t3_pc~0); 1774#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1775#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1529#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1474#L396 assume 1 == ~t4_pc~0; 1475#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1302#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1303#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1721#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1443#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1444#L415 assume 1 == ~t5_pc~0; 1510#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1555#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1838#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1345#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1346#L434 assume !(1 == ~t6_pc~0); 1660#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1661#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1800#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1801#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1541#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1542#L743 assume !(1 == ~M_E~0); 1435#L743-2 assume !(1 == ~T1_E~0); 1436#L748-1 assume !(1 == ~T2_E~0); 1724#L753-1 assume !(1 == ~T3_E~0); 1725#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1824#L763-1 assume !(1 == ~T5_E~0); 1856#L768-1 assume !(1 == ~T6_E~0); 1536#L773-1 assume !(1 == ~E_1~0); 1537#L778-1 assume !(1 == ~E_2~0); 1516#L783-1 assume !(1 == ~E_3~0); 1517#L788-1 assume !(1 == ~E_4~0); 1786#L793-1 assume !(1 == ~E_5~0); 1751#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1407#L803-1 assume { :end_inline_reset_delta_events } true; 1408#L1024-2 [2021-12-19 19:17:27,674 INFO L793 eck$LassoCheckResult]: Loop: 1408#L1024-2 assume !false; 1693#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1748#L645 assume !false; 1625#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1626#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1353#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1830#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1863#L556 assume !(0 != eval_~tmp~0#1); 1897#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1807#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1402#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1562#L675-3 assume !(0 == ~T2_E~0); 1563#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1783#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1784#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1894#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1794#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1456#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1457#L715-3 assume !(0 == ~E_4~0); 1688#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1689#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1763#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1538#L320-21 assume 1 == ~m_pc~0; 1539#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1686#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1612#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1613#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1848#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1469#L339-21 assume !(1 == ~t1_pc~0); 1470#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1573#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1445#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1327#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1328#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1427#L358-21 assume !(1 == ~t2_pc~0); 1481#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1409#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1692#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1446#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447#L377-21 assume 1 == ~t3_pc~0; 1859#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1718#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1719#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1739#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1584#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1585#L396-21 assume 1 == ~t4_pc~0; 1752#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1611#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1582#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1309#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 1310#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L415-21 assume 1 == ~t5_pc~0; 1561#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1535#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1632#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633#L434-21 assume !(1 == ~t6_pc~0); 1332#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1333#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1835#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1556#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1557#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1552#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1872#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1714#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1652#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1575#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1576#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1860#L773-3 assume !(1 == ~E_1~0); 1494#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1884#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1885#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1756#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1485#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1381#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1645#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1646#L1043 assume !(0 == start_simulation_~tmp~3#1); 1839#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1715#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1684#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1673#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1395#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1396#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1543#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1408#L1024-2 [2021-12-19 19:17:27,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2021-12-19 19:17:27,675 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,675 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936286591] [2021-12-19 19:17:27,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936286591] [2021-12-19 19:17:27,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936286591] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,712 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010565287] [2021-12-19 19:17:27,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,713 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:27,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,714 INFO L85 PathProgramCache]: Analyzing trace with hash 2030983010, now seen corresponding path program 1 times [2021-12-19 19:17:27,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372706500] [2021-12-19 19:17:27,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,714 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,782 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372706500] [2021-12-19 19:17:27,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372706500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,783 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990594025] [2021-12-19 19:17:27,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,784 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,785 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:27,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:27,786 INFO L87 Difference]: Start difference. First operand 626 states and 937 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,801 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2021-12-19 19:17:27,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:27,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 936 transitions. [2021-12-19 19:17:27,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 936 transitions. [2021-12-19 19:17:27,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:27,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:27,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 936 transitions. [2021-12-19 19:17:27,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,814 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-19 19:17:27,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 936 transitions. [2021-12-19 19:17:27,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:27,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 936 transitions. [2021-12-19 19:17:27,835 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-19 19:17:27,835 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-19 19:17:27,835 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:27,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 936 transitions. [2021-12-19 19:17:27,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,842 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,843 INFO L791 eck$LassoCheckResult]: Stem: 3158#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 3141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3093#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2537#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2533#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2534#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3049#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3152#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2629#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2630#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2782#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2647#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2648#L670 assume !(0 == ~M_E~0); 3017#L670-2 assume !(0 == ~T1_E~0); 2965#L675-1 assume !(0 == ~T2_E~0); 2966#L680-1 assume !(0 == ~T3_E~0); 3047#L685-1 assume !(0 == ~T4_E~0); 3021#L690-1 assume !(0 == ~T5_E~0); 3022#L695-1 assume !(0 == ~T6_E~0); 3079#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3071#L705-1 assume !(0 == ~E_2~0); 3072#L710-1 assume !(0 == ~E_3~0); 2964#L715-1 assume !(0 == ~E_4~0); 2888#L720-1 assume !(0 == ~E_5~0); 2889#L725-1 assume !(0 == ~E_6~0); 2942#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2989#L320 assume 1 == ~m_pc~0; 2930#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2824#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2825#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2783#L825 assume !(0 != activate_threads_~tmp~1#1); 2784#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2790#L339 assume !(1 == ~t1_pc~0); 2791#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2767#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2768#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2649#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2650#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2558#L358 assume 1 == ~t2_pc~0; 2559#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3067#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3018#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2946#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2780#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2781#L377 assume !(1 == ~t3_pc~0); 3033#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3034#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3029#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2787#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2788#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2735#L396 assume 1 == ~t4_pc~0; 2736#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2561#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2562#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2980#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2702#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2703#L415 assume 1 == ~t5_pc~0; 2770#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2814#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2990#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3097#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2604#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2605#L434 assume !(1 == ~t6_pc~0); 2920#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2921#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3059#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3060#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2800#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L743 assume !(1 == ~M_E~0); 2694#L743-2 assume !(1 == ~T1_E~0); 2695#L748-1 assume !(1 == ~T2_E~0); 2984#L753-1 assume !(1 == ~T3_E~0); 2985#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3083#L763-1 assume !(1 == ~T5_E~0); 3115#L768-1 assume !(1 == ~T6_E~0); 2798#L773-1 assume !(1 == ~E_1~0); 2799#L778-1 assume !(1 == ~E_2~0); 2775#L783-1 assume !(1 == ~E_3~0); 2776#L788-1 assume !(1 == ~E_4~0); 3045#L793-1 assume !(1 == ~E_5~0); 3010#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2668#L803-1 assume { :end_inline_reset_delta_events } true; 2669#L1024-2 [2021-12-19 19:17:27,844 INFO L793 eck$LassoCheckResult]: Loop: 2669#L1024-2 assume !false; 2952#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3007#L645 assume !false; 2884#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2885#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2612#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3089#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3124#L556 assume !(0 != eval_~tmp~0#1); 3156#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3066#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2662#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2663#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2821#L675-3 assume !(0 == ~T2_E~0); 2822#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3042#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3043#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3153#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3051#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3052#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2715#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2716#L715-3 assume !(0 == ~E_4~0); 2947#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2948#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3020#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2793#L320-21 assume 1 == ~m_pc~0; 2794#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2945#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2871#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2872#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3106#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2728#L339-21 assume !(1 == ~t1_pc~0); 2729#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 2832#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2586#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2587#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2686#L358-21 assume !(1 == ~t2_pc~0); 2740#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2666#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2667#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2951#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2705#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2706#L377-21 assume !(1 == ~t3_pc~0); 3062#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2977#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2978#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2998#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2843#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2844#L396-21 assume 1 == ~t4_pc~0; 3011#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2870#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2841#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2568#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 2569#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2819#L415-21 assume 1 == ~t5_pc~0; 2820#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2797#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2690#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2691#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2891#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2892#L434-21 assume !(1 == ~t6_pc~0); 2593#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 2594#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3095#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2815#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2816#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2810#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2973#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2911#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2834#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2835#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3119#L773-3 assume !(1 == ~E_1~0); 2753#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2754#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2976#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3143#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3144#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3016#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2744#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2904#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2905#L1043 assume !(0 == start_simulation_~tmp~3#1); 3098#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2974#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2761#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2944#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2932#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2654#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2655#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2802#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2669#L1024-2 [2021-12-19 19:17:27,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,847 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2021-12-19 19:17:27,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798947597] [2021-12-19 19:17:27,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798947597] [2021-12-19 19:17:27,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798947597] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,896 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,896 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247888662] [2021-12-19 19:17:27,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,896 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:27,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,897 INFO L85 PathProgramCache]: Analyzing trace with hash 300645953, now seen corresponding path program 1 times [2021-12-19 19:17:27,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136711611] [2021-12-19 19:17:27,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,898 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:27,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:27,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:27,956 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:27,956 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136711611] [2021-12-19 19:17:27,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136711611] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:27,957 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:27,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:27,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694843722] [2021-12-19 19:17:27,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:27,957 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:27,958 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:27,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:27,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:27,958 INFO L87 Difference]: Start difference. First operand 626 states and 936 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:27,970 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2021-12-19 19:17:27,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:27,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 935 transitions. [2021-12-19 19:17:27,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 935 transitions. [2021-12-19 19:17:27,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:27,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:27,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 935 transitions. [2021-12-19 19:17:27,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:27,978 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-19 19:17:27,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 935 transitions. [2021-12-19 19:17:27,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:27,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:27,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 935 transitions. [2021-12-19 19:17:27,987 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-19 19:17:27,987 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-19 19:17:27,987 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:27,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 935 transitions. [2021-12-19 19:17:27,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:27,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:27,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:27,994 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,994 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:27,994 INFO L791 eck$LassoCheckResult]: Stem: 4417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4352#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3796#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3792#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3793#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4307#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4411#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3886#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3887#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4041#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3906#L670 assume !(0 == ~M_E~0); 4276#L670-2 assume !(0 == ~T1_E~0); 4224#L675-1 assume !(0 == ~T2_E~0); 4225#L680-1 assume !(0 == ~T3_E~0); 4306#L685-1 assume !(0 == ~T4_E~0); 4279#L690-1 assume !(0 == ~T5_E~0); 4280#L695-1 assume !(0 == ~T6_E~0); 4338#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4330#L705-1 assume !(0 == ~E_2~0); 4331#L710-1 assume !(0 == ~E_3~0); 4222#L715-1 assume !(0 == ~E_4~0); 4145#L720-1 assume !(0 == ~E_5~0); 4146#L725-1 assume !(0 == ~E_6~0); 4201#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4248#L320 assume 1 == ~m_pc~0; 4189#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4083#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4084#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4042#L825 assume !(0 != activate_threads_~tmp~1#1); 4043#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4048#L339 assume !(1 == ~t1_pc~0); 4049#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4026#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4027#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3908#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3909#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3817#L358 assume 1 == ~t2_pc~0; 3818#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4326#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4277#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4205#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4037#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4038#L377 assume !(1 == ~t3_pc~0); 4292#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4293#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4288#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4046#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4047#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L396 assume 1 == ~t4_pc~0; 3993#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3820#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3821#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4239#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3961#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3962#L415 assume 1 == ~t5_pc~0; 4028#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4071#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4249#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4356#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3863#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3864#L434 assume !(1 == ~t6_pc~0); 4178#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4179#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4318#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4319#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4059#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4060#L743 assume !(1 == ~M_E~0); 3953#L743-2 assume !(1 == ~T1_E~0); 3954#L748-1 assume !(1 == ~T2_E~0); 4242#L753-1 assume !(1 == ~T3_E~0); 4243#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4342#L763-1 assume !(1 == ~T5_E~0); 4374#L768-1 assume !(1 == ~T6_E~0); 4052#L773-1 assume !(1 == ~E_1~0); 4053#L778-1 assume !(1 == ~E_2~0); 4034#L783-1 assume !(1 == ~E_3~0); 4035#L788-1 assume !(1 == ~E_4~0); 4304#L793-1 assume !(1 == ~E_5~0); 4269#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3925#L803-1 assume { :end_inline_reset_delta_events } true; 3926#L1024-2 [2021-12-19 19:17:27,995 INFO L793 eck$LassoCheckResult]: Loop: 3926#L1024-2 assume !false; 4211#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4266#L645 assume !false; 4143#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4144#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4348#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4381#L556 assume !(0 != eval_~tmp~0#1); 4415#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4325#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3917#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3918#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4078#L675-3 assume !(0 == ~T2_E~0); 4079#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4301#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4302#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4412#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4310#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4311#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3974#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3975#L715-3 assume !(0 == ~E_4~0); 4206#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4207#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4281#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4054#L320-21 assume 1 == ~m_pc~0; 4055#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4204#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4130#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4131#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4365#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3987#L339-21 assume !(1 == ~t1_pc~0); 3988#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4091#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3963#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3845#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3846#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3945#L358-21 assume 1 == ~t2_pc~0; 4051#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3927#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3928#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4210#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3964#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3965#L377-21 assume !(1 == ~t3_pc~0); 4321#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4237#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4238#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4257#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4102#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4103#L396-21 assume !(1 == ~t4_pc~0); 4128#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4129#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4100#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3827#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 3828#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4080#L415-21 assume 1 == ~t5_pc~0; 4081#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4058#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3949#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3950#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4150#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4151#L434-21 assume 1 == ~t6_pc~0; 4162#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3853#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4354#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4074#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4075#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4070#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4390#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4232#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4170#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4093#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4094#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4378#L773-3 assume !(1 == ~E_1~0); 4012#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4013#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4235#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4402#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4403#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4275#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4003#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3899#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4163#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4164#L1043 assume !(0 == start_simulation_~tmp~3#1); 4357#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4233#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4021#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4203#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4191#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3913#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3914#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4061#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3926#L1024-2 [2021-12-19 19:17:27,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:27,996 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2021-12-19 19:17:27,996 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:27,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180005528] [2021-12-19 19:17:27,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:27,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180005528] [2021-12-19 19:17:28,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180005528] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,052 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949050679] [2021-12-19 19:17:28,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,055 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1901181918, now seen corresponding path program 1 times [2021-12-19 19:17:28,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480824829] [2021-12-19 19:17:28,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480824829] [2021-12-19 19:17:28,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480824829] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,115 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007246049] [2021-12-19 19:17:28,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,116 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,118 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,119 INFO L87 Difference]: Start difference. First operand 626 states and 935 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,130 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2021-12-19 19:17:28,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 934 transitions. [2021-12-19 19:17:28,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 934 transitions. [2021-12-19 19:17:28,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:28,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:28,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 934 transitions. [2021-12-19 19:17:28,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,137 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-19 19:17:28,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 934 transitions. [2021-12-19 19:17:28,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:28,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 934 transitions. [2021-12-19 19:17:28,144 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-19 19:17:28,144 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-19 19:17:28,144 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:28,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 934 transitions. [2021-12-19 19:17:28,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,148 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,148 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,148 INFO L791 eck$LassoCheckResult]: Stem: 5676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5611#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5055#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5051#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5052#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5566#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5670#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5145#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5146#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5300#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5164#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5165#L670 assume !(0 == ~M_E~0); 5535#L670-2 assume !(0 == ~T1_E~0); 5483#L675-1 assume !(0 == ~T2_E~0); 5484#L680-1 assume !(0 == ~T3_E~0); 5565#L685-1 assume !(0 == ~T4_E~0); 5538#L690-1 assume !(0 == ~T5_E~0); 5539#L695-1 assume !(0 == ~T6_E~0); 5597#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5589#L705-1 assume !(0 == ~E_2~0); 5590#L710-1 assume !(0 == ~E_3~0); 5481#L715-1 assume !(0 == ~E_4~0); 5404#L720-1 assume !(0 == ~E_5~0); 5405#L725-1 assume !(0 == ~E_6~0); 5460#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5507#L320 assume 1 == ~m_pc~0; 5448#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5342#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5343#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5301#L825 assume !(0 != activate_threads_~tmp~1#1); 5302#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5307#L339 assume !(1 == ~t1_pc~0); 5308#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5285#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5286#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5167#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5168#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5076#L358 assume 1 == ~t2_pc~0; 5077#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5585#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5536#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5464#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5296#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5297#L377 assume !(1 == ~t3_pc~0); 5551#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5552#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5547#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5305#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5306#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5251#L396 assume 1 == ~t4_pc~0; 5252#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5079#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5080#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5498#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5220#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L415 assume 1 == ~t5_pc~0; 5287#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5330#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5508#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5615#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5122#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5123#L434 assume !(1 == ~t6_pc~0); 5437#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5438#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5577#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5578#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5318#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5319#L743 assume !(1 == ~M_E~0); 5212#L743-2 assume !(1 == ~T1_E~0); 5213#L748-1 assume !(1 == ~T2_E~0); 5501#L753-1 assume !(1 == ~T3_E~0); 5502#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5601#L763-1 assume !(1 == ~T5_E~0); 5633#L768-1 assume !(1 == ~T6_E~0); 5311#L773-1 assume !(1 == ~E_1~0); 5312#L778-1 assume !(1 == ~E_2~0); 5293#L783-1 assume !(1 == ~E_3~0); 5294#L788-1 assume !(1 == ~E_4~0); 5563#L793-1 assume !(1 == ~E_5~0); 5528#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5184#L803-1 assume { :end_inline_reset_delta_events } true; 5185#L1024-2 [2021-12-19 19:17:28,148 INFO L793 eck$LassoCheckResult]: Loop: 5185#L1024-2 assume !false; 5470#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5525#L645 assume !false; 5402#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5403#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5130#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5607#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5640#L556 assume !(0 != eval_~tmp~0#1); 5674#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5584#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5176#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5177#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5337#L675-3 assume !(0 == ~T2_E~0); 5338#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5560#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5561#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5671#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5569#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5570#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5233#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5234#L715-3 assume !(0 == ~E_4~0); 5465#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5466#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5540#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5313#L320-21 assume 1 == ~m_pc~0; 5314#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5463#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5389#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5390#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5624#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5246#L339-21 assume 1 == ~t1_pc~0; 5248#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5350#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5222#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5104#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5105#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5204#L358-21 assume !(1 == ~t2_pc~0); 5258#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5186#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5187#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5469#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5223#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5224#L377-21 assume 1 == ~t3_pc~0; 5636#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5496#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5497#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5516#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5362#L396-21 assume 1 == ~t4_pc~0; 5529#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5359#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5086#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 5087#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5339#L415-21 assume !(1 == ~t5_pc~0); 5316#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5317#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5208#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5209#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5409#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5410#L434-21 assume !(1 == ~t6_pc~0); 5111#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 5112#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5613#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5333#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5334#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5328#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5329#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5649#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5491#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5429#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5352#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5353#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5637#L773-3 assume !(1 == ~E_1~0); 5271#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5272#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5494#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5661#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5662#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5534#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5262#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5158#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5422#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5423#L1043 assume !(0 == start_simulation_~tmp~3#1); 5616#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5492#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5280#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5462#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5450#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5172#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5173#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5320#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5185#L1024-2 [2021-12-19 19:17:28,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2021-12-19 19:17:28,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41177300] [2021-12-19 19:17:28,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,171 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,171 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41177300] [2021-12-19 19:17:28,171 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41177300] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,171 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,171 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,171 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854404458] [2021-12-19 19:17:28,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,172 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,172 INFO L85 PathProgramCache]: Analyzing trace with hash 734577762, now seen corresponding path program 1 times [2021-12-19 19:17:28,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280915860] [2021-12-19 19:17:28,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,210 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280915860] [2021-12-19 19:17:28,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280915860] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,210 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217362819] [2021-12-19 19:17:28,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,211 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,211 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,212 INFO L87 Difference]: Start difference. First operand 626 states and 934 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,221 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2021-12-19 19:17:28,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 933 transitions. [2021-12-19 19:17:28,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 933 transitions. [2021-12-19 19:17:28,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:28,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:28,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 933 transitions. [2021-12-19 19:17:28,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,230 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-19 19:17:28,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 933 transitions. [2021-12-19 19:17:28,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:28,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 933 transitions. [2021-12-19 19:17:28,237 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-19 19:17:28,237 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-19 19:17:28,237 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:28,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 933 transitions. [2021-12-19 19:17:28,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,240 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,240 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,241 INFO L791 eck$LassoCheckResult]: Stem: 6935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6870#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6314#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6310#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6311#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6826#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6929#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6404#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6405#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6559#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6423#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6424#L670 assume !(0 == ~M_E~0); 6794#L670-2 assume !(0 == ~T1_E~0); 6742#L675-1 assume !(0 == ~T2_E~0); 6743#L680-1 assume !(0 == ~T3_E~0); 6824#L685-1 assume !(0 == ~T4_E~0); 6797#L690-1 assume !(0 == ~T5_E~0); 6798#L695-1 assume !(0 == ~T6_E~0); 6856#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6848#L705-1 assume !(0 == ~E_2~0); 6849#L710-1 assume !(0 == ~E_3~0); 6740#L715-1 assume !(0 == ~E_4~0); 6663#L720-1 assume !(0 == ~E_5~0); 6664#L725-1 assume !(0 == ~E_6~0); 6719#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6766#L320 assume 1 == ~m_pc~0; 6707#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6601#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6602#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6560#L825 assume !(0 != activate_threads_~tmp~1#1); 6561#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6566#L339 assume !(1 == ~t1_pc~0); 6567#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6544#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6545#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6426#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6427#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6335#L358 assume 1 == ~t2_pc~0; 6336#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6844#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6795#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6723#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6557#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6558#L377 assume !(1 == ~t3_pc~0); 6810#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6811#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6806#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6564#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6510#L396 assume 1 == ~t4_pc~0; 6511#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6338#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6339#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6757#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6479#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6480#L415 assume 1 == ~t5_pc~0; 6546#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6591#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6767#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6874#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6381#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6382#L434 assume !(1 == ~t6_pc~0); 6696#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6697#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6836#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6837#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6577#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6578#L743 assume !(1 == ~M_E~0); 6471#L743-2 assume !(1 == ~T1_E~0); 6472#L748-1 assume !(1 == ~T2_E~0); 6760#L753-1 assume !(1 == ~T3_E~0); 6761#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6860#L763-1 assume !(1 == ~T5_E~0); 6892#L768-1 assume !(1 == ~T6_E~0); 6572#L773-1 assume !(1 == ~E_1~0); 6573#L778-1 assume !(1 == ~E_2~0); 6552#L783-1 assume !(1 == ~E_3~0); 6553#L788-1 assume !(1 == ~E_4~0); 6822#L793-1 assume !(1 == ~E_5~0); 6787#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6443#L803-1 assume { :end_inline_reset_delta_events } true; 6444#L1024-2 [2021-12-19 19:17:28,241 INFO L793 eck$LassoCheckResult]: Loop: 6444#L1024-2 assume !false; 6729#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6784#L645 assume !false; 6661#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6662#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6389#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6866#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6899#L556 assume !(0 != eval_~tmp~0#1); 6933#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6843#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6437#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6438#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6598#L675-3 assume !(0 == ~T2_E~0); 6599#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6819#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6820#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6930#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6828#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6829#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6492#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6493#L715-3 assume !(0 == ~E_4~0); 6724#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6725#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6799#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6574#L320-21 assume !(1 == ~m_pc~0); 6576#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6722#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6648#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6649#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6884#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6505#L339-21 assume !(1 == ~t1_pc~0); 6506#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 6609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6481#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6363#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6364#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6463#L358-21 assume !(1 == ~t2_pc~0); 6517#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 6445#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6446#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6728#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6482#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6483#L377-21 assume 1 == ~t3_pc~0; 6896#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6755#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6756#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6775#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6621#L396-21 assume 1 == ~t4_pc~0; 6788#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6647#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6618#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6345#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 6346#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6596#L415-21 assume 1 == ~t5_pc~0; 6597#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6571#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6467#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6468#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6668#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6669#L434-21 assume !(1 == ~t6_pc~0); 6368#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6369#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6871#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6592#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6593#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6587#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6588#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6908#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6750#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6687#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6895#L773-3 assume !(1 == ~E_1~0); 6530#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6531#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6753#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6920#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6921#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6792#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6521#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6417#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6681#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6682#L1043 assume !(0 == start_simulation_~tmp~3#1); 6875#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6751#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6538#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6720#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6709#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6431#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6432#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6579#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6444#L1024-2 [2021-12-19 19:17:28,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,245 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2021-12-19 19:17:28,245 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540425857] [2021-12-19 19:17:28,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540425857] [2021-12-19 19:17:28,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540425857] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329411619] [2021-12-19 19:17:28,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,274 INFO L85 PathProgramCache]: Analyzing trace with hash -426171263, now seen corresponding path program 1 times [2021-12-19 19:17:28,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552417667] [2021-12-19 19:17:28,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,314 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552417667] [2021-12-19 19:17:28,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552417667] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,318 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566353873] [2021-12-19 19:17:28,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,319 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,319 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,320 INFO L87 Difference]: Start difference. First operand 626 states and 933 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,329 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2021-12-19 19:17:28,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 932 transitions. [2021-12-19 19:17:28,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 932 transitions. [2021-12-19 19:17:28,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:28,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:28,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 932 transitions. [2021-12-19 19:17:28,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,337 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-19 19:17:28,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 932 transitions. [2021-12-19 19:17:28,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:28,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 932 transitions. [2021-12-19 19:17:28,344 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-19 19:17:28,344 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-19 19:17:28,344 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:28,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 932 transitions. [2021-12-19 19:17:28,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,348 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,348 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,348 INFO L791 eck$LassoCheckResult]: Stem: 8194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8129#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7573#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7569#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7570#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8085#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8188#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7665#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7666#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7818#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7683#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7684#L670 assume !(0 == ~M_E~0); 8053#L670-2 assume !(0 == ~T1_E~0); 8001#L675-1 assume !(0 == ~T2_E~0); 8002#L680-1 assume !(0 == ~T3_E~0); 8083#L685-1 assume !(0 == ~T4_E~0); 8057#L690-1 assume !(0 == ~T5_E~0); 8058#L695-1 assume !(0 == ~T6_E~0); 8115#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8107#L705-1 assume !(0 == ~E_2~0); 8108#L710-1 assume !(0 == ~E_3~0); 8000#L715-1 assume !(0 == ~E_4~0); 7924#L720-1 assume !(0 == ~E_5~0); 7925#L725-1 assume !(0 == ~E_6~0); 7978#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8025#L320 assume 1 == ~m_pc~0; 7966#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7860#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7861#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7819#L825 assume !(0 != activate_threads_~tmp~1#1); 7820#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7826#L339 assume !(1 == ~t1_pc~0); 7827#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7803#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7804#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7685#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7686#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7594#L358 assume 1 == ~t2_pc~0; 7595#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8103#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8054#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7982#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7816#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7817#L377 assume !(1 == ~t3_pc~0); 8069#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8070#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8065#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7823#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7824#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7769#L396 assume 1 == ~t4_pc~0; 7770#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7597#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7598#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8016#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7738#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7739#L415 assume 1 == ~t5_pc~0; 7806#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7850#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8026#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8133#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7640#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7641#L434 assume !(1 == ~t6_pc~0); 7955#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7956#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8095#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8096#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7836#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7837#L743 assume !(1 == ~M_E~0); 7730#L743-2 assume !(1 == ~T1_E~0); 7731#L748-1 assume !(1 == ~T2_E~0); 8019#L753-1 assume !(1 == ~T3_E~0); 8020#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8119#L763-1 assume !(1 == ~T5_E~0); 8151#L768-1 assume !(1 == ~T6_E~0); 7834#L773-1 assume !(1 == ~E_1~0); 7835#L778-1 assume !(1 == ~E_2~0); 7811#L783-1 assume !(1 == ~E_3~0); 7812#L788-1 assume !(1 == ~E_4~0); 8081#L793-1 assume !(1 == ~E_5~0); 8046#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7704#L803-1 assume { :end_inline_reset_delta_events } true; 7705#L1024-2 [2021-12-19 19:17:28,348 INFO L793 eck$LassoCheckResult]: Loop: 7705#L1024-2 assume !false; 7988#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8043#L645 assume !false; 7920#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7921#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7648#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8125#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8160#L556 assume !(0 != eval_~tmp~0#1); 8192#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8102#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7696#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7697#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7857#L675-3 assume !(0 == ~T2_E~0); 7858#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8078#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8079#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8189#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8089#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8090#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7751#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7752#L715-3 assume !(0 == ~E_4~0); 7983#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7984#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8056#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7829#L320-21 assume 1 == ~m_pc~0; 7830#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7981#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7907#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7908#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8142#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7764#L339-21 assume !(1 == ~t1_pc~0); 7765#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7868#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7740#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7622#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7623#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7722#L358-21 assume !(1 == ~t2_pc~0); 7776#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7702#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7703#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7987#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7741#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7742#L377-21 assume !(1 == ~t3_pc~0); 8098#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8013#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8014#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8034#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7879#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7880#L396-21 assume !(1 == ~t4_pc~0); 7905#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7906#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7877#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7604#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 7605#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L415-21 assume 1 == ~t5_pc~0; 7856#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7833#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7726#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7727#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7927#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7928#L434-21 assume 1 == ~t6_pc~0; 7939#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7630#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8131#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7851#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7852#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7846#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7847#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8167#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8009#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7947#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7870#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7871#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8155#L773-3 assume !(1 == ~E_1~0); 7789#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7790#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8012#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8179#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8052#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7780#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7676#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7940#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7941#L1043 assume !(0 == start_simulation_~tmp~3#1); 8134#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8010#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7797#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7980#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7968#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7690#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7691#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7838#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7705#L1024-2 [2021-12-19 19:17:28,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,349 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2021-12-19 19:17:28,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94221037] [2021-12-19 19:17:28,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94221037] [2021-12-19 19:17:28,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94221037] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,379 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:28,379 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487694167] [2021-12-19 19:17:28,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,379 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,380 INFO L85 PathProgramCache]: Analyzing trace with hash -1893431359, now seen corresponding path program 1 times [2021-12-19 19:17:28,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138901323] [2021-12-19 19:17:28,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,380 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138901323] [2021-12-19 19:17:28,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138901323] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,412 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459041785] [2021-12-19 19:17:28,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,413 INFO L87 Difference]: Start difference. First operand 626 states and 932 transitions. cyclomatic complexity: 307 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,442 INFO L93 Difference]: Finished difference Result 626 states and 919 transitions. [2021-12-19 19:17:28,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 919 transitions. [2021-12-19 19:17:28,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 919 transitions. [2021-12-19 19:17:28,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-19 19:17:28,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-19 19:17:28,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 919 transitions. [2021-12-19 19:17:28,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,450 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 919 transitions. [2021-12-19 19:17:28,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 919 transitions. [2021-12-19 19:17:28,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-19 19:17:28,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4680511182108626) internal successors, (919), 625 states have internal predecessors, (919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 919 transitions. [2021-12-19 19:17:28,478 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 919 transitions. [2021-12-19 19:17:28,478 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 919 transitions. [2021-12-19 19:17:28,479 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:28,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 919 transitions. [2021-12-19 19:17:28,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-19 19:17:28,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,482 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,482 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,483 INFO L791 eck$LassoCheckResult]: Stem: 9453#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9436#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9387#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8832#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8828#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 8829#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9343#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9447#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8921#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8922#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9076#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8940#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8941#L670 assume !(0 == ~M_E~0); 9312#L670-2 assume !(0 == ~T1_E~0); 9259#L675-1 assume !(0 == ~T2_E~0); 9260#L680-1 assume !(0 == ~T3_E~0); 9342#L685-1 assume !(0 == ~T4_E~0); 9315#L690-1 assume !(0 == ~T5_E~0); 9316#L695-1 assume !(0 == ~T6_E~0); 9374#L700-1 assume !(0 == ~E_1~0); 9366#L705-1 assume !(0 == ~E_2~0); 9367#L710-1 assume !(0 == ~E_3~0); 9257#L715-1 assume !(0 == ~E_4~0); 9179#L720-1 assume !(0 == ~E_5~0); 9180#L725-1 assume !(0 == ~E_6~0); 9236#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9284#L320 assume 1 == ~m_pc~0; 9224#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9118#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9119#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9077#L825 assume !(0 != activate_threads_~tmp~1#1); 9078#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9083#L339 assume !(1 == ~t1_pc~0); 9084#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9061#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9062#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8943#L833 assume !(0 != activate_threads_~tmp___0~0#1); 8944#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8852#L358 assume 1 == ~t2_pc~0; 8853#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9362#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9313#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9240#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9072#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9073#L377 assume !(1 == ~t3_pc~0); 9328#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9329#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9324#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9081#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9082#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9027#L396 assume 1 == ~t4_pc~0; 9028#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8855#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8856#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9274#L857 assume !(0 != activate_threads_~tmp___3~0#1); 8996#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8997#L415 assume 1 == ~t5_pc~0; 9063#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9106#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9285#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9392#L865 assume !(0 != activate_threads_~tmp___4~0#1); 8898#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8899#L434 assume !(1 == ~t6_pc~0); 9213#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9214#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9354#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9355#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9094#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9095#L743 assume !(1 == ~M_E~0); 8988#L743-2 assume !(1 == ~T1_E~0); 8989#L748-1 assume !(1 == ~T2_E~0); 9278#L753-1 assume !(1 == ~T3_E~0); 9279#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9378#L763-1 assume !(1 == ~T5_E~0); 9410#L768-1 assume !(1 == ~T6_E~0); 9087#L773-1 assume !(1 == ~E_1~0); 9088#L778-1 assume !(1 == ~E_2~0); 9069#L783-1 assume !(1 == ~E_3~0); 9070#L788-1 assume !(1 == ~E_4~0); 9340#L793-1 assume !(1 == ~E_5~0); 9305#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8960#L803-1 assume { :end_inline_reset_delta_events } true; 8961#L1024-2 [2021-12-19 19:17:28,483 INFO L793 eck$LassoCheckResult]: Loop: 8961#L1024-2 assume !false; 9246#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9302#L645 assume !false; 9177#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9178#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8906#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9384#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9417#L556 assume !(0 != eval_~tmp~0#1); 9451#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9361#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8952#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8953#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9113#L675-3 assume !(0 == ~T2_E~0); 9114#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9337#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9338#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9448#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9346#L700-3 assume !(0 == ~E_1~0); 9347#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9009#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9010#L715-3 assume !(0 == ~E_4~0); 9241#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9242#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9317#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9089#L320-21 assume 1 == ~m_pc~0; 9090#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9239#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9164#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9165#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9401#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9022#L339-21 assume !(1 == ~t1_pc~0); 9023#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 9276#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8998#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8880#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8881#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8980#L358-21 assume !(1 == ~t2_pc~0); 9034#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 8962#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8963#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9245#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8999#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9000#L377-21 assume 1 == ~t3_pc~0; 9413#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9272#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9273#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9293#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9136#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9137#L396-21 assume !(1 == ~t4_pc~0); 9162#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9163#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9134#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8862#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 8863#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9115#L415-21 assume !(1 == ~t5_pc~0); 9092#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9093#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8984#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8985#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9184#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9185#L434-21 assume !(1 == ~t6_pc~0); 8887#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 8888#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9389#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9109#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9110#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9104#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9105#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9426#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9267#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9204#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9127#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9128#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9414#L773-3 assume !(1 == ~E_1~0); 9047#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9048#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9270#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9438#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9439#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9311#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9038#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8934#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9197#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9198#L1043 assume !(0 == start_simulation_~tmp~3#1); 9393#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9268#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9056#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9238#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9226#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8948#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8949#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9096#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 8961#L1024-2 [2021-12-19 19:17:28,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,484 INFO L85 PathProgramCache]: Analyzing trace with hash -976775521, now seen corresponding path program 1 times [2021-12-19 19:17:28,484 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210522738] [2021-12-19 19:17:28,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210522738] [2021-12-19 19:17:28,506 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210522738] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,507 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,507 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:28,507 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165405686] [2021-12-19 19:17:28,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,508 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1281661854, now seen corresponding path program 1 times [2021-12-19 19:17:28,508 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716242732] [2021-12-19 19:17:28,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,513 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,548 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716242732] [2021-12-19 19:17:28,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716242732] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,549 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:28,550 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087805928] [2021-12-19 19:17:28,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,550 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,551 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,551 INFO L87 Difference]: Start difference. First operand 626 states and 919 transitions. cyclomatic complexity: 294 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,603 INFO L93 Difference]: Finished difference Result 1153 states and 1675 transitions. [2021-12-19 19:17:28,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:28,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1153 states and 1675 transitions. [2021-12-19 19:17:28,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1063 [2021-12-19 19:17:28,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1153 states to 1153 states and 1675 transitions. [2021-12-19 19:17:28,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1153 [2021-12-19 19:17:28,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1153 [2021-12-19 19:17:28,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1153 states and 1675 transitions. [2021-12-19 19:17:28,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,616 INFO L681 BuchiCegarLoop]: Abstraction has 1153 states and 1675 transitions. [2021-12-19 19:17:28,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1153 states and 1675 transitions. [2021-12-19 19:17:28,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1153 to 1103. [2021-12-19 19:17:28,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1103 states, 1103 states have (on average 1.4560290117860382) internal successors, (1606), 1102 states have internal predecessors, (1606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1103 states to 1103 states and 1606 transitions. [2021-12-19 19:17:28,632 INFO L704 BuchiCegarLoop]: Abstraction has 1103 states and 1606 transitions. [2021-12-19 19:17:28,632 INFO L587 BuchiCegarLoop]: Abstraction has 1103 states and 1606 transitions. [2021-12-19 19:17:28,632 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:28,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1103 states and 1606 transitions. [2021-12-19 19:17:28,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1013 [2021-12-19 19:17:28,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,637 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,637 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,637 INFO L791 eck$LassoCheckResult]: Stem: 11258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 11234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11181#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10620#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10616#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 10617#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11130#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11248#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10710#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10711#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10860#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10728#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10729#L670 assume !(0 == ~M_E~0); 11092#L670-2 assume !(0 == ~T1_E~0); 11040#L675-1 assume !(0 == ~T2_E~0); 11041#L680-1 assume !(0 == ~T3_E~0); 11128#L685-1 assume !(0 == ~T4_E~0); 11095#L690-1 assume !(0 == ~T5_E~0); 11096#L695-1 assume !(0 == ~T6_E~0); 11159#L700-1 assume !(0 == ~E_1~0); 11151#L705-1 assume !(0 == ~E_2~0); 11152#L710-1 assume !(0 == ~E_3~0); 11039#L715-1 assume !(0 == ~E_4~0); 10964#L720-1 assume !(0 == ~E_5~0); 10965#L725-1 assume !(0 == ~E_6~0); 11017#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11064#L320 assume !(1 == ~m_pc~0); 11177#L320-2 is_master_triggered_~__retres1~0#1 := 0; 10901#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10902#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10861#L825 assume !(0 != activate_threads_~tmp~1#1); 10862#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10868#L339 assume !(1 == ~t1_pc~0); 10869#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10845#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10846#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10730#L833 assume !(0 != activate_threads_~tmp___0~0#1); 10731#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10640#L358 assume 1 == ~t2_pc~0; 10641#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11147#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11093#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11021#L841 assume !(0 != activate_threads_~tmp___1~0#1); 10858#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10859#L377 assume !(1 == ~t3_pc~0); 11112#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11113#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11108#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10865#L849 assume !(0 != activate_threads_~tmp___2~0#1); 10866#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10813#L396 assume 1 == ~t4_pc~0; 10814#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10643#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10644#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11054#L857 assume !(0 != activate_threads_~tmp___3~0#1); 10783#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10784#L415 assume 1 == ~t5_pc~0; 10847#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10891#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11065#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11186#L865 assume !(0 != activate_threads_~tmp___4~0#1); 10686#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10687#L434 assume !(1 == ~t6_pc~0); 10996#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10997#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11140#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11141#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10877#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L743 assume !(1 == ~M_E~0); 10775#L743-2 assume !(1 == ~T1_E~0); 10776#L748-1 assume !(1 == ~T2_E~0); 11058#L753-1 assume !(1 == ~T3_E~0); 11059#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11163#L763-1 assume !(1 == ~T5_E~0); 11207#L768-1 assume !(1 == ~T6_E~0); 10873#L773-1 assume !(1 == ~E_1~0); 10874#L778-1 assume !(1 == ~E_2~0); 10853#L783-1 assume !(1 == ~E_3~0); 10854#L788-1 assume !(1 == ~E_4~0); 11125#L793-1 assume !(1 == ~E_5~0); 11085#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 10749#L803-1 assume { :end_inline_reset_delta_events } true; 10750#L1024-2 [2021-12-19 19:17:28,638 INFO L793 eck$LassoCheckResult]: Loop: 10750#L1024-2 assume !false; 11027#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11082#L645 assume !false; 10960#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10961#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10693#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11172#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11217#L556 assume !(0 != eval_~tmp~0#1); 11260#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11654#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11653#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11652#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11651#L675-3 assume !(0 == ~T2_E~0); 11650#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11649#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11648#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11647#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11646#L700-3 assume !(0 == ~E_1~0); 11645#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11644#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11643#L715-3 assume !(0 == ~E_4~0); 11641#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11097#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11098#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10875#L320-21 assume !(1 == ~m_pc~0); 10876#L320-23 is_master_triggered_~__retres1~0#1 := 0; 11020#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10947#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10948#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11195#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10808#L339-21 assume !(1 == ~t1_pc~0); 10809#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 11056#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10785#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10668#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10669#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10767#L358-21 assume 1 == ~t2_pc~0; 10867#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10747#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10748#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11026#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10786#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10787#L377-21 assume !(1 == ~t3_pc~0); 11143#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 11051#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11052#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11073#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10919#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10920#L396-21 assume !(1 == ~t4_pc~0); 10945#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 10946#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10917#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10652#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 10653#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10896#L415-21 assume 1 == ~t5_pc~0; 10897#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10872#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10773#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10774#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10967#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10968#L434-21 assume !(1 == ~t6_pc~0); 10673#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 10674#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11182#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10892#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10893#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10887#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10888#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11224#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11047#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10988#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10910#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10911#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11211#L773-3 assume !(1 == ~E_1~0); 10833#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10834#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11050#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11236#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11237#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11090#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10824#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10721#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10980#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10981#L1043 assume !(0 == start_simulation_~tmp~3#1); 11188#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11048#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10840#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11018#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 11007#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10735#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10736#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10879#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 10750#L1024-2 [2021-12-19 19:17:28,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,638 INFO L85 PathProgramCache]: Analyzing trace with hash -969024962, now seen corresponding path program 1 times [2021-12-19 19:17:28,639 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,639 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387378163] [2021-12-19 19:17:28,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,639 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387378163] [2021-12-19 19:17:28,668 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387378163] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,669 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:28,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939945742] [2021-12-19 19:17:28,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,669 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,670 INFO L85 PathProgramCache]: Analyzing trace with hash -1705257118, now seen corresponding path program 1 times [2021-12-19 19:17:28,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657321752] [2021-12-19 19:17:28,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657321752] [2021-12-19 19:17:28,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657321752] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,696 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:28,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77334081] [2021-12-19 19:17:28,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,697 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,697 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:28,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:28,698 INFO L87 Difference]: Start difference. First operand 1103 states and 1606 transitions. cyclomatic complexity: 505 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:28,822 INFO L93 Difference]: Finished difference Result 2855 states and 4121 transitions. [2021-12-19 19:17:28,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:28,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2855 states and 4121 transitions. [2021-12-19 19:17:28,837 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2747 [2021-12-19 19:17:28,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2855 states to 2855 states and 4121 transitions. [2021-12-19 19:17:28,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2855 [2021-12-19 19:17:28,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2855 [2021-12-19 19:17:28,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2855 states and 4121 transitions. [2021-12-19 19:17:28,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:28,854 INFO L681 BuchiCegarLoop]: Abstraction has 2855 states and 4121 transitions. [2021-12-19 19:17:28,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2855 states and 4121 transitions. [2021-12-19 19:17:28,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2855 to 2771. [2021-12-19 19:17:28,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2771 states, 2771 states have (on average 1.446770119090581) internal successors, (4009), 2770 states have internal predecessors, (4009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:28,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2771 states to 2771 states and 4009 transitions. [2021-12-19 19:17:28,892 INFO L704 BuchiCegarLoop]: Abstraction has 2771 states and 4009 transitions. [2021-12-19 19:17:28,892 INFO L587 BuchiCegarLoop]: Abstraction has 2771 states and 4009 transitions. [2021-12-19 19:17:28,892 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:28,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2771 states and 4009 transitions. [2021-12-19 19:17:28,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2675 [2021-12-19 19:17:28,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:28,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:28,904 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,904 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:28,904 INFO L791 eck$LassoCheckResult]: Stem: 15303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 15262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15194#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14590#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14586#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 14587#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15132#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15280#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14679#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14680#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14839#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14697#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14698#L670 assume !(0 == ~M_E~0); 15094#L670-2 assume !(0 == ~T1_E~0); 15035#L675-1 assume !(0 == ~T2_E~0); 15036#L680-1 assume !(0 == ~T3_E~0); 15130#L685-1 assume !(0 == ~T4_E~0); 15100#L690-1 assume !(0 == ~T5_E~0); 15101#L695-1 assume !(0 == ~T6_E~0); 15171#L700-1 assume !(0 == ~E_1~0); 15158#L705-1 assume !(0 == ~E_2~0); 15159#L710-1 assume !(0 == ~E_3~0); 15034#L715-1 assume !(0 == ~E_4~0); 14953#L720-1 assume !(0 == ~E_5~0); 14954#L725-1 assume !(0 == ~E_6~0); 15012#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L320 assume !(1 == ~m_pc~0); 15189#L320-2 is_master_triggered_~__retres1~0#1 := 0; 14882#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14883#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14840#L825 assume !(0 != activate_threads_~tmp~1#1); 14841#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14849#L339 assume !(1 == ~t1_pc~0); 14850#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14823#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14824#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14699#L833 assume !(0 != activate_threads_~tmp___0~0#1); 14700#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14610#L358 assume !(1 == ~t2_pc~0); 14611#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15153#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15095#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15016#L841 assume !(0 != activate_threads_~tmp___1~0#1); 14837#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14838#L377 assume !(1 == ~t3_pc~0); 15113#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15114#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15112#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14844#L849 assume !(0 != activate_threads_~tmp___2~0#1); 14845#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14787#L396 assume 1 == ~t4_pc~0; 14788#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14612#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14613#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15050#L857 assume !(0 != activate_threads_~tmp___3~0#1); 14754#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14755#L415 assume 1 == ~t5_pc~0; 14826#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14872#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15064#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15201#L865 assume !(0 != activate_threads_~tmp___4~0#1); 14654#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14655#L434 assume !(1 == ~t6_pc~0); 14991#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14992#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15143#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15144#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14858#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14859#L743 assume !(1 == ~M_E~0); 14745#L743-2 assume !(1 == ~T1_E~0); 14746#L748-1 assume !(1 == ~T2_E~0); 15054#L753-1 assume !(1 == ~T3_E~0); 15055#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15175#L763-1 assume !(1 == ~T5_E~0); 15225#L768-1 assume !(1 == ~T6_E~0); 14856#L773-1 assume !(1 == ~E_1~0); 14857#L778-1 assume !(1 == ~E_2~0); 14831#L783-1 assume !(1 == ~E_3~0); 14832#L788-1 assume !(1 == ~E_4~0); 15128#L793-1 assume !(1 == ~E_5~0); 15085#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 14717#L803-1 assume { :end_inline_reset_delta_events } true; 14718#L1024-2 [2021-12-19 19:17:28,905 INFO L793 eck$LassoCheckResult]: Loop: 14718#L1024-2 assume !false; 15936#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15852#L645 assume !false; 15842#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15486#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15477#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15475#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15304#L556 assume !(0 != eval_~tmp~0#1); 15305#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16237#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16236#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16235#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16234#L675-3 assume !(0 == ~T2_E~0); 16233#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16232#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16230#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16227#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16226#L700-3 assume !(0 == ~E_1~0); 16225#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16224#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16223#L715-3 assume !(0 == ~E_4~0); 16222#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16221#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16220#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16219#L320-21 assume !(1 == ~m_pc~0); 16218#L320-23 is_master_triggered_~__retres1~0#1 := 0; 16217#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16216#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16215#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16213#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16211#L339-21 assume !(1 == ~t1_pc~0); 16209#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 16207#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16205#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16203#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16201#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16199#L358-21 assume !(1 == ~t2_pc~0); 16197#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 16195#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16193#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16191#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16189#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16187#L377-21 assume !(1 == ~t3_pc~0); 16184#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 16182#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16180#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16178#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16176#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16173#L396-21 assume 1 == ~t4_pc~0; 16170#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16168#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16166#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16164#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 16162#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16159#L415-21 assume 1 == ~t5_pc~0; 16156#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16154#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16152#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16150#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16148#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16145#L434-21 assume !(1 == ~t6_pc~0); 16142#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 16140#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16138#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16136#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16134#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16131#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16129#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16127#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16125#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16123#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16119#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16117#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16115#L773-3 assume !(1 == ~E_1~0); 16110#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16105#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16100#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16099#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16098#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16097#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16093#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16089#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16088#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 15964#L1043 assume !(0 == start_simulation_~tmp~3#1); 15962#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15954#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15948#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15946#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 15945#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15943#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15941#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 15939#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 14718#L1024-2 [2021-12-19 19:17:28,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,905 INFO L85 PathProgramCache]: Analyzing trace with hash 2050839645, now seen corresponding path program 1 times [2021-12-19 19:17:28,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623303366] [2021-12-19 19:17:28,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623303366] [2021-12-19 19:17:28,924 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623303366] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,925 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,925 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:28,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483450195] [2021-12-19 19:17:28,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,925 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:28,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:28,926 INFO L85 PathProgramCache]: Analyzing trace with hash -422403870, now seen corresponding path program 1 times [2021-12-19 19:17:28,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:28,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614761698] [2021-12-19 19:17:28,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:28,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:28,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:28,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:28,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:28,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614761698] [2021-12-19 19:17:28,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614761698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:28,951 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:28,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:28,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449534658] [2021-12-19 19:17:28,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:28,951 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:28,951 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:28,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:28,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:28,952 INFO L87 Difference]: Start difference. First operand 2771 states and 4009 transitions. cyclomatic complexity: 1242 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,009 INFO L93 Difference]: Finished difference Result 5119 states and 7377 transitions. [2021-12-19 19:17:29,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:29,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5119 states and 7377 transitions. [2021-12-19 19:17:29,033 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5002 [2021-12-19 19:17:29,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5119 states to 5119 states and 7377 transitions. [2021-12-19 19:17:29,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5119 [2021-12-19 19:17:29,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5119 [2021-12-19 19:17:29,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5119 states and 7377 transitions. [2021-12-19 19:17:29,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,095 INFO L681 BuchiCegarLoop]: Abstraction has 5119 states and 7377 transitions. [2021-12-19 19:17:29,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5119 states and 7377 transitions. [2021-12-19 19:17:29,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5119 to 5107. [2021-12-19 19:17:29,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5107 states, 5107 states have (on average 1.4421382416291364) internal successors, (7365), 5106 states have internal predecessors, (7365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5107 states to 5107 states and 7365 transitions. [2021-12-19 19:17:29,155 INFO L704 BuchiCegarLoop]: Abstraction has 5107 states and 7365 transitions. [2021-12-19 19:17:29,155 INFO L587 BuchiCegarLoop]: Abstraction has 5107 states and 7365 transitions. [2021-12-19 19:17:29,155 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:29,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5107 states and 7365 transitions. [2021-12-19 19:17:29,172 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4990 [2021-12-19 19:17:29,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,174 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,174 INFO L791 eck$LassoCheckResult]: Stem: 23211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 23156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 23078#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22489#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22485#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 22486#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23023#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23183#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22577#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22578#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22730#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22596#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22597#L670 assume !(0 == ~M_E~0); 22984#L670-2 assume !(0 == ~T1_E~0); 22924#L675-1 assume !(0 == ~T2_E~0); 22925#L680-1 assume !(0 == ~T3_E~0); 23021#L685-1 assume !(0 == ~T4_E~0); 22987#L690-1 assume !(0 == ~T5_E~0); 22988#L695-1 assume !(0 == ~T6_E~0); 23059#L700-1 assume !(0 == ~E_1~0); 23050#L705-1 assume !(0 == ~E_2~0); 23051#L710-1 assume !(0 == ~E_3~0); 22922#L715-1 assume !(0 == ~E_4~0); 22839#L720-1 assume !(0 == ~E_5~0); 22840#L725-1 assume !(0 == ~E_6~0); 22899#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22952#L320 assume !(1 == ~m_pc~0); 23074#L320-2 is_master_triggered_~__retres1~0#1 := 0; 22772#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22773#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22731#L825 assume !(0 != activate_threads_~tmp~1#1); 22732#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22737#L339 assume !(1 == ~t1_pc~0); 22738#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22715#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22716#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22600#L833 assume !(0 != activate_threads_~tmp___0~0#1); 22601#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22509#L358 assume !(1 == ~t2_pc~0); 22510#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23046#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22985#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22904#L841 assume !(0 != activate_threads_~tmp___1~0#1); 22726#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22727#L377 assume !(1 == ~t3_pc~0); 23004#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23005#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22999#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22735#L849 assume !(0 != activate_threads_~tmp___2~0#1); 22736#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22682#L396 assume !(1 == ~t4_pc~0); 22683#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22511#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22512#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22940#L857 assume !(0 != activate_threads_~tmp___3~0#1); 22653#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22654#L415 assume 1 == ~t5_pc~0; 22717#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22760#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22953#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23085#L865 assume !(0 != activate_threads_~tmp___4~0#1); 22554#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22555#L434 assume !(1 == ~t6_pc~0); 22876#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22877#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23036#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23037#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22748#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22749#L743 assume !(1 == ~M_E~0); 22643#L743-2 assume !(1 == ~T1_E~0); 22644#L748-1 assume !(1 == ~T2_E~0); 22945#L753-1 assume !(1 == ~T3_E~0); 22946#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23062#L763-1 assume !(1 == ~T5_E~0); 23115#L768-1 assume !(1 == ~T6_E~0); 22742#L773-1 assume !(1 == ~E_1~0); 22743#L778-1 assume !(1 == ~E_2~0); 22723#L783-1 assume !(1 == ~E_3~0); 22724#L788-1 assume !(1 == ~E_4~0); 23019#L793-1 assume !(1 == ~E_5~0); 22978#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 22616#L803-1 assume { :end_inline_reset_delta_events } true; 22617#L1024-2 [2021-12-19 19:17:29,174 INFO L793 eck$LassoCheckResult]: Loop: 22617#L1024-2 assume !false; 25748#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25743#L645 assume !false; 25742#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 25737#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 25729#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 25728#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23212#L556 assume !(0 != eval_~tmp~0#1); 23213#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26015#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26014#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26013#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26011#L675-3 assume !(0 == ~T2_E~0); 26009#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26007#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26005#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26003#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26001#L700-3 assume !(0 == ~E_1~0); 25999#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25997#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25995#L715-3 assume !(0 == ~E_4~0); 25993#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25991#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25989#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25987#L320-21 assume !(1 == ~m_pc~0); 25985#L320-23 is_master_triggered_~__retres1~0#1 := 0; 25983#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25981#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25979#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25977#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25975#L339-21 assume !(1 == ~t1_pc~0); 25972#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 25970#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25968#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25966#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25964#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25962#L358-21 assume !(1 == ~t2_pc~0); 25960#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 25958#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25956#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25954#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25952#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25950#L377-21 assume !(1 == ~t3_pc~0); 25946#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 25944#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25942#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25940#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25938#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25936#L396-21 assume !(1 == ~t4_pc~0); 25933#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 25931#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25929#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25927#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 25925#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25924#L415-21 assume 1 == ~t5_pc~0; 25922#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25918#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25916#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25914#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25913#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25912#L434-21 assume !(1 == ~t6_pc~0); 25907#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 25906#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25905#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25904#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25903#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25902#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25901#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25900#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25899#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25898#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25897#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25896#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25894#L773-3 assume !(1 == ~E_1~0); 25892#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25890#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25888#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25886#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25884#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25882#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 25873#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 25868#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 25866#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 25783#L1043 assume !(0 == start_simulation_~tmp~3#1); 25781#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 25772#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 25766#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 25764#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 25760#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25758#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25756#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 25752#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 22617#L1024-2 [2021-12-19 19:17:29,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1325153028, now seen corresponding path program 1 times [2021-12-19 19:17:29,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526403515] [2021-12-19 19:17:29,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,175 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,195 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526403515] [2021-12-19 19:17:29,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526403515] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,196 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:29,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613147357] [2021-12-19 19:17:29,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,196 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:29,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1697506559, now seen corresponding path program 1 times [2021-12-19 19:17:29,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998108473] [2021-12-19 19:17:29,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,219 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998108473] [2021-12-19 19:17:29,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998108473] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,220 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,220 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:29,220 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813742002] [2021-12-19 19:17:29,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,220 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:29,221 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:29,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:29,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:29,221 INFO L87 Difference]: Start difference. First operand 5107 states and 7365 transitions. cyclomatic complexity: 2266 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,398 INFO L93 Difference]: Finished difference Result 13554 states and 19474 transitions. [2021-12-19 19:17:29,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:29,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13554 states and 19474 transitions. [2021-12-19 19:17:29,461 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13294 [2021-12-19 19:17:29,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13554 states to 13554 states and 19474 transitions. [2021-12-19 19:17:29,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13554 [2021-12-19 19:17:29,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13554 [2021-12-19 19:17:29,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13554 states and 19474 transitions. [2021-12-19 19:17:29,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,541 INFO L681 BuchiCegarLoop]: Abstraction has 13554 states and 19474 transitions. [2021-12-19 19:17:29,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13554 states and 19474 transitions. [2021-12-19 19:17:29,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13554 to 13294. [2021-12-19 19:17:29,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13294 states, 13294 states have (on average 1.4401985858281932) internal successors, (19146), 13293 states have internal predecessors, (19146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13294 states to 13294 states and 19146 transitions. [2021-12-19 19:17:29,762 INFO L704 BuchiCegarLoop]: Abstraction has 13294 states and 19146 transitions. [2021-12-19 19:17:29,762 INFO L587 BuchiCegarLoop]: Abstraction has 13294 states and 19146 transitions. [2021-12-19 19:17:29,762 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:29,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13294 states and 19146 transitions. [2021-12-19 19:17:29,847 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13114 [2021-12-19 19:17:29,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,849 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,849 INFO L791 eck$LassoCheckResult]: Stem: 41885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 41835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 41761#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41162#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41158#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 41159#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41698#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41860#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41251#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41252#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41406#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41270#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41271#L670 assume !(0 == ~M_E~0); 41658#L670-2 assume !(0 == ~T1_E~0); 41597#L675-1 assume !(0 == ~T2_E~0); 41598#L680-1 assume !(0 == ~T3_E~0); 41696#L685-1 assume !(0 == ~T4_E~0); 41662#L690-1 assume !(0 == ~T5_E~0); 41663#L695-1 assume !(0 == ~T6_E~0); 41735#L700-1 assume !(0 == ~E_1~0); 41724#L705-1 assume !(0 == ~E_2~0); 41725#L710-1 assume !(0 == ~E_3~0); 41596#L715-1 assume !(0 == ~E_4~0); 41515#L720-1 assume !(0 == ~E_5~0); 41516#L725-1 assume !(0 == ~E_6~0); 41574#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41626#L320 assume !(1 == ~m_pc~0); 41757#L320-2 is_master_triggered_~__retres1~0#1 := 0; 41448#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41449#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41407#L825 assume !(0 != activate_threads_~tmp~1#1); 41408#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41415#L339 assume !(1 == ~t1_pc~0); 41416#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41392#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41393#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41272#L833 assume !(0 != activate_threads_~tmp___0~0#1); 41273#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41182#L358 assume !(1 == ~t2_pc~0); 41183#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41719#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41659#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41578#L841 assume !(0 != activate_threads_~tmp___1~0#1); 41404#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41405#L377 assume !(1 == ~t3_pc~0); 41680#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41681#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41679#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41410#L849 assume !(0 != activate_threads_~tmp___2~0#1); 41411#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41359#L396 assume !(1 == ~t4_pc~0); 41360#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41184#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41185#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41613#L857 assume !(0 != activate_threads_~tmp___3~0#1); 41326#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41327#L415 assume !(1 == ~t5_pc~0); 41395#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41438#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41627#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41767#L865 assume !(0 != activate_threads_~tmp___4~0#1); 41225#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41226#L434 assume !(1 == ~t6_pc~0); 41550#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41551#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41710#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41711#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41424#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41425#L743 assume !(1 == ~M_E~0); 41316#L743-2 assume !(1 == ~T1_E~0); 41317#L748-1 assume !(1 == ~T2_E~0); 41618#L753-1 assume !(1 == ~T3_E~0); 41619#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41738#L763-1 assume !(1 == ~T5_E~0); 41795#L768-1 assume !(1 == ~T6_E~0); 41422#L773-1 assume !(1 == ~E_1~0); 41423#L778-1 assume !(1 == ~E_2~0); 41399#L783-1 assume !(1 == ~E_3~0); 41400#L788-1 assume !(1 == ~E_4~0); 41694#L793-1 assume !(1 == ~E_5~0); 41650#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41291#L803-1 assume { :end_inline_reset_delta_events } true; 41292#L1024-2 [2021-12-19 19:17:29,849 INFO L793 eck$LassoCheckResult]: Loop: 41292#L1024-2 assume !false; 49365#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49359#L645 assume !false; 49357#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49358#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 50062#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49282#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49283#L556 assume !(0 != eval_~tmp~0#1); 50052#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52842#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52841#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52840#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52839#L675-3 assume !(0 == ~T2_E~0); 52838#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52837#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52836#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52835#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52834#L700-3 assume !(0 == ~E_1~0); 52833#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52832#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52831#L715-3 assume !(0 == ~E_4~0); 52830#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52829#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52828#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52827#L320-21 assume !(1 == ~m_pc~0); 52826#L320-23 is_master_triggered_~__retres1~0#1 := 0; 52825#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52824#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52823#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52822#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52821#L339-21 assume !(1 == ~t1_pc~0); 52820#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 52819#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52818#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52817#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52816#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52815#L358-21 assume !(1 == ~t2_pc~0); 52814#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 52813#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52812#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52811#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52810#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52809#L377-21 assume !(1 == ~t3_pc~0); 52807#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 52806#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52805#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52804#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52803#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52802#L396-21 assume !(1 == ~t4_pc~0); 52801#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 52800#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52799#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52798#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 52797#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52796#L415-21 assume !(1 == ~t5_pc~0); 52795#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 52794#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52793#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52792#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52791#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52790#L434-21 assume !(1 == ~t6_pc~0); 52788#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 52787#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52786#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52785#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52784#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52783#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52782#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52781#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52780#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52779#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52778#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52777#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52776#L773-3 assume !(1 == ~E_1~0); 52775#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52774#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52773#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52772#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52771#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52770#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49407#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49402#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49399#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 49394#L1043 assume !(0 == start_simulation_~tmp~3#1); 49395#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49385#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49378#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49376#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 49374#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49372#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49370#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 49368#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 41292#L1024-2 [2021-12-19 19:17:29,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,850 INFO L85 PathProgramCache]: Analyzing trace with hash -686368549, now seen corresponding path program 1 times [2021-12-19 19:17:29,850 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013328915] [2021-12-19 19:17:29,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,850 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013328915] [2021-12-19 19:17:29,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013328915] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,885 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:29,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009732228] [2021-12-19 19:17:29,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,887 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:29,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1174185888, now seen corresponding path program 1 times [2021-12-19 19:17:29,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,888 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424089905] [2021-12-19 19:17:29,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,912 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424089905] [2021-12-19 19:17:29,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424089905] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,913 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,913 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:29,913 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299677776] [2021-12-19 19:17:29,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,914 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:29,914 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:29,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:29,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:29,924 INFO L87 Difference]: Start difference. First operand 13294 states and 19146 transitions. cyclomatic complexity: 5868 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,148 INFO L93 Difference]: Finished difference Result 30823 states and 44959 transitions. [2021-12-19 19:17:30,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:30,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30823 states and 44959 transitions. [2021-12-19 19:17:30,357 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30418 [2021-12-19 19:17:30,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30823 states to 30823 states and 44959 transitions. [2021-12-19 19:17:30,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30823 [2021-12-19 19:17:30,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30823 [2021-12-19 19:17:30,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30823 states and 44959 transitions. [2021-12-19 19:17:30,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,577 INFO L681 BuchiCegarLoop]: Abstraction has 30823 states and 44959 transitions. [2021-12-19 19:17:30,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30823 states and 44959 transitions. [2021-12-19 19:17:30,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30823 to 13849. [2021-12-19 19:17:30,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13849 states, 13849 states have (on average 1.4225575853852264) internal successors, (19701), 13848 states have internal predecessors, (19701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13849 states to 13849 states and 19701 transitions. [2021-12-19 19:17:30,846 INFO L704 BuchiCegarLoop]: Abstraction has 13849 states and 19701 transitions. [2021-12-19 19:17:30,846 INFO L587 BuchiCegarLoop]: Abstraction has 13849 states and 19701 transitions. [2021-12-19 19:17:30,846 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:30,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13849 states and 19701 transitions. [2021-12-19 19:17:30,886 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13666 [2021-12-19 19:17:30,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,888 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,888 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,888 INFO L791 eck$LassoCheckResult]: Stem: 86040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 85977#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 85898#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85294#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85290#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 85291#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85832#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86004#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85382#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85383#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 85533#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85400#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85401#L670 assume !(0 == ~M_E~0); 85791#L670-2 assume !(0 == ~T1_E~0); 85730#L675-1 assume !(0 == ~T2_E~0); 85731#L680-1 assume !(0 == ~T3_E~0); 85830#L685-1 assume !(0 == ~T4_E~0); 85798#L690-1 assume !(0 == ~T5_E~0); 85799#L695-1 assume !(0 == ~T6_E~0); 85876#L700-1 assume !(0 == ~E_1~0); 85865#L705-1 assume !(0 == ~E_2~0); 85866#L710-1 assume !(0 == ~E_3~0); 85729#L715-1 assume !(0 == ~E_4~0); 85645#L720-1 assume !(0 == ~E_5~0); 85646#L725-1 assume !(0 == ~E_6~0); 85706#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85759#L320 assume !(1 == ~m_pc~0); 85896#L320-2 is_master_triggered_~__retres1~0#1 := 0; 85575#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85576#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 85534#L825 assume !(0 != activate_threads_~tmp~1#1); 85535#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85542#L339 assume !(1 == ~t1_pc~0); 85543#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 85518#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85519#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85402#L833 assume !(0 != activate_threads_~tmp___0~0#1); 85403#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85314#L358 assume !(1 == ~t2_pc~0); 85315#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85856#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85795#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85711#L841 assume !(0 != activate_threads_~tmp___1~0#1); 85531#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85532#L377 assume !(1 == ~t3_pc~0); 85814#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85815#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85813#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 85537#L849 assume !(0 != activate_threads_~tmp___2~0#1); 85538#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85487#L396 assume !(1 == ~t4_pc~0); 85488#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 85316#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85317#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85747#L857 assume !(0 != activate_threads_~tmp___3~0#1); 85455#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85456#L415 assume !(1 == ~t5_pc~0); 85521#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85564#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85760#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 85907#L865 assume !(0 != activate_threads_~tmp___4~0#1); 85357#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85358#L434 assume !(1 == ~t6_pc~0); 85683#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 85684#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85844#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 85845#L873 assume !(0 != activate_threads_~tmp___5~0#1); 85550#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85551#L743 assume !(1 == ~M_E~0); 85445#L743-2 assume !(1 == ~T1_E~0); 85446#L748-1 assume !(1 == ~T2_E~0); 85752#L753-1 assume !(1 == ~T3_E~0); 85753#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85879#L763-1 assume !(1 == ~T5_E~0); 85933#L768-1 assume !(1 == ~T6_E~0); 85548#L773-1 assume !(1 == ~E_1~0); 85549#L778-1 assume !(1 == ~E_2~0); 85526#L783-1 assume !(1 == ~E_3~0); 85527#L788-1 assume !(1 == ~E_4~0); 85826#L793-1 assume !(1 == ~E_5~0); 85781#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 85420#L803-1 assume { :end_inline_reset_delta_events } true; 85421#L1024-2 [2021-12-19 19:17:30,888 INFO L793 eck$LassoCheckResult]: Loop: 85421#L1024-2 assume !false; 97224#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97183#L645 assume !false; 97180#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 95983#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 95975#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 95973#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95970#L556 assume !(0 != eval_~tmp~0#1); 95971#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99078#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99077#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99066#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99013#L675-3 assume !(0 == ~T2_E~0); 99002#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99000#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98998#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98996#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 98994#L700-3 assume !(0 == ~E_1~0); 98992#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98990#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98988#L715-3 assume !(0 == ~E_4~0); 98985#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98983#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85962#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85546#L320-21 assume !(1 == ~m_pc~0); 85547#L320-23 is_master_triggered_~__retres1~0#1 := 0; 99076#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99075#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 99074#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99073#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99071#L339-21 assume !(1 == ~t1_pc~0); 99070#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 99069#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99068#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99067#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99064#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99063#L358-21 assume !(1 == ~t2_pc~0); 99062#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 99061#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99060#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99059#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99051#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99049#L377-21 assume !(1 == ~t3_pc~0); 99043#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 99041#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99039#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 99037#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99035#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85782#L396-21 assume !(1 == ~t4_pc~0); 85783#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98826#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98825#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98824#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 98823#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98822#L415-21 assume !(1 == ~t5_pc~0); 98821#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 98820#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98819#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98818#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98817#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98816#L434-21 assume !(1 == ~t6_pc~0); 98815#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 98813#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98811#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98809#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 98807#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98806#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98805#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98758#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98756#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98754#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98752#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98750#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98748#L773-3 assume !(1 == ~E_1~0); 98745#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98742#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98739#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98736#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98733#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98732#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98725#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98718#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98715#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 98711#L1043 assume !(0 == start_simulation_~tmp~3#1); 98709#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98702#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98693#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98646#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 98644#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98642#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98640#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 98617#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 85421#L1024-2 [2021-12-19 19:17:30,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2021-12-19 19:17:30,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712662082] [2021-12-19 19:17:30,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,889 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [712662082] [2021-12-19 19:17:30,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [712662082] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,928 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661288999] [2021-12-19 19:17:30,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,929 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,930 INFO L85 PathProgramCache]: Analyzing trace with hash -1683658978, now seen corresponding path program 1 times [2021-12-19 19:17:30,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585897506] [2021-12-19 19:17:30,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585897506] [2021-12-19 19:17:30,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585897506] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:30,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111291203] [2021-12-19 19:17:30,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,968 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:30,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:30,968 INFO L87 Difference]: Start difference. First operand 13849 states and 19701 transitions. cyclomatic complexity: 5868 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:31,289 INFO L93 Difference]: Finished difference Result 27710 states and 39205 transitions. [2021-12-19 19:17:31,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:31,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27710 states and 39205 transitions. [2021-12-19 19:17:31,413 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27296 [2021-12-19 19:17:31,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27710 states to 27710 states and 39205 transitions. [2021-12-19 19:17:31,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27710 [2021-12-19 19:17:31,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27710 [2021-12-19 19:17:31,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27710 states and 39205 transitions. [2021-12-19 19:17:31,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:31,558 INFO L681 BuchiCegarLoop]: Abstraction has 27710 states and 39205 transitions. [2021-12-19 19:17:31,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27710 states and 39205 transitions. [2021-12-19 19:17:31,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27710 to 27710. [2021-12-19 19:17:31,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27710 states, 27710 states have (on average 1.4148321905449297) internal successors, (39205), 27709 states have internal predecessors, (39205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27710 states to 27710 states and 39205 transitions. [2021-12-19 19:17:32,127 INFO L704 BuchiCegarLoop]: Abstraction has 27710 states and 39205 transitions. [2021-12-19 19:17:32,127 INFO L587 BuchiCegarLoop]: Abstraction has 27710 states and 39205 transitions. [2021-12-19 19:17:32,128 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:32,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27710 states and 39205 transitions. [2021-12-19 19:17:32,191 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27296 [2021-12-19 19:17:32,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:32,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:32,192 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,192 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,192 INFO L791 eck$LassoCheckResult]: Stem: 127622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 127558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 127467#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126865#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126861#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 126862#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127405#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127589#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126949#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126950#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127100#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126969#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126970#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 127567#L670-2 assume !(0 == ~T1_E~0); 127294#L675-1 assume !(0 == ~T2_E~0); 127295#L680-1 assume !(0 == ~T3_E~0); 127483#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 127484#L690-1 assume !(0 == ~T5_E~0); 127616#L695-1 assume !(0 == ~T6_E~0); 127442#L700-1 assume !(0 == ~E_1~0); 127429#L705-1 assume !(0 == ~E_2~0); 127430#L710-1 assume !(0 == ~E_3~0); 127715#L715-1 assume !(0 == ~E_4~0); 127713#L720-1 assume !(0 == ~E_5~0); 127711#L725-1 assume !(0 == ~E_6~0); 127325#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127326#L320 assume !(1 == ~m_pc~0); 127463#L320-2 is_master_triggered_~__retres1~0#1 := 0; 127140#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127141#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 127101#L825 assume !(0 != activate_threads_~tmp~1#1); 127102#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127494#L339 assume !(1 == ~t1_pc~0); 127697#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 127695#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127693#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127691#L833 assume !(0 != activate_threads_~tmp___0~0#1); 127572#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126885#L358 assume !(1 == ~t2_pc~0); 126886#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 127424#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127360#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127275#L841 assume !(0 != activate_threads_~tmp___1~0#1); 127096#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127097#L377 assume !(1 == ~t3_pc~0); 127501#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 127659#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127656#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127654#L849 assume !(0 != activate_threads_~tmp___2~0#1); 127653#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127652#L396 assume !(1 == ~t4_pc~0); 127651#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127650#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127649#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127648#L857 assume !(0 != activate_threads_~tmp___3~0#1); 127647#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127646#L415 assume !(1 == ~t5_pc~0); 127645#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 127644#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127643#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 127642#L865 assume !(0 != activate_threads_~tmp___4~0#1); 127641#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 127640#L434 assume !(1 == ~t6_pc~0); 127639#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 127658#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 127655#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 127634#L873 assume !(0 != activate_threads_~tmp___5~0#1); 127633#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127632#L743 assume !(1 == ~M_E~0); 127631#L743-2 assume !(1 == ~T1_E~0); 127630#L748-1 assume !(1 == ~T2_E~0); 127629#L753-1 assume !(1 == ~T3_E~0); 127628#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 127446#L763-1 assume !(1 == ~T5_E~0); 127511#L768-1 assume !(1 == ~T6_E~0); 127109#L773-1 assume !(1 == ~E_1~0); 127110#L778-1 assume !(1 == ~E_2~0); 127093#L783-1 assume !(1 == ~E_3~0); 127094#L788-1 assume !(1 == ~E_4~0); 127401#L793-1 assume !(1 == ~E_5~0); 127351#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 126989#L803-1 assume { :end_inline_reset_delta_events } true; 126990#L1024-2 [2021-12-19 19:17:32,193 INFO L793 eck$LassoCheckResult]: Loop: 126990#L1024-2 assume !false; 143934#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143928#L645 assume !false; 143892#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 143868#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 143861#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 143860#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143857#L556 assume !(0 != eval_~tmp~0#1); 143858#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 152163#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 152161#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 143692#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 152158#L675-3 assume !(0 == ~T2_E~0); 152156#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 152154#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143687#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152607#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 152177#L700-3 assume !(0 == ~E_1~0); 152176#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152175#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152174#L715-3 assume !(0 == ~E_4~0); 152173#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152172#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 152171#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152169#L320-21 assume !(1 == ~m_pc~0); 152168#L320-23 is_master_triggered_~__retres1~0#1 := 0; 152167#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152166#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 152165#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 152164#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152162#L339-21 assume !(1 == ~t1_pc~0); 152160#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 152159#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152157#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 152155#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152153#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152151#L358-21 assume !(1 == ~t2_pc~0); 152149#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 152147#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152145#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152143#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152141#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152139#L377-21 assume !(1 == ~t3_pc~0); 152136#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 152134#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152132#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152130#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 152128#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152126#L396-21 assume !(1 == ~t4_pc~0); 152124#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 152122#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152120#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152118#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 152116#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152114#L415-21 assume !(1 == ~t5_pc~0); 152112#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 152110#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152108#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152106#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 152104#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152102#L434-21 assume !(1 == ~t6_pc~0); 152098#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 152096#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152094#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152091#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 152088#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152086#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 152084#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152082#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152080#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152038#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152037#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152034#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 152032#L773-3 assume !(1 == ~E_1~0); 152030#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 152028#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 152026#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152024#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152022#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152021#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 152010#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 152005#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 152003#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 151828#L1043 assume !(0 == start_simulation_~tmp~3#1); 144217#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 144202#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 144190#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 144188#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 144186#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144184#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 144183#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 144182#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 126990#L1024-2 [2021-12-19 19:17:32,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1411040029, now seen corresponding path program 1 times [2021-12-19 19:17:32,193 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86568928] [2021-12-19 19:17:32,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86568928] [2021-12-19 19:17:32,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86568928] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:32,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689910544] [2021-12-19 19:17:32,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,213 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:32,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,213 INFO L85 PathProgramCache]: Analyzing trace with hash -1683658978, now seen corresponding path program 2 times [2021-12-19 19:17:32,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019803597] [2021-12-19 19:17:32,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019803597] [2021-12-19 19:17:32,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019803597] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,240 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,240 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:32,241 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425838796] [2021-12-19 19:17:32,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,241 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:32,241 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:32,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:32,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:32,242 INFO L87 Difference]: Start difference. First operand 27710 states and 39205 transitions. cyclomatic complexity: 11527 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:32,408 INFO L93 Difference]: Finished difference Result 41839 states and 59201 transitions. [2021-12-19 19:17:32,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:32,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41839 states and 59201 transitions. [2021-12-19 19:17:32,753 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41394 [2021-12-19 19:17:32,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41839 states to 41839 states and 59201 transitions. [2021-12-19 19:17:32,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41839 [2021-12-19 19:17:32,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41839 [2021-12-19 19:17:32,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41839 states and 59201 transitions. [2021-12-19 19:17:32,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:32,942 INFO L681 BuchiCegarLoop]: Abstraction has 41839 states and 59201 transitions. [2021-12-19 19:17:32,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41839 states and 59201 transitions. [2021-12-19 19:17:33,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41839 to 30376. [2021-12-19 19:17:33,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30376 states, 30376 states have (on average 1.4178957071372136) internal successors, (43070), 30375 states have internal predecessors, (43070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30376 states to 30376 states and 43070 transitions. [2021-12-19 19:17:33,422 INFO L704 BuchiCegarLoop]: Abstraction has 30376 states and 43070 transitions. [2021-12-19 19:17:33,422 INFO L587 BuchiCegarLoop]: Abstraction has 30376 states and 43070 transitions. [2021-12-19 19:17:33,422 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:33,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30376 states and 43070 transitions. [2021-12-19 19:17:33,514 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30036 [2021-12-19 19:17:33,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,516 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,516 INFO L791 eck$LassoCheckResult]: Stem: 197213#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 197139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 197048#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196423#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196419#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 196420#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 196971#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197165#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196510#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196511#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196664#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 196529#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196530#L670 assume !(0 == ~M_E~0); 196925#L670-2 assume !(0 == ~T1_E~0); 196860#L675-1 assume !(0 == ~T2_E~0); 196861#L680-1 assume !(0 == ~T3_E~0); 196970#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 197067#L690-1 assume !(0 == ~T5_E~0); 197205#L695-1 assume !(0 == ~T6_E~0); 197206#L700-1 assume !(0 == ~E_1~0); 197004#L705-1 assume !(0 == ~E_2~0); 197005#L710-1 assume !(0 == ~E_3~0); 197235#L715-1 assume !(0 == ~E_4~0); 196771#L720-1 assume !(0 == ~E_5~0); 196772#L725-1 assume !(0 == ~E_6~0); 196890#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 196891#L320 assume !(1 == ~m_pc~0); 197172#L320-2 is_master_triggered_~__retres1~0#1 := 0; 197173#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197234#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 197233#L825 assume !(0 != activate_threads_~tmp~1#1); 197077#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197078#L339 assume !(1 == ~t1_pc~0); 197053#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197054#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197021#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197022#L833 assume !(0 != activate_threads_~tmp___0~0#1); 197149#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197150#L358 assume !(1 == ~t2_pc~0); 196997#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 196998#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197137#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197231#L841 assume !(0 != activate_threads_~tmp___1~0#1); 197230#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197083#L377 assume !(1 == ~t3_pc~0); 197084#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 196955#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196956#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196668#L849 assume !(0 != activate_threads_~tmp___2~0#1); 196669#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 196617#L396 assume !(1 == ~t4_pc~0); 196618#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 197129#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197201#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 196876#L857 assume !(0 != activate_threads_~tmp___3~0#1); 196877#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 197227#L415 assume !(1 == ~t5_pc~0); 196691#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 196692#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 197183#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 197184#L865 assume !(0 != activate_threads_~tmp___4~0#1); 196486#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 196487#L434 assume !(1 == ~t6_pc~0); 197226#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 197222#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197223#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196987#L873 assume !(0 != activate_threads_~tmp___5~0#1); 196988#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197147#L743 assume !(1 == ~M_E~0); 197148#L743-2 assume !(1 == ~T1_E~0); 197224#L748-1 assume !(1 == ~T2_E~0); 196883#L753-1 assume !(1 == ~T3_E~0); 196884#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 197024#L763-1 assume !(1 == ~T5_E~0); 197093#L768-1 assume !(1 == ~T6_E~0); 196673#L773-1 assume !(1 == ~E_1~0); 196674#L778-1 assume !(1 == ~E_2~0); 196657#L783-1 assume !(1 == ~E_3~0); 196658#L788-1 assume !(1 == ~E_4~0); 196967#L793-1 assume !(1 == ~E_5~0); 196918#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 196548#L803-1 assume { :end_inline_reset_delta_events } true; 196549#L1024-2 [2021-12-19 19:17:33,516 INFO L793 eck$LassoCheckResult]: Loop: 196549#L1024-2 assume !false; 214934#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 214928#L645 assume !false; 214926#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 214912#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 214904#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 214903#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 214900#L556 assume !(0 != eval_~tmp~0#1); 214898#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 214896#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 214894#L670-3 assume !(0 == ~M_E~0); 214892#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 214889#L675-3 assume !(0 == ~T2_E~0); 214887#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 214884#L685-3 assume !(0 == ~T4_E~0); 214882#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 214880#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 214878#L700-3 assume !(0 == ~E_1~0); 214842#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 214840#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 214838#L715-3 assume !(0 == ~E_4~0); 214836#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 214834#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 214832#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214830#L320-21 assume !(1 == ~m_pc~0); 214829#L320-23 is_master_triggered_~__retres1~0#1 := 0; 214827#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214825#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 214823#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 214821#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214819#L339-21 assume !(1 == ~t1_pc~0); 214818#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 214815#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214813#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 214811#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 214809#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214807#L358-21 assume !(1 == ~t2_pc~0); 214805#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 214802#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214800#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 214798#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 214796#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214794#L377-21 assume !(1 == ~t3_pc~0); 214791#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 214790#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214788#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 214786#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 214784#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214782#L396-21 assume !(1 == ~t4_pc~0); 214778#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 214776#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214774#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214772#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 214769#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214767#L415-21 assume !(1 == ~t5_pc~0); 214764#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 214762#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214760#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214758#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 214757#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214756#L434-21 assume !(1 == ~t6_pc~0); 214754#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 214873#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214871#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214749#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 214746#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214745#L743-3 assume !(1 == ~M_E~0); 212376#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 214742#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 214740#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 214738#L758-3 assume !(1 == ~T4_E~0); 214733#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 214731#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 214729#L773-3 assume !(1 == ~E_1~0); 214727#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 214724#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 214722#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 214719#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 214717#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 214715#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 213634#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 213629#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 213627#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 212364#L1043 assume !(0 == start_simulation_~tmp~3#1); 212365#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 214954#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 214947#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 214945#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 214943#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 214942#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 214940#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 214938#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 196549#L1024-2 [2021-12-19 19:17:33,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,517 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2021-12-19 19:17:33,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281868669] [2021-12-19 19:17:33,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,540 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281868669] [2021-12-19 19:17:33,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281868669] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,540 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,541 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517266265] [2021-12-19 19:17:33,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,541 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1003026966, now seen corresponding path program 1 times [2021-12-19 19:17:33,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740026155] [2021-12-19 19:17:33,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740026155] [2021-12-19 19:17:33,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740026155] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,729 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:33,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922074480] [2021-12-19 19:17:33,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,730 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:33,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:33,730 INFO L87 Difference]: Start difference. First operand 30376 states and 43070 transitions. cyclomatic complexity: 12710 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,902 INFO L93 Difference]: Finished difference Result 37225 states and 52575 transitions. [2021-12-19 19:17:33,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:33,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37225 states and 52575 transitions. [2021-12-19 19:17:34,045 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36850 [2021-12-19 19:17:34,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37225 states to 37225 states and 52575 transitions. [2021-12-19 19:17:34,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37225 [2021-12-19 19:17:34,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37225 [2021-12-19 19:17:34,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37225 states and 52575 transitions. [2021-12-19 19:17:34,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,320 INFO L681 BuchiCegarLoop]: Abstraction has 37225 states and 52575 transitions. [2021-12-19 19:17:34,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37225 states and 52575 transitions. [2021-12-19 19:17:34,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37225 to 25771. [2021-12-19 19:17:34,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25771 states, 25771 states have (on average 1.4161654572969617) internal successors, (36496), 25770 states have internal predecessors, (36496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25771 states to 25771 states and 36496 transitions. [2021-12-19 19:17:34,609 INFO L704 BuchiCegarLoop]: Abstraction has 25771 states and 36496 transitions. [2021-12-19 19:17:34,609 INFO L587 BuchiCegarLoop]: Abstraction has 25771 states and 36496 transitions. [2021-12-19 19:17:34,610 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:34,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25771 states and 36496 transitions. [2021-12-19 19:17:34,745 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25492 [2021-12-19 19:17:34,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,746 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,746 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,746 INFO L791 eck$LassoCheckResult]: Stem: 264764#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 264704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 264628#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264036#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264032#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 264033#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264563#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264735#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264122#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264123#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264275#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 264141#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264142#L670 assume !(0 == ~M_E~0); 264525#L670-2 assume !(0 == ~T1_E~0); 264467#L675-1 assume !(0 == ~T2_E~0); 264468#L680-1 assume !(0 == ~T3_E~0); 264561#L685-1 assume !(0 == ~T4_E~0); 264528#L690-1 assume !(0 == ~T5_E~0); 264529#L695-1 assume !(0 == ~T6_E~0); 264602#L700-1 assume !(0 == ~E_1~0); 264591#L705-1 assume !(0 == ~E_2~0); 264592#L710-1 assume !(0 == ~E_3~0); 264465#L715-1 assume !(0 == ~E_4~0); 264383#L720-1 assume !(0 == ~E_5~0); 264384#L725-1 assume !(0 == ~E_6~0); 264444#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264495#L320 assume !(1 == ~m_pc~0); 264624#L320-2 is_master_triggered_~__retres1~0#1 := 0; 264316#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264317#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 264276#L825 assume !(0 != activate_threads_~tmp~1#1); 264277#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264281#L339 assume !(1 == ~t1_pc~0); 264282#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264261#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264262#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264144#L833 assume !(0 != activate_threads_~tmp___0~0#1); 264145#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264056#L358 assume !(1 == ~t2_pc~0); 264057#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264584#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264526#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264448#L841 assume !(0 != activate_threads_~tmp___1~0#1); 264271#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264272#L377 assume !(1 == ~t3_pc~0); 264547#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264548#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264541#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264279#L849 assume !(0 != activate_threads_~tmp___2~0#1); 264280#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264227#L396 assume !(1 == ~t4_pc~0); 264228#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264058#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264059#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264482#L857 assume !(0 != activate_threads_~tmp___3~0#1); 264198#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264199#L415 assume !(1 == ~t5_pc~0); 264263#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264304#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264496#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 264634#L865 assume !(0 != activate_threads_~tmp___4~0#1); 264099#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264100#L434 assume !(1 == ~t6_pc~0); 264421#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 264422#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264757#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264575#L873 assume !(0 != activate_threads_~tmp___5~0#1); 264292#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264293#L743 assume !(1 == ~M_E~0); 264188#L743-2 assume !(1 == ~T1_E~0); 264189#L748-1 assume !(1 == ~T2_E~0); 264487#L753-1 assume !(1 == ~T3_E~0); 264488#L758-1 assume !(1 == ~T4_E~0); 264605#L763-1 assume !(1 == ~T5_E~0); 264665#L768-1 assume !(1 == ~T6_E~0); 264288#L773-1 assume !(1 == ~E_1~0); 264289#L778-1 assume !(1 == ~E_2~0); 264268#L783-1 assume !(1 == ~E_3~0); 264269#L788-1 assume !(1 == ~E_4~0); 264559#L793-1 assume !(1 == ~E_5~0); 264518#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 264160#L803-1 assume { :end_inline_reset_delta_events } true; 264161#L1024-2 [2021-12-19 19:17:34,747 INFO L793 eck$LassoCheckResult]: Loop: 264161#L1024-2 assume !false; 282004#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 281998#L645 assume !false; 281996#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 281994#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 281986#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 281452#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 281440#L556 assume !(0 != eval_~tmp~0#1); 264751#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 264582#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 264583#L670-3 assume !(0 == ~M_E~0); 289696#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 289695#L675-3 assume !(0 == ~T2_E~0); 289694#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 289693#L685-3 assume !(0 == ~T4_E~0); 289692#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 289689#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 289687#L700-3 assume !(0 == ~E_1~0); 264769#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 264212#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 264213#L715-3 assume !(0 == ~E_4~0); 264449#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 264450#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 264530#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264290#L320-21 assume !(1 == ~m_pc~0); 264291#L320-23 is_master_triggered_~__retres1~0#1 := 0; 264447#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264368#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 264369#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 264650#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264223#L339-21 assume !(1 == ~t1_pc~0); 264224#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 264484#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264200#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264082#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 264083#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264179#L358-21 assume !(1 == ~t2_pc~0); 264233#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 264162#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264163#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264453#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 264201#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264202#L377-21 assume !(1 == ~t3_pc~0); 264577#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 264480#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264481#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264505#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 264336#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264337#L396-21 assume !(1 == ~t4_pc~0); 264366#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 264367#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264334#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264065#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 264066#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264311#L415-21 assume !(1 == ~t5_pc~0); 264286#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 264287#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264183#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 264184#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 264388#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264389#L434-21 assume !(1 == ~t6_pc~0); 264086#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 264087#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264630#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264307#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 264308#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264302#L743-3 assume !(1 == ~M_E~0); 264303#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 264734#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 264474#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 264411#L758-3 assume !(1 == ~T4_E~0); 264327#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 264328#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 264715#L773-3 assume !(1 == ~E_1~0); 284462#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 284452#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 284405#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 284404#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 284403#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 284402#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 284397#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 284393#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 284392#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 277070#L1043 assume !(0 == start_simulation_~tmp~3#1); 277071#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 282024#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 282018#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282015#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 282013#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 282011#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282009#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 282007#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 264161#L1024-2 [2021-12-19 19:17:34,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,747 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2021-12-19 19:17:34,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987300707] [2021-12-19 19:17:34,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987300707] [2021-12-19 19:17:34,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987300707] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,768 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:34,768 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48818403] [2021-12-19 19:17:34,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,768 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1003026966, now seen corresponding path program 2 times [2021-12-19 19:17:34,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624922250] [2021-12-19 19:17:34,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624922250] [2021-12-19 19:17:34,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624922250] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,791 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,791 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:34,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282828766] [2021-12-19 19:17:34,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:34,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:34,792 INFO L87 Difference]: Start difference. First operand 25771 states and 36496 transitions. cyclomatic complexity: 10741 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,880 INFO L93 Difference]: Finished difference Result 24844 states and 34733 transitions. [2021-12-19 19:17:34,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:34,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24844 states and 34733 transitions. [2021-12-19 19:17:34,974 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24568 [2021-12-19 19:17:35,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24844 states to 24844 states and 34733 transitions. [2021-12-19 19:17:35,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24844 [2021-12-19 19:17:35,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24844 [2021-12-19 19:17:35,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24844 states and 34733 transitions. [2021-12-19 19:17:35,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:35,070 INFO L681 BuchiCegarLoop]: Abstraction has 24844 states and 34733 transitions. [2021-12-19 19:17:35,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24844 states and 34733 transitions. [2021-12-19 19:17:35,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24844 to 24844. [2021-12-19 19:17:35,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24844 states, 24844 states have (on average 1.3980437932700047) internal successors, (34733), 24843 states have internal predecessors, (34733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24844 states to 24844 states and 34733 transitions. [2021-12-19 19:17:35,484 INFO L704 BuchiCegarLoop]: Abstraction has 24844 states and 34733 transitions. [2021-12-19 19:17:35,484 INFO L587 BuchiCegarLoop]: Abstraction has 24844 states and 34733 transitions. [2021-12-19 19:17:35,485 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:35,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24844 states and 34733 transitions. [2021-12-19 19:17:35,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24568 [2021-12-19 19:17:35,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:35,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:35,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,561 INFO L791 eck$LassoCheckResult]: Stem: 315366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 315323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 315245#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 314660#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 314656#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 314657#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 315177#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 315341#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 314746#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 314747#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 314897#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 314765#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 314766#L670 assume !(0 == ~M_E~0); 315142#L670-2 assume !(0 == ~T1_E~0); 315086#L675-1 assume !(0 == ~T2_E~0); 315087#L680-1 assume !(0 == ~T3_E~0); 315176#L685-1 assume !(0 == ~T4_E~0); 315145#L690-1 assume !(0 == ~T5_E~0); 315146#L695-1 assume !(0 == ~T6_E~0); 315218#L700-1 assume !(0 == ~E_1~0); 315207#L705-1 assume !(0 == ~E_2~0); 315208#L710-1 assume !(0 == ~E_3~0); 315083#L715-1 assume !(0 == ~E_4~0); 315003#L720-1 assume !(0 == ~E_5~0); 315004#L725-1 assume !(0 == ~E_6~0); 315061#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315114#L320 assume !(1 == ~m_pc~0); 315241#L320-2 is_master_triggered_~__retres1~0#1 := 0; 314938#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 314939#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 314898#L825 assume !(0 != activate_threads_~tmp~1#1); 314899#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 314903#L339 assume !(1 == ~t1_pc~0); 314904#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 314883#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 314884#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 314768#L833 assume !(0 != activate_threads_~tmp___0~0#1); 314769#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314680#L358 assume !(1 == ~t2_pc~0); 314681#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 315201#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315143#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 315065#L841 assume !(0 != activate_threads_~tmp___1~0#1); 314893#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 314894#L377 assume !(1 == ~t3_pc~0); 315160#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 315161#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315155#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 314901#L849 assume !(0 != activate_threads_~tmp___2~0#1); 314902#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 314851#L396 assume !(1 == ~t4_pc~0); 314852#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 314682#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314683#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 315101#L857 assume !(0 != activate_threads_~tmp___3~0#1); 314821#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314822#L415 assume !(1 == ~t5_pc~0); 314885#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 314926#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315115#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 315251#L865 assume !(0 != activate_threads_~tmp___4~0#1); 314723#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314724#L434 assume !(1 == ~t6_pc~0); 315038#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 315039#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 315190#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315191#L873 assume !(0 != activate_threads_~tmp___5~0#1); 314914#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314915#L743 assume !(1 == ~M_E~0); 314811#L743-2 assume !(1 == ~T1_E~0); 314812#L748-1 assume !(1 == ~T2_E~0); 315107#L753-1 assume !(1 == ~T3_E~0); 315108#L758-1 assume !(1 == ~T4_E~0); 315222#L763-1 assume !(1 == ~T5_E~0); 315278#L768-1 assume !(1 == ~T6_E~0); 314908#L773-1 assume !(1 == ~E_1~0); 314909#L778-1 assume !(1 == ~E_2~0); 314890#L783-1 assume !(1 == ~E_3~0); 314891#L788-1 assume !(1 == ~E_4~0); 315174#L793-1 assume !(1 == ~E_5~0); 315136#L798-1 assume !(1 == ~E_6~0); 314785#L803-1 assume { :end_inline_reset_delta_events } true; 314786#L1024-2 [2021-12-19 19:17:35,561 INFO L793 eck$LassoCheckResult]: Loop: 314786#L1024-2 assume !false; 331642#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 331639#L645 assume !false; 333095#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 333093#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 331622#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 331609#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 331610#L556 assume !(0 != eval_~tmp~0#1); 333081#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338918#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 338916#L670-3 assume !(0 == ~M_E~0); 338914#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 338911#L675-3 assume !(0 == ~T2_E~0); 338909#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 338907#L685-3 assume !(0 == ~T4_E~0); 338905#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 338903#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 338900#L700-3 assume !(0 == ~E_1~0); 338898#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 338896#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 338894#L715-3 assume !(0 == ~E_4~0); 338892#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 338890#L725-3 assume !(0 == ~E_6~0); 338888#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 338887#L320-21 assume !(1 == ~m_pc~0); 338885#L320-23 is_master_triggered_~__retres1~0#1 := 0; 338883#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 338881#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 338879#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 338877#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 338874#L339-21 assume !(1 == ~t1_pc~0); 338872#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 338870#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 338868#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338866#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 338864#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 338861#L358-21 assume !(1 == ~t2_pc~0); 338859#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 338857#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 338856#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 338855#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 338854#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 338853#L377-21 assume 1 == ~t3_pc~0; 338852#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 338850#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 338849#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 338848#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 338846#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 338844#L396-21 assume !(1 == ~t4_pc~0); 338842#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 338841#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 338840#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 338839#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 338838#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 338837#L415-21 assume !(1 == ~t5_pc~0); 338836#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 338835#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 338834#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 338833#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 331980#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331981#L434-21 assume !(1 == ~t6_pc~0); 337826#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 337825#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 337824#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 337823#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 337822#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337821#L743-3 assume !(1 == ~M_E~0); 334674#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 337820#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 337819#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 337818#L758-3 assume !(1 == ~T4_E~0); 337817#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 337816#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 337815#L773-3 assume !(1 == ~E_1~0); 337814#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 337813#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 337812#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 337811#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 337810#L798-3 assume !(1 == ~E_6~0); 337809#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 331757#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 331752#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 331736#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 331728#L1043 assume !(0 == start_simulation_~tmp~3#1); 331729#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 335016#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 335011#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 335010#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 335009#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 335008#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 335007#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 335006#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 314786#L1024-2 [2021-12-19 19:17:35,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,562 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2021-12-19 19:17:35,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130651398] [2021-12-19 19:17:35,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:35,572 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:35,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:35,610 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:35,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,611 INFO L85 PathProgramCache]: Analyzing trace with hash -664262733, now seen corresponding path program 1 times [2021-12-19 19:17:35,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372355322] [2021-12-19 19:17:35,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:35,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:35,636 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:35,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372355322] [2021-12-19 19:17:35,637 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372355322] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:35,637 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:35,637 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:35,637 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300857391] [2021-12-19 19:17:35,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:35,637 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:35,638 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:35,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:35,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:35,638 INFO L87 Difference]: Start difference. First operand 24844 states and 34733 transitions. cyclomatic complexity: 9905 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:35,817 INFO L93 Difference]: Finished difference Result 43548 states and 59948 transitions. [2021-12-19 19:17:35,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:17:35,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43548 states and 59948 transitions. [2021-12-19 19:17:36,005 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43080 [2021-12-19 19:17:36,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43548 states to 43548 states and 59948 transitions. [2021-12-19 19:17:36,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43548 [2021-12-19 19:17:36,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43548 [2021-12-19 19:17:36,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43548 states and 59948 transitions. [2021-12-19 19:17:36,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:36,405 INFO L681 BuchiCegarLoop]: Abstraction has 43548 states and 59948 transitions. [2021-12-19 19:17:36,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43548 states and 59948 transitions. [2021-12-19 19:17:36,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43548 to 25060. [2021-12-19 19:17:36,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25060 states, 25060 states have (on average 1.394612928970471) internal successors, (34949), 25059 states have internal predecessors, (34949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25060 states to 25060 states and 34949 transitions. [2021-12-19 19:17:36,733 INFO L704 BuchiCegarLoop]: Abstraction has 25060 states and 34949 transitions. [2021-12-19 19:17:36,733 INFO L587 BuchiCegarLoop]: Abstraction has 25060 states and 34949 transitions. [2021-12-19 19:17:36,733 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:36,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25060 states and 34949 transitions. [2021-12-19 19:17:36,804 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24784 [2021-12-19 19:17:36,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,805 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,806 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,806 INFO L791 eck$LassoCheckResult]: Stem: 383800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 383743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 383664#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 383068#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 383064#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 383065#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 383596#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 383769#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 383152#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 383153#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 383309#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 383172#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 383173#L670 assume !(0 == ~M_E~0); 383558#L670-2 assume !(0 == ~T1_E~0); 383503#L675-1 assume !(0 == ~T2_E~0); 383504#L680-1 assume !(0 == ~T3_E~0); 383595#L685-1 assume !(0 == ~T4_E~0); 383562#L690-1 assume !(0 == ~T5_E~0); 383563#L695-1 assume !(0 == ~T6_E~0); 383640#L700-1 assume !(0 == ~E_1~0); 383627#L705-1 assume !(0 == ~E_2~0); 383628#L710-1 assume !(0 == ~E_3~0); 383501#L715-1 assume !(0 == ~E_4~0); 383417#L720-1 assume !(0 == ~E_5~0); 383418#L725-1 assume !(0 == ~E_6~0); 383478#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 383530#L320 assume !(1 == ~m_pc~0); 383660#L320-2 is_master_triggered_~__retres1~0#1 := 0; 383350#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 383351#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 383310#L825 assume !(0 != activate_threads_~tmp~1#1); 383311#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 383315#L339 assume !(1 == ~t1_pc~0); 383316#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 383295#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 383296#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 383176#L833 assume !(0 != activate_threads_~tmp___0~0#1); 383177#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 383088#L358 assume !(1 == ~t2_pc~0); 383089#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 383620#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 383559#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 383484#L841 assume !(0 != activate_threads_~tmp___1~0#1); 383305#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 383306#L377 assume !(1 == ~t3_pc~0); 383579#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 383580#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383575#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 383313#L849 assume !(0 != activate_threads_~tmp___2~0#1); 383314#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 383261#L396 assume !(1 == ~t4_pc~0); 383262#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 383090#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383091#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 383518#L857 assume !(0 != activate_threads_~tmp___3~0#1); 383231#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 383232#L415 assume !(1 == ~t5_pc~0); 383297#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 383338#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 383531#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 383670#L865 assume !(0 != activate_threads_~tmp___4~0#1); 383130#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383131#L434 assume !(1 == ~t6_pc~0); 383453#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 383454#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 383609#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 383610#L873 assume !(0 != activate_threads_~tmp___5~0#1); 383326#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 383327#L743 assume !(1 == ~M_E~0); 383220#L743-2 assume !(1 == ~T1_E~0); 383221#L748-1 assume !(1 == ~T2_E~0); 383524#L753-1 assume !(1 == ~T3_E~0); 383525#L758-1 assume !(1 == ~T4_E~0); 383643#L763-1 assume !(1 == ~T5_E~0); 383702#L768-1 assume !(1 == ~T6_E~0); 383320#L773-1 assume !(1 == ~E_1~0); 383321#L778-1 assume !(1 == ~E_2~0); 383302#L783-1 assume !(1 == ~E_3~0); 383303#L788-1 assume !(1 == ~E_4~0); 383593#L793-1 assume !(1 == ~E_5~0); 383550#L798-1 assume !(1 == ~E_6~0); 383192#L803-1 assume { :end_inline_reset_delta_events } true; 383193#L1024-2 [2021-12-19 19:17:36,806 INFO L793 eck$LassoCheckResult]: Loop: 383193#L1024-2 assume !false; 406282#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 406277#L645 assume !false; 406276#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 406275#L504 assume !(0 == ~m_st~0); 406271#L508 assume !(0 == ~t1_st~0); 406272#L512 assume !(0 == ~t2_st~0); 406274#L516 assume !(0 == ~t3_st~0); 406268#L520 assume !(0 == ~t4_st~0); 406270#L524 assume !(0 == ~t5_st~0); 406273#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 406248#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 396722#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 396723#L556 assume !(0 != eval_~tmp~0#1); 406599#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 406597#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 406595#L670-3 assume !(0 == ~M_E~0); 406593#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 406591#L675-3 assume !(0 == ~T2_E~0); 406589#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 406587#L685-3 assume !(0 == ~T4_E~0); 406585#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 406583#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 406581#L700-3 assume !(0 == ~E_1~0); 406579#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 406577#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 406575#L715-3 assume !(0 == ~E_4~0); 406573#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 406571#L725-3 assume !(0 == ~E_6~0); 406569#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 406567#L320-21 assume !(1 == ~m_pc~0); 406565#L320-23 is_master_triggered_~__retres1~0#1 := 0; 406563#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406561#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 406559#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 406557#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406555#L339-21 assume !(1 == ~t1_pc~0); 406553#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 406551#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 406549#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 406547#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 406545#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 406543#L358-21 assume !(1 == ~t2_pc~0); 406541#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 406539#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 406537#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 406535#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 406533#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 406531#L377-21 assume !(1 == ~t3_pc~0); 406528#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 406525#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406523#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 406521#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 406519#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406517#L396-21 assume !(1 == ~t4_pc~0); 406515#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 406513#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 406511#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 406509#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 406507#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406505#L415-21 assume !(1 == ~t5_pc~0); 406503#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 406501#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 406499#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 406497#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 406495#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 406493#L434-21 assume !(1 == ~t6_pc~0); 406489#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 406487#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406485#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 406483#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 406481#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 406479#L743-3 assume !(1 == ~M_E~0); 406476#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 406475#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 406474#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 406473#L758-3 assume !(1 == ~T4_E~0); 406472#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 406471#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 406470#L773-3 assume !(1 == ~E_1~0); 406469#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 406468#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 406467#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 406466#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 406465#L798-3 assume !(1 == ~E_6~0); 406464#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 406460#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 406305#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 406304#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 406301#L1043 assume !(0 == start_simulation_~tmp~3#1); 406298#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 406295#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 406289#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 406288#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 406287#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 406286#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 406285#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 406284#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 383193#L1024-2 [2021-12-19 19:17:36,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,807 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2021-12-19 19:17:36,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221461406] [2021-12-19 19:17:36,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,807 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:36,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:36,815 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:36,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:36,841 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:36,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,842 INFO L85 PathProgramCache]: Analyzing trace with hash -390598815, now seen corresponding path program 1 times [2021-12-19 19:17:36,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850826918] [2021-12-19 19:17:36,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:36,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:36,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:36,890 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:36,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850826918] [2021-12-19 19:17:36,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850826918] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:36,891 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:36,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:36,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675392327] [2021-12-19 19:17:36,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:36,892 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:36,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:36,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:36,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:36,893 INFO L87 Difference]: Start difference. First operand 25060 states and 34949 transitions. cyclomatic complexity: 9905 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,102 INFO L93 Difference]: Finished difference Result 43221 states and 60658 transitions. [2021-12-19 19:17:37,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:37,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43221 states and 60658 transitions. [2021-12-19 19:17:37,480 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42825 [2021-12-19 19:17:37,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43221 states to 43221 states and 60658 transitions. [2021-12-19 19:17:37,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43221 [2021-12-19 19:17:37,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43221 [2021-12-19 19:17:37,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43221 states and 60658 transitions. [2021-12-19 19:17:37,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,649 INFO L681 BuchiCegarLoop]: Abstraction has 43221 states and 60658 transitions. [2021-12-19 19:17:37,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43221 states and 60658 transitions. [2021-12-19 19:17:37,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43221 to 25363. [2021-12-19 19:17:37,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25363 states, 25363 states have (on average 1.3807514883885976) internal successors, (35020), 25362 states have internal predecessors, (35020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25363 states to 25363 states and 35020 transitions. [2021-12-19 19:17:37,947 INFO L704 BuchiCegarLoop]: Abstraction has 25363 states and 35020 transitions. [2021-12-19 19:17:37,947 INFO L587 BuchiCegarLoop]: Abstraction has 25363 states and 35020 transitions. [2021-12-19 19:17:37,947 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:37,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25363 states and 35020 transitions. [2021-12-19 19:17:38,010 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25087 [2021-12-19 19:17:38,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,012 INFO L791 eck$LassoCheckResult]: Stem: 452151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 452080#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 451994#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 451362#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 451358#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 451359#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 451914#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 452114#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 451448#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 451449#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 451605#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 451467#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 451468#L670 assume !(0 == ~M_E~0); 451871#L670-2 assume !(0 == ~T1_E~0); 451808#L675-1 assume !(0 == ~T2_E~0); 451809#L680-1 assume !(0 == ~T3_E~0); 451913#L685-1 assume !(0 == ~T4_E~0); 451874#L690-1 assume !(0 == ~T5_E~0); 451875#L695-1 assume !(0 == ~T6_E~0); 451963#L700-1 assume !(0 == ~E_1~0); 451950#L705-1 assume !(0 == ~E_2~0); 451951#L710-1 assume !(0 == ~E_3~0); 451806#L715-1 assume !(0 == ~E_4~0); 451719#L720-1 assume !(0 == ~E_5~0); 451720#L725-1 assume !(0 == ~E_6~0); 451784#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 451837#L320 assume !(1 == ~m_pc~0); 451987#L320-2 is_master_triggered_~__retres1~0#1 := 0; 451648#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 451649#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 451606#L825 assume !(0 != activate_threads_~tmp~1#1); 451607#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 451611#L339 assume !(1 == ~t1_pc~0); 451612#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 451591#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 451592#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 451470#L833 assume !(0 != activate_threads_~tmp___0~0#1); 451471#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 451382#L358 assume !(1 == ~t2_pc~0); 451383#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 451942#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 451872#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 451789#L841 assume !(0 != activate_threads_~tmp___1~0#1); 451601#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 451602#L377 assume !(1 == ~t3_pc~0); 451897#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 451898#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 451891#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 451609#L849 assume !(0 != activate_threads_~tmp___2~0#1); 451610#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 451552#L396 assume !(1 == ~t4_pc~0); 451553#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 451384#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 451385#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 451822#L857 assume !(0 != activate_threads_~tmp___3~0#1); 451522#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 451523#L415 assume !(1 == ~t5_pc~0); 451593#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 451635#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 451838#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 451999#L865 assume !(0 != activate_threads_~tmp___4~0#1); 451425#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 451426#L434 assume !(1 == ~t6_pc~0); 451758#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 451759#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 451930#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451931#L873 assume !(0 != activate_threads_~tmp___5~0#1); 451623#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 451624#L743 assume !(1 == ~M_E~0); 451512#L743-2 assume !(1 == ~T1_E~0); 451513#L748-1 assume !(1 == ~T2_E~0); 451829#L753-1 assume !(1 == ~T3_E~0); 451830#L758-1 assume !(1 == ~T4_E~0); 451968#L763-1 assume !(1 == ~T5_E~0); 452031#L768-1 assume !(1 == ~T6_E~0); 451616#L773-1 assume !(1 == ~E_1~0); 451617#L778-1 assume !(1 == ~E_2~0); 451598#L783-1 assume !(1 == ~E_3~0); 451599#L788-1 assume !(1 == ~E_4~0); 451910#L793-1 assume !(1 == ~E_5~0); 451862#L798-1 assume !(1 == ~E_6~0); 451486#L803-1 assume { :end_inline_reset_delta_events } true; 451487#L1024-2 [2021-12-19 19:17:38,012 INFO L793 eck$LassoCheckResult]: Loop: 451487#L1024-2 assume !false; 457500#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 457496#L645 assume !false; 457495#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 457494#L504 assume !(0 == ~m_st~0); 457489#L508 assume !(0 == ~t1_st~0); 457490#L512 assume !(0 == ~t2_st~0); 457492#L516 assume !(0 == ~t3_st~0); 457487#L520 assume !(0 == ~t4_st~0); 457488#L524 assume !(0 == ~t5_st~0); 457491#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 457493#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 456280#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 456281#L556 assume !(0 != eval_~tmp~0#1); 457746#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 457744#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 457742#L670-3 assume !(0 == ~M_E~0); 457739#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 457736#L675-3 assume !(0 == ~T2_E~0); 457733#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 457730#L685-3 assume !(0 == ~T4_E~0); 457727#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 457724#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 457721#L700-3 assume !(0 == ~E_1~0); 457718#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 457715#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 457712#L715-3 assume !(0 == ~E_4~0); 457709#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 457706#L725-3 assume !(0 == ~E_6~0); 457697#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 457694#L320-21 assume !(1 == ~m_pc~0); 457691#L320-23 is_master_triggered_~__retres1~0#1 := 0; 457687#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 457685#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 457682#L825-21 assume !(0 != activate_threads_~tmp~1#1); 457679#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 457676#L339-21 assume !(1 == ~t1_pc~0); 457673#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 457670#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 457667#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 457664#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 457661#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 457658#L358-21 assume !(1 == ~t2_pc~0); 457655#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 457652#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 457649#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 457646#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457643#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 457640#L377-21 assume !(1 == ~t3_pc~0); 457636#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 457632#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 457629#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 457626#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 457622#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 457619#L396-21 assume !(1 == ~t4_pc~0); 457616#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 457613#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 457610#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 457607#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 457604#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 457601#L415-21 assume !(1 == ~t5_pc~0); 457598#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 457595#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 457592#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 457589#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 457586#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 457583#L434-21 assume !(1 == ~t6_pc~0); 457578#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 457575#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 457572#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 457568#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 457565#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457562#L743-3 assume !(1 == ~M_E~0); 457558#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 457556#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 457554#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 457551#L758-3 assume !(1 == ~T4_E~0); 457549#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 457547#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 457545#L773-3 assume !(1 == ~E_1~0); 457543#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 457541#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 457539#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 457537#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 457535#L798-3 assume !(1 == ~E_6~0); 457533#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 457528#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 457523#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 457521#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 457518#L1043 assume !(0 == start_simulation_~tmp~3#1); 457517#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 457514#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 457509#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 457508#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 457507#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 457506#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 457505#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 457503#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 451487#L1024-2 [2021-12-19 19:17:38,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,013 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2021-12-19 19:17:38,013 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439868703] [2021-12-19 19:17:38,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,013 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:38,019 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:38,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:38,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:38,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,033 INFO L85 PathProgramCache]: Analyzing trace with hash -444991713, now seen corresponding path program 1 times [2021-12-19 19:17:38,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747680580] [2021-12-19 19:17:38,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747680580] [2021-12-19 19:17:38,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747680580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,053 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998203618] [2021-12-19 19:17:38,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,054 INFO L87 Difference]: Start difference. First operand 25363 states and 35020 transitions. cyclomatic complexity: 9673 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,311 INFO L93 Difference]: Finished difference Result 38446 states and 52280 transitions. [2021-12-19 19:17:38,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38446 states and 52280 transitions. [2021-12-19 19:17:38,458 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38114 [2021-12-19 19:17:38,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38446 states to 38446 states and 52280 transitions. [2021-12-19 19:17:38,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38446 [2021-12-19 19:17:38,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38446 [2021-12-19 19:17:38,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38446 states and 52280 transitions. [2021-12-19 19:17:38,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,596 INFO L681 BuchiCegarLoop]: Abstraction has 38446 states and 52280 transitions. [2021-12-19 19:17:38,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38446 states and 52280 transitions. [2021-12-19 19:17:39,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38446 to 37661. [2021-12-19 19:17:39,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37661 states, 37661 states have (on average 1.36196595948063) internal successors, (51293), 37660 states have internal predecessors, (51293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37661 states to 37661 states and 51293 transitions. [2021-12-19 19:17:39,180 INFO L704 BuchiCegarLoop]: Abstraction has 37661 states and 51293 transitions. [2021-12-19 19:17:39,180 INFO L587 BuchiCegarLoop]: Abstraction has 37661 states and 51293 transitions. [2021-12-19 19:17:39,180 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:39,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37661 states and 51293 transitions. [2021-12-19 19:17:39,279 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37329 [2021-12-19 19:17:39,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,281 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,281 INFO L791 eck$LassoCheckResult]: Stem: 515911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 515850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 515769#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 515177#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515173#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 515174#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515697#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515875#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 515262#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 515263#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 515413#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515281#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515282#L670 assume !(0 == ~M_E~0); 515658#L670-2 assume !(0 == ~T1_E~0); 515601#L675-1 assume !(0 == ~T2_E~0); 515602#L680-1 assume !(0 == ~T3_E~0); 515696#L685-1 assume !(0 == ~T4_E~0); 515661#L690-1 assume !(0 == ~T5_E~0); 515662#L695-1 assume !(0 == ~T6_E~0); 515738#L700-1 assume !(0 == ~E_1~0); 515725#L705-1 assume !(0 == ~E_2~0); 515726#L710-1 assume !(0 == ~E_3~0); 515599#L715-1 assume !(0 == ~E_4~0); 515519#L720-1 assume !(0 == ~E_5~0); 515520#L725-1 assume !(0 == ~E_6~0); 515578#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 515630#L320 assume !(1 == ~m_pc~0); 515761#L320-2 is_master_triggered_~__retres1~0#1 := 0; 515453#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 515454#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 515414#L825 assume !(0 != activate_threads_~tmp~1#1); 515415#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515419#L339 assume !(1 == ~t1_pc~0); 515420#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 515399#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 515400#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 515284#L833 assume !(0 != activate_threads_~tmp___0~0#1); 515285#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 515197#L358 assume !(1 == ~t2_pc~0); 515198#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 515719#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 515659#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 515582#L841 assume !(0 != activate_threads_~tmp___1~0#1); 515409#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 515410#L377 assume !(1 == ~t3_pc~0); 515679#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 515680#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515674#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 515417#L849 assume !(0 != activate_threads_~tmp___2~0#1); 515418#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 515366#L396 assume !(1 == ~t4_pc~0); 515367#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 515199#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 515200#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 515616#L857 assume !(0 != activate_threads_~tmp___3~0#1); 515337#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 515338#L415 assume !(1 == ~t5_pc~0); 515401#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 515440#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 515631#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515775#L865 assume !(0 != activate_threads_~tmp___4~0#1); 515239#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515240#L434 assume !(1 == ~t6_pc~0); 515554#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 515555#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515709#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 515710#L873 assume !(0 != activate_threads_~tmp___5~0#1); 515428#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515429#L743 assume !(1 == ~M_E~0); 515326#L743-2 assume !(1 == ~T1_E~0); 515327#L748-1 assume !(1 == ~T2_E~0); 515622#L753-1 assume !(1 == ~T3_E~0); 515623#L758-1 assume !(1 == ~T4_E~0); 515742#L763-1 assume !(1 == ~T5_E~0); 515804#L768-1 assume !(1 == ~T6_E~0); 515422#L773-1 assume !(1 == ~E_1~0); 515423#L778-1 assume !(1 == ~E_2~0); 515406#L783-1 assume !(1 == ~E_3~0); 515407#L788-1 assume !(1 == ~E_4~0); 515694#L793-1 assume !(1 == ~E_5~0); 515652#L798-1 assume !(1 == ~E_6~0); 515300#L803-1 assume { :end_inline_reset_delta_events } true; 515301#L1024-2 assume !false; 530781#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530782#L645 [2021-12-19 19:17:39,281 INFO L793 eck$LassoCheckResult]: Loop: 530782#L645 assume !false; 532205#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 532203#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 532202#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 532201#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 532200#L556 assume 0 != eval_~tmp~0#1; 532199#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 532198#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 530756#L561 assume !(0 == ~t1_st~0); 530755#L575 assume !(0 == ~t2_st~0); 530804#L589 assume !(0 == ~t3_st~0); 530800#L603 assume !(0 == ~t4_st~0); 530786#L617 assume !(0 == ~t5_st~0); 526275#L631 assume !(0 == ~t6_st~0); 530782#L645 [2021-12-19 19:17:39,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,282 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2021-12-19 19:17:39,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803780507] [2021-12-19 19:17:39,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,282 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:39,289 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:39,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:39,304 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:39,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1489034978, now seen corresponding path program 1 times [2021-12-19 19:17:39,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092477096] [2021-12-19 19:17:39,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:39,309 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:39,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:39,311 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:39,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1336774676, now seen corresponding path program 1 times [2021-12-19 19:17:39,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313321622] [2021-12-19 19:17:39,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313321622] [2021-12-19 19:17:39,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313321622] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888626019] [2021-12-19 19:17:39,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,415 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:39,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:39,416 INFO L87 Difference]: Start difference. First operand 37661 states and 51293 transitions. cyclomatic complexity: 13656 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,636 INFO L93 Difference]: Finished difference Result 70652 states and 95079 transitions. [2021-12-19 19:17:39,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:39,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70652 states and 95079 transitions. [2021-12-19 19:17:39,920 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 63797 [2021-12-19 19:17:40,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70652 states to 70652 states and 95079 transitions. [2021-12-19 19:17:40,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70652 [2021-12-19 19:17:40,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70652 [2021-12-19 19:17:40,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70652 states and 95079 transitions. [2021-12-19 19:17:40,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:40,207 INFO L681 BuchiCegarLoop]: Abstraction has 70652 states and 95079 transitions. [2021-12-19 19:17:40,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70652 states and 95079 transitions. [2021-12-19 19:17:40,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70652 to 68552. [2021-12-19 19:17:41,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68552 states, 68552 states have (on average 1.3481590617341581) internal successors, (92419), 68551 states have internal predecessors, (92419), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68552 states to 68552 states and 92419 transitions. [2021-12-19 19:17:41,129 INFO L704 BuchiCegarLoop]: Abstraction has 68552 states and 92419 transitions. [2021-12-19 19:17:41,137 INFO L587 BuchiCegarLoop]: Abstraction has 68552 states and 92419 transitions. [2021-12-19 19:17:41,137 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:41,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68552 states and 92419 transitions. [2021-12-19 19:17:41,318 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 61697 [2021-12-19 19:17:41,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:41,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:41,319 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:41,319 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:41,319 INFO L791 eck$LassoCheckResult]: Stem: 624271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 624206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 624119#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 623498#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 623494#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 623495#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 624043#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 657606#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 657605#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 657604#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 657603#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 657602#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 657601#L670 assume !(0 == ~M_E~0); 657600#L670-2 assume !(0 == ~T1_E~0); 657599#L675-1 assume !(0 == ~T2_E~0); 657598#L680-1 assume !(0 == ~T3_E~0); 657597#L685-1 assume !(0 == ~T4_E~0); 657596#L690-1 assume !(0 == ~T5_E~0); 657595#L695-1 assume !(0 == ~T6_E~0); 657594#L700-1 assume !(0 == ~E_1~0); 657593#L705-1 assume !(0 == ~E_2~0); 657592#L710-1 assume !(0 == ~E_3~0); 657591#L715-1 assume !(0 == ~E_4~0); 657590#L720-1 assume !(0 == ~E_5~0); 657589#L725-1 assume !(0 == ~E_6~0); 657588#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657587#L320 assume !(1 == ~m_pc~0); 657586#L320-2 is_master_triggered_~__retres1~0#1 := 0; 657585#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 657584#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 657583#L825 assume !(0 != activate_threads_~tmp~1#1); 657582#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 657581#L339 assume !(1 == ~t1_pc~0); 657580#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 657579#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657578#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 657577#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 623606#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 623518#L358 assume !(1 == ~t2_pc~0); 623519#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 624069#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 624002#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 623917#L841 assume !(0 != activate_threads_~tmp___1~0#1); 623732#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 623733#L377 assume !(1 == ~t3_pc~0); 624023#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 624024#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 624016#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 624017#L849 assume !(0 != activate_threads_~tmp___2~0#1); 624037#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 624038#L396 assume !(1 == ~t4_pc~0); 624198#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 624199#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 624259#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 624260#L857 assume !(0 != activate_threads_~tmp___3~0#1); 623661#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 623662#L415 assume !(1 == ~t5_pc~0); 623766#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 623767#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624247#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 624248#L865 assume !(0 != activate_threads_~tmp___4~0#1); 623561#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 623562#L434 assume !(1 == ~t6_pc~0); 623887#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 623888#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 624257#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 624258#L873 assume !(0 != activate_threads_~tmp___5~0#1); 623754#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 623755#L743 assume !(1 == ~M_E~0); 623651#L743-2 assume !(1 == ~T1_E~0); 623652#L748-1 assume !(1 == ~T2_E~0); 623959#L753-1 assume !(1 == ~T3_E~0); 623960#L758-1 assume !(1 == ~T4_E~0); 624158#L763-1 assume !(1 == ~T5_E~0); 624159#L768-1 assume !(1 == ~T6_E~0); 623748#L773-1 assume !(1 == ~E_1~0); 623749#L778-1 assume !(1 == ~E_2~0); 623728#L783-1 assume !(1 == ~E_3~0); 623729#L788-1 assume !(1 == ~E_4~0); 624039#L793-1 assume !(1 == ~E_5~0); 624040#L798-1 assume !(1 == ~E_6~0); 623622#L803-1 assume { :end_inline_reset_delta_events } true; 623623#L1024-2 assume !false; 660292#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 660285#L645 [2021-12-19 19:17:41,319 INFO L793 eck$LassoCheckResult]: Loop: 660285#L645 assume !false; 660283#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 660280#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 660278#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 660276#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 660274#L556 assume 0 != eval_~tmp~0#1; 660269#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 660266#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 660264#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 657402#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 660255#L575 assume !(0 == ~t2_st~0); 660253#L589 assume !(0 == ~t3_st~0); 660302#L603 assume !(0 == ~t4_st~0); 660298#L617 assume !(0 == ~t5_st~0); 660291#L631 assume !(0 == ~t6_st~0); 660285#L645 [2021-12-19 19:17:41,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:41,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2021-12-19 19:17:41,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:41,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911607011] [2021-12-19 19:17:41,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:41,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:41,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:41,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:41,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:41,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911607011] [2021-12-19 19:17:41,333 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911607011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:41,333 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:41,333 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:41,333 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053131226] [2021-12-19 19:17:41,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:41,334 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:41,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:41,334 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 1 times [2021-12-19 19:17:41,334 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:41,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86888555] [2021-12-19 19:17:41,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:41,334 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:41,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:41,337 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:41,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:41,339 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:41,416 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:41,417 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:41,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:41,417 INFO L87 Difference]: Start difference. First operand 68552 states and 92419 transitions. cyclomatic complexity: 23927 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:41,781 INFO L93 Difference]: Finished difference Result 39037 states and 52499 transitions. [2021-12-19 19:17:41,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:41,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39037 states and 52499 transitions. [2021-12-19 19:17:41,923 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38212 [2021-12-19 19:17:42,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39037 states to 39037 states and 52499 transitions. [2021-12-19 19:17:42,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39037 [2021-12-19 19:17:42,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39037 [2021-12-19 19:17:42,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39037 states and 52499 transitions. [2021-12-19 19:17:42,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:42,050 INFO L681 BuchiCegarLoop]: Abstraction has 39037 states and 52499 transitions. [2021-12-19 19:17:42,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39037 states and 52499 transitions. [2021-12-19 19:17:42,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39037 to 39037. [2021-12-19 19:17:42,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39037 states, 39037 states have (on average 1.344852319594231) internal successors, (52499), 39036 states have internal predecessors, (52499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:42,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39037 states to 39037 states and 52499 transitions. [2021-12-19 19:17:42,374 INFO L704 BuchiCegarLoop]: Abstraction has 39037 states and 52499 transitions. [2021-12-19 19:17:42,374 INFO L587 BuchiCegarLoop]: Abstraction has 39037 states and 52499 transitions. [2021-12-19 19:17:42,374 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:42,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39037 states and 52499 transitions. [2021-12-19 19:17:42,477 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38212 [2021-12-19 19:17:42,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:42,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:42,477 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,478 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,478 INFO L791 eck$LassoCheckResult]: Stem: 731843#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 731777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 731702#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 731093#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 731089#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 731090#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 731624#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 731803#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 731181#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 731182#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 731337#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 731199#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 731200#L670 assume !(0 == ~M_E~0); 731586#L670-2 assume !(0 == ~T1_E~0); 731528#L675-1 assume !(0 == ~T2_E~0); 731529#L680-1 assume !(0 == ~T3_E~0); 731622#L685-1 assume !(0 == ~T4_E~0); 731590#L690-1 assume !(0 == ~T5_E~0); 731591#L695-1 assume !(0 == ~T6_E~0); 731675#L700-1 assume !(0 == ~E_1~0); 731663#L705-1 assume !(0 == ~E_2~0); 731664#L710-1 assume !(0 == ~E_3~0); 731527#L715-1 assume !(0 == ~E_4~0); 731446#L720-1 assume !(0 == ~E_5~0); 731447#L725-1 assume !(0 == ~E_6~0); 731503#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 731556#L320 assume !(1 == ~m_pc~0); 731694#L320-2 is_master_triggered_~__retres1~0#1 := 0; 731378#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 731379#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 731338#L825 assume !(0 != activate_threads_~tmp~1#1); 731339#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 731344#L339 assume !(1 == ~t1_pc~0); 731345#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 731322#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 731323#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 731201#L833 assume !(0 != activate_threads_~tmp___0~0#1); 731202#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 731113#L358 assume !(1 == ~t2_pc~0); 731114#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 731655#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 731587#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 731508#L841 assume !(0 != activate_threads_~tmp___1~0#1); 731333#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 731334#L377 assume !(1 == ~t3_pc~0); 731605#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 731606#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 731602#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 731341#L849 assume !(0 != activate_threads_~tmp___2~0#1); 731342#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 731288#L396 assume !(1 == ~t4_pc~0); 731289#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 731115#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 731116#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 731543#L857 assume !(0 != activate_threads_~tmp___3~0#1); 731255#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 731256#L415 assume !(1 == ~t5_pc~0); 731325#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 731364#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 731557#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 731709#L865 assume !(0 != activate_threads_~tmp___4~0#1); 731157#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 731158#L434 assume !(1 == ~t6_pc~0); 731480#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 731481#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 731638#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 731639#L873 assume !(0 != activate_threads_~tmp___5~0#1); 731352#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 731353#L743 assume !(1 == ~M_E~0); 731246#L743-2 assume !(1 == ~T1_E~0); 731247#L748-1 assume !(1 == ~T2_E~0); 731550#L753-1 assume !(1 == ~T3_E~0); 731551#L758-1 assume !(1 == ~T4_E~0); 731678#L763-1 assume !(1 == ~T5_E~0); 731741#L768-1 assume !(1 == ~T6_E~0); 731350#L773-1 assume !(1 == ~E_1~0); 731351#L778-1 assume !(1 == ~E_2~0); 731329#L783-1 assume !(1 == ~E_3~0); 731330#L788-1 assume !(1 == ~E_4~0); 731620#L793-1 assume !(1 == ~E_5~0); 731576#L798-1 assume !(1 == ~E_6~0); 731220#L803-1 assume { :end_inline_reset_delta_events } true; 731221#L1024-2 assume !false; 741520#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 741515#L645 [2021-12-19 19:17:42,478 INFO L793 eck$LassoCheckResult]: Loop: 741515#L645 assume !false; 741512#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 741509#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 741506#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 741507#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 741570#L556 assume 0 != eval_~tmp~0#1; 741568#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 741565#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 741492#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 741490#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 741488#L575 assume !(0 == ~t2_st~0); 741486#L589 assume !(0 == ~t3_st~0); 741530#L603 assume !(0 == ~t4_st~0); 741526#L617 assume !(0 == ~t5_st~0); 740243#L631 assume !(0 == ~t6_st~0); 741515#L645 [2021-12-19 19:17:42,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,479 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2021-12-19 19:17:42,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282637758] [2021-12-19 19:17:42,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,479 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:42,485 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:42,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:42,498 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:42,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,498 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 2 times [2021-12-19 19:17:42,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589787060] [2021-12-19 19:17:42,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:42,501 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:42,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:42,503 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:42,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,504 INFO L85 PathProgramCache]: Analyzing trace with hash -447706070, now seen corresponding path program 1 times [2021-12-19 19:17:42,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,504 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115297589] [2021-12-19 19:17:42,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,504 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115297589] [2021-12-19 19:17:42,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115297589] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119023421] [2021-12-19 19:17:42,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:42,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:42,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:42,621 INFO L87 Difference]: Start difference. First operand 39037 states and 52499 transitions. cyclomatic complexity: 13486 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:43,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:43,024 INFO L93 Difference]: Finished difference Result 71689 states and 95933 transitions. [2021-12-19 19:17:43,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:43,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71689 states and 95933 transitions. [2021-12-19 19:17:43,305 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 70472 [2021-12-19 19:17:43,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71689 states to 71689 states and 95933 transitions. [2021-12-19 19:17:43,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71689 [2021-12-19 19:17:43,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71689 [2021-12-19 19:17:43,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71689 states and 95933 transitions. [2021-12-19 19:17:43,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:43,582 INFO L681 BuchiCegarLoop]: Abstraction has 71689 states and 95933 transitions. [2021-12-19 19:17:43,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71689 states and 95933 transitions. [2021-12-19 19:17:44,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71689 to 69770. [2021-12-19 19:17:44,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69770 states, 69770 states have (on average 1.340461516411065) internal successors, (93524), 69769 states have internal predecessors, (93524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:44,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69770 states to 69770 states and 93524 transitions. [2021-12-19 19:17:44,449 INFO L704 BuchiCegarLoop]: Abstraction has 69770 states and 93524 transitions. [2021-12-19 19:17:44,449 INFO L587 BuchiCegarLoop]: Abstraction has 69770 states and 93524 transitions. [2021-12-19 19:17:44,449 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:44,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69770 states and 93524 transitions. [2021-12-19 19:17:44,675 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 68553 [2021-12-19 19:17:44,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:44,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:44,676 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:44,676 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:44,677 INFO L791 eck$LassoCheckResult]: Stem: 842573#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 842501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 842430#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 841827#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841823#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 841824#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 842364#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 842530#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 841914#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 841915#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 842071#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 841933#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 841934#L670 assume !(0 == ~M_E~0); 842325#L670-2 assume !(0 == ~T1_E~0); 842266#L675-1 assume !(0 == ~T2_E~0); 842267#L680-1 assume !(0 == ~T3_E~0); 842362#L685-1 assume !(0 == ~T4_E~0); 842330#L690-1 assume !(0 == ~T5_E~0); 842331#L695-1 assume !(0 == ~T6_E~0); 842408#L700-1 assume !(0 == ~E_1~0); 842395#L705-1 assume !(0 == ~E_2~0); 842396#L710-1 assume !(0 == ~E_3~0); 842265#L715-1 assume !(0 == ~E_4~0); 842185#L720-1 assume !(0 == ~E_5~0); 842186#L725-1 assume !(0 == ~E_6~0); 842241#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 842296#L320 assume !(1 == ~m_pc~0); 842426#L320-2 is_master_triggered_~__retres1~0#1 := 0; 842115#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842116#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 842072#L825 assume !(0 != activate_threads_~tmp~1#1); 842073#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 842080#L339 assume !(1 == ~t1_pc~0); 842081#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842056#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 842057#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 841935#L833 assume !(0 != activate_threads_~tmp___0~0#1); 841936#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 841847#L358 assume !(1 == ~t2_pc~0); 841848#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 842389#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 842327#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 842247#L841 assume !(0 != activate_threads_~tmp___1~0#1); 842069#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 842070#L377 assume !(1 == ~t3_pc~0); 842344#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 842345#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 842343#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 842075#L849 assume !(0 != activate_threads_~tmp___2~0#1); 842076#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 842024#L396 assume !(1 == ~t4_pc~0); 842025#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 841849#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 841850#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 842281#L857 assume !(0 != activate_threads_~tmp___3~0#1); 841990#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 841991#L415 assume !(1 == ~t5_pc~0); 842059#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 842103#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 842297#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 842438#L865 assume !(0 != activate_threads_~tmp___4~0#1); 841890#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 841891#L434 assume !(1 == ~t6_pc~0); 842219#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 842220#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 842378#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 842379#L873 assume !(0 != activate_threads_~tmp___5~0#1); 842088#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 842089#L743 assume !(1 == ~M_E~0); 841981#L743-2 assume !(1 == ~T1_E~0); 841982#L748-1 assume !(1 == ~T2_E~0); 842289#L753-1 assume !(1 == ~T3_E~0); 842290#L758-1 assume !(1 == ~T4_E~0); 842411#L763-1 assume !(1 == ~T5_E~0); 842465#L768-1 assume !(1 == ~T6_E~0); 842086#L773-1 assume !(1 == ~E_1~0); 842087#L778-1 assume !(1 == ~E_2~0); 842064#L783-1 assume !(1 == ~E_3~0); 842065#L788-1 assume !(1 == ~E_4~0); 842359#L793-1 assume !(1 == ~E_5~0); 842317#L798-1 assume !(1 == ~E_6~0); 841954#L803-1 assume { :end_inline_reset_delta_events } true; 841955#L1024-2 assume !false; 862973#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 862967#L645 [2021-12-19 19:17:44,677 INFO L793 eck$LassoCheckResult]: Loop: 862967#L645 assume !false; 862966#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 862964#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 862963#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 862960#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 862955#L556 assume 0 != eval_~tmp~0#1; 862952#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 862949#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 862946#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 862943#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 862944#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 862986#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 862983#L589 assume !(0 == ~t3_st~0); 862980#L603 assume !(0 == ~t4_st~0); 862978#L617 assume !(0 == ~t5_st~0); 862972#L631 assume !(0 == ~t6_st~0); 862967#L645 [2021-12-19 19:17:44,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:44,677 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2021-12-19 19:17:44,678 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:44,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334361436] [2021-12-19 19:17:44,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:44,678 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:44,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:44,684 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:44,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:44,698 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:44,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:44,699 INFO L85 PathProgramCache]: Analyzing trace with hash 488929788, now seen corresponding path program 1 times [2021-12-19 19:17:44,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:44,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514547324] [2021-12-19 19:17:44,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:44,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:44,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:44,702 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:44,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:44,704 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:44,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:44,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1672676210, now seen corresponding path program 1 times [2021-12-19 19:17:44,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:44,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376039960] [2021-12-19 19:17:44,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:44,705 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:44,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:44,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:44,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:44,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376039960] [2021-12-19 19:17:44,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376039960] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:44,724 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:44,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:44,725 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023324099] [2021-12-19 19:17:44,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:44,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:44,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:44,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:44,824 INFO L87 Difference]: Start difference. First operand 69770 states and 93524 transitions. cyclomatic complexity: 23778 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:45,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:45,154 INFO L93 Difference]: Finished difference Result 128042 states and 170916 transitions. [2021-12-19 19:17:45,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:45,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128042 states and 170916 transitions. [2021-12-19 19:17:46,103 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 125694 [2021-12-19 19:17:46,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128042 states to 128042 states and 170916 transitions. [2021-12-19 19:17:46,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128042 [2021-12-19 19:17:46,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128042 [2021-12-19 19:17:46,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128042 states and 170916 transitions. [2021-12-19 19:17:46,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:46,587 INFO L681 BuchiCegarLoop]: Abstraction has 128042 states and 170916 transitions. [2021-12-19 19:17:46,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128042 states and 170916 transitions. [2021-12-19 19:17:47,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128042 to 121673. [2021-12-19 19:17:47,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121673 states, 121673 states have (on average 1.3416863231776976) internal successors, (163247), 121672 states have internal predecessors, (163247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:47,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121673 states to 121673 states and 163247 transitions. [2021-12-19 19:17:47,931 INFO L704 BuchiCegarLoop]: Abstraction has 121673 states and 163247 transitions. [2021-12-19 19:17:47,931 INFO L587 BuchiCegarLoop]: Abstraction has 121673 states and 163247 transitions. [2021-12-19 19:17:47,931 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:17:47,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121673 states and 163247 transitions. [2021-12-19 19:17:48,304 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 119325 [2021-12-19 19:17:48,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:48,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:48,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:48,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:48,305 INFO L791 eck$LassoCheckResult]: Stem: 1040423#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1040347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1040262#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1039647#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1039643#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1039644#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1040185#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1040378#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1039734#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1039735#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1039889#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1039753#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1039754#L670 assume !(0 == ~M_E~0); 1040147#L670-2 assume !(0 == ~T1_E~0); 1040087#L675-1 assume !(0 == ~T2_E~0); 1040088#L680-1 assume !(0 == ~T3_E~0); 1040184#L685-1 assume !(0 == ~T4_E~0); 1040150#L690-1 assume !(0 == ~T5_E~0); 1040151#L695-1 assume !(0 == ~T6_E~0); 1040232#L700-1 assume !(0 == ~E_1~0); 1040221#L705-1 assume !(0 == ~E_2~0); 1040222#L710-1 assume !(0 == ~E_3~0); 1040085#L715-1 assume !(0 == ~E_4~0); 1040002#L720-1 assume !(0 == ~E_5~0); 1040003#L725-1 assume !(0 == ~E_6~0); 1040062#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1040116#L320 assume !(1 == ~m_pc~0); 1040256#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1039934#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1039935#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1039890#L825 assume !(0 != activate_threads_~tmp~1#1); 1039891#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1039896#L339 assume !(1 == ~t1_pc~0); 1039897#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1039875#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1039876#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1039756#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1039757#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1039667#L358 assume !(1 == ~t2_pc~0); 1039668#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1040215#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1040148#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1040068#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1039885#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1039886#L377 assume !(1 == ~t3_pc~0); 1040167#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1040168#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1040162#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1039894#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1039895#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1039842#L396 assume !(1 == ~t4_pc~0); 1039843#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1039669#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1039670#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1040102#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1039812#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1039813#L415 assume !(1 == ~t5_pc~0); 1039877#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1039919#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1040117#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1040269#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1039711#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1039712#L434 assume !(1 == ~t6_pc~0); 1040037#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1040038#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1040201#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1040202#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1039907#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1039908#L743 assume !(1 == ~M_E~0); 1039801#L743-2 assume !(1 == ~T1_E~0); 1039802#L748-1 assume !(1 == ~T2_E~0); 1040109#L753-1 assume !(1 == ~T3_E~0); 1040110#L758-1 assume !(1 == ~T4_E~0); 1040235#L763-1 assume !(1 == ~T5_E~0); 1040299#L768-1 assume !(1 == ~T6_E~0); 1039901#L773-1 assume !(1 == ~E_1~0); 1039902#L778-1 assume !(1 == ~E_2~0); 1039882#L783-1 assume !(1 == ~E_3~0); 1039883#L788-1 assume !(1 == ~E_4~0); 1040182#L793-1 assume !(1 == ~E_5~0); 1040140#L798-1 assume !(1 == ~E_6~0); 1039773#L803-1 assume { :end_inline_reset_delta_events } true; 1039774#L1024-2 assume !false; 1078350#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1078345#L645 [2021-12-19 19:17:48,305 INFO L793 eck$LassoCheckResult]: Loop: 1078345#L645 assume !false; 1078343#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1078339#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1078340#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1083975#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1078330#L556 assume 0 != eval_~tmp~0#1; 1078331#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1083955#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1083949#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1071150#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1066116#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1066113#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1066114#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1071549#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1071547#L603 assume !(0 == ~t4_st~0); 1071541#L617 assume !(0 == ~t5_st~0); 1071539#L631 assume !(0 == ~t6_st~0); 1078345#L645 [2021-12-19 19:17:48,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:48,307 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2021-12-19 19:17:48,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:48,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658627448] [2021-12-19 19:17:48,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:48,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:48,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:48,314 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:48,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:48,329 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:48,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:48,330 INFO L85 PathProgramCache]: Analyzing trace with hash 2080854914, now seen corresponding path program 1 times [2021-12-19 19:17:48,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:48,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499006048] [2021-12-19 19:17:48,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:48,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:48,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:48,334 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:48,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:48,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:48,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:48,338 INFO L85 PathProgramCache]: Analyzing trace with hash 122288332, now seen corresponding path program 1 times [2021-12-19 19:17:48,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:48,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323692894] [2021-12-19 19:17:48,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:48,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:48,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:48,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:48,356 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:48,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323692894] [2021-12-19 19:17:48,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323692894] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:48,356 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:48,357 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:48,357 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131195857] [2021-12-19 19:17:48,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:48,495 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:48,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:48,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:48,495 INFO L87 Difference]: Start difference. First operand 121673 states and 163247 transitions. cyclomatic complexity: 41598 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:49,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:49,269 INFO L93 Difference]: Finished difference Result 140862 states and 187801 transitions. [2021-12-19 19:17:49,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:49,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140862 states and 187801 transitions. [2021-12-19 19:17:49,873 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 136234 [2021-12-19 19:17:50,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140862 states to 140862 states and 187801 transitions. [2021-12-19 19:17:50,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 140862 [2021-12-19 19:17:50,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 140862 [2021-12-19 19:17:50,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140862 states and 187801 transitions. [2021-12-19 19:17:50,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:50,415 INFO L681 BuchiCegarLoop]: Abstraction has 140862 states and 187801 transitions. [2021-12-19 19:17:50,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140862 states and 187801 transitions. [2021-12-19 19:17:51,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140862 to 136222. [2021-12-19 19:17:52,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136222 states, 136222 states have (on average 1.3389393783676646) internal successors, (182393), 136221 states have internal predecessors, (182393), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:52,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136222 states to 136222 states and 182393 transitions. [2021-12-19 19:17:52,705 INFO L704 BuchiCegarLoop]: Abstraction has 136222 states and 182393 transitions. [2021-12-19 19:17:52,705 INFO L587 BuchiCegarLoop]: Abstraction has 136222 states and 182393 transitions. [2021-12-19 19:17:52,705 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:17:52,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136222 states and 182393 transitions. [2021-12-19 19:17:53,064 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 131594 [2021-12-19 19:17:53,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:53,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:53,065 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,065 INFO L791 eck$LassoCheckResult]: Stem: 1302966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1302895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1302805#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1302190#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1302186#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1302187#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1302732#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1302924#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1302277#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1302278#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1302433#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1302296#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1302297#L670 assume !(0 == ~M_E~0); 1302694#L670-2 assume !(0 == ~T1_E~0); 1302630#L675-1 assume !(0 == ~T2_E~0); 1302631#L680-1 assume !(0 == ~T3_E~0); 1302731#L685-1 assume !(0 == ~T4_E~0); 1302698#L690-1 assume !(0 == ~T5_E~0); 1302699#L695-1 assume !(0 == ~T6_E~0); 1302782#L700-1 assume !(0 == ~E_1~0); 1302769#L705-1 assume !(0 == ~E_2~0); 1302770#L710-1 assume !(0 == ~E_3~0); 1302628#L715-1 assume !(0 == ~E_4~0); 1302545#L720-1 assume !(0 == ~E_5~0); 1302546#L725-1 assume !(0 == ~E_6~0); 1302604#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1302660#L320 assume !(1 == ~m_pc~0); 1302801#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1302475#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1302476#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1302434#L825 assume !(0 != activate_threads_~tmp~1#1); 1302435#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1302440#L339 assume !(1 == ~t1_pc~0); 1302441#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1302419#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1302420#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1302299#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1302300#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1302210#L358 assume !(1 == ~t2_pc~0); 1302211#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1302761#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1302696#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1302610#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1302429#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1302430#L377 assume !(1 == ~t3_pc~0); 1302714#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1302715#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1302708#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1302438#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1302439#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1302383#L396 assume !(1 == ~t4_pc~0); 1302384#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1302212#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1302213#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1302646#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1302353#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1302354#L415 assume !(1 == ~t5_pc~0); 1302421#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1302463#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1302661#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1302814#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1302255#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1302256#L434 assume !(1 == ~t6_pc~0); 1302580#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1302581#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1302748#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1302749#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1302451#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1302452#L743 assume !(1 == ~M_E~0); 1302344#L743-2 assume !(1 == ~T1_E~0); 1302345#L748-1 assume !(1 == ~T2_E~0); 1302653#L753-1 assume !(1 == ~T3_E~0); 1302654#L758-1 assume !(1 == ~T4_E~0); 1302785#L763-1 assume !(1 == ~T5_E~0); 1302843#L768-1 assume !(1 == ~T6_E~0); 1302445#L773-1 assume !(1 == ~E_1~0); 1302446#L778-1 assume !(1 == ~E_2~0); 1302426#L783-1 assume !(1 == ~E_3~0); 1302427#L788-1 assume !(1 == ~E_4~0); 1302729#L793-1 assume !(1 == ~E_5~0); 1302685#L798-1 assume !(1 == ~E_6~0); 1302315#L803-1 assume { :end_inline_reset_delta_events } true; 1302316#L1024-2 assume !false; 1334856#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1334852#L645 [2021-12-19 19:17:53,065 INFO L793 eck$LassoCheckResult]: Loop: 1334852#L645 assume !false; 1334842#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1334843#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1334833#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1334834#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1334825#L556 assume 0 != eval_~tmp~0#1; 1334826#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1334815#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1334816#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1334806#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1334808#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1334798#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1334800#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1334790#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1334791#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1334870#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1334872#L617 assume !(0 == ~t5_st~0); 1334855#L631 assume !(0 == ~t6_st~0); 1334852#L645 [2021-12-19 19:17:53,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,069 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2021-12-19 19:17:53,069 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642194234] [2021-12-19 19:17:53,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,077 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:53,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,096 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:53,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,097 INFO L85 PathProgramCache]: Analyzing trace with hash 75836122, now seen corresponding path program 1 times [2021-12-19 19:17:53,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635110899] [2021-12-19 19:17:53,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,098 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,101 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:53,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:53,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,106 INFO L85 PathProgramCache]: Analyzing trace with hash -510185776, now seen corresponding path program 1 times [2021-12-19 19:17:53,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100744518] [2021-12-19 19:17:53,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,106 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:53,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:53,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:53,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100744518] [2021-12-19 19:17:53,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100744518] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:53,128 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:53,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:53,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681415037] [2021-12-19 19:17:53,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:53,260 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:53,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:53,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:53,260 INFO L87 Difference]: Start difference. First operand 136222 states and 182393 transitions. cyclomatic complexity: 46195 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:53,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:53,915 INFO L93 Difference]: Finished difference Result 244881 states and 326876 transitions. [2021-12-19 19:17:53,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:53,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244881 states and 326876 transitions. [2021-12-19 19:17:55,390 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 237471 [2021-12-19 19:17:56,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244881 states to 244881 states and 326876 transitions. [2021-12-19 19:17:56,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 244881 [2021-12-19 19:17:56,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 244881 [2021-12-19 19:17:56,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 244881 states and 326876 transitions. [2021-12-19 19:17:56,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:56,717 INFO L681 BuchiCegarLoop]: Abstraction has 244881 states and 326876 transitions. [2021-12-19 19:17:56,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244881 states and 326876 transitions. [2021-12-19 19:17:58,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244881 to 240821. [2021-12-19 19:17:58,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 240821 states, 240821 states have (on average 1.336868462467974) internal successors, (321946), 240820 states have internal predecessors, (321946), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:59,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240821 states to 240821 states and 321946 transitions. [2021-12-19 19:17:59,297 INFO L704 BuchiCegarLoop]: Abstraction has 240821 states and 321946 transitions. [2021-12-19 19:17:59,297 INFO L587 BuchiCegarLoop]: Abstraction has 240821 states and 321946 transitions. [2021-12-19 19:17:59,297 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:17:59,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 240821 states and 321946 transitions. [2021-12-19 19:18:00,543 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 233411 [2021-12-19 19:18:00,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:00,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:00,544 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,544 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,544 INFO L791 eck$LassoCheckResult]: Stem: 1684131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1684042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1683949#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1683301#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1683297#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1683298#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1683872#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1684080#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1683390#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1683391#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1683551#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1683409#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1683410#L670 assume !(0 == ~M_E~0); 1683829#L670-2 assume !(0 == ~T1_E~0); 1683758#L675-1 assume !(0 == ~T2_E~0); 1683759#L680-1 assume !(0 == ~T3_E~0); 1683869#L685-1 assume !(0 == ~T4_E~0); 1683834#L690-1 assume !(0 == ~T5_E~0); 1683835#L695-1 assume !(0 == ~T6_E~0); 1683924#L700-1 assume !(0 == ~E_1~0); 1683912#L705-1 assume !(0 == ~E_2~0); 1683913#L710-1 assume !(0 == ~E_3~0); 1683757#L715-1 assume !(0 == ~E_4~0); 1683666#L720-1 assume !(0 == ~E_5~0); 1683667#L725-1 assume !(0 == ~E_6~0); 1683732#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1683792#L320 assume !(1 == ~m_pc~0); 1683946#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1683593#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1683594#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1683552#L825 assume !(0 != activate_threads_~tmp~1#1); 1683553#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1683559#L339 assume !(1 == ~t1_pc~0); 1683560#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1683535#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1683536#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1683411#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1683412#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1683321#L358 assume !(1 == ~t2_pc~0); 1683322#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1683902#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1683831#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1683739#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1683549#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1683550#L377 assume !(1 == ~t3_pc~0); 1683849#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1683850#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1683848#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1683556#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1683557#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1683502#L396 assume !(1 == ~t4_pc~0); 1683503#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1683323#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1683324#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1683776#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1683467#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1683468#L415 assume !(1 == ~t5_pc~0); 1683538#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1683580#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1683793#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1683956#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1683365#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1683366#L434 assume !(1 == ~t6_pc~0); 1683705#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1683706#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1683886#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1683887#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1683567#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1683568#L743 assume !(1 == ~M_E~0); 1683456#L743-2 assume !(1 == ~T1_E~0); 1683457#L748-1 assume !(1 == ~T2_E~0); 1683783#L753-1 assume !(1 == ~T3_E~0); 1683784#L758-1 assume !(1 == ~T4_E~0); 1683927#L763-1 assume !(1 == ~T5_E~0); 1683994#L768-1 assume !(1 == ~T6_E~0); 1683565#L773-1 assume !(1 == ~E_1~0); 1683566#L778-1 assume !(1 == ~E_2~0); 1683543#L783-1 assume !(1 == ~E_3~0); 1683544#L788-1 assume !(1 == ~E_4~0); 1683867#L793-1 assume !(1 == ~E_5~0); 1683818#L798-1 assume !(1 == ~E_6~0); 1683430#L803-1 assume { :end_inline_reset_delta_events } true; 1683431#L1024-2 assume !false; 1743577#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1743572#L645 [2021-12-19 19:18:00,545 INFO L793 eck$LassoCheckResult]: Loop: 1743572#L645 assume !false; 1743570#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1743567#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1743565#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1743563#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1743561#L556 assume 0 != eval_~tmp~0#1; 1743558#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1743555#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1743553#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1743551#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1743549#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1743547#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1743545#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1743518#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1743543#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1746803#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1746800#L617 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1731182#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1731184#L631 assume !(0 == ~t6_st~0); 1743572#L645 [2021-12-19 19:18:00,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,545 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2021-12-19 19:18:00,545 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447631016] [2021-12-19 19:18:00,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,546 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,550 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:00,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,562 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:00,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1944239452, now seen corresponding path program 1 times [2021-12-19 19:18:00,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528839116] [2021-12-19 19:18:00,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,565 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:00,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,567 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:00,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,568 INFO L85 PathProgramCache]: Analyzing trace with hash 1363918190, now seen corresponding path program 1 times [2021-12-19 19:18:00,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837150051] [2021-12-19 19:18:00,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:00,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:00,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:00,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837150051] [2021-12-19 19:18:00,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837150051] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:00,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:00,584 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:18:00,584 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818296287] [2021-12-19 19:18:00,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:00,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:00,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:00,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:00,729 INFO L87 Difference]: Start difference. First operand 240821 states and 321946 transitions. cyclomatic complexity: 81149 Second operand has 3 states, 2 states have (on average 51.5) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:02,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:02,359 INFO L93 Difference]: Finished difference Result 435844 states and 578690 transitions. [2021-12-19 19:18:02,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:02,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435844 states and 578690 transitions. [2021-12-19 19:18:04,838 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 421110 [2021-12-19 19:18:05,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435844 states to 435844 states and 578690 transitions. [2021-12-19 19:18:05,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435844 [2021-12-19 19:18:05,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435844 [2021-12-19 19:18:05,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435844 states and 578690 transitions. [2021-12-19 19:18:06,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:06,457 INFO L681 BuchiCegarLoop]: Abstraction has 435844 states and 578690 transitions. [2021-12-19 19:18:06,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435844 states and 578690 transitions.