./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:26,738 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:26,739 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:26,767 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:26,767 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:26,770 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:26,772 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:26,777 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:26,779 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:26,783 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:26,784 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:26,785 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:26,785 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:26,787 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:26,789 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:26,793 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:26,794 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:26,794 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:26,798 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:26,801 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:26,803 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:26,804 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:26,805 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:26,806 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:26,809 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:26,809 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:26,809 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:26,811 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:26,811 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:26,812 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:26,812 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:26,813 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:26,814 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:26,815 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:26,816 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:26,816 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:26,816 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:26,816 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:26,817 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:26,817 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:26,817 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:26,818 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:26,855 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:26,855 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:26,856 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:26,856 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:26,857 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:26,857 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:26,857 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:26,857 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:26,857 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:26,858 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:26,858 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:26,858 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:26,858 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:26,859 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:26,859 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:26,859 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:26,859 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:26,859 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:26,859 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:26,860 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:26,860 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:26,860 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:26,860 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:26,860 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:26,861 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:26,861 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:26,861 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:26,862 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:26,862 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:26,862 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:26,862 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:26,862 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:26,863 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:26,863 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2021-12-19 19:17:27,019 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:27,031 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:27,033 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:27,034 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:27,034 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:27,035 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.07.cil.c [2021-12-19 19:17:27,111 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d910d182/339b05fe02dc49b3adbc62fb552d8533/FLAG11a3ad6de [2021-12-19 19:17:27,458 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:27,458 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c [2021-12-19 19:17:27,473 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d910d182/339b05fe02dc49b3adbc62fb552d8533/FLAG11a3ad6de [2021-12-19 19:17:27,481 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d910d182/339b05fe02dc49b3adbc62fb552d8533 [2021-12-19 19:17:27,483 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:27,485 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:27,487 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:27,487 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:27,489 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:27,489 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,490 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6f48e5d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27, skipping insertion in model container [2021-12-19 19:17:27,490 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,515 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:27,558 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:27,700 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2021-12-19 19:17:27,768 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:27,783 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:27,795 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2021-12-19 19:17:27,835 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:27,849 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:27,851 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27 WrapperNode [2021-12-19 19:17:27,851 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:27,852 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:27,852 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:27,852 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:27,857 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,875 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,944 INFO L137 Inliner]: procedures = 42, calls = 51, calls flagged for inlining = 46, calls inlined = 124, statements flattened = 1845 [2021-12-19 19:17:27,945 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:27,946 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:27,946 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:27,946 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:27,952 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,952 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,956 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,959 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:27,974 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:28,011 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:28,014 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:28,034 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:28,035 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:28,035 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:28,035 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:28,039 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (1/1) ... [2021-12-19 19:17:28,043 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:28,052 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:28,069 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:28,094 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:28,118 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:28,119 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:28,119 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:28,119 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:28,182 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:28,183 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:28,999 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:29,012 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:29,013 INFO L301 CfgBuilder]: Removed 11 assume(true) statements. [2021-12-19 19:17:29,015 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:29 BoogieIcfgContainer [2021-12-19 19:17:29,015 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:29,016 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:29,016 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:29,020 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:29,020 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:29,021 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:27" (1/3) ... [2021-12-19 19:17:29,021 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7de727a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:29, skipping insertion in model container [2021-12-19 19:17:29,021 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:29,022 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:27" (2/3) ... [2021-12-19 19:17:29,022 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7de727a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:29, skipping insertion in model container [2021-12-19 19:17:29,022 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:29,022 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:29" (3/3) ... [2021-12-19 19:17:29,023 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2021-12-19 19:17:29,070 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:29,071 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:29,071 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:29,071 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:29,071 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:29,071 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:29,071 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:29,071 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:29,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2021-12-19 19:17:29,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,157 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,158 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,158 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:29,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2021-12-19 19:17:29,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,187 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,187 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,193 INFO L791 eck$LassoCheckResult]: Stem: 386#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 711#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 717#L1111true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453#L514true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 641#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 606#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 635#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 192#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 552#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 238#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 142#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 599#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 125#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683#L754true assume !(0 == ~M_E~0); 728#L754-2true assume !(0 == ~T1_E~0); 512#L759-1true assume !(0 == ~T2_E~0); 380#L764-1true assume !(0 == ~T3_E~0); 342#L769-1true assume !(0 == ~T4_E~0); 381#L774-1true assume !(0 == ~T5_E~0); 625#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 524#L784-1true assume !(0 == ~T7_E~0); 340#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 755#L799-1true assume !(0 == ~E_3~0); 349#L804-1true assume !(0 == ~E_4~0); 377#L809-1true assume !(0 == ~E_5~0); 553#L814-1true assume !(0 == ~E_6~0); 11#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 170#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141#L361true assume 1 == ~m_pc~0; 666#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 708#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77#L373true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 624#L930true assume !(0 != activate_threads_~tmp~1#1); 269#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137#L380true assume !(1 == ~t1_pc~0); 756#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 636#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325#L392true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 760#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 462#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 440#L399true assume 1 == ~t2_pc~0; 628#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 645#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344#L411true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174#L946true assume !(0 != activate_threads_~tmp___1~0#1); 416#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L418true assume !(1 == ~t3_pc~0); 692#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 555#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 696#L430true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768#L954true assume !(0 != activate_threads_~tmp___2~0#1); 364#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 685#L437true assume 1 == ~t4_pc~0; 747#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 495#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441#L449true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204#L962true assume !(0 != activate_threads_~tmp___3~0#1); 591#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 333#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 673#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274#L468true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 412#L970true assume !(0 != activate_threads_~tmp___4~0#1); 726#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694#L487true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 403#L978true assume !(0 != activate_threads_~tmp___5~0#1); 355#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 551#L494true assume 1 == ~t7_pc~0; 301#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 315#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265#L506true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 383#L986true assume !(0 != activate_threads_~tmp___6~0#1); 752#L986-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L837true assume !(1 == ~M_E~0); 571#L837-2true assume !(1 == ~T1_E~0); 435#L842-1true assume !(1 == ~T2_E~0); 212#L847-1true assume !(1 == ~T3_E~0); 262#L852-1true assume !(1 == ~T4_E~0); 772#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 179#L862-1true assume !(1 == ~T6_E~0); 188#L867-1true assume !(1 == ~T7_E~0); 237#L872-1true assume !(1 == ~E_1~0); 394#L877-1true assume !(1 == ~E_2~0); 581#L882-1true assume !(1 == ~E_3~0); 703#L887-1true assume !(1 == ~E_4~0); 456#L892-1true assume !(1 == ~E_5~0); 651#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 197#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 229#L1148-2true [2021-12-19 19:17:29,199 INFO L793 eck$LassoCheckResult]: Loop: 229#L1148-2true assume !false; 12#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112#L729true assume !true; 214#L744true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 215#L514-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 18#L754-5true assume !(0 == ~T1_E~0); 534#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 224#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 609#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 365#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 93#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 16#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 765#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 13#L794-3true assume !(0 == ~E_2~0); 35#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 154#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 291#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 34#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 529#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234#L361-24true assume 1 == ~m_pc~0; 85#L362-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 300#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406#L373-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 556#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 618#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253#L392-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508#L399-24true assume 1 == ~t2_pc~0; 741#L400-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49#L411-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 146#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 616#L418-24true assume !(1 == ~t3_pc~0); 33#L418-26true is_transmit3_triggered_~__retres1~3#1 := 0; 183#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147#L430-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 414#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560#L437-24true assume !(1 == ~t4_pc~0); 775#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 733#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 457#L449-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 354#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 637#L456-24true assume 1 == ~t5_pc~0; 329#L457-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 304#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110#L468-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 576#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 759#L475-24true assume !(1 == ~t6_pc~0); 586#L475-26true is_transmit6_triggered_~__retres1~6#1 := 0; 313#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 670#L487-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 7#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 308#L494-24true assume 1 == ~t7_pc~0; 246#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 173#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 532#L506-8true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 519#L837-3true assume !(1 == ~M_E~0); 661#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 267#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 603#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 409#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 312#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 739#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 699#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 245#L872-3true assume !(1 == ~E_1~0); 303#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 721#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 358#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 106#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 518#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 763#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 194#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 583#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 382#L612-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 679#L1167true assume !(0 == start_simulation_~tmp~3#1); 232#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 738#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 674#L612-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 306#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8#L1130true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 124#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 229#L1148-2true [2021-12-19 19:17:29,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,210 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2021-12-19 19:17:29,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565150319] [2021-12-19 19:17:29,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565150319] [2021-12-19 19:17:29,425 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565150319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,425 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,425 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:29,427 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738954625] [2021-12-19 19:17:29,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:29,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1169217165, now seen corresponding path program 1 times [2021-12-19 19:17:29,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681499115] [2021-12-19 19:17:29,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681499115] [2021-12-19 19:17:29,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681499115] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,478 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:29,478 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545693289] [2021-12-19 19:17:29,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,479 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:29,479 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:29,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:29,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:29,531 INFO L87 Difference]: Start difference. First operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,608 INFO L93 Difference]: Finished difference Result 774 states and 1154 transitions. [2021-12-19 19:17:29,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:29,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1154 transitions. [2021-12-19 19:17:29,623 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:29,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 768 states and 1148 transitions. [2021-12-19 19:17:29,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:29,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:29,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1148 transitions. [2021-12-19 19:17:29,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,639 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-19 19:17:29,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1148 transitions. [2021-12-19 19:17:29,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:29,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1148 transitions. [2021-12-19 19:17:29,691 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-19 19:17:29,691 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-19 19:17:29,691 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:29,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1148 transitions. [2021-12-19 19:17:29,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:29,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,701 INFO L791 eck$LassoCheckResult]: Stem: 2325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2305#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1765#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1766#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2182#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2183#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2151#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2074#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2075#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2064#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2065#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2024#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2025#L754 assume !(0 == ~M_E~0); 2283#L754-2 assume !(0 == ~T1_E~0); 1967#L759-1 assume !(0 == ~T2_E~0); 1968#L764-1 assume !(0 == ~T3_E~0); 2312#L769-1 assume !(0 == ~T4_E~0); 2313#L774-1 assume !(0 == ~T5_E~0); 2213#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1998#L784-1 assume !(0 == ~T7_E~0); 1999#L789-1 assume !(0 == ~E_1~0); 1678#L794-1 assume !(0 == ~E_2~0); 1679#L799-1 assume !(0 == ~E_3~0); 2314#L804-1 assume !(0 == ~E_4~0); 2315#L809-1 assume !(0 == ~E_5~0); 2078#L814-1 assume !(0 == ~E_6~0); 1594#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1595#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2060#L361 assume 1 == ~m_pc~0; 2061#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2102#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1883#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1884#L930 assume !(0 != activate_threads_~tmp~1#1); 2208#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054#L380 assume !(1 == ~t1_pc~0); 1728#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2233#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2308#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1804#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1729#L399 assume 1 == ~t2_pc~0; 1730#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1936#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2243#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2122#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1634#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602#L418 assume !(1 == ~t3_pc~0); 1563#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1564#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2082#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2290#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2320#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2285#L437 assume 1 == ~t4_pc~0; 2286#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1904#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1732#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1733#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2161#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1860#L456 assume !(1 == ~t5_pc~0); 1861#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1964#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2264#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1624#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1625#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1748#L475 assume 1 == ~t6_pc~0; 1749#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1824#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1825#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1584#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1585#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2067#L494 assume 1 == ~t7_pc~0; 2068#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2108#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2260#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2261#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2323#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L837 assume !(1 == ~M_E~0); 2125#L837-2 assume !(1 == ~T1_E~0); 1711#L842-1 assume !(1 == ~T2_E~0); 1712#L847-1 assume !(1 == ~T3_E~0); 2178#L852-1 assume !(1 == ~T4_E~0); 2255#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2134#L862-1 assume !(1 == ~T6_E~0); 2135#L867-1 assume !(1 == ~T7_E~0); 2144#L872-1 assume !(1 == ~E_1~0); 2210#L877-1 assume !(1 == ~E_2~0); 2140#L882-1 assume !(1 == ~E_3~0); 2141#L887-1 assume !(1 == ~E_4~0); 1771#L892-1 assume !(1 == ~E_5~0); 1772#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2158#L902-1 assume !(1 == ~E_7~0); 1852#L907-1 assume { :end_inline_reset_delta_events } true; 1853#L1148-2 [2021-12-19 19:17:29,702 INFO L793 eck$LassoCheckResult]: Loop: 1853#L1148-2 assume !false; 1596#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1597#L729 assume !false; 1995#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1991#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2011#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2049#L626 assume !(0 != eval_~tmp~0#1); 2050#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2180#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2084#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1637#L754-5 assume !(0 == ~T1_E~0); 1638#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2020#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2188#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2189#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1952#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1613#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1614#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1598#L794-3 assume !(0 == ~E_2~0); 1599#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1693#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2090#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1686#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1687#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1886#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1887#L361-24 assume 1 == ~m_pc~0; 1923#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1924#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1607#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2083#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2147#L380-24 assume 1 == ~t1_pc~0; 2148#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1774#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2206#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2079#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1734#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1735#L399-24 assume 1 == ~t2_pc~0; 1947#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1997#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1775#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1776#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L418-24 assume !(1 == ~t3_pc~0); 1682#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1683#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2073#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1951#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1626#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L437-24 assume 1 == ~t4_pc~0; 1898#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1899#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1778#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1926#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2235#L456-24 assume 1 == ~t5_pc~0; 2236#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2296#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1989#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2129#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2263#L475-24 assume 1 == ~t6_pc~0; 1628#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1629#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2272#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2273#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1571#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1572#L494-24 assume 1 == ~t7_pc~0; 2229#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2016#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2017#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L837-3 assume !(1 == ~M_E~0); 1979#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2259#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2175#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1615#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1616#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2300#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2292#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2226#L872-3 assume !(1 == ~E_1~0); 2227#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2295#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2310#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1982#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1975#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1976#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2152#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2145#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1601#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2321#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2281#L1167 assume !(0 == start_simulation_~tmp~3#1); 2176#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2203#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2008#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2242#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2275#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2190#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1577#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1578#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1853#L1148-2 [2021-12-19 19:17:29,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,702 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2021-12-19 19:17:29,703 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290514917] [2021-12-19 19:17:29,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,756 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290514917] [2021-12-19 19:17:29,757 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290514917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,757 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,757 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:29,757 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649844945] [2021-12-19 19:17:29,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,757 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:29,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 1 times [2021-12-19 19:17:29,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998545218] [2021-12-19 19:17:29,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:29,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:29,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:29,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998545218] [2021-12-19 19:17:29,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998545218] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:29,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:29,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:29,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1670171990] [2021-12-19 19:17:29,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:29,895 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:29,896 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:29,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:29,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:29,896 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:29,927 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2021-12-19 19:17:29,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:29,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1147 transitions. [2021-12-19 19:17:29,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:29,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1147 transitions. [2021-12-19 19:17:29,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:29,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:29,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1147 transitions. [2021-12-19 19:17:29,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:29,938 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-19 19:17:29,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1147 transitions. [2021-12-19 19:17:29,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:29,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:29,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1147 transitions. [2021-12-19 19:17:29,947 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-19 19:17:29,948 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-19 19:17:29,948 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:29,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1147 transitions. [2021-12-19 19:17:29,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:29,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:29,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:29,953 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,953 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:29,954 INFO L791 eck$LassoCheckResult]: Stem: 3868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3847#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3308#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3309#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3725#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3726#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3694#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3614#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3615#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3607#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3608#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3567#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3568#L754 assume !(0 == ~M_E~0); 3826#L754-2 assume !(0 == ~T1_E~0); 3510#L759-1 assume !(0 == ~T2_E~0); 3511#L764-1 assume !(0 == ~T3_E~0); 3855#L769-1 assume !(0 == ~T4_E~0); 3856#L774-1 assume !(0 == ~T5_E~0); 3754#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3541#L784-1 assume !(0 == ~T7_E~0); 3542#L789-1 assume !(0 == ~E_1~0); 3217#L794-1 assume !(0 == ~E_2~0); 3218#L799-1 assume !(0 == ~E_3~0); 3857#L804-1 assume !(0 == ~E_4~0); 3858#L809-1 assume !(0 == ~E_5~0); 3619#L814-1 assume !(0 == ~E_6~0); 3137#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3138#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3603#L361 assume 1 == ~m_pc~0; 3604#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3645#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3426#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3427#L930 assume !(0 != activate_threads_~tmp~1#1); 3751#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3597#L380 assume !(1 == ~t1_pc~0); 3271#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3270#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3774#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3851#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3347#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3272#L399 assume 1 == ~t2_pc~0; 3273#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3479#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3786#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3665#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3177#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3145#L418 assume !(1 == ~t3_pc~0); 3106#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3107#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3625#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3833#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3863#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3827#L437 assume 1 == ~t4_pc~0; 3828#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3447#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3275#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3276#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3704#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3398#L456 assume !(1 == ~t5_pc~0); 3399#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3507#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3807#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3164#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3165#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3288#L475 assume 1 == ~t6_pc~0; 3289#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3367#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3368#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3127#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3128#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3610#L494 assume 1 == ~t7_pc~0; 3611#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3651#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3801#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3802#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3866#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3803#L837 assume !(1 == ~M_E~0); 3668#L837-2 assume !(1 == ~T1_E~0); 3254#L842-1 assume !(1 == ~T2_E~0); 3255#L847-1 assume !(1 == ~T3_E~0); 3721#L852-1 assume !(1 == ~T4_E~0); 3796#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3676#L862-1 assume !(1 == ~T6_E~0); 3677#L867-1 assume !(1 == ~T7_E~0); 3685#L872-1 assume !(1 == ~E_1~0); 3753#L877-1 assume !(1 == ~E_2~0); 3683#L882-1 assume !(1 == ~E_3~0); 3684#L887-1 assume !(1 == ~E_4~0); 3314#L892-1 assume !(1 == ~E_5~0); 3315#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3699#L902-1 assume !(1 == ~E_7~0); 3395#L907-1 assume { :end_inline_reset_delta_events } true; 3396#L1148-2 [2021-12-19 19:17:29,954 INFO L793 eck$LassoCheckResult]: Loop: 3396#L1148-2 assume !false; 3139#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3140#L729 assume !false; 3538#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3534#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3485#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3554#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3591#L626 assume !(0 != eval_~tmp~0#1); 3592#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3722#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3627#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3178#L754-5 assume !(0 == ~T1_E~0); 3179#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3563#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3732#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3490#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3154#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3155#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3141#L794-3 assume !(0 == ~E_2~0); 3142#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3236#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3633#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3231#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3232#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3429#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3430#L361-24 assume 1 == ~m_pc~0; 3466#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3467#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3149#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3150#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3626#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3690#L380-24 assume !(1 == ~t1_pc~0); 3316#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 3317#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3749#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3622#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3277#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3278#L399-24 assume 1 == ~t2_pc~0; 3491#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3540#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3319#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3616#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3617#L418-24 assume 1 == ~t3_pc~0; 3620#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3226#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3618#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3495#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3169#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3170#L437-24 assume 1 == ~t4_pc~0; 3441#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3442#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3321#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3469#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3778#L456-24 assume 1 == ~t5_pc~0; 3779#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3839#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3532#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3533#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3674#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3806#L475-24 assume 1 == ~t6_pc~0; 3171#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3172#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3815#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3816#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 3114#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3115#L494-24 assume !(1 == ~t7_pc~0); 3682#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3663#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3559#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3560#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3439#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3440#L837-3 assume !(1 == ~M_E~0); 3522#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3805#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3719#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3158#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3159#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3843#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3835#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3770#L872-3 assume !(1 == ~E_1~0); 3771#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3838#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3853#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3527#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3520#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3521#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3695#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3688#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3144#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3864#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3824#L1167 assume !(0 == start_simulation_~tmp~3#1); 3718#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3746#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3552#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3785#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3818#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3733#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3120#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3121#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3396#L1148-2 [2021-12-19 19:17:29,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:29,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2021-12-19 19:17:29,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:29,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793603430] [2021-12-19 19:17:29,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:29,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:29,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,015 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,015 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793603430] [2021-12-19 19:17:30,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793603430] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554291616] [2021-12-19 19:17:30,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,017 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 1 times [2021-12-19 19:17:30,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017227634] [2021-12-19 19:17:30,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,108 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017227634] [2021-12-19 19:17:30,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017227634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206288414] [2021-12-19 19:17:30,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,111 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,111 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,112 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,126 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2021-12-19 19:17:30,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1146 transitions. [2021-12-19 19:17:30,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1146 transitions. [2021-12-19 19:17:30,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:30,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:30,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1146 transitions. [2021-12-19 19:17:30,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,138 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-19 19:17:30,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1146 transitions. [2021-12-19 19:17:30,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:30,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1146 transitions. [2021-12-19 19:17:30,148 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-19 19:17:30,148 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-19 19:17:30,148 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:30,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1146 transitions. [2021-12-19 19:17:30,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,156 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,157 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,157 INFO L791 eck$LassoCheckResult]: Stem: 5411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5391#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4851#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4852#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5268#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5269#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5237#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5160#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5161#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5150#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5151#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5110#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5111#L754 assume !(0 == ~M_E~0); 5369#L754-2 assume !(0 == ~T1_E~0); 5053#L759-1 assume !(0 == ~T2_E~0); 5054#L764-1 assume !(0 == ~T3_E~0); 5398#L769-1 assume !(0 == ~T4_E~0); 5399#L774-1 assume !(0 == ~T5_E~0); 5299#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5084#L784-1 assume !(0 == ~T7_E~0); 5085#L789-1 assume !(0 == ~E_1~0); 4764#L794-1 assume !(0 == ~E_2~0); 4765#L799-1 assume !(0 == ~E_3~0); 5400#L804-1 assume !(0 == ~E_4~0); 5401#L809-1 assume !(0 == ~E_5~0); 5164#L814-1 assume !(0 == ~E_6~0); 4680#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4681#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5146#L361 assume 1 == ~m_pc~0; 5147#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5188#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4969#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4970#L930 assume !(0 != activate_threads_~tmp~1#1); 5294#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5140#L380 assume !(1 == ~t1_pc~0); 4814#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4813#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5319#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5394#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4890#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4815#L399 assume 1 == ~t2_pc~0; 4816#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5022#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5329#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5208#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4720#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4688#L418 assume !(1 == ~t3_pc~0); 4649#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5168#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5376#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5406#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5371#L437 assume 1 == ~t4_pc~0; 5372#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4991#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4818#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4819#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5247#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4946#L456 assume !(1 == ~t5_pc~0); 4947#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5050#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5350#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4710#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4711#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4834#L475 assume 1 == ~t6_pc~0; 4835#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4910#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4911#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4670#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4671#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5153#L494 assume 1 == ~t7_pc~0; 5154#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5194#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5346#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5347#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5409#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5348#L837 assume !(1 == ~M_E~0); 5211#L837-2 assume !(1 == ~T1_E~0); 4797#L842-1 assume !(1 == ~T2_E~0); 4798#L847-1 assume !(1 == ~T3_E~0); 5264#L852-1 assume !(1 == ~T4_E~0); 5341#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5220#L862-1 assume !(1 == ~T6_E~0); 5221#L867-1 assume !(1 == ~T7_E~0); 5230#L872-1 assume !(1 == ~E_1~0); 5296#L877-1 assume !(1 == ~E_2~0); 5226#L882-1 assume !(1 == ~E_3~0); 5227#L887-1 assume !(1 == ~E_4~0); 4857#L892-1 assume !(1 == ~E_5~0); 4858#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5244#L902-1 assume !(1 == ~E_7~0); 4938#L907-1 assume { :end_inline_reset_delta_events } true; 4939#L1148-2 [2021-12-19 19:17:30,157 INFO L793 eck$LassoCheckResult]: Loop: 4939#L1148-2 assume !false; 4682#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4683#L729 assume !false; 5081#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5077#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5028#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5097#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5135#L626 assume !(0 != eval_~tmp~0#1); 5136#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5266#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5170#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume !(0 == ~T1_E~0); 4724#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5274#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5038#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4699#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4700#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4684#L794-3 assume !(0 == ~E_2~0); 4685#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4776#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5176#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4772#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4773#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4972#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4973#L361-24 assume 1 == ~m_pc~0; 5009#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5010#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4692#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4693#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5169#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5233#L380-24 assume 1 == ~t1_pc~0; 5234#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4860#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5292#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5165#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4820#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4821#L399-24 assume 1 == ~t2_pc~0; 5033#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5083#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5157#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5158#L418-24 assume !(1 == ~t3_pc~0); 4768#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4769#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5159#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5037#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4712#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4713#L437-24 assume 1 == ~t4_pc~0; 4984#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4985#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4863#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4864#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5012#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5321#L456-24 assume 1 == ~t5_pc~0; 5322#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5382#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5075#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5076#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5215#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5349#L475-24 assume 1 == ~t6_pc~0; 4714#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4715#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5358#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5359#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4657#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L494-24 assume 1 == ~t7_pc~0; 5315#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5205#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5102#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5103#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4982#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4983#L837-3 assume !(1 == ~M_E~0); 5065#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5345#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5261#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4701#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4702#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5386#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5378#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5312#L872-3 assume !(1 == ~E_1~0); 5313#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5381#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5396#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5068#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5061#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5062#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5238#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5231#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4687#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5407#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5367#L1167 assume !(0 == start_simulation_~tmp~3#1); 5262#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5289#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5094#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5328#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5361#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5276#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4664#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4939#L1148-2 [2021-12-19 19:17:30,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,158 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2021-12-19 19:17:30,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874640542] [2021-12-19 19:17:30,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874640542] [2021-12-19 19:17:30,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874640542] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,202 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,202 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259290020] [2021-12-19 19:17:30,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,203 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 2 times [2021-12-19 19:17:30,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629565529] [2021-12-19 19:17:30,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,240 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629565529] [2021-12-19 19:17:30,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629565529] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,240 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,240 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,240 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843748615] [2021-12-19 19:17:30,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,241 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,241 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,242 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,251 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2021-12-19 19:17:30,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1145 transitions. [2021-12-19 19:17:30,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1145 transitions. [2021-12-19 19:17:30,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:30,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:30,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1145 transitions. [2021-12-19 19:17:30,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,260 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-19 19:17:30,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1145 transitions. [2021-12-19 19:17:30,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:30,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1145 transitions. [2021-12-19 19:17:30,267 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-19 19:17:30,267 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-19 19:17:30,268 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:30,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1145 transitions. [2021-12-19 19:17:30,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,271 INFO L791 eck$LassoCheckResult]: Stem: 6954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6933#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6394#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6395#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 6811#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6812#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6780#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6700#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6701#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6693#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6694#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6653#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6654#L754 assume !(0 == ~M_E~0); 6912#L754-2 assume !(0 == ~T1_E~0); 6596#L759-1 assume !(0 == ~T2_E~0); 6597#L764-1 assume !(0 == ~T3_E~0); 6941#L769-1 assume !(0 == ~T4_E~0); 6942#L774-1 assume !(0 == ~T5_E~0); 6840#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6627#L784-1 assume !(0 == ~T7_E~0); 6628#L789-1 assume !(0 == ~E_1~0); 6303#L794-1 assume !(0 == ~E_2~0); 6304#L799-1 assume !(0 == ~E_3~0); 6943#L804-1 assume !(0 == ~E_4~0); 6944#L809-1 assume !(0 == ~E_5~0); 6705#L814-1 assume !(0 == ~E_6~0); 6223#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6224#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6689#L361 assume 1 == ~m_pc~0; 6690#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6731#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6512#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6513#L930 assume !(0 != activate_threads_~tmp~1#1); 6837#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6683#L380 assume !(1 == ~t1_pc~0); 6357#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6356#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6860#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6937#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6433#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6358#L399 assume 1 == ~t2_pc~0; 6359#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6565#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6872#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6751#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6263#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6231#L418 assume !(1 == ~t3_pc~0); 6192#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6193#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6711#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6919#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6949#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6913#L437 assume 1 == ~t4_pc~0; 6914#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6533#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6361#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6362#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6790#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6484#L456 assume !(1 == ~t5_pc~0); 6485#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6593#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6893#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6250#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6251#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6374#L475 assume 1 == ~t6_pc~0; 6375#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6453#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6454#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6213#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6214#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L494 assume 1 == ~t7_pc~0; 6697#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6737#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6887#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6888#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6952#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6889#L837 assume !(1 == ~M_E~0); 6754#L837-2 assume !(1 == ~T1_E~0); 6340#L842-1 assume !(1 == ~T2_E~0); 6341#L847-1 assume !(1 == ~T3_E~0); 6807#L852-1 assume !(1 == ~T4_E~0); 6882#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6762#L862-1 assume !(1 == ~T6_E~0); 6763#L867-1 assume !(1 == ~T7_E~0); 6771#L872-1 assume !(1 == ~E_1~0); 6839#L877-1 assume !(1 == ~E_2~0); 6769#L882-1 assume !(1 == ~E_3~0); 6770#L887-1 assume !(1 == ~E_4~0); 6400#L892-1 assume !(1 == ~E_5~0); 6401#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6785#L902-1 assume !(1 == ~E_7~0); 6481#L907-1 assume { :end_inline_reset_delta_events } true; 6482#L1148-2 [2021-12-19 19:17:30,272 INFO L793 eck$LassoCheckResult]: Loop: 6482#L1148-2 assume !false; 6225#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6226#L729 assume !false; 6624#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6620#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6571#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6640#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6677#L626 assume !(0 != eval_~tmp~0#1); 6678#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6808#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6713#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6264#L754-5 assume !(0 == ~T1_E~0); 6265#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6649#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6817#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6818#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6576#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6242#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6243#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6227#L794-3 assume !(0 == ~E_2~0); 6228#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6322#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6719#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6317#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6318#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6515#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6516#L361-24 assume 1 == ~m_pc~0; 6552#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6553#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6235#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6236#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6712#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6776#L380-24 assume !(1 == ~t1_pc~0); 6402#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6403#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6835#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6708#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6363#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6364#L399-24 assume 1 == ~t2_pc~0; 6577#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6626#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6404#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6405#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6702#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6703#L418-24 assume 1 == ~t3_pc~0; 6706#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6312#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6704#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6581#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6255#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6256#L437-24 assume !(1 == ~t4_pc~0); 6529#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 6528#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6406#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6407#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6555#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6864#L456-24 assume 1 == ~t5_pc~0; 6865#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6925#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6618#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6619#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6760#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6892#L475-24 assume 1 == ~t6_pc~0; 6257#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6258#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6901#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6902#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 6200#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6201#L494-24 assume !(1 == ~t7_pc~0); 6768#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6749#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6645#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6646#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6525#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6526#L837-3 assume !(1 == ~M_E~0); 6608#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6891#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6805#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6244#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6245#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6929#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6921#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6856#L872-3 assume !(1 == ~E_1~0); 6857#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6924#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6939#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6613#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6607#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6781#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6774#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6230#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6950#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6910#L1167 assume !(0 == start_simulation_~tmp~3#1); 6804#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6832#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6638#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6871#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6904#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6819#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6206#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6207#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6482#L1148-2 [2021-12-19 19:17:30,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2021-12-19 19:17:30,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666466259] [2021-12-19 19:17:30,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666466259] [2021-12-19 19:17:30,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666466259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,295 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380827628] [2021-12-19 19:17:30,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,295 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,295 INFO L85 PathProgramCache]: Analyzing trace with hash 859459238, now seen corresponding path program 1 times [2021-12-19 19:17:30,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976362769] [2021-12-19 19:17:30,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,296 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,337 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976362769] [2021-12-19 19:17:30,337 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976362769] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,337 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,337 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349572004] [2021-12-19 19:17:30,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,338 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,339 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,349 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2021-12-19 19:17:30,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1144 transitions. [2021-12-19 19:17:30,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1144 transitions. [2021-12-19 19:17:30,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:30,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:30,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1144 transitions. [2021-12-19 19:17:30,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,359 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-19 19:17:30,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1144 transitions. [2021-12-19 19:17:30,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:30,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1144 transitions. [2021-12-19 19:17:30,367 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-19 19:17:30,389 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-19 19:17:30,389 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:30,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1144 transitions. [2021-12-19 19:17:30,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,393 INFO L791 eck$LassoCheckResult]: Stem: 8497#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8477#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7937#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7938#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8354#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8355#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8323#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8247#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8236#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8237#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8196#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8197#L754 assume !(0 == ~M_E~0); 8455#L754-2 assume !(0 == ~T1_E~0); 8139#L759-1 assume !(0 == ~T2_E~0); 8140#L764-1 assume !(0 == ~T3_E~0); 8484#L769-1 assume !(0 == ~T4_E~0); 8485#L774-1 assume !(0 == ~T5_E~0); 8385#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8170#L784-1 assume !(0 == ~T7_E~0); 8171#L789-1 assume !(0 == ~E_1~0); 7850#L794-1 assume !(0 == ~E_2~0); 7851#L799-1 assume !(0 == ~E_3~0); 8486#L804-1 assume !(0 == ~E_4~0); 8487#L809-1 assume !(0 == ~E_5~0); 8250#L814-1 assume !(0 == ~E_6~0); 7768#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7769#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8232#L361 assume 1 == ~m_pc~0; 8233#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8274#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8055#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8056#L930 assume !(0 != activate_threads_~tmp~1#1); 8380#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8226#L380 assume !(1 == ~t1_pc~0); 7900#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7899#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8405#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8481#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7976#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7901#L399 assume 1 == ~t2_pc~0; 7902#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8108#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8294#L946 assume !(0 != activate_threads_~tmp___1~0#1); 7806#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7774#L418 assume !(1 == ~t3_pc~0); 7735#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7736#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8254#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8462#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8492#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8457#L437 assume 1 == ~t4_pc~0; 8458#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8077#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7904#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7905#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8333#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8032#L456 assume !(1 == ~t5_pc~0); 8033#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8136#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8436#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7796#L970 assume !(0 != activate_threads_~tmp___4~0#1); 7797#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7920#L475 assume 1 == ~t6_pc~0; 7921#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7996#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7997#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7756#L978 assume !(0 != activate_threads_~tmp___5~0#1); 7757#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8239#L494 assume 1 == ~t7_pc~0; 8240#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8280#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8432#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8433#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8495#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8434#L837 assume !(1 == ~M_E~0); 8297#L837-2 assume !(1 == ~T1_E~0); 7883#L842-1 assume !(1 == ~T2_E~0); 7884#L847-1 assume !(1 == ~T3_E~0); 8350#L852-1 assume !(1 == ~T4_E~0); 8427#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8306#L862-1 assume !(1 == ~T6_E~0); 8307#L867-1 assume !(1 == ~T7_E~0); 8316#L872-1 assume !(1 == ~E_1~0); 8382#L877-1 assume !(1 == ~E_2~0); 8312#L882-1 assume !(1 == ~E_3~0); 8313#L887-1 assume !(1 == ~E_4~0); 7943#L892-1 assume !(1 == ~E_5~0); 7944#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8330#L902-1 assume !(1 == ~E_7~0); 8024#L907-1 assume { :end_inline_reset_delta_events } true; 8025#L1148-2 [2021-12-19 19:17:30,393 INFO L793 eck$LassoCheckResult]: Loop: 8025#L1148-2 assume !false; 7770#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7771#L729 assume !false; 8167#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8163#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8114#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8183#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8221#L626 assume !(0 != eval_~tmp~0#1); 8222#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8352#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8256#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7809#L754-5 assume !(0 == ~T1_E~0); 7810#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8192#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8360#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8361#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8124#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7785#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7786#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7766#L794-3 assume !(0 == ~E_2~0); 7767#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7862#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8262#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7858#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7859#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8058#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8059#L361-24 assume !(1 == ~m_pc~0); 8097#L361-26 is_master_triggered_~__retres1~0#1 := 0; 8096#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7778#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7779#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8255#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8319#L380-24 assume 1 == ~t1_pc~0; 8320#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7946#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8378#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8251#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L399-24 assume 1 == ~t2_pc~0; 8119#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8169#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7948#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8243#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8244#L418-24 assume 1 == ~t3_pc~0; 8248#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7855#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8245#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8123#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7798#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7799#L437-24 assume 1 == ~t4_pc~0; 8070#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8071#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7949#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7950#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8098#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8407#L456-24 assume 1 == ~t5_pc~0; 8408#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8468#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8161#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8162#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8301#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8435#L475-24 assume 1 == ~t6_pc~0; 7800#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7801#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8444#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8445#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7743#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7744#L494-24 assume 1 == ~t7_pc~0; 8401#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8291#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8189#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8068#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8069#L837-3 assume !(1 == ~M_E~0); 8151#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8431#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8347#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7787#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7788#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8472#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8464#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8398#L872-3 assume !(1 == ~E_1~0); 8399#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8467#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8482#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8154#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8147#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8148#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8324#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8317#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7773#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8493#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8453#L1167 assume !(0 == start_simulation_~tmp~3#1); 8348#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8375#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8180#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8414#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8447#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8362#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7749#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7750#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8025#L1148-2 [2021-12-19 19:17:30,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,396 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2021-12-19 19:17:30,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492591519] [2021-12-19 19:17:30,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,397 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492591519] [2021-12-19 19:17:30,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492591519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,413 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827985673] [2021-12-19 19:17:30,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1932928152, now seen corresponding path program 1 times [2021-12-19 19:17:30,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672786637] [2021-12-19 19:17:30,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672786637] [2021-12-19 19:17:30,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672786637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,445 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891494086] [2021-12-19 19:17:30,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,447 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,447 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,448 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,457 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2021-12-19 19:17:30,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1143 transitions. [2021-12-19 19:17:30,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1143 transitions. [2021-12-19 19:17:30,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:30,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:30,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1143 transitions. [2021-12-19 19:17:30,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,466 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-19 19:17:30,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1143 transitions. [2021-12-19 19:17:30,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:30,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1143 transitions. [2021-12-19 19:17:30,474 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-19 19:17:30,474 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-19 19:17:30,475 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:30,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1143 transitions. [2021-12-19 19:17:30,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,478 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,478 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,478 INFO L791 eck$LassoCheckResult]: Stem: 10040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 10018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10019#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9480#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9481#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 9897#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9898#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9866#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9786#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9787#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9779#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9780#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9739#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9740#L754 assume !(0 == ~M_E~0); 9998#L754-2 assume !(0 == ~T1_E~0); 9682#L759-1 assume !(0 == ~T2_E~0); 9683#L764-1 assume !(0 == ~T3_E~0); 10027#L769-1 assume !(0 == ~T4_E~0); 10028#L774-1 assume !(0 == ~T5_E~0); 9926#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9713#L784-1 assume !(0 == ~T7_E~0); 9714#L789-1 assume !(0 == ~E_1~0); 9389#L794-1 assume !(0 == ~E_2~0); 9390#L799-1 assume !(0 == ~E_3~0); 10029#L804-1 assume !(0 == ~E_4~0); 10030#L809-1 assume !(0 == ~E_5~0); 9791#L814-1 assume !(0 == ~E_6~0); 9309#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9310#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9775#L361 assume 1 == ~m_pc~0; 9776#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9817#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9598#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9599#L930 assume !(0 != activate_threads_~tmp~1#1); 9923#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9769#L380 assume !(1 == ~t1_pc~0); 9443#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9442#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9946#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10023#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9519#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9444#L399 assume 1 == ~t2_pc~0; 9445#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9651#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9958#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9837#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9349#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9317#L418 assume !(1 == ~t3_pc~0); 9278#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9279#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9797#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10005#L954 assume !(0 != activate_threads_~tmp___2~0#1); 10035#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9999#L437 assume 1 == ~t4_pc~0; 10000#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9619#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9447#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9448#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9876#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9570#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9679#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9979#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9336#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9337#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9460#L475 assume 1 == ~t6_pc~0; 9461#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9539#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9299#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9300#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9782#L494 assume 1 == ~t7_pc~0; 9783#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9823#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9973#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9974#L986 assume !(0 != activate_threads_~tmp___6~0#1); 10038#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9975#L837 assume !(1 == ~M_E~0); 9840#L837-2 assume !(1 == ~T1_E~0); 9426#L842-1 assume !(1 == ~T2_E~0); 9427#L847-1 assume !(1 == ~T3_E~0); 9893#L852-1 assume !(1 == ~T4_E~0); 9968#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9848#L862-1 assume !(1 == ~T6_E~0); 9849#L867-1 assume !(1 == ~T7_E~0); 9857#L872-1 assume !(1 == ~E_1~0); 9925#L877-1 assume !(1 == ~E_2~0); 9855#L882-1 assume !(1 == ~E_3~0); 9856#L887-1 assume !(1 == ~E_4~0); 9486#L892-1 assume !(1 == ~E_5~0); 9487#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9871#L902-1 assume !(1 == ~E_7~0); 9567#L907-1 assume { :end_inline_reset_delta_events } true; 9568#L1148-2 [2021-12-19 19:17:30,479 INFO L793 eck$LassoCheckResult]: Loop: 9568#L1148-2 assume !false; 9311#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9312#L729 assume !false; 9710#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9706#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9657#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9726#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9763#L626 assume !(0 != eval_~tmp~0#1); 9764#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9894#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9799#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9350#L754-5 assume !(0 == ~T1_E~0); 9351#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9735#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9903#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9904#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9662#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9328#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9329#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9313#L794-3 assume !(0 == ~E_2~0); 9314#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9408#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9805#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9403#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9404#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9601#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9602#L361-24 assume 1 == ~m_pc~0; 9638#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9639#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9321#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9322#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9798#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9862#L380-24 assume !(1 == ~t1_pc~0); 9488#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 9489#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9921#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9794#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9449#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9450#L399-24 assume !(1 == ~t2_pc~0); 9664#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9712#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9490#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9491#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9788#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9789#L418-24 assume 1 == ~t3_pc~0; 9792#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9398#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9790#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9667#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9341#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9342#L437-24 assume 1 == ~t4_pc~0; 9613#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9614#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9492#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9493#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9641#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9950#L456-24 assume !(1 == ~t5_pc~0); 9952#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 10011#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9705#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9846#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9978#L475-24 assume !(1 == ~t6_pc~0); 9345#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 9344#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9987#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9988#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 9286#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9287#L494-24 assume 1 == ~t7_pc~0; 9944#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9835#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9731#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9732#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9611#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9612#L837-3 assume !(1 == ~M_E~0); 9694#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9977#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9891#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9330#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9331#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10015#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10007#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L872-3 assume !(1 == ~E_1~0); 9943#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10010#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10025#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9699#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9692#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9693#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9867#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9860#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9316#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10036#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9996#L1167 assume !(0 == start_simulation_~tmp~3#1); 9890#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9918#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9724#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9957#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9990#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9905#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9292#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9293#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9568#L1148-2 [2021-12-19 19:17:30,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2021-12-19 19:17:30,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514346042] [2021-12-19 19:17:30,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,480 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,497 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514346042] [2021-12-19 19:17:30,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514346042] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,498 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,498 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,498 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361368941] [2021-12-19 19:17:30,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,498 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,499 INFO L85 PathProgramCache]: Analyzing trace with hash -1308384443, now seen corresponding path program 1 times [2021-12-19 19:17:30,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477613393] [2021-12-19 19:17:30,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,520 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,520 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477613393] [2021-12-19 19:17:30,520 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [477613393] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,520 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,520 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,521 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233776682] [2021-12-19 19:17:30,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,521 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,521 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,522 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,530 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2021-12-19 19:17:30,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1142 transitions. [2021-12-19 19:17:30,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1142 transitions. [2021-12-19 19:17:30,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-19 19:17:30,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-19 19:17:30,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1142 transitions. [2021-12-19 19:17:30,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,539 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-19 19:17:30,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1142 transitions. [2021-12-19 19:17:30,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-19 19:17:30,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1142 transitions. [2021-12-19 19:17:30,547 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-19 19:17:30,547 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-19 19:17:30,547 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:30,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1142 transitions. [2021-12-19 19:17:30,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-19 19:17:30,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,551 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,551 INFO L791 eck$LassoCheckResult]: Stem: 11583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11563#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11023#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11024#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11440#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11441#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11409#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11332#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11333#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11322#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11323#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11282#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11283#L754 assume !(0 == ~M_E~0); 11541#L754-2 assume !(0 == ~T1_E~0); 11225#L759-1 assume !(0 == ~T2_E~0); 11226#L764-1 assume !(0 == ~T3_E~0); 11570#L769-1 assume !(0 == ~T4_E~0); 11571#L774-1 assume !(0 == ~T5_E~0); 11471#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11256#L784-1 assume !(0 == ~T7_E~0); 11257#L789-1 assume !(0 == ~E_1~0); 10936#L794-1 assume !(0 == ~E_2~0); 10937#L799-1 assume !(0 == ~E_3~0); 11572#L804-1 assume !(0 == ~E_4~0); 11573#L809-1 assume !(0 == ~E_5~0); 11336#L814-1 assume !(0 == ~E_6~0); 10854#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10855#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11318#L361 assume 1 == ~m_pc~0; 11319#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11360#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11141#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11142#L930 assume !(0 != activate_threads_~tmp~1#1); 11466#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11312#L380 assume !(1 == ~t1_pc~0); 10986#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10985#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11491#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11567#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11062#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10987#L399 assume 1 == ~t2_pc~0; 10988#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11194#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11501#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11380#L946 assume !(0 != activate_threads_~tmp___1~0#1); 10892#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10860#L418 assume !(1 == ~t3_pc~0); 10821#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10822#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11340#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11548#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11578#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11543#L437 assume 1 == ~t4_pc~0; 11544#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11163#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10990#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10991#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11419#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11118#L456 assume !(1 == ~t5_pc~0); 11119#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11222#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11522#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10882#L970 assume !(0 != activate_threads_~tmp___4~0#1); 10883#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11006#L475 assume 1 == ~t6_pc~0; 11007#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11082#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11083#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10842#L978 assume !(0 != activate_threads_~tmp___5~0#1); 10843#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11325#L494 assume 1 == ~t7_pc~0; 11326#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11366#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11518#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11519#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11581#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11520#L837 assume !(1 == ~M_E~0); 11383#L837-2 assume !(1 == ~T1_E~0); 10969#L842-1 assume !(1 == ~T2_E~0); 10970#L847-1 assume !(1 == ~T3_E~0); 11436#L852-1 assume !(1 == ~T4_E~0); 11513#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11392#L862-1 assume !(1 == ~T6_E~0); 11393#L867-1 assume !(1 == ~T7_E~0); 11402#L872-1 assume !(1 == ~E_1~0); 11468#L877-1 assume !(1 == ~E_2~0); 11398#L882-1 assume !(1 == ~E_3~0); 11399#L887-1 assume !(1 == ~E_4~0); 11029#L892-1 assume !(1 == ~E_5~0); 11030#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11416#L902-1 assume !(1 == ~E_7~0); 11111#L907-1 assume { :end_inline_reset_delta_events } true; 11112#L1148-2 [2021-12-19 19:17:30,552 INFO L793 eck$LassoCheckResult]: Loop: 11112#L1148-2 assume !false; 10856#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10857#L729 assume !false; 11253#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11249#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11200#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11269#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11307#L626 assume !(0 != eval_~tmp~0#1); 11308#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11438#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11342#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10895#L754-5 assume !(0 == ~T1_E~0); 10896#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11278#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11446#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11447#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11210#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10871#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10872#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10852#L794-3 assume !(0 == ~E_2~0); 10853#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10948#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11348#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10946#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10947#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11144#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11145#L361-24 assume 1 == ~m_pc~0; 11181#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11182#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10864#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10865#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11341#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11405#L380-24 assume !(1 == ~t1_pc~0); 11031#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11337#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10992#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10993#L399-24 assume 1 == ~t2_pc~0; 11205#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11255#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11033#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11034#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11329#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L418-24 assume 1 == ~t3_pc~0; 11334#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10941#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11331#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11209#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10884#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10885#L437-24 assume 1 == ~t4_pc~0; 11156#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11157#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11035#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11036#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11184#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11493#L456-24 assume 1 == ~t5_pc~0; 11494#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11554#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11247#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11248#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11387#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L475-24 assume 1 == ~t6_pc~0; 10886#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10887#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11530#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11531#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10829#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10830#L494-24 assume !(1 == ~t7_pc~0); 11397#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 11377#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11274#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11275#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11154#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11155#L837-3 assume !(1 == ~M_E~0); 11237#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11517#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11433#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10873#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10874#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11558#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11550#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11484#L872-3 assume !(1 == ~E_1~0); 11485#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11553#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11568#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11240#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11233#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11234#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11410#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11403#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10859#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11579#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11539#L1167 assume !(0 == start_simulation_~tmp~3#1); 11434#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11461#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11266#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11500#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11533#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11448#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10835#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10836#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11112#L1148-2 [2021-12-19 19:17:30,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,552 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2021-12-19 19:17:30,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771667186] [2021-12-19 19:17:30,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771667186] [2021-12-19 19:17:30,580 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771667186] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446151605] [2021-12-19 19:17:30,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,581 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 2 times [2021-12-19 19:17:30,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145272094] [2021-12-19 19:17:30,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,587 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,608 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145272094] [2021-12-19 19:17:30,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145272094] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,612 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,612 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,613 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684080773] [2021-12-19 19:17:30,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,614 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,614 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:30,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:30,614 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,730 INFO L93 Difference]: Finished difference Result 1377 states and 2040 transitions. [2021-12-19 19:17:30,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:30,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2040 transitions. [2021-12-19 19:17:30,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1261 [2021-12-19 19:17:30,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2040 transitions. [2021-12-19 19:17:30,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2021-12-19 19:17:30,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2021-12-19 19:17:30,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2040 transitions. [2021-12-19 19:17:30,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,744 INFO L681 BuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2021-12-19 19:17:30,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2040 transitions. [2021-12-19 19:17:30,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2021-12-19 19:17:30,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4814814814814814) internal successors, (2040), 1376 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2040 transitions. [2021-12-19 19:17:30,763 INFO L704 BuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2021-12-19 19:17:30,763 INFO L587 BuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2021-12-19 19:17:30,764 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:30,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2040 transitions. [2021-12-19 19:17:30,768 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1261 [2021-12-19 19:17:30,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,769 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,769 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,769 INFO L791 eck$LassoCheckResult]: Stem: 13767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13738#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13179#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13180#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13610#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13611#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13573#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13492#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13493#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13482#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13483#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13441#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13442#L754 assume !(0 == ~M_E~0); 13717#L754-2 assume !(0 == ~T1_E~0); 13383#L759-1 assume !(0 == ~T2_E~0); 13384#L764-1 assume !(0 == ~T3_E~0); 13746#L769-1 assume !(0 == ~T4_E~0); 13747#L774-1 assume !(0 == ~T5_E~0); 13643#L779-1 assume !(0 == ~T6_E~0); 13414#L784-1 assume !(0 == ~T7_E~0); 13415#L789-1 assume !(0 == ~E_1~0); 13091#L794-1 assume !(0 == ~E_2~0); 13092#L799-1 assume !(0 == ~E_3~0); 13748#L804-1 assume !(0 == ~E_4~0); 13749#L809-1 assume !(0 == ~E_5~0); 13496#L814-1 assume !(0 == ~E_6~0); 13007#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13008#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13478#L361 assume 1 == ~m_pc~0; 13479#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13522#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13299#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13300#L930 assume !(0 != activate_threads_~tmp~1#1); 13638#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13471#L380 assume !(1 == ~t1_pc~0); 13142#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13141#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13664#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13742#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13219#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13143#L399 assume 1 == ~t2_pc~0; 13144#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13352#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13674#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13542#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13047#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13015#L418 assume !(1 == ~t3_pc~0); 12976#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12977#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13500#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13724#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13756#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13718#L437 assume 1 == ~t4_pc~0; 13719#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13320#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13146#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13147#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13586#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13276#L456 assume !(1 == ~t5_pc~0); 13277#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13380#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13698#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13037#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13038#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13162#L475 assume 1 == ~t6_pc~0; 13163#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13239#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13240#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12997#L978 assume !(0 != activate_threads_~tmp___5~0#1); 12998#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13485#L494 assume 1 == ~t7_pc~0; 13486#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13528#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13693#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13694#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13765#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13695#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 13547#L837-2 assume !(1 == ~T1_E~0); 13125#L842-1 assume !(1 == ~T2_E~0); 13126#L847-1 assume !(1 == ~T3_E~0); 13603#L852-1 assume !(1 == ~T4_E~0); 13688#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13556#L862-1 assume !(1 == ~T6_E~0); 13557#L867-1 assume !(1 == ~T7_E~0); 13566#L872-1 assume !(1 == ~E_1~0); 13640#L877-1 assume !(1 == ~E_2~0); 13562#L882-1 assume !(1 == ~E_3~0); 13563#L887-1 assume !(1 == ~E_4~0); 13185#L892-1 assume !(1 == ~E_5~0); 13186#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13581#L902-1 assume !(1 == ~E_7~0); 13267#L907-1 assume { :end_inline_reset_delta_events } true; 13268#L1148-2 [2021-12-19 19:17:30,769 INFO L793 eck$LassoCheckResult]: Loop: 13268#L1148-2 assume !false; 13009#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13010#L729 assume !false; 13411#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13760#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13427#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13428#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13465#L626 assume !(0 != eval_~tmp~0#1); 13466#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13607#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13608#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13050#L754-5 assume !(0 == ~T1_E~0); 13051#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13437#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13616#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13617#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13368#L779-3 assume !(0 == ~T6_E~0); 13026#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13027#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13011#L794-3 assume !(0 == ~E_2~0); 13012#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13107#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13509#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13102#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13103#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13305#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13306#L361-24 assume 1 == ~m_pc~0; 13339#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13340#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13019#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13020#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13501#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13569#L380-24 assume !(1 == ~t1_pc~0); 13187#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 13188#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13636#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13497#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13150#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13151#L399-24 assume 1 == ~t2_pc~0; 13363#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13413#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13189#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13190#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13489#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13490#L418-24 assume 1 == ~t3_pc~0; 13494#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13096#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13491#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13367#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13039#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13040#L437-24 assume 1 == ~t4_pc~0; 13314#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13315#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13191#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13192#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13342#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13666#L456-24 assume 1 == ~t5_pc~0; 13667#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13730#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13405#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13406#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13551#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13697#L475-24 assume 1 == ~t6_pc~0; 13041#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13042#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13706#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13707#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 12982#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12983#L494-24 assume !(1 == ~t7_pc~0); 13561#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 13538#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13433#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13434#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13312#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13313#L837-3 assume !(1 == ~M_E~0); 13395#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13692#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13600#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13028#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13029#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13734#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13725#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13657#L872-3 assume !(1 == ~E_1~0); 13658#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13729#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13744#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13398#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13391#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13392#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13576#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13567#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13014#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13758#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13715#L1167 assume !(0 == start_simulation_~tmp~3#1); 13601#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13633#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13423#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13673#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13709#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13618#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12990#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12991#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13268#L1148-2 [2021-12-19 19:17:30,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,770 INFO L85 PathProgramCache]: Analyzing trace with hash -2131996243, now seen corresponding path program 1 times [2021-12-19 19:17:30,770 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764963320] [2021-12-19 19:17:30,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,770 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764963320] [2021-12-19 19:17:30,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764963320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,792 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:30,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954986905] [2021-12-19 19:17:30,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,793 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,793 INFO L85 PathProgramCache]: Analyzing trace with hash -397547323, now seen corresponding path program 1 times [2021-12-19 19:17:30,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,794 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627419034] [2021-12-19 19:17:30,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,794 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627419034] [2021-12-19 19:17:30,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627419034] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,816 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639085466] [2021-12-19 19:17:30,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,818 INFO L87 Difference]: Start difference. First operand 1377 states and 2040 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,847 INFO L93 Difference]: Finished difference Result 1377 states and 2016 transitions. [2021-12-19 19:17:30,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2016 transitions. [2021-12-19 19:17:30,853 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1261 [2021-12-19 19:17:30,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2016 transitions. [2021-12-19 19:17:30,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2021-12-19 19:17:30,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2021-12-19 19:17:30,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2016 transitions. [2021-12-19 19:17:30,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:30,860 INFO L681 BuchiCegarLoop]: Abstraction has 1377 states and 2016 transitions. [2021-12-19 19:17:30,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2016 transitions. [2021-12-19 19:17:30,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2021-12-19 19:17:30,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4640522875816993) internal successors, (2016), 1376 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2016 transitions. [2021-12-19 19:17:30,874 INFO L704 BuchiCegarLoop]: Abstraction has 1377 states and 2016 transitions. [2021-12-19 19:17:30,874 INFO L587 BuchiCegarLoop]: Abstraction has 1377 states and 2016 transitions. [2021-12-19 19:17:30,874 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:30,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2016 transitions. [2021-12-19 19:17:30,878 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1261 [2021-12-19 19:17:30,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:30,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:30,879 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:30,880 INFO L791 eck$LassoCheckResult]: Stem: 16547#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16519#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15938#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15939#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16379#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16380#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16342#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16255#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16256#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16248#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16249#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16203#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16204#L754 assume !(0 == ~M_E~0); 16490#L754-2 assume !(0 == ~T1_E~0); 16140#L759-1 assume !(0 == ~T2_E~0); 16141#L764-1 assume !(0 == ~T3_E~0); 16527#L769-1 assume !(0 == ~T4_E~0); 16528#L774-1 assume !(0 == ~T5_E~0); 16412#L779-1 assume !(0 == ~T6_E~0); 16173#L784-1 assume !(0 == ~T7_E~0); 16174#L789-1 assume !(0 == ~E_1~0); 15848#L794-1 assume !(0 == ~E_2~0); 15849#L799-1 assume !(0 == ~E_3~0); 16531#L804-1 assume !(0 == ~E_4~0); 16532#L809-1 assume !(0 == ~E_5~0); 16260#L814-1 assume !(0 == ~E_6~0); 15768#L819-1 assume !(0 == ~E_7~0); 15769#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16244#L361 assume 1 == ~m_pc~0; 16245#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16288#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16056#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16057#L930 assume !(0 != activate_threads_~tmp~1#1); 16409#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16237#L380 assume !(1 == ~t1_pc~0); 15902#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15901#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16432#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16523#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15977#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15903#L399 assume 1 == ~t2_pc~0; 15904#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16108#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16444#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16309#L946 assume !(0 != activate_threads_~tmp___1~0#1); 15808#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15776#L418 assume !(1 == ~t3_pc~0); 15737#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15738#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16264#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16500#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16539#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16491#L437 assume 1 == ~t4_pc~0; 16492#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16077#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15906#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15907#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16351#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16028#L456 assume !(1 == ~t5_pc~0); 16029#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16137#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16468#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15795#L970 assume !(0 != activate_threads_~tmp___4~0#1); 15796#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15919#L475 assume 1 == ~t6_pc~0; 15920#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15997#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15998#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15758#L978 assume !(0 != activate_threads_~tmp___5~0#1); 15759#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16251#L494 assume !(1 == ~t7_pc~0); 16253#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16294#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16460#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16461#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16544#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16462#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 16463#L837-2 assume !(1 == ~T1_E~0); 16865#L842-1 assume !(1 == ~T2_E~0); 16864#L847-1 assume !(1 == ~T3_E~0); 16863#L852-1 assume !(1 == ~T4_E~0); 16862#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16861#L862-1 assume !(1 == ~T6_E~0); 16321#L867-1 assume !(1 == ~T7_E~0); 16860#L872-1 assume !(1 == ~E_1~0); 16859#L877-1 assume !(1 == ~E_2~0); 16858#L882-1 assume !(1 == ~E_3~0); 16857#L887-1 assume !(1 == ~E_4~0); 16856#L892-1 assume !(1 == ~E_5~0); 16855#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16854#L902-1 assume !(1 == ~E_7~0); 16568#L907-1 assume { :end_inline_reset_delta_events } true; 16399#L1148-2 [2021-12-19 19:17:30,880 INFO L793 eck$LassoCheckResult]: Loop: 16399#L1148-2 assume !false; 16400#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16558#L729 assume !false; 16557#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16166#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16115#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16549#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16230#L626 assume !(0 != eval_~tmp~0#1); 16231#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16376#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16377#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16548#L754-5 assume !(0 == ~T1_E~0); 16851#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16850#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16849#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16848#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16847#L779-3 assume !(0 == ~T6_E~0); 16846#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16845#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16844#L794-3 assume !(0 == ~E_2~0); 16843#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16842#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16841#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16840#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16839#L819-3 assume !(0 == ~E_7~0); 16838#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16837#L361-24 assume 1 == ~m_pc~0; 16835#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16834#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16833#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16832#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16831#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16830#L380-24 assume !(1 == ~t1_pc~0); 16828#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 16827#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16826#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16825#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16824#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16823#L399-24 assume 1 == ~t2_pc~0; 16821#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16820#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16819#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16818#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16817#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16816#L418-24 assume !(1 == ~t3_pc~0); 16814#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 16813#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16812#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16811#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16810#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16809#L437-24 assume 1 == ~t4_pc~0; 16807#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16806#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16805#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16804#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16803#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16802#L456-24 assume !(1 == ~t5_pc~0); 16800#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 16799#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16798#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16797#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16796#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16795#L475-24 assume 1 == ~t6_pc~0; 16793#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16792#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16791#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16790#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 16789#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16788#L494-24 assume !(1 == ~t7_pc~0); 16786#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 16785#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16784#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16783#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16782#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16781#L837-3 assume !(1 == ~M_E~0); 16154#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16780#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16779#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16778#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16777#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16776#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16537#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16775#L872-3 assume !(1 == ~E_1~0); 16774#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16773#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16772#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16771#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16770#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16769#L902-3 assume !(1 == ~E_7~0); 16768#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16766#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16759#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16758#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16757#L1167 assume !(0 == start_simulation_~tmp~3#1); 16371#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16579#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16574#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16573#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16572#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16571#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16570#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16569#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16399#L1148-2 [2021-12-19 19:17:30,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1317616970, now seen corresponding path program 1 times [2021-12-19 19:17:30,881 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227922476] [2021-12-19 19:17:30,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227922476] [2021-12-19 19:17:30,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227922476] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,913 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,913 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:30,913 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418652413] [2021-12-19 19:17:30,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,914 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:30,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:30,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1275684223, now seen corresponding path program 1 times [2021-12-19 19:17:30,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:30,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154114509] [2021-12-19 19:17:30,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:30,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:30,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:30,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:30,934 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:30,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154114509] [2021-12-19 19:17:30,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154114509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:30,935 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:30,935 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:30,935 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538939799] [2021-12-19 19:17:30,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:30,935 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:30,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:30,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:30,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:30,936 INFO L87 Difference]: Start difference. First operand 1377 states and 2016 transitions. cyclomatic complexity: 641 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:30,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:30,983 INFO L93 Difference]: Finished difference Result 2618 states and 3795 transitions. [2021-12-19 19:17:30,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:30,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2618 states and 3795 transitions. [2021-12-19 19:17:30,999 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2499 [2021-12-19 19:17:31,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2618 states to 2618 states and 3795 transitions. [2021-12-19 19:17:31,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2618 [2021-12-19 19:17:31,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2618 [2021-12-19 19:17:31,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2618 states and 3795 transitions. [2021-12-19 19:17:31,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:31,011 INFO L681 BuchiCegarLoop]: Abstraction has 2618 states and 3795 transitions. [2021-12-19 19:17:31,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2618 states and 3795 transitions. [2021-12-19 19:17:31,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2618 to 2504. [2021-12-19 19:17:31,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2504 states, 2504 states have (on average 1.4532747603833867) internal successors, (3639), 2503 states have internal predecessors, (3639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 3639 transitions. [2021-12-19 19:17:31,078 INFO L704 BuchiCegarLoop]: Abstraction has 2504 states and 3639 transitions. [2021-12-19 19:17:31,078 INFO L587 BuchiCegarLoop]: Abstraction has 2504 states and 3639 transitions. [2021-12-19 19:17:31,078 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:31,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2504 states and 3639 transitions. [2021-12-19 19:17:31,084 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2385 [2021-12-19 19:17:31,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:31,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:31,086 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,086 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,086 INFO L791 eck$LassoCheckResult]: Stem: 20606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20556#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19943#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19944#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 20389#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20390#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20351#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20261#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20262#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20253#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20254#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20211#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20212#L754 assume !(0 == ~M_E~0); 20519#L754-2 assume !(0 == ~T1_E~0); 20148#L759-1 assume !(0 == ~T2_E~0); 20149#L764-1 assume !(0 == ~T3_E~0); 20573#L769-1 assume !(0 == ~T4_E~0); 20574#L774-1 assume !(0 == ~T5_E~0); 20428#L779-1 assume !(0 == ~T6_E~0); 20181#L784-1 assume !(0 == ~T7_E~0); 20182#L789-1 assume !(0 == ~E_1~0); 19851#L794-1 assume !(0 == ~E_2~0); 19852#L799-1 assume !(0 == ~E_3~0); 20579#L804-1 assume !(0 == ~E_4~0); 20580#L809-1 assume !(0 == ~E_5~0); 20266#L814-1 assume !(0 == ~E_6~0); 19770#L819-1 assume !(0 == ~E_7~0); 19771#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20250#L361 assume !(1 == ~m_pc~0); 20251#L361-2 is_master_triggered_~__retres1~0#1 := 0; 20294#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20062#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20063#L930 assume !(0 != activate_threads_~tmp~1#1); 20423#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20244#L380 assume !(1 == ~t1_pc~0); 19907#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19906#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20450#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20563#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19982#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19908#L399 assume 1 == ~t2_pc~0; 19909#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20118#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20466#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20315#L946 assume !(0 != activate_threads_~tmp___1~0#1); 19810#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19778#L418 assume !(1 == ~t3_pc~0); 19739#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19740#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20270#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20532#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20592#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20521#L437 assume 1 == ~t4_pc~0; 20522#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20085#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19911#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19912#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20361#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20034#L456 assume !(1 == ~t5_pc~0); 20035#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20145#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20496#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19797#L970 assume !(0 != activate_threads_~tmp___4~0#1); 19798#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19924#L475 assume 1 == ~t6_pc~0; 19925#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20002#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20003#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19760#L978 assume !(0 != activate_threads_~tmp___5~0#1); 19761#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20256#L494 assume !(1 == ~t7_pc~0); 20258#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20300#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20489#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20490#L986 assume !(0 != activate_threads_~tmp___6~0#1); 20598#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20491#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 20318#L837-2 assume !(1 == ~T1_E~0); 20319#L842-1 assume !(1 == ~T2_E~0); 20382#L847-1 assume !(1 == ~T3_E~0); 20383#L852-1 assume !(1 == ~T4_E~0); 20611#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20612#L862-1 assume !(1 == ~T6_E~0); 20330#L867-1 assume !(1 == ~T7_E~0); 20342#L872-1 assume !(1 == ~E_1~0); 20427#L877-1 assume !(1 == ~E_2~0); 21123#L882-1 assume !(1 == ~E_3~0); 21121#L887-1 assume !(1 == ~E_4~0); 21119#L892-1 assume !(1 == ~E_5~0); 21118#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 21117#L902-1 assume !(1 == ~E_7~0); 20031#L907-1 assume { :end_inline_reset_delta_events } true; 20032#L1148-2 [2021-12-19 19:17:31,086 INFO L793 eck$LassoCheckResult]: Loop: 20032#L1148-2 assume !false; 20413#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21095#L729 assume !false; 20596#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20174#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20124#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21086#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21085#L626 assume !(0 != eval_~tmp~0#1); 21084#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21082#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21079#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21080#L754-5 assume !(0 == ~T1_E~0); 22133#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22132#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22131#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22130#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22129#L779-3 assume !(0 == ~T6_E~0); 22128#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22127#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22126#L794-3 assume !(0 == ~E_2~0); 22125#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22124#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22123#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22122#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22121#L819-3 assume !(0 == ~E_7~0); 22120#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22119#L361-24 assume !(1 == ~m_pc~0); 22118#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22117#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22116#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22115#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22114#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22113#L380-24 assume 1 == ~t1_pc~0; 22112#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20419#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20420#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20269#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19913#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19914#L399-24 assume 1 == ~t2_pc~0; 20130#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20180#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19953#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19954#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20263#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20264#L418-24 assume !(1 == ~t3_pc~0); 19859#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 19860#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20265#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20134#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19802#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19803#L437-24 assume !(1 == ~t4_pc~0); 20080#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 20079#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19955#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19956#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20109#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20454#L456-24 assume 1 == ~t5_pc~0; 20455#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20540#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20172#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20173#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20327#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20495#L475-24 assume 1 == ~t6_pc~0; 19804#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19805#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20506#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20507#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 19747#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19748#L494-24 assume !(1 == ~t7_pc~0); 20338#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20313#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20200#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20201#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20076#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20077#L837-3 assume !(1 == ~M_E~0); 20161#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20494#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20379#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19791#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19792#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20549#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20534#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20446#L872-3 assume !(1 == ~E_1~0); 20447#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20539#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21048#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21047#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21046#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21045#L902-3 assume !(1 == ~E_7~0); 21043#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21044#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21173#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21171#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 21169#L1167 assume !(0 == start_simulation_~tmp~3#1); 20380#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21138#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21133#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21132#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20541#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20399#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19753#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19754#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20032#L1148-2 [2021-12-19 19:17:31,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,087 INFO L85 PathProgramCache]: Analyzing trace with hash 2022535657, now seen corresponding path program 1 times [2021-12-19 19:17:31,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494247498] [2021-12-19 19:17:31,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494247498] [2021-12-19 19:17:31,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494247498] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,121 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:31,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72372732] [2021-12-19 19:17:31,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,121 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:31,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1054482175, now seen corresponding path program 1 times [2021-12-19 19:17:31,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228684443] [2021-12-19 19:17:31,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228684443] [2021-12-19 19:17:31,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228684443] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,150 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:31,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550300802] [2021-12-19 19:17:31,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,150 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:31,150 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:31,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:31,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:31,151 INFO L87 Difference]: Start difference. First operand 2504 states and 3639 transitions. cyclomatic complexity: 1139 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:31,328 INFO L93 Difference]: Finished difference Result 6934 states and 10047 transitions. [2021-12-19 19:17:31,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:31,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6934 states and 10047 transitions. [2021-12-19 19:17:31,362 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6656 [2021-12-19 19:17:31,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6934 states to 6934 states and 10047 transitions. [2021-12-19 19:17:31,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6934 [2021-12-19 19:17:31,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6934 [2021-12-19 19:17:31,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6934 states and 10047 transitions. [2021-12-19 19:17:31,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:31,410 INFO L681 BuchiCegarLoop]: Abstraction has 6934 states and 10047 transitions. [2021-12-19 19:17:31,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6934 states and 10047 transitions. [2021-12-19 19:17:31,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6934 to 2603. [2021-12-19 19:17:31,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2603 states, 2603 states have (on average 1.4360353438340376) internal successors, (3738), 2602 states have internal predecessors, (3738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2603 states to 2603 states and 3738 transitions. [2021-12-19 19:17:31,471 INFO L704 BuchiCegarLoop]: Abstraction has 2603 states and 3738 transitions. [2021-12-19 19:17:31,471 INFO L587 BuchiCegarLoop]: Abstraction has 2603 states and 3738 transitions. [2021-12-19 19:17:31,472 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:31,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2603 states and 3738 transitions. [2021-12-19 19:17:31,477 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2481 [2021-12-19 19:17:31,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:31,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:31,479 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,479 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,479 INFO L791 eck$LassoCheckResult]: Stem: 30133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 30068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30069#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29395#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29396#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 29873#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29874#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29831#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29728#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29729#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29720#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29721#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29676#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29677#L754 assume !(0 == ~M_E~0); 30018#L754-2 assume !(0 == ~T1_E~0); 29603#L759-1 assume !(0 == ~T2_E~0); 29604#L764-1 assume !(0 == ~T3_E~0); 30089#L769-1 assume !(0 == ~T4_E~0); 30090#L774-1 assume !(0 == ~T5_E~0); 29913#L779-1 assume !(0 == ~T6_E~0); 29641#L784-1 assume !(0 == ~T7_E~0); 29642#L789-1 assume !(0 == ~E_1~0); 29302#L794-1 assume !(0 == ~E_2~0); 29303#L799-1 assume !(0 == ~E_3~0); 30096#L804-1 assume !(0 == ~E_4~0); 30097#L809-1 assume !(0 == ~E_5~0); 29733#L814-1 assume !(0 == ~E_6~0); 29221#L819-1 assume !(0 == ~E_7~0); 29222#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29716#L361 assume !(1 == ~m_pc~0); 29717#L361-2 is_master_triggered_~__retres1~0#1 := 0; 29762#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29517#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29518#L930 assume !(0 != activate_threads_~tmp~1#1); 29908#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29709#L380 assume !(1 == ~t1_pc~0); 29358#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29938#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29939#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30132#L938 assume !(0 != activate_threads_~tmp___0~0#1); 29437#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29359#L399 assume 1 == ~t2_pc~0; 29360#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29573#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29957#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29788#L946 assume !(0 != activate_threads_~tmp___1~0#1); 29261#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29229#L418 assume !(1 == ~t3_pc~0); 29190#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29191#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29737#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30042#L954 assume !(0 != activate_threads_~tmp___2~0#1); 30116#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30022#L437 assume 1 == ~t4_pc~0; 30023#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29540#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29362#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29363#L962 assume !(0 != activate_threads_~tmp___3~0#1); 29841#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29489#L456 assume !(1 == ~t5_pc~0); 29490#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29600#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29989#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29248#L970 assume !(0 != activate_threads_~tmp___4~0#1); 29249#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29375#L475 assume 1 == ~t6_pc~0; 29376#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29457#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29458#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29211#L978 assume !(0 != activate_threads_~tmp___5~0#1); 29212#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29723#L494 assume !(1 == ~t7_pc~0); 29725#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29768#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29980#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29981#L986 assume !(0 != activate_threads_~tmp___6~0#1); 30127#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29982#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 29793#L837-2 assume !(1 == ~T1_E~0); 29340#L842-1 assume !(1 == ~T2_E~0); 29341#L847-1 assume !(1 == ~T3_E~0); 29866#L852-1 assume !(1 == ~T4_E~0); 29974#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29803#L862-1 assume !(1 == ~T6_E~0); 29804#L867-1 assume !(1 == ~T7_E~0); 29816#L872-1 assume !(1 == ~E_1~0); 29912#L877-1 assume !(1 == ~E_2~0); 29814#L882-1 assume !(1 == ~E_3~0); 29815#L887-1 assume !(1 == ~E_4~0); 29402#L892-1 assume !(1 == ~E_5~0); 29403#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 29836#L902-1 assume !(1 == ~E_7~0); 29486#L907-1 assume { :end_inline_reset_delta_events } true; 29487#L1148-2 [2021-12-19 19:17:31,479 INFO L793 eck$LassoCheckResult]: Loop: 29487#L1148-2 assume !false; 30305#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30285#L729 assume !false; 30286#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30262#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30258#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30249#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30250#L626 assume !(0 != eval_~tmp~0#1); 30914#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30913#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30895#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30896#L754-5 assume !(0 == ~T1_E~0); 30891#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30892#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30887#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30888#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30883#L779-3 assume !(0 == ~T6_E~0); 30884#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30879#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30880#L794-3 assume !(0 == ~E_2~0); 30875#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30876#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30871#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30872#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30867#L819-3 assume !(0 == ~E_7~0); 30868#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29909#L361-24 assume !(1 == ~m_pc~0); 29910#L361-26 is_master_triggered_~__retres1~0#1 := 0; 30950#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30859#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30860#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30855#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30856#L380-24 assume 1 == ~t1_pc~0; 30849#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30851#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30841#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30842#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30836#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30837#L399-24 assume !(1 == ~t2_pc~0); 30832#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 30831#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29406#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29407#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30728#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30729#L418-24 assume !(1 == ~t3_pc~0); 30722#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 30723#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30718#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30719#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30678#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30679#L437-24 assume 1 == ~t4_pc~0; 30628#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30629#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30610#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30611#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30593#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30594#L456-24 assume !(1 == ~t5_pc~0); 30572#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 30573#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30554#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30555#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30537#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30538#L475-24 assume 1 == ~t6_pc~0; 30516#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30517#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30498#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30499#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 30481#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30482#L494-24 assume !(1 == ~t7_pc~0); 30462#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 30463#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30455#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30456#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30449#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30450#L837-3 assume !(1 == ~M_E~0); 30443#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30444#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30436#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30437#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30425#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30426#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30418#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30419#L872-3 assume !(1 == ~E_1~0); 30408#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30409#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30398#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30399#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30227#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30228#L902-3 assume !(1 == ~E_7~0); 30212#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30213#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30941#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30940#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 30939#L1167 assume !(0 == start_simulation_~tmp~3#1); 30350#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30325#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30318#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30316#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 30313#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30311#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30309#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 30307#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 29487#L1148-2 [2021-12-19 19:17:31,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1396412633, now seen corresponding path program 1 times [2021-12-19 19:17:31,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062339367] [2021-12-19 19:17:31,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,534 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062339367] [2021-12-19 19:17:31,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062339367] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,535 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:31,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278296808] [2021-12-19 19:17:31,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,536 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:31,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1152964318, now seen corresponding path program 1 times [2021-12-19 19:17:31,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649189642] [2021-12-19 19:17:31,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,554 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649189642] [2021-12-19 19:17:31,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649189642] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,554 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,555 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:31,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190607512] [2021-12-19 19:17:31,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,555 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:31,555 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:31,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:31,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:31,556 INFO L87 Difference]: Start difference. First operand 2603 states and 3738 transitions. cyclomatic complexity: 1139 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:31,687 INFO L93 Difference]: Finished difference Result 6846 states and 9732 transitions. [2021-12-19 19:17:31,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:31,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6846 states and 9732 transitions. [2021-12-19 19:17:31,713 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6689 [2021-12-19 19:17:31,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6846 states to 6846 states and 9732 transitions. [2021-12-19 19:17:31,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6846 [2021-12-19 19:17:31,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6846 [2021-12-19 19:17:31,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6846 states and 9732 transitions. [2021-12-19 19:17:31,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:31,745 INFO L681 BuchiCegarLoop]: Abstraction has 6846 states and 9732 transitions. [2021-12-19 19:17:31,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6846 states and 9732 transitions. [2021-12-19 19:17:31,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6846 to 6650. [2021-12-19 19:17:31,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.4243609022556392) internal successors, (9472), 6649 states have internal predecessors, (9472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:31,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 9472 transitions. [2021-12-19 19:17:31,849 INFO L704 BuchiCegarLoop]: Abstraction has 6650 states and 9472 transitions. [2021-12-19 19:17:31,849 INFO L587 BuchiCegarLoop]: Abstraction has 6650 states and 9472 transitions. [2021-12-19 19:17:31,849 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:31,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 9472 transitions. [2021-12-19 19:17:31,870 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6517 [2021-12-19 19:17:31,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:31,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:31,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,871 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:31,872 INFO L791 eck$LassoCheckResult]: Stem: 39539#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 39484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 39485#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38847#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38848#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 39310#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39311#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39272#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39182#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39183#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39172#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39173#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39127#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39128#L754 assume !(0 == ~M_E~0); 39440#L754-2 assume !(0 == ~T1_E~0); 39055#L759-1 assume !(0 == ~T2_E~0); 39056#L764-1 assume !(0 == ~T3_E~0); 39501#L769-1 assume !(0 == ~T4_E~0); 39502#L774-1 assume !(0 == ~T5_E~0); 39351#L779-1 assume !(0 == ~T6_E~0); 39095#L784-1 assume !(0 == ~T7_E~0); 39096#L789-1 assume !(0 == ~E_1~0); 38764#L794-1 assume !(0 == ~E_2~0); 38765#L799-1 assume !(0 == ~E_3~0); 39506#L804-1 assume !(0 == ~E_4~0); 39507#L809-1 assume !(0 == ~E_5~0); 39186#L814-1 assume !(0 == ~E_6~0); 38684#L819-1 assume !(0 == ~E_7~0); 38685#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39168#L361 assume !(1 == ~m_pc~0); 39169#L361-2 is_master_triggered_~__retres1~0#1 := 0; 39212#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38970#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38971#L930 assume !(0 != activate_threads_~tmp~1#1); 39343#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39159#L380 assume !(1 == ~t1_pc~0); 39160#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39374#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39375#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39490#L938 assume !(0 != activate_threads_~tmp___0~0#1); 38888#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38813#L399 assume !(1 == ~t2_pc~0); 38814#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39024#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39387#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39234#L946 assume !(0 != activate_threads_~tmp___1~0#1); 38720#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38691#L418 assume !(1 == ~t3_pc~0); 38649#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38650#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39190#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39454#L954 assume !(0 != activate_threads_~tmp___2~0#1); 39523#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39444#L437 assume 1 == ~t4_pc~0; 39445#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38994#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38815#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38816#L962 assume !(0 != activate_threads_~tmp___3~0#1); 39282#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38945#L456 assume !(1 == ~t5_pc~0); 38946#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39052#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39412#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38710#L970 assume !(0 != activate_threads_~tmp___4~0#1); 38711#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38831#L475 assume 1 == ~t6_pc~0; 38832#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38908#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38909#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38670#L978 assume !(0 != activate_threads_~tmp___5~0#1); 38671#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39174#L494 assume !(1 == ~t7_pc~0); 39176#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 39218#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39407#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39408#L986 assume !(0 != activate_threads_~tmp___6~0#1); 39530#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39409#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 39410#L837-2 assume !(1 == ~T1_E~0); 42739#L842-1 assume !(1 == ~T2_E~0); 42737#L847-1 assume !(1 == ~T3_E~0); 39401#L852-1 assume !(1 == ~T4_E~0); 39402#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39248#L862-1 assume !(1 == ~T6_E~0); 39249#L867-1 assume !(1 == ~T7_E~0); 39347#L872-1 assume !(1 == ~E_1~0); 39348#L877-1 assume !(1 == ~E_2~0); 39255#L882-1 assume !(1 == ~E_3~0); 39256#L887-1 assume !(1 == ~E_4~0); 38854#L892-1 assume !(1 == ~E_5~0); 38855#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 39278#L902-1 assume !(1 == ~E_7~0); 39279#L907-1 assume { :end_inline_reset_delta_events } true; 42472#L1148-2 [2021-12-19 19:17:31,872 INFO L793 eck$LassoCheckResult]: Loop: 42472#L1148-2 assume !false; 42434#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42429#L729 assume !false; 42342#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42301#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42292#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42288#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42283#L626 assume !(0 != eval_~tmp~0#1); 42284#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43221#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43218#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43214#L754-5 assume !(0 == ~T1_E~0); 43210#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43206#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43202#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43198#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43193#L779-3 assume !(0 == ~T6_E~0); 43189#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43185#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43181#L794-3 assume !(0 == ~E_2~0); 43177#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43173#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43167#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43162#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43157#L819-3 assume !(0 == ~E_7~0); 43152#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43148#L361-24 assume !(1 == ~m_pc~0); 43144#L361-26 is_master_triggered_~__retres1~0#1 := 0; 43140#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43136#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43133#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43130#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43126#L380-24 assume !(1 == ~t1_pc~0); 43123#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 43120#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43116#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43112#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 43108#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43104#L399-24 assume !(1 == ~t2_pc~0); 43100#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 43096#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43092#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43088#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43084#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43080#L418-24 assume !(1 == ~t3_pc~0); 43075#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 43070#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43067#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43064#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43060#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43056#L437-24 assume 1 == ~t4_pc~0; 43051#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43046#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43042#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43038#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43033#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43028#L456-24 assume !(1 == ~t5_pc~0); 43022#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 43016#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43011#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43005#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42998#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42992#L475-24 assume 1 == ~t6_pc~0; 42985#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42978#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42972#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42966#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 42959#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42954#L494-24 assume !(1 == ~t7_pc~0); 42946#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 42941#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42936#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42929#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42923#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42917#L837-3 assume !(1 == ~M_E~0); 42909#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42903#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42897#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42889#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42884#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42856#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42847#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42839#L872-3 assume !(1 == ~E_1~0); 42833#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42827#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42822#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42817#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42811#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42806#L902-3 assume !(1 == ~E_7~0); 42802#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42792#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42780#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42776#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 42770#L1167 assume !(0 == start_simulation_~tmp~3#1); 42766#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42692#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42684#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 42680#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 42674#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42670#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42665#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 42474#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 42472#L1148-2 [2021-12-19 19:17:31,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,872 INFO L85 PathProgramCache]: Analyzing trace with hash -2097980858, now seen corresponding path program 1 times [2021-12-19 19:17:31,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885563213] [2021-12-19 19:17:31,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885563213] [2021-12-19 19:17:31,893 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885563213] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,893 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,893 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:31,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495909596] [2021-12-19 19:17:31,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,894 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:31,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:31,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1327753339, now seen corresponding path program 1 times [2021-12-19 19:17:31,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:31,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026571921] [2021-12-19 19:17:31,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:31,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:31,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:31,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:31,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:31,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026571921] [2021-12-19 19:17:31,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026571921] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:31,914 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:31,914 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:31,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855303027] [2021-12-19 19:17:31,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:31,914 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:31,914 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:31,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:31,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:31,915 INFO L87 Difference]: Start difference. First operand 6650 states and 9472 transitions. cyclomatic complexity: 2830 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:32,136 INFO L93 Difference]: Finished difference Result 17819 states and 25203 transitions. [2021-12-19 19:17:32,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:32,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17819 states and 25203 transitions. [2021-12-19 19:17:32,201 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17567 [2021-12-19 19:17:32,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17819 states to 17819 states and 25203 transitions. [2021-12-19 19:17:32,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17819 [2021-12-19 19:17:32,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17819 [2021-12-19 19:17:32,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17819 states and 25203 transitions. [2021-12-19 19:17:32,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:32,275 INFO L681 BuchiCegarLoop]: Abstraction has 17819 states and 25203 transitions. [2021-12-19 19:17:32,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17819 states and 25203 transitions. [2021-12-19 19:17:32,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17819 to 17391. [2021-12-19 19:17:32,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17391 states, 17391 states have (on average 1.4172273014777759) internal successors, (24647), 17390 states have internal predecessors, (24647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17391 states to 17391 states and 24647 transitions. [2021-12-19 19:17:32,671 INFO L704 BuchiCegarLoop]: Abstraction has 17391 states and 24647 transitions. [2021-12-19 19:17:32,671 INFO L587 BuchiCegarLoop]: Abstraction has 17391 states and 24647 transitions. [2021-12-19 19:17:32,671 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:32,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17391 states and 24647 transitions. [2021-12-19 19:17:32,712 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17219 [2021-12-19 19:17:32,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:32,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:32,714 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,714 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,714 INFO L791 eck$LassoCheckResult]: Stem: 64017#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 63960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 63961#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63323#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63324#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 63792#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63793#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63751#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63654#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63655#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63647#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63648#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63603#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63604#L754 assume !(0 == ~M_E~0); 63924#L754-2 assume !(0 == ~T1_E~0); 63526#L759-1 assume !(0 == ~T2_E~0); 63527#L764-1 assume !(0 == ~T3_E~0); 63982#L769-1 assume !(0 == ~T4_E~0); 63983#L774-1 assume !(0 == ~T5_E~0); 63830#L779-1 assume !(0 == ~T6_E~0); 63572#L784-1 assume !(0 == ~T7_E~0); 63573#L789-1 assume !(0 == ~E_1~0); 63236#L794-1 assume !(0 == ~E_2~0); 63237#L799-1 assume !(0 == ~E_3~0); 63985#L804-1 assume !(0 == ~E_4~0); 63986#L809-1 assume !(0 == ~E_5~0); 63659#L814-1 assume !(0 == ~E_6~0); 63157#L819-1 assume !(0 == ~E_7~0); 63158#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63644#L361 assume !(1 == ~m_pc~0); 63645#L361-2 is_master_triggered_~__retres1~0#1 := 0; 63686#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63444#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63445#L930 assume !(0 != activate_threads_~tmp~1#1); 63827#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63637#L380 assume !(1 == ~t1_pc~0); 63638#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63851#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63852#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63970#L938 assume !(0 != activate_threads_~tmp___0~0#1); 63363#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63289#L399 assume !(1 == ~t2_pc~0); 63290#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63496#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63867#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63713#L946 assume !(0 != activate_threads_~tmp___1~0#1); 63196#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63165#L418 assume !(1 == ~t3_pc~0); 63128#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63129#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63663#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63941#L954 assume !(0 != activate_threads_~tmp___2~0#1); 63998#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63925#L437 assume !(1 == ~t4_pc~0); 63795#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63465#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63291#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63292#L962 assume !(0 != activate_threads_~tmp___3~0#1); 63760#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63414#L456 assume !(1 == ~t5_pc~0); 63415#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63523#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63900#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63184#L970 assume !(0 != activate_threads_~tmp___4~0#1); 63185#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63304#L475 assume 1 == ~t6_pc~0; 63305#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63382#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63383#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63149#L978 assume !(0 != activate_threads_~tmp___5~0#1); 63150#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63650#L494 assume !(1 == ~t7_pc~0); 63652#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 63692#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63889#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63890#L986 assume !(0 != activate_threads_~tmp___6~0#1); 64012#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63891#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 63716#L837-2 assume !(1 == ~T1_E~0); 63273#L842-1 assume !(1 == ~T2_E~0); 63274#L847-1 assume !(1 == ~T3_E~0); 63786#L852-1 assume !(1 == ~T4_E~0); 63883#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63727#L862-1 assume !(1 == ~T6_E~0); 63728#L867-1 assume !(1 == ~T7_E~0); 63739#L872-1 assume !(1 == ~E_1~0); 63829#L877-1 assume !(1 == ~E_2~0); 63736#L882-1 assume !(1 == ~E_3~0); 63737#L887-1 assume !(1 == ~E_4~0); 63329#L892-1 assume !(1 == ~E_5~0); 63330#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 63755#L902-1 assume !(1 == ~E_7~0); 63410#L907-1 assume { :end_inline_reset_delta_events } true; 63411#L1148-2 [2021-12-19 19:17:32,715 INFO L793 eck$LassoCheckResult]: Loop: 63411#L1148-2 assume !false; 78182#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78180#L729 assume !false; 78174#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 78163#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 78154#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 78148#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78141#L626 assume !(0 != eval_~tmp~0#1); 78142#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79165#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79163#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 79160#L754-5 assume !(0 == ~T1_E~0); 79158#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79156#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79154#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79152#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79150#L779-3 assume !(0 == ~T6_E~0); 79149#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79147#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79145#L794-3 assume !(0 == ~E_2~0); 79143#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79141#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79139#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79136#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79134#L819-3 assume !(0 == ~E_7~0); 79132#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79130#L361-24 assume !(1 == ~m_pc~0); 79128#L361-26 is_master_triggered_~__retres1~0#1 := 0; 79126#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79123#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79121#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79119#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79117#L380-24 assume !(1 == ~t1_pc~0); 79115#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 78807#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78804#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78802#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 78800#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78797#L399-24 assume !(1 == ~t2_pc~0); 78795#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 78793#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78791#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78789#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78787#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78786#L418-24 assume 1 == ~t3_pc~0; 78783#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78780#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78778#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78776#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78774#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78772#L437-24 assume !(1 == ~t4_pc~0); 78771#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 78769#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78767#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78765#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78763#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78761#L456-24 assume !(1 == ~t5_pc~0); 78741#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 78739#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78737#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78735#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78732#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78730#L475-24 assume !(1 == ~t6_pc~0); 78727#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 78724#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78722#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78720#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 78705#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78696#L494-24 assume !(1 == ~t7_pc~0); 78688#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 78681#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78671#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78665#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78605#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78602#L837-3 assume !(1 == ~M_E~0); 72201#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78599#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78597#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78595#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78592#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78590#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72172#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78570#L872-3 assume !(1 == ~E_1~0); 78565#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78560#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78554#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78547#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78542#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78537#L902-3 assume !(1 == ~E_7~0); 78534#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 78466#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 78453#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 78446#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 78439#L1167 assume !(0 == start_simulation_~tmp~3#1); 78432#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 78251#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 78244#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 78242#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 78240#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78238#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78236#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 78214#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 63411#L1148-2 [2021-12-19 19:17:32,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1697989659, now seen corresponding path program 1 times [2021-12-19 19:17:32,716 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498465566] [2021-12-19 19:17:32,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498465566] [2021-12-19 19:17:32,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498465566] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,747 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,747 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:32,747 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498754783] [2021-12-19 19:17:32,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,747 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:32,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,748 INFO L85 PathProgramCache]: Analyzing trace with hash -2127143590, now seen corresponding path program 1 times [2021-12-19 19:17:32,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075063758] [2021-12-19 19:17:32,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,766 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075063758] [2021-12-19 19:17:32,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075063758] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:32,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1886531546] [2021-12-19 19:17:32,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,767 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:32,767 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:32,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:32,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:32,768 INFO L87 Difference]: Start difference. First operand 17391 states and 24647 transitions. cyclomatic complexity: 7272 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,045 INFO L93 Difference]: Finished difference Result 46604 states and 65710 transitions. [2021-12-19 19:17:33,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:33,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46604 states and 65710 transitions. [2021-12-19 19:17:33,264 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46105 [2021-12-19 19:17:33,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46604 states to 46604 states and 65710 transitions. [2021-12-19 19:17:33,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46604 [2021-12-19 19:17:33,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46604 [2021-12-19 19:17:33,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46604 states and 65710 transitions. [2021-12-19 19:17:33,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,531 INFO L681 BuchiCegarLoop]: Abstraction has 46604 states and 65710 transitions. [2021-12-19 19:17:33,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46604 states and 65710 transitions. [2021-12-19 19:17:34,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46604 to 45840. [2021-12-19 19:17:34,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45840 states, 45840 states have (on average 1.412347294938918) internal successors, (64742), 45839 states have internal predecessors, (64742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45840 states to 45840 states and 64742 transitions. [2021-12-19 19:17:34,234 INFO L704 BuchiCegarLoop]: Abstraction has 45840 states and 64742 transitions. [2021-12-19 19:17:34,234 INFO L587 BuchiCegarLoop]: Abstraction has 45840 states and 64742 transitions. [2021-12-19 19:17:34,234 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:34,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45840 states and 64742 transitions. [2021-12-19 19:17:34,348 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45565 [2021-12-19 19:17:34,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,350 INFO L791 eck$LassoCheckResult]: Stem: 128054#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 127995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 127996#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127329#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127330#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 127810#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127811#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127768#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127669#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127670#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127661#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127662#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 127618#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127619#L754 assume !(0 == ~M_E~0); 127953#L754-2 assume !(0 == ~T1_E~0); 127541#L759-1 assume !(0 == ~T2_E~0); 127542#L764-1 assume !(0 == ~T3_E~0); 128017#L769-1 assume !(0 == ~T4_E~0); 128018#L774-1 assume !(0 == ~T5_E~0); 127854#L779-1 assume !(0 == ~T6_E~0); 127586#L784-1 assume !(0 == ~T7_E~0); 127587#L789-1 assume !(0 == ~E_1~0); 127241#L794-1 assume !(0 == ~E_2~0); 127242#L799-1 assume !(0 == ~E_3~0); 128021#L804-1 assume !(0 == ~E_4~0); 128022#L809-1 assume !(0 == ~E_5~0); 127674#L814-1 assume !(0 == ~E_6~0); 127162#L819-1 assume !(0 == ~E_7~0); 127163#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127657#L361 assume !(1 == ~m_pc~0); 127658#L361-2 is_master_triggered_~__retres1~0#1 := 0; 127704#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127451#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127452#L930 assume !(0 != activate_threads_~tmp~1#1); 127851#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127650#L380 assume !(1 == ~t1_pc~0); 127651#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 127876#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127877#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 128001#L938 assume !(0 != activate_threads_~tmp___0~0#1); 127369#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127294#L399 assume !(1 == ~t2_pc~0); 127295#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 127509#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127894#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127731#L946 assume !(0 != activate_threads_~tmp___1~0#1); 127202#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127170#L418 assume !(1 == ~t3_pc~0); 127133#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 127134#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127679#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127972#L954 assume !(0 != activate_threads_~tmp___2~0#1); 128036#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127954#L437 assume !(1 == ~t4_pc~0); 127814#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127473#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127296#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 127297#L962 assume !(0 != activate_threads_~tmp___3~0#1); 127782#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127421#L456 assume !(1 == ~t5_pc~0); 127422#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 127538#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127928#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 127189#L970 assume !(0 != activate_threads_~tmp___4~0#1); 127190#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 127309#L475 assume !(1 == ~t6_pc~0); 127310#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 127389#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 127390#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 127154#L978 assume !(0 != activate_threads_~tmp___5~0#1); 127155#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127664#L494 assume !(1 == ~t7_pc~0); 127666#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 127712#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 127917#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 127918#L986 assume !(0 != activate_threads_~tmp___6~0#1); 128049#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127919#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 127734#L837-2 assume !(1 == ~T1_E~0); 127279#L842-1 assume !(1 == ~T2_E~0); 127280#L847-1 assume !(1 == ~T3_E~0); 127806#L852-1 assume !(1 == ~T4_E~0); 127911#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 127744#L862-1 assume !(1 == ~T6_E~0); 127745#L867-1 assume !(1 == ~T7_E~0); 127755#L872-1 assume !(1 == ~E_1~0); 127853#L877-1 assume !(1 == ~E_2~0); 128060#L882-1 assume !(1 == ~E_3~0); 127982#L887-1 assume !(1 == ~E_4~0); 127983#L892-1 assume !(1 == ~E_5~0); 164314#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 164313#L902-1 assume !(1 == ~E_7~0); 127417#L907-1 assume { :end_inline_reset_delta_events } true; 127418#L1148-2 [2021-12-19 19:17:34,350 INFO L793 eck$LassoCheckResult]: Loop: 127418#L1148-2 assume !false; 166711#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 166709#L729 assume !false; 166706#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 166701#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 166695#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 166693#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 166690#L626 assume !(0 != eval_~tmp~0#1); 166691#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 166997#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 166996#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 166995#L754-5 assume !(0 == ~T1_E~0); 166994#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 166993#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 166992#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 166991#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 166990#L779-3 assume !(0 == ~T6_E~0); 166989#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 166988#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 166987#L794-3 assume !(0 == ~E_2~0); 166986#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 166985#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 166984#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 166983#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 166982#L819-3 assume !(0 == ~E_7~0); 166981#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 166980#L361-24 assume !(1 == ~m_pc~0); 166979#L361-26 is_master_triggered_~__retres1~0#1 := 0; 166978#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 166977#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 166976#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 166975#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 166974#L380-24 assume !(1 == ~t1_pc~0); 166973#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 166972#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 166971#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 166970#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 166969#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166968#L399-24 assume !(1 == ~t2_pc~0); 166967#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 166966#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 166965#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 166964#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 166963#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166961#L418-24 assume !(1 == ~t3_pc~0); 166958#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 166956#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 166954#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 166952#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 166950#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 166948#L437-24 assume !(1 == ~t4_pc~0); 166946#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 166944#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 166942#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 166940#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 166938#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166936#L456-24 assume 1 == ~t5_pc~0; 166934#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166931#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 166929#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 166927#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 166925#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 166923#L475-24 assume !(1 == ~t6_pc~0); 166920#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 166918#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 166916#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 166914#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 166912#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 166910#L494-24 assume !(1 == ~t7_pc~0); 166907#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 166905#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 166902#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 166899#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 166895#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 166891#L837-3 assume !(1 == ~M_E~0); 164457#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 166883#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 166879#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 166875#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 166871#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 166867#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 164431#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 166860#L872-3 assume !(1 == ~E_1~0); 166856#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 166852#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 166848#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 166843#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 166839#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 166835#L902-3 assume !(1 == ~E_7~0); 166832#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 166780#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 166770#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 166765#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 166761#L1167 assume !(0 == start_simulation_~tmp~3#1); 166757#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 166749#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 166742#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 166739#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 166734#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 166731#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 166727#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 166721#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 127418#L1148-2 [2021-12-19 19:17:34,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,351 INFO L85 PathProgramCache]: Analyzing trace with hash -2006428668, now seen corresponding path program 1 times [2021-12-19 19:17:34,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652108945] [2021-12-19 19:17:34,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652108945] [2021-12-19 19:17:34,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652108945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:34,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344905309] [2021-12-19 19:17:34,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,369 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,369 INFO L85 PathProgramCache]: Analyzing trace with hash -1960786214, now seen corresponding path program 1 times [2021-12-19 19:17:34,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089186174] [2021-12-19 19:17:34,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089186174] [2021-12-19 19:17:34,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089186174] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,387 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381582131] [2021-12-19 19:17:34,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,388 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,388 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:34,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:34,389 INFO L87 Difference]: Start difference. First operand 45840 states and 64742 transitions. cyclomatic complexity: 18934 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,873 INFO L93 Difference]: Finished difference Result 67600 states and 95394 transitions. [2021-12-19 19:17:34,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:34,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67600 states and 95394 transitions. [2021-12-19 19:17:35,435 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67249 [2021-12-19 19:17:35,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67600 states to 67600 states and 95394 transitions. [2021-12-19 19:17:35,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67600 [2021-12-19 19:17:35,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67600 [2021-12-19 19:17:35,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67600 states and 95394 transitions. [2021-12-19 19:17:36,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:36,084 INFO L681 BuchiCegarLoop]: Abstraction has 67600 states and 95394 transitions. [2021-12-19 19:17:36,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67600 states and 95394 transitions. [2021-12-19 19:17:36,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67600 to 46635. [2021-12-19 19:17:36,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46635 states, 46635 states have (on average 1.415846467245631) internal successors, (66028), 46634 states have internal predecessors, (66028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46635 states to 46635 states and 66028 transitions. [2021-12-19 19:17:36,863 INFO L704 BuchiCegarLoop]: Abstraction has 46635 states and 66028 transitions. [2021-12-19 19:17:36,863 INFO L587 BuchiCegarLoop]: Abstraction has 46635 states and 66028 transitions. [2021-12-19 19:17:36,863 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:36,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46635 states and 66028 transitions. [2021-12-19 19:17:37,265 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46375 [2021-12-19 19:17:37,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,280 INFO L791 eck$LassoCheckResult]: Stem: 241466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 241409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 241410#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 240774#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240775#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 241241#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 241242#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 241202#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 241107#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 241108#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 241100#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 241101#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 241057#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 241058#L754 assume !(0 == ~M_E~0); 241374#L754-2 assume !(0 == ~T1_E~0); 240982#L759-1 assume !(0 == ~T2_E~0); 240983#L764-1 assume !(0 == ~T3_E~0); 241425#L769-1 assume !(0 == ~T4_E~0); 241426#L774-1 assume !(0 == ~T5_E~0); 241285#L779-1 assume !(0 == ~T6_E~0); 241024#L784-1 assume !(0 == ~T7_E~0); 241025#L789-1 assume !(0 == ~E_1~0); 240687#L794-1 assume !(0 == ~E_2~0); 240688#L799-1 assume !(0 == ~E_3~0); 241428#L804-1 assume !(0 == ~E_4~0); 241429#L809-1 assume !(0 == ~E_5~0); 241112#L814-1 assume !(0 == ~E_6~0); 240609#L819-1 assume !(0 == ~E_7~0); 240610#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 241097#L361 assume !(1 == ~m_pc~0); 241098#L361-2 is_master_triggered_~__retres1~0#1 := 0; 241140#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240895#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 240896#L930 assume !(0 != activate_threads_~tmp~1#1); 241282#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 241089#L380 assume !(1 == ~t1_pc~0); 241090#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 241305#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241306#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 241417#L938 assume !(0 != activate_threads_~tmp___0~0#1); 240813#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240741#L399 assume !(1 == ~t2_pc~0); 240742#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 240951#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241321#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 241166#L946 assume !(0 != activate_threads_~tmp___1~0#1); 240647#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240617#L418 assume !(1 == ~t3_pc~0); 240580#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 240581#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241117#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 241390#L954 assume !(0 != activate_threads_~tmp___2~0#1); 241447#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241376#L437 assume !(1 == ~t4_pc~0); 241245#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 240916#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 240743#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 240744#L962 assume !(0 != activate_threads_~tmp___3~0#1); 241214#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240865#L456 assume !(1 == ~t5_pc~0); 240866#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 240979#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241350#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 240635#L970 assume !(0 != activate_threads_~tmp___4~0#1); 240636#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 240756#L475 assume !(1 == ~t6_pc~0); 240757#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 240833#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240834#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 240601#L978 assume !(0 != activate_threads_~tmp___5~0#1); 240602#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241103#L494 assume !(1 == ~t7_pc~0); 241105#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 241147#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 241345#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 241346#L986 assume !(0 != activate_threads_~tmp___6~0#1); 241460#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 241344#L837 assume !(1 == ~M_E~0); 241169#L837-2 assume !(1 == ~T1_E~0); 240725#L842-1 assume !(1 == ~T2_E~0); 240726#L847-1 assume !(1 == ~T3_E~0); 241237#L852-1 assume !(1 == ~T4_E~0); 241336#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 241181#L862-1 assume !(1 == ~T6_E~0); 241182#L867-1 assume !(1 == ~T7_E~0); 241192#L872-1 assume !(1 == ~E_1~0); 241284#L877-1 assume !(1 == ~E_2~0); 241189#L882-1 assume !(1 == ~E_3~0); 241190#L887-1 assume !(1 == ~E_4~0); 240780#L892-1 assume !(1 == ~E_5~0); 240781#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 241208#L902-1 assume !(1 == ~E_7~0); 240861#L907-1 assume { :end_inline_reset_delta_events } true; 240862#L1148-2 [2021-12-19 19:17:37,285 INFO L793 eck$LassoCheckResult]: Loop: 240862#L1148-2 assume !false; 270315#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270313#L729 assume !false; 270311#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270300#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270294#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270292#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 270289#L626 assume !(0 != eval_~tmp~0#1); 270287#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270285#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270283#L754-3 assume !(0 == ~M_E~0); 270281#L754-5 assume !(0 == ~T1_E~0); 270279#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 270277#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270275#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270273#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 270271#L779-3 assume !(0 == ~T6_E~0); 270269#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 270266#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 270264#L794-3 assume !(0 == ~E_2~0); 270262#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 270260#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 270258#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 270256#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 270254#L819-3 assume !(0 == ~E_7~0); 270252#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270250#L361-24 assume !(1 == ~m_pc~0); 270248#L361-26 is_master_triggered_~__retres1~0#1 := 0; 270246#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270244#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270241#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 270239#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270237#L380-24 assume !(1 == ~t1_pc~0); 270235#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 270233#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270231#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270229#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 270227#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270225#L399-24 assume !(1 == ~t2_pc~0); 270223#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 270221#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270218#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270216#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 270214#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270212#L418-24 assume !(1 == ~t3_pc~0); 270209#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 270207#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270205#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270204#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270202#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270200#L437-24 assume !(1 == ~t4_pc~0); 270198#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 270196#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270194#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270192#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 270190#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270188#L456-24 assume !(1 == ~t5_pc~0); 268873#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 268871#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268869#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 268867#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 268865#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 268863#L475-24 assume !(1 == ~t6_pc~0); 268861#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 268859#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268857#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268855#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 268852#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 268850#L494-24 assume !(1 == ~t7_pc~0); 268847#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 268845#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 268843#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268841#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 268840#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268838#L837-3 assume !(1 == ~M_E~0); 262210#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 268835#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 268833#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 268830#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 268828#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 268826#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 268824#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 268822#L872-3 assume !(1 == ~E_1~0); 268820#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 268819#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 268818#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 268814#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268812#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 268810#L902-3 assume !(1 == ~E_7~0); 268808#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 268802#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 268794#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 268792#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 262129#L1167 assume !(0 == start_simulation_~tmp~3#1); 262130#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270811#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270805#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270803#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 270800#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270798#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 270796#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 270794#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 240862#L1148-2 [2021-12-19 19:17:37,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2021-12-19 19:17:37,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691855020] [2021-12-19 19:17:37,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,286 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691855020] [2021-12-19 19:17:37,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691855020] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,578 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,578 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186622103] [2021-12-19 19:17:37,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,578 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,578 INFO L85 PathProgramCache]: Analyzing trace with hash 997676023, now seen corresponding path program 1 times [2021-12-19 19:17:37,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022109308] [2021-12-19 19:17:37,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022109308] [2021-12-19 19:17:37,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022109308] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465968934] [2021-12-19 19:17:37,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,617 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:37,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:37,618 INFO L87 Difference]: Start difference. First operand 46635 states and 66028 transitions. cyclomatic complexity: 19409 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,012 INFO L93 Difference]: Finished difference Result 75194 states and 105781 transitions. [2021-12-19 19:17:38,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:38,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75194 states and 105781 transitions. [2021-12-19 19:17:38,319 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 74775 [2021-12-19 19:17:38,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75194 states to 75194 states and 105781 transitions. [2021-12-19 19:17:38,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75194 [2021-12-19 19:17:38,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75194 [2021-12-19 19:17:38,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75194 states and 105781 transitions. [2021-12-19 19:17:38,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,711 INFO L681 BuchiCegarLoop]: Abstraction has 75194 states and 105781 transitions. [2021-12-19 19:17:38,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75194 states and 105781 transitions. [2021-12-19 19:17:39,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75194 to 54228. [2021-12-19 19:17:39,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54228 states, 54228 states have (on average 1.4101017924319539) internal successors, (76467), 54227 states have internal predecessors, (76467), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54228 states to 54228 states and 76467 transitions. [2021-12-19 19:17:39,428 INFO L704 BuchiCegarLoop]: Abstraction has 54228 states and 76467 transitions. [2021-12-19 19:17:39,428 INFO L587 BuchiCegarLoop]: Abstraction has 54228 states and 76467 transitions. [2021-12-19 19:17:39,428 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:39,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54228 states and 76467 transitions. [2021-12-19 19:17:39,705 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53901 [2021-12-19 19:17:39,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,706 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,707 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,707 INFO L791 eck$LassoCheckResult]: Stem: 363371#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 363287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 363288#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 362617#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 362618#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 363102#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363103#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363055#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 362954#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362955#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 362947#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 362948#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 362905#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 362906#L754 assume !(0 == ~M_E~0); 363237#L754-2 assume !(0 == ~T1_E~0); 362826#L759-1 assume !(0 == ~T2_E~0); 362827#L764-1 assume !(0 == ~T3_E~0); 363310#L769-1 assume !(0 == ~T4_E~0); 363311#L774-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 363147#L779-1 assume !(0 == ~T6_E~0); 362869#L784-1 assume !(0 == ~T7_E~0); 362870#L789-1 assume !(0 == ~E_1~0); 363397#L794-1 assume !(0 == ~E_2~0); 363363#L799-1 assume !(0 == ~E_3~0); 363364#L804-1 assume !(0 == ~E_4~0); 363357#L809-1 assume !(0 == ~E_5~0); 363358#L814-1 assume !(0 == ~E_6~0); 362448#L819-1 assume !(0 == ~E_7~0); 362449#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 362944#L361 assume !(1 == ~m_pc~0); 362945#L361-2 is_master_triggered_~__retres1~0#1 := 0; 363278#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363279#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 363396#L930 assume !(0 != activate_threads_~tmp~1#1); 363205#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363206#L380 assume !(1 == ~t1_pc~0); 363395#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363394#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363294#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 363295#L938 assume !(0 != activate_threads_~tmp___0~0#1); 362657#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362658#L399 assume !(1 == ~t2_pc~0); 363391#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363390#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363313#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 363314#L946 assume !(0 != activate_threads_~tmp___1~0#1); 362488#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 362489#L418 assume !(1 == ~t3_pc~0); 362419#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 362420#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363257#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 363258#L954 assume !(0 != activate_threads_~tmp___2~0#1); 363376#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363238#L437 assume !(1 == ~t4_pc~0); 363106#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363107#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 362586#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 362587#L962 assume !(0 != activate_threads_~tmp___3~0#1); 363070#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363071#L456 assume !(1 == ~t5_pc~0); 362823#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 362822#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363208#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362476#L970 assume !(0 != activate_threads_~tmp___4~0#1); 362477#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363384#L475 assume !(1 == ~t6_pc~0); 363270#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 363271#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363256#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 362440#L978 assume !(0 != activate_threads_~tmp___5~0#1); 362441#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 362950#L494 assume !(1 == ~t7_pc~0); 362952#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 363282#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363283#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 363381#L986 assume !(0 != activate_threads_~tmp___6~0#1); 363359#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363360#L837 assume !(1 == ~M_E~0); 363022#L837-2 assume !(1 == ~T1_E~0); 363023#L842-1 assume !(1 == ~T2_E~0); 363380#L847-1 assume !(1 == ~T3_E~0); 363379#L852-1 assume !(1 == ~T4_E~0); 363378#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 363033#L862-1 assume !(1 == ~T6_E~0); 363034#L867-1 assume !(1 == ~T7_E~0); 363043#L872-1 assume !(1 == ~E_1~0); 363146#L877-1 assume !(1 == ~E_2~0); 363040#L882-1 assume !(1 == ~E_3~0); 363041#L887-1 assume !(1 == ~E_4~0); 362624#L892-1 assume !(1 == ~E_5~0); 362625#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 363063#L902-1 assume !(1 == ~E_7~0); 362704#L907-1 assume { :end_inline_reset_delta_events } true; 362705#L1148-2 [2021-12-19 19:17:39,707 INFO L793 eck$LassoCheckResult]: Loop: 362705#L1148-2 assume !false; 391946#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 391944#L729 assume !false; 391942#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 391927#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 391921#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 391920#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 391918#L626 assume !(0 != eval_~tmp~0#1); 391919#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 403390#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 403388#L754-3 assume !(0 == ~M_E~0); 403386#L754-5 assume !(0 == ~T1_E~0); 403384#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 403381#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 403379#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 403376#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 403377#L779-3 assume !(0 == ~T6_E~0); 408881#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 408879#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 408877#L794-3 assume !(0 == ~E_2~0); 408876#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 408875#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 408874#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 408873#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 408871#L819-3 assume !(0 == ~E_7~0); 408869#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 408868#L361-24 assume !(1 == ~m_pc~0); 408867#L361-26 is_master_triggered_~__retres1~0#1 := 0; 408865#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 408863#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 408861#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 408859#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 408857#L380-24 assume !(1 == ~t1_pc~0); 408855#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 408853#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 408850#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 408848#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 408846#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 408843#L399-24 assume !(1 == ~t2_pc~0); 408841#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 408838#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 408837#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 408834#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 408832#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 408830#L418-24 assume 1 == ~t3_pc~0; 403312#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 403308#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 403306#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 403304#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 403302#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 403300#L437-24 assume !(1 == ~t4_pc~0); 403298#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 403296#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 403294#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 403292#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 403290#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 403288#L456-24 assume 1 == ~t5_pc~0; 403286#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 403282#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 403280#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 403278#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 403276#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 403274#L475-24 assume !(1 == ~t6_pc~0); 403272#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 403270#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 403268#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 403266#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 403264#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 403262#L494-24 assume !(1 == ~t7_pc~0); 403258#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 403256#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 403254#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 403252#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 403250#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 403248#L837-3 assume !(1 == ~M_E~0); 376564#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 403246#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 403244#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 403242#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 403239#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 403238#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 403237#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 403234#L872-3 assume !(1 == ~E_1~0); 403233#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 403232#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 403230#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 403226#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 403225#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 403223#L902-3 assume !(1 == ~E_7~0); 402984#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 402976#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 402966#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 402961#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 376816#L1167 assume !(0 == start_simulation_~tmp~3#1); 376817#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 391979#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 391973#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 391971#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 391969#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 391967#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 391965#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 391963#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 362705#L1148-2 [2021-12-19 19:17:39,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,708 INFO L85 PathProgramCache]: Analyzing trace with hash -466634176, now seen corresponding path program 1 times [2021-12-19 19:17:39,708 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668892312] [2021-12-19 19:17:39,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668892312] [2021-12-19 19:17:39,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668892312] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309720818] [2021-12-19 19:17:39,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,732 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,732 INFO L85 PathProgramCache]: Analyzing trace with hash -847639111, now seen corresponding path program 1 times [2021-12-19 19:17:39,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696600617] [2021-12-19 19:17:39,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696600617] [2021-12-19 19:17:39,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696600617] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,748 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076312517] [2021-12-19 19:17:39,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,748 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,748 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:39,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:39,749 INFO L87 Difference]: Start difference. First operand 54228 states and 76467 transitions. cyclomatic complexity: 22255 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,968 INFO L93 Difference]: Finished difference Result 67591 states and 94944 transitions. [2021-12-19 19:17:39,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67591 states and 94944 transitions. [2021-12-19 19:17:40,520 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67249 [2021-12-19 19:17:40,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67591 states to 67591 states and 94944 transitions. [2021-12-19 19:17:40,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67591 [2021-12-19 19:17:40,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67591 [2021-12-19 19:17:40,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67591 states and 94944 transitions. [2021-12-19 19:17:40,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:40,817 INFO L681 BuchiCegarLoop]: Abstraction has 67591 states and 94944 transitions. [2021-12-19 19:17:40,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67591 states and 94944 transitions. [2021-12-19 19:17:41,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67591 to 46635. [2021-12-19 19:17:41,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46635 states, 46635 states have (on average 1.4088560094349738) internal successors, (65702), 46634 states have internal predecessors, (65702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46635 states to 46635 states and 65702 transitions. [2021-12-19 19:17:41,870 INFO L704 BuchiCegarLoop]: Abstraction has 46635 states and 65702 transitions. [2021-12-19 19:17:41,871 INFO L587 BuchiCegarLoop]: Abstraction has 46635 states and 65702 transitions. [2021-12-19 19:17:41,871 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:41,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46635 states and 65702 transitions. [2021-12-19 19:17:42,004 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46375 [2021-12-19 19:17:42,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:42,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:42,006 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,006 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,006 INFO L791 eck$LassoCheckResult]: Stem: 485136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 485078#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 485079#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 484442#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 484443#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 484911#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 484912#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 484866#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 484771#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 484772#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 484764#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 484765#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 484721#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 484722#L754 assume !(0 == ~M_E~0); 485044#L754-2 assume !(0 == ~T1_E~0); 484648#L759-1 assume !(0 == ~T2_E~0); 484649#L764-1 assume !(0 == ~T3_E~0); 485097#L769-1 assume !(0 == ~T4_E~0); 485098#L774-1 assume !(0 == ~T5_E~0); 484957#L779-1 assume !(0 == ~T6_E~0); 484689#L784-1 assume !(0 == ~T7_E~0); 484690#L789-1 assume !(0 == ~E_1~0); 484355#L794-1 assume !(0 == ~E_2~0); 484356#L799-1 assume !(0 == ~E_3~0); 485103#L804-1 assume !(0 == ~E_4~0); 485104#L809-1 assume !(0 == ~E_5~0); 484776#L814-1 assume !(0 == ~E_6~0); 484277#L819-1 assume !(0 == ~E_7~0); 484278#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484761#L361 assume !(1 == ~m_pc~0); 484762#L361-2 is_master_triggered_~__retres1~0#1 := 0; 484804#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484565#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 484566#L930 assume !(0 != activate_threads_~tmp~1#1); 484953#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 484753#L380 assume !(1 == ~t1_pc~0); 484754#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 484980#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 484981#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 485087#L938 assume !(0 != activate_threads_~tmp___0~0#1); 484482#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 484408#L399 assume !(1 == ~t2_pc~0); 484409#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 484619#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 484996#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 484829#L946 assume !(0 != activate_threads_~tmp___1~0#1); 484315#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484285#L418 assume !(1 == ~t3_pc~0); 484248#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 484249#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484781#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 485060#L954 assume !(0 != activate_threads_~tmp___2~0#1); 485120#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485046#L437 assume !(1 == ~t4_pc~0); 484915#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 484587#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484410#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 484411#L962 assume !(0 != activate_threads_~tmp___3~0#1); 484879#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 484535#L456 assume !(1 == ~t5_pc~0); 484536#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 484645#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 485022#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 484303#L970 assume !(0 != activate_threads_~tmp___4~0#1); 484304#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 484423#L475 assume !(1 == ~t6_pc~0); 484424#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 484503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 484504#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 484269#L978 assume !(0 != activate_threads_~tmp___5~0#1); 484270#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 484767#L494 assume !(1 == ~t7_pc~0); 484769#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 484811#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 485016#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 485017#L986 assume !(0 != activate_threads_~tmp___6~0#1); 485133#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 485015#L837 assume !(1 == ~M_E~0); 484832#L837-2 assume !(1 == ~T1_E~0); 484393#L842-1 assume !(1 == ~T2_E~0); 484394#L847-1 assume !(1 == ~T3_E~0); 484906#L852-1 assume !(1 == ~T4_E~0); 485010#L857-1 assume !(1 == ~T5_E~0); 484843#L862-1 assume !(1 == ~T6_E~0); 484844#L867-1 assume !(1 == ~T7_E~0); 484855#L872-1 assume !(1 == ~E_1~0); 484956#L877-1 assume !(1 == ~E_2~0); 484852#L882-1 assume !(1 == ~E_3~0); 484853#L887-1 assume !(1 == ~E_4~0); 484449#L892-1 assume !(1 == ~E_5~0); 484450#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 484873#L902-1 assume !(1 == ~E_7~0); 484531#L907-1 assume { :end_inline_reset_delta_events } true; 484532#L1148-2 [2021-12-19 19:17:42,007 INFO L793 eck$LassoCheckResult]: Loop: 484532#L1148-2 assume !false; 509044#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 509043#L729 assume !false; 509042#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 509038#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 509033#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 509032#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 509028#L626 assume !(0 != eval_~tmp~0#1); 509024#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 509020#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 509015#L754-3 assume !(0 == ~M_E~0); 509010#L754-5 assume !(0 == ~T1_E~0); 509005#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 509004#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 509000#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 508994#L774-3 assume !(0 == ~T5_E~0); 508992#L779-3 assume !(0 == ~T6_E~0); 508990#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 508989#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 508988#L794-3 assume !(0 == ~E_2~0); 508987#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 508986#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 508985#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 508976#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 508974#L819-3 assume !(0 == ~E_7~0); 508972#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508969#L361-24 assume !(1 == ~m_pc~0); 508967#L361-26 is_master_triggered_~__retres1~0#1 := 0; 508965#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 508963#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 508961#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 508959#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 508957#L380-24 assume !(1 == ~t1_pc~0); 508955#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 508953#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 508951#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 508949#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 508947#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508945#L399-24 assume !(1 == ~t2_pc~0); 508943#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 508941#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 508939#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 508937#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 508935#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 508933#L418-24 assume 1 == ~t3_pc~0; 508931#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 508928#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508926#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 508924#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 508922#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 508920#L437-24 assume !(1 == ~t4_pc~0); 508918#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 508916#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508914#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 508912#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 508910#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 508908#L456-24 assume 1 == ~t5_pc~0; 508906#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 508903#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 508901#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 508899#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 508897#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508895#L475-24 assume !(1 == ~t6_pc~0); 508893#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 508890#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 508888#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 508886#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 508884#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 508882#L494-24 assume !(1 == ~t7_pc~0); 508879#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 508878#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508875#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 508102#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 508101#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508100#L837-3 assume !(1 == ~M_E~0); 501780#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 508097#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 508095#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 508094#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 508093#L857-3 assume !(1 == ~T5_E~0); 508092#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 508091#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 508090#L872-3 assume !(1 == ~E_1~0); 508089#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 508088#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 508087#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 508086#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 508085#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 508084#L902-3 assume !(1 == ~E_7~0); 508083#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 508081#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 508074#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 508073#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 501983#L1167 assume !(0 == start_simulation_~tmp~3#1); 501984#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 509203#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 509197#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 509195#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 509193#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509189#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 509187#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 509185#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 484532#L1148-2 [2021-12-19 19:17:42,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2021-12-19 19:17:42,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453026412] [2021-12-19 19:17:42,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,031 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453026412] [2021-12-19 19:17:42,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453026412] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,031 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,031 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,031 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763201616] [2021-12-19 19:17:42,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,032 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:42,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1055613629, now seen corresponding path program 1 times [2021-12-19 19:17:42,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823828074] [2021-12-19 19:17:42,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,052 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823828074] [2021-12-19 19:17:42,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823828074] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,052 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968908212] [2021-12-19 19:17:42,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:42,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:42,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:42,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:42,054 INFO L87 Difference]: Start difference. First operand 46635 states and 65702 transitions. cyclomatic complexity: 19083 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:42,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:42,280 INFO L93 Difference]: Finished difference Result 72629 states and 101784 transitions. [2021-12-19 19:17:42,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:42,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72629 states and 101784 transitions. [2021-12-19 19:17:42,800 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72164 [2021-12-19 19:17:42,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72629 states to 72629 states and 101784 transitions. [2021-12-19 19:17:42,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72629 [2021-12-19 19:17:43,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72629 [2021-12-19 19:17:43,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72629 states and 101784 transitions. [2021-12-19 19:17:43,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:43,059 INFO L681 BuchiCegarLoop]: Abstraction has 72629 states and 101784 transitions. [2021-12-19 19:17:43,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72629 states and 101784 transitions. [2021-12-19 19:17:43,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72629 to 54192. [2021-12-19 19:17:43,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54192 states, 54192 states have (on average 1.4009632418069087) internal successors, (75921), 54191 states have internal predecessors, (75921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:43,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54192 states to 54192 states and 75921 transitions. [2021-12-19 19:17:43,811 INFO L704 BuchiCegarLoop]: Abstraction has 54192 states and 75921 transitions. [2021-12-19 19:17:43,811 INFO L587 BuchiCegarLoop]: Abstraction has 54192 states and 75921 transitions. [2021-12-19 19:17:43,811 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:43,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54192 states and 75921 transitions. [2021-12-19 19:17:43,987 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53865 [2021-12-19 19:17:43,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:43,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:43,988 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:43,988 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:43,989 INFO L791 eck$LassoCheckResult]: Stem: 604468#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 604397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 604398#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 603715#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 603716#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 604211#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 604212#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 604167#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 604057#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 604058#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 604050#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 604051#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 604004#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 604005#L754 assume !(0 == ~M_E~0); 604348#L754-2 assume !(0 == ~T1_E~0); 603924#L759-1 assume !(0 == ~T2_E~0); 603925#L764-1 assume !(0 == ~T3_E~0); 604414#L769-1 assume !(0 == ~T4_E~0); 604415#L774-1 assume !(0 == ~T5_E~0); 604254#L779-1 assume !(0 == ~T6_E~0); 603968#L784-1 assume !(0 == ~T7_E~0); 603969#L789-1 assume !(0 == ~E_1~0); 603629#L794-1 assume !(0 == ~E_2~0); 603630#L799-1 assume !(0 == ~E_3~0); 604422#L804-1 assume !(0 == ~E_4~0); 604423#L809-1 assume !(0 == ~E_5~0); 604062#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 603551#L819-1 assume !(0 == ~E_7~0); 603552#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 604047#L361 assume !(1 == ~m_pc~0); 604048#L361-2 is_master_triggered_~__retres1~0#1 := 0; 604391#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 604392#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 604491#L930 assume !(0 != activate_threads_~tmp~1#1); 604312#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604313#L380 assume !(1 == ~t1_pc~0); 604460#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 604275#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604276#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 604467#L938 assume !(0 != activate_threads_~tmp___0~0#1); 603755#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603756#L399 assume !(1 == ~t2_pc~0); 603892#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 603893#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 604289#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 604123#L946 assume !(0 != activate_threads_~tmp___1~0#1); 604124#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603559#L418 assume !(1 == ~t3_pc~0); 603560#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 604068#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 604069#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 604472#L954 assume !(0 != activate_threads_~tmp___2~0#1); 604473#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 604351#L437 assume !(1 == ~t4_pc~0); 604215#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 604216#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603685#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603686#L962 assume !(0 != activate_threads_~tmp___3~0#1); 604192#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603807#L456 assume !(1 == ~t5_pc~0); 603808#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 604332#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 604333#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 604485#L970 assume !(0 != activate_threads_~tmp___4~0#1); 604420#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 604421#L475 assume !(1 == ~t6_pc~0); 604383#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 604384#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 604369#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 604370#L978 assume !(0 != activate_threads_~tmp___5~0#1); 604427#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 604428#L494 assume !(1 == ~t7_pc~0); 604101#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 604102#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 604305#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 604306#L986 assume !(0 != activate_threads_~tmp___6~0#1); 604455#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 604456#L837 assume !(1 == ~M_E~0); 604127#L837-2 assume !(1 == ~T1_E~0); 604128#L842-1 assume !(1 == ~T2_E~0); 604483#L847-1 assume !(1 == ~T3_E~0); 604482#L852-1 assume !(1 == ~T4_E~0); 604477#L857-1 assume !(1 == ~T5_E~0); 604478#L862-1 assume !(1 == ~T6_E~0); 604154#L867-1 assume !(1 == ~T7_E~0); 604155#L872-1 assume !(1 == ~E_1~0); 604253#L877-1 assume !(1 == ~E_2~0); 604151#L882-1 assume !(1 == ~E_3~0); 604152#L887-1 assume !(1 == ~E_4~0); 604480#L892-1 assume !(1 == ~E_5~0); 604479#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 604172#L902-1 assume !(1 == ~E_7~0); 603803#L907-1 assume { :end_inline_reset_delta_events } true; 603804#L1148-2 [2021-12-19 19:17:43,989 INFO L793 eck$LassoCheckResult]: Loop: 603804#L1148-2 assume !false; 630720#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630718#L729 assume !false; 630716#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 630685#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 630678#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 630648#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 630639#L626 assume !(0 != eval_~tmp~0#1); 630631#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 630621#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 630613#L754-3 assume !(0 == ~M_E~0); 630605#L754-5 assume !(0 == ~T1_E~0); 630598#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 630592#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 630583#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 630574#L774-3 assume !(0 == ~T5_E~0); 630566#L779-3 assume !(0 == ~T6_E~0); 630558#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 630550#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 630542#L794-3 assume !(0 == ~E_2~0); 630533#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 630524#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 630516#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 630507#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 630506#L819-3 assume !(0 == ~E_7~0); 630505#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630504#L361-24 assume !(1 == ~m_pc~0); 630503#L361-26 is_master_triggered_~__retres1~0#1 := 0; 630502#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630501#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 630500#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630499#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630498#L380-24 assume !(1 == ~t1_pc~0); 630497#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 630496#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630495#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 630494#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 630493#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630492#L399-24 assume !(1 == ~t2_pc~0); 630491#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 630490#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630489#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 630488#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 630487#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630486#L418-24 assume 1 == ~t3_pc~0; 630485#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 630483#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630482#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630481#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 630480#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 630479#L437-24 assume !(1 == ~t4_pc~0); 630478#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 630477#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630476#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630475#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 630474#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630473#L456-24 assume 1 == ~t5_pc~0; 630472#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 630470#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630469#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 630468#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 630467#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630466#L475-24 assume !(1 == ~t6_pc~0); 630465#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 630464#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630463#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630462#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 630461#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 630460#L494-24 assume !(1 == ~t7_pc~0); 630458#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 630457#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 630456#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630455#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 630454#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 630453#L837-3 assume !(1 == ~M_E~0); 630130#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 630452#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 630451#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 630450#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 630449#L857-3 assume !(1 == ~T5_E~0); 630448#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 630447#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 630446#L872-3 assume !(1 == ~E_1~0); 630445#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 630444#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 630443#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 630442#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 630440#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 630433#L902-3 assume !(1 == ~E_7~0); 630292#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 630280#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 630255#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 630250#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 630088#L1167 assume !(0 == start_simulation_~tmp~3#1); 630089#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 630743#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 630737#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 630735#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 630733#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 630731#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630729#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 630727#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 603804#L1148-2 [2021-12-19 19:17:43,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:43,989 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2021-12-19 19:17:43,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:43,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223252653] [2021-12-19 19:17:43,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:43,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:43,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:44,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:44,023 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:44,024 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223252653] [2021-12-19 19:17:44,024 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223252653] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:44,024 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:44,024 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:44,024 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686295163] [2021-12-19 19:17:44,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:44,024 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:44,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:44,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1055613629, now seen corresponding path program 2 times [2021-12-19 19:17:44,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:44,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227991668] [2021-12-19 19:17:44,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:44,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:44,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:44,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:44,055 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:44,055 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227991668] [2021-12-19 19:17:44,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227991668] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:44,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:44,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:44,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236484124] [2021-12-19 19:17:44,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:44,056 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:44,057 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:44,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:44,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:44,057 INFO L87 Difference]: Start difference. First operand 54192 states and 75921 transitions. cyclomatic complexity: 21745 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:44,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:44,267 INFO L93 Difference]: Finished difference Result 64638 states and 90459 transitions. [2021-12-19 19:17:44,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:44,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64638 states and 90459 transitions. [2021-12-19 19:17:44,830 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 64242 [2021-12-19 19:17:45,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64638 states to 64638 states and 90459 transitions. [2021-12-19 19:17:45,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64638 [2021-12-19 19:17:45,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64638 [2021-12-19 19:17:45,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64638 states and 90459 transitions. [2021-12-19 19:17:45,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:45,110 INFO L681 BuchiCegarLoop]: Abstraction has 64638 states and 90459 transitions. [2021-12-19 19:17:45,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64638 states and 90459 transitions. [2021-12-19 19:17:45,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64638 to 46635. [2021-12-19 19:17:45,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46635 states, 46635 states have (on average 1.3979200171544977) internal successors, (65192), 46634 states have internal predecessors, (65192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:45,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46635 states to 46635 states and 65192 transitions. [2021-12-19 19:17:45,646 INFO L704 BuchiCegarLoop]: Abstraction has 46635 states and 65192 transitions. [2021-12-19 19:17:45,647 INFO L587 BuchiCegarLoop]: Abstraction has 46635 states and 65192 transitions. [2021-12-19 19:17:45,647 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:45,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46635 states and 65192 transitions. [2021-12-19 19:17:45,778 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46375 [2021-12-19 19:17:45,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:45,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:45,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,780 INFO L791 eck$LassoCheckResult]: Stem: 723260#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 723203#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 723204#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 722552#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 722553#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 723032#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 723033#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 722986#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 722890#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 722891#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 722883#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 722884#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 722839#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 722840#L754 assume !(0 == ~M_E~0); 723161#L754-2 assume !(0 == ~T1_E~0); 722762#L759-1 assume !(0 == ~T2_E~0); 722763#L764-1 assume !(0 == ~T3_E~0); 723220#L769-1 assume !(0 == ~T4_E~0); 723221#L774-1 assume !(0 == ~T5_E~0); 723075#L779-1 assume !(0 == ~T6_E~0); 722805#L784-1 assume !(0 == ~T7_E~0); 722806#L789-1 assume !(0 == ~E_1~0); 722467#L794-1 assume !(0 == ~E_2~0); 722468#L799-1 assume !(0 == ~E_3~0); 723225#L804-1 assume !(0 == ~E_4~0); 723226#L809-1 assume !(0 == ~E_5~0); 722896#L814-1 assume !(0 == ~E_6~0); 722391#L819-1 assume !(0 == ~E_7~0); 722392#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 722880#L361 assume !(1 == ~m_pc~0); 722881#L361-2 is_master_triggered_~__retres1~0#1 := 0; 722926#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 722675#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 722676#L930 assume !(0 != activate_threads_~tmp~1#1); 723070#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 722872#L380 assume !(1 == ~t1_pc~0); 722873#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 723096#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 723097#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 723209#L938 assume !(0 != activate_threads_~tmp___0~0#1); 722592#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 722520#L399 assume !(1 == ~t2_pc~0); 722521#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 722729#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 723111#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 722951#L946 assume !(0 != activate_threads_~tmp___1~0#1); 722429#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 722399#L418 assume !(1 == ~t3_pc~0); 722362#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 722363#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 722900#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 723182#L954 assume !(0 != activate_threads_~tmp___2~0#1); 723242#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 723163#L437 assume !(1 == ~t4_pc~0); 723036#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 722697#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 722522#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 722523#L962 assume !(0 != activate_threads_~tmp___3~0#1); 723003#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 722645#L456 assume !(1 == ~t5_pc~0); 722646#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 722759#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 723137#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 722417#L970 assume !(0 != activate_threads_~tmp___4~0#1); 722418#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 722535#L475 assume !(1 == ~t6_pc~0); 722536#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 722612#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 722613#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 722383#L978 assume !(0 != activate_threads_~tmp___5~0#1); 722384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 722886#L494 assume !(1 == ~t7_pc~0); 722888#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 722932#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 723130#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 723131#L986 assume !(0 != activate_threads_~tmp___6~0#1); 723254#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 723129#L837 assume !(1 == ~M_E~0); 722954#L837-2 assume !(1 == ~T1_E~0); 722505#L842-1 assume !(1 == ~T2_E~0); 722506#L847-1 assume !(1 == ~T3_E~0); 723028#L852-1 assume !(1 == ~T4_E~0); 723122#L857-1 assume !(1 == ~T5_E~0); 722966#L862-1 assume !(1 == ~T6_E~0); 722967#L867-1 assume !(1 == ~T7_E~0); 722975#L872-1 assume !(1 == ~E_1~0); 723074#L877-1 assume !(1 == ~E_2~0); 722973#L882-1 assume !(1 == ~E_3~0); 722974#L887-1 assume !(1 == ~E_4~0); 722559#L892-1 assume !(1 == ~E_5~0); 722560#L897-1 assume !(1 == ~E_6~0); 722997#L902-1 assume !(1 == ~E_7~0); 722641#L907-1 assume { :end_inline_reset_delta_events } true; 722642#L1148-2 [2021-12-19 19:17:45,781 INFO L793 eck$LassoCheckResult]: Loop: 722642#L1148-2 assume !false; 757972#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 757971#L729 assume !false; 757970#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 757852#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 757846#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 757844#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 757841#L626 assume !(0 != eval_~tmp~0#1); 757839#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 757836#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 757834#L754-3 assume !(0 == ~M_E~0); 757832#L754-5 assume !(0 == ~T1_E~0); 757556#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 757553#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 757551#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 757549#L774-3 assume !(0 == ~T5_E~0); 757547#L779-3 assume !(0 == ~T6_E~0); 757545#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 757543#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 757541#L794-3 assume !(0 == ~E_2~0); 757539#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 757537#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 757535#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 757533#L814-3 assume !(0 == ~E_6~0); 757531#L819-3 assume !(0 == ~E_7~0); 757529#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 757527#L361-24 assume !(1 == ~m_pc~0); 757525#L361-26 is_master_triggered_~__retres1~0#1 := 0; 757523#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 757521#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 757519#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 757517#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 757514#L380-24 assume !(1 == ~t1_pc~0); 757512#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 757510#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 757508#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 757506#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 757503#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 757500#L399-24 assume !(1 == ~t2_pc~0); 757498#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 757496#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 757494#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 757492#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 757490#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757487#L418-24 assume 1 == ~t3_pc~0; 757485#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 757482#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 757480#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 757478#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 757475#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 757473#L437-24 assume !(1 == ~t4_pc~0); 757471#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 757469#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 757467#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 757465#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 757463#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 757460#L456-24 assume 1 == ~t5_pc~0; 757458#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 757455#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 757453#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 757451#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 757449#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 757448#L475-24 assume !(1 == ~t6_pc~0); 757446#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 757442#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 757440#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 757438#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 757437#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 757436#L494-24 assume !(1 == ~t7_pc~0); 757430#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 757427#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757425#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 757422#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 757419#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 757416#L837-3 assume !(1 == ~M_E~0); 739660#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 757411#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 757408#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 757405#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 757402#L857-3 assume !(1 == ~T5_E~0); 757399#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 757396#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 757393#L872-3 assume !(1 == ~E_1~0); 757390#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 757387#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 757384#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 757381#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 757378#L897-3 assume !(1 == ~E_6~0); 757375#L902-3 assume !(1 == ~E_7~0); 757372#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 757358#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 757349#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 757346#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 739768#L1167 assume !(0 == start_simulation_~tmp~3#1); 739769#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 758097#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 758092#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 758090#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 758088#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 758086#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 758084#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 758082#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 722642#L1148-2 [2021-12-19 19:17:45,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2021-12-19 19:17:45,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728472110] [2021-12-19 19:17:45,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:45,788 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:45,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:45,846 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:45,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,847 INFO L85 PathProgramCache]: Analyzing trace with hash 15989697, now seen corresponding path program 1 times [2021-12-19 19:17:45,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412985414] [2021-12-19 19:17:45,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:45,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:45,879 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:45,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412985414] [2021-12-19 19:17:45,879 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412985414] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:45,879 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:45,879 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:45,880 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965680549] [2021-12-19 19:17:45,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:45,880 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:45,880 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:45,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:45,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:45,881 INFO L87 Difference]: Start difference. First operand 46635 states and 65192 transitions. cyclomatic complexity: 18573 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:46,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:46,279 INFO L93 Difference]: Finished difference Result 65588 states and 91102 transitions. [2021-12-19 19:17:46,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:46,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65588 states and 91102 transitions. [2021-12-19 19:17:46,516 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65229 [2021-12-19 19:17:46,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65588 states to 65588 states and 91102 transitions. [2021-12-19 19:17:46,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65588 [2021-12-19 19:17:46,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65588 [2021-12-19 19:17:46,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65588 states and 91102 transitions. [2021-12-19 19:17:46,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:46,758 INFO L681 BuchiCegarLoop]: Abstraction has 65588 states and 91102 transitions. [2021-12-19 19:17:46,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65588 states and 91102 transitions. [2021-12-19 19:17:47,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65588 to 65492. [2021-12-19 19:17:47,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65492 states, 65492 states have (on average 1.3893299945031454) internal successors, (90990), 65491 states have internal predecessors, (90990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:47,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65492 states to 65492 states and 90990 transitions. [2021-12-19 19:17:47,604 INFO L704 BuchiCegarLoop]: Abstraction has 65492 states and 90990 transitions. [2021-12-19 19:17:47,604 INFO L587 BuchiCegarLoop]: Abstraction has 65492 states and 90990 transitions. [2021-12-19 19:17:47,604 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:47,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65492 states and 90990 transitions. [2021-12-19 19:17:47,764 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65165 [2021-12-19 19:17:47,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:47,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:47,767 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:47,767 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:47,768 INFO L791 eck$LassoCheckResult]: Stem: 835567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 835484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 835485#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 834784#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 834785#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 835287#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 835288#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 835240#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 835131#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 835132#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 835122#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 835123#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 835076#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 835077#L754 assume !(0 == ~M_E~0); 835436#L754-2 assume !(0 == ~T1_E~0); 834995#L759-1 assume !(0 == ~T2_E~0); 834996#L764-1 assume !(0 == ~T3_E~0); 835506#L769-1 assume !(0 == ~T4_E~0); 835507#L774-1 assume !(0 == ~T5_E~0); 835339#L779-1 assume !(0 == ~T6_E~0); 835039#L784-1 assume !(0 == ~T7_E~0); 835040#L789-1 assume 0 == ~E_1~0;~E_1~0 := 1; 835504#L794-1 assume !(0 == ~E_2~0); 835559#L799-1 assume !(0 == ~E_3~0); 835560#L804-1 assume !(0 == ~E_4~0); 835552#L809-1 assume !(0 == ~E_5~0); 835553#L814-1 assume !(0 == ~E_6~0); 834624#L819-1 assume !(0 == ~E_7~0); 834625#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 835118#L361 assume !(1 == ~m_pc~0); 835119#L361-2 is_master_triggered_~__retres1~0#1 := 0; 835476#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 835477#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 835597#L930 assume !(0 != activate_threads_~tmp~1#1); 835401#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 835402#L380 assume !(1 == ~t1_pc~0); 835563#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 835360#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 835361#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 835566#L938 assume !(0 != activate_threads_~tmp___0~0#1); 834823#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 834824#L399 assume !(1 == ~t2_pc~0); 834961#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 834962#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 835372#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 835196#L946 assume !(0 != activate_threads_~tmp___1~0#1); 835197#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 834631#L418 assume !(1 == ~t3_pc~0); 834632#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 835142#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 835143#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 835593#L954 assume !(0 != activate_threads_~tmp___2~0#1); 835535#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 835536#L437 assume !(1 == ~t4_pc~0); 835592#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 834929#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 834930#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 835591#L962 assume !(0 != activate_threads_~tmp___3~0#1); 835590#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 834880#L456 assume !(1 == ~t5_pc~0); 834881#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 835422#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 835423#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 835589#L970 assume !(0 != activate_threads_~tmp___4~0#1); 835510#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 835511#L475 assume !(1 == ~t6_pc~0); 835470#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 835471#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 835452#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 834612#L978 assume !(0 != activate_threads_~tmp___5~0#1); 834613#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 835124#L494 assume !(1 == ~t7_pc~0); 835126#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 835478#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 835479#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 835586#L986 assume !(0 != activate_threads_~tmp___6~0#1); 835554#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 835555#L837 assume !(1 == ~M_E~0); 835200#L837-2 assume !(1 == ~T1_E~0); 835201#L842-1 assume !(1 == ~T2_E~0); 835585#L847-1 assume !(1 == ~T3_E~0); 835388#L852-1 assume !(1 == ~T4_E~0); 835389#L857-1 assume !(1 == ~T5_E~0); 835213#L862-1 assume !(1 == ~T6_E~0); 835214#L867-1 assume !(1 == ~T7_E~0); 835228#L872-1 assume 1 == ~E_1~0;~E_1~0 := 2; 835336#L877-1 assume !(1 == ~E_2~0); 835222#L882-1 assume !(1 == ~E_3~0); 835223#L887-1 assume !(1 == ~E_4~0); 834791#L892-1 assume !(1 == ~E_5~0); 834792#L897-1 assume !(1 == ~E_6~0); 835249#L902-1 assume !(1 == ~E_7~0); 834873#L907-1 assume { :end_inline_reset_delta_events } true; 834874#L1148-2 [2021-12-19 19:17:47,768 INFO L793 eck$LassoCheckResult]: Loop: 834874#L1148-2 assume !false; 867648#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867647#L729 assume !false; 867646#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 867642#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 867637#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 867636#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 867634#L626 assume !(0 != eval_~tmp~0#1); 867633#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 867632#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 867631#L754-3 assume !(0 == ~M_E~0); 867629#L754-5 assume !(0 == ~T1_E~0); 867627#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 867625#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 867623#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 867621#L774-3 assume !(0 == ~T5_E~0); 867619#L779-3 assume !(0 == ~T6_E~0); 867617#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 867614#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 867612#L794-3 assume !(0 == ~E_2~0); 867610#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 867608#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 867606#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 867604#L814-3 assume !(0 == ~E_6~0); 867602#L819-3 assume !(0 == ~E_7~0); 867600#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 867598#L361-24 assume !(1 == ~m_pc~0); 867596#L361-26 is_master_triggered_~__retres1~0#1 := 0; 867594#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 867592#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 867590#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 867588#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 867586#L380-24 assume !(1 == ~t1_pc~0); 867584#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 867582#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 867580#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 867577#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 867575#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 867573#L399-24 assume !(1 == ~t2_pc~0); 867571#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 867569#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 867567#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 867565#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 867563#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 867561#L418-24 assume 1 == ~t3_pc~0; 867559#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 867556#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 867554#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 867551#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 867549#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 867547#L437-24 assume !(1 == ~t4_pc~0); 867545#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 867543#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 867541#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 867539#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 867537#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 867535#L456-24 assume 1 == ~t5_pc~0; 867533#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 867530#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 867527#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 867525#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 867523#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 867521#L475-24 assume !(1 == ~t6_pc~0); 867519#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 867517#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 867513#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 867511#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 867509#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867507#L494-24 assume !(1 == ~t7_pc~0); 867504#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 867502#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 867500#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 867498#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 867497#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 867496#L837-3 assume !(1 == ~M_E~0); 867355#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 867493#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 867491#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 867489#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 867487#L857-3 assume !(1 == ~T5_E~0); 867485#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 867483#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 867481#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 867478#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 867475#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 867473#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 867471#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 867469#L897-3 assume !(1 == ~E_6~0); 867467#L902-3 assume !(1 == ~E_7~0); 867465#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 867459#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 867451#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 867449#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 867446#L1167 assume !(0 == start_simulation_~tmp~3#1); 867447#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 867820#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 867814#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 867812#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 867810#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 867808#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 867806#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 867804#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 834874#L1148-2 [2021-12-19 19:17:47,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:47,769 INFO L85 PathProgramCache]: Analyzing trace with hash -1593984694, now seen corresponding path program 1 times [2021-12-19 19:17:47,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:47,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464330797] [2021-12-19 19:17:47,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:47,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:47,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:47,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:47,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:47,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464330797] [2021-12-19 19:17:47,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464330797] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:47,798 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:47,798 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:47,798 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025607352] [2021-12-19 19:17:47,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:47,799 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:47,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:47,799 INFO L85 PathProgramCache]: Analyzing trace with hash 833638147, now seen corresponding path program 1 times [2021-12-19 19:17:47,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:47,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365098217] [2021-12-19 19:17:47,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:47,799 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:47,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:47,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:47,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:47,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365098217] [2021-12-19 19:17:47,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365098217] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:47,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:47,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:47,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337888531] [2021-12-19 19:17:47,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:47,819 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:47,819 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:47,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:47,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:47,820 INFO L87 Difference]: Start difference. First operand 65492 states and 90990 transitions. cyclomatic complexity: 25514 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:47,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:47,938 INFO L93 Difference]: Finished difference Result 46059 states and 63890 transitions. [2021-12-19 19:17:47,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:47,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46059 states and 63890 transitions. [2021-12-19 19:17:48,106 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45799 [2021-12-19 19:17:48,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46059 states to 46059 states and 63890 transitions. [2021-12-19 19:17:48,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46059 [2021-12-19 19:17:48,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46059 [2021-12-19 19:17:48,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46059 states and 63890 transitions. [2021-12-19 19:17:48,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:48,293 INFO L681 BuchiCegarLoop]: Abstraction has 46059 states and 63890 transitions. [2021-12-19 19:17:48,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46059 states and 63890 transitions. [2021-12-19 19:17:48,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46059 to 46059. [2021-12-19 19:17:49,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46059 states, 46059 states have (on average 1.387133893484444) internal successors, (63890), 46058 states have internal predecessors, (63890), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:49,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46059 states to 46059 states and 63890 transitions. [2021-12-19 19:17:49,099 INFO L704 BuchiCegarLoop]: Abstraction has 46059 states and 63890 transitions. [2021-12-19 19:17:49,099 INFO L587 BuchiCegarLoop]: Abstraction has 46059 states and 63890 transitions. [2021-12-19 19:17:49,099 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:49,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46059 states and 63890 transitions. [2021-12-19 19:17:49,223 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45799 [2021-12-19 19:17:49,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:49,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:49,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:49,224 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:49,225 INFO L791 eck$LassoCheckResult]: Stem: 947035#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 946975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 946976#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 946342#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 946343#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 946813#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 946814#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 946768#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 946672#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 946673#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 946662#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 946663#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 946617#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 946618#L754 assume !(0 == ~M_E~0); 946944#L754-2 assume !(0 == ~T1_E~0); 946548#L759-1 assume !(0 == ~T2_E~0); 946549#L764-1 assume !(0 == ~T3_E~0); 946992#L769-1 assume !(0 == ~T4_E~0); 946993#L774-1 assume !(0 == ~T5_E~0); 946859#L779-1 assume !(0 == ~T6_E~0); 946588#L784-1 assume !(0 == ~T7_E~0); 946589#L789-1 assume !(0 == ~E_1~0); 946259#L794-1 assume !(0 == ~E_2~0); 946260#L799-1 assume !(0 == ~E_3~0); 946994#L804-1 assume !(0 == ~E_4~0); 946995#L809-1 assume !(0 == ~E_5~0); 946677#L814-1 assume !(0 == ~E_6~0); 946184#L819-1 assume !(0 == ~E_7~0); 946185#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 946658#L361 assume !(1 == ~m_pc~0); 946659#L361-2 is_master_triggered_~__retres1~0#1 := 0; 946705#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 946462#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 946463#L930 assume !(0 != activate_threads_~tmp~1#1); 946854#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 946650#L380 assume !(1 == ~t1_pc~0); 946651#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 946879#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 946880#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 946983#L938 assume !(0 != activate_threads_~tmp___0~0#1); 946380#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 946309#L399 assume !(1 == ~t2_pc~0); 946310#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 946518#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 946893#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 946732#L946 assume !(0 != activate_threads_~tmp___1~0#1); 946217#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 946190#L418 assume !(1 == ~t3_pc~0); 946151#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 946152#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 946681#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 946957#L954 assume !(0 != activate_threads_~tmp___2~0#1); 947013#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 946947#L437 assume !(1 == ~t4_pc~0); 946817#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 946486#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 946311#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 946312#L962 assume !(0 != activate_threads_~tmp___3~0#1); 946782#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 946437#L456 assume !(1 == ~t5_pc~0); 946438#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 946545#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 946919#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 946208#L970 assume !(0 != activate_threads_~tmp___4~0#1); 946209#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 946326#L475 assume !(1 == ~t6_pc~0); 946327#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 946400#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 946401#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 946172#L978 assume !(0 != activate_threads_~tmp___5~0#1); 946173#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 946664#L494 assume !(1 == ~t7_pc~0); 946666#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 946713#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 946914#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 946915#L986 assume !(0 != activate_threads_~tmp___6~0#1); 947028#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 946916#L837 assume !(1 == ~M_E~0); 946735#L837-2 assume !(1 == ~T1_E~0); 946294#L842-1 assume !(1 == ~T2_E~0); 946295#L847-1 assume !(1 == ~T3_E~0); 946808#L852-1 assume !(1 == ~T4_E~0); 946906#L857-1 assume !(1 == ~T5_E~0); 946746#L862-1 assume !(1 == ~T6_E~0); 946747#L867-1 assume !(1 == ~T7_E~0); 946758#L872-1 assume !(1 == ~E_1~0); 946856#L877-1 assume !(1 == ~E_2~0); 946753#L882-1 assume !(1 == ~E_3~0); 946754#L887-1 assume !(1 == ~E_4~0); 946348#L892-1 assume !(1 == ~E_5~0); 946349#L897-1 assume !(1 == ~E_6~0); 946778#L902-1 assume !(1 == ~E_7~0); 946430#L907-1 assume { :end_inline_reset_delta_events } true; 946431#L1148-2 [2021-12-19 19:17:49,228 INFO L793 eck$LassoCheckResult]: Loop: 946431#L1148-2 assume !false; 966427#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966426#L729 assume !false; 966425#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 966370#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 966365#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 966364#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 966362#L626 assume !(0 != eval_~tmp~0#1); 966363#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 966865#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 966864#L754-3 assume !(0 == ~M_E~0); 966863#L754-5 assume !(0 == ~T1_E~0); 966862#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 966861#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 966860#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 966859#L774-3 assume !(0 == ~T5_E~0); 966858#L779-3 assume !(0 == ~T6_E~0); 966857#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 966856#L789-3 assume !(0 == ~E_1~0); 966855#L794-3 assume !(0 == ~E_2~0); 966854#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 966853#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 966852#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 966851#L814-3 assume !(0 == ~E_6~0); 966850#L819-3 assume !(0 == ~E_7~0); 966849#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 966848#L361-24 assume !(1 == ~m_pc~0); 966847#L361-26 is_master_triggered_~__retres1~0#1 := 0; 966846#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 966845#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 966844#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 966843#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 966842#L380-24 assume !(1 == ~t1_pc~0); 966841#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 966840#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 966839#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 966838#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 966837#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 966836#L399-24 assume !(1 == ~t2_pc~0); 966835#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 966834#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 966833#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 966832#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 966831#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 966830#L418-24 assume !(1 == ~t3_pc~0); 966828#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 966827#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966826#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 966825#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 966824#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 966823#L437-24 assume !(1 == ~t4_pc~0); 966822#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 966821#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 966820#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 966819#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 966818#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 966817#L456-24 assume !(1 == ~t5_pc~0); 966815#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 966814#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 966813#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 966812#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 966811#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 966810#L475-24 assume !(1 == ~t6_pc~0); 966809#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 966808#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 952955#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 952956#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 952947#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 952948#L494-24 assume !(1 == ~t7_pc~0); 952938#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 952939#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 952931#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 952932#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 952923#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 952924#L837-3 assume !(1 == ~M_E~0); 966524#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 966523#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 966522#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 966521#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 966520#L857-3 assume !(1 == ~T5_E~0); 966519#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 966518#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 966517#L872-3 assume !(1 == ~E_1~0); 966516#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 966515#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 966514#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 966513#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 966512#L897-3 assume !(1 == ~E_6~0); 966511#L902-3 assume !(1 == ~E_7~0); 966510#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 966508#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 966501#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 966500#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 966498#L1167 assume !(0 == start_simulation_~tmp~3#1); 966497#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 966444#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 966439#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 966438#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 966437#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 966436#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 966435#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 966434#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 946431#L1148-2 [2021-12-19 19:17:49,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:49,230 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2021-12-19 19:17:49,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:49,230 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6465700] [2021-12-19 19:17:49,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:49,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:49,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:49,263 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:49,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:49,310 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:49,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:49,311 INFO L85 PathProgramCache]: Analyzing trace with hash -17826115, now seen corresponding path program 1 times [2021-12-19 19:17:49,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:49,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284343805] [2021-12-19 19:17:49,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:49,311 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:49,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:49,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:49,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:49,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284343805] [2021-12-19 19:17:49,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284343805] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:49,348 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:49,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:49,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214786851] [2021-12-19 19:17:49,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:49,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:49,349 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:49,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:49,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:49,350 INFO L87 Difference]: Start difference. First operand 46059 states and 63890 transitions. cyclomatic complexity: 17847 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:49,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:49,615 INFO L93 Difference]: Finished difference Result 81568 states and 111613 transitions. [2021-12-19 19:17:49,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:17:49,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81568 states and 111613 transitions. [2021-12-19 19:17:49,916 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 81144 [2021-12-19 19:17:50,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81568 states to 81568 states and 111613 transitions. [2021-12-19 19:17:50,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81568 [2021-12-19 19:17:50,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81568 [2021-12-19 19:17:50,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81568 states and 111613 transitions. [2021-12-19 19:17:50,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:50,554 INFO L681 BuchiCegarLoop]: Abstraction has 81568 states and 111613 transitions. [2021-12-19 19:17:50,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81568 states and 111613 transitions. [2021-12-19 19:17:51,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81568 to 46383. [2021-12-19 19:17:51,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46383 states, 46383 states have (on average 1.38442964016989) internal successors, (64214), 46382 states have internal predecessors, (64214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:51,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46383 states to 46383 states and 64214 transitions. [2021-12-19 19:17:51,257 INFO L704 BuchiCegarLoop]: Abstraction has 46383 states and 64214 transitions. [2021-12-19 19:17:51,258 INFO L587 BuchiCegarLoop]: Abstraction has 46383 states and 64214 transitions. [2021-12-19 19:17:51,258 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:51,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46383 states and 64214 transitions. [2021-12-19 19:17:51,377 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46123 [2021-12-19 19:17:51,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:51,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:51,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:51,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:51,380 INFO L791 eck$LassoCheckResult]: Stem: 1074699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1074635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1074636#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1073984#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1073985#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1074457#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1074458#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1074420#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1074317#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1074318#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1074306#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1074307#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1074265#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1074266#L754 assume !(0 == ~M_E~0); 1074594#L754-2 assume !(0 == ~T1_E~0); 1074187#L759-1 assume !(0 == ~T2_E~0); 1074188#L764-1 assume !(0 == ~T3_E~0); 1074650#L769-1 assume !(0 == ~T4_E~0); 1074651#L774-1 assume !(0 == ~T5_E~0); 1074505#L779-1 assume !(0 == ~T6_E~0); 1074230#L784-1 assume !(0 == ~T7_E~0); 1074231#L789-1 assume !(0 == ~E_1~0); 1073902#L794-1 assume !(0 == ~E_2~0); 1073903#L799-1 assume !(0 == ~E_3~0); 1074653#L804-1 assume !(0 == ~E_4~0); 1074654#L809-1 assume !(0 == ~E_5~0); 1074321#L814-1 assume !(0 == ~E_6~0); 1073827#L819-1 assume !(0 == ~E_7~0); 1073828#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1074302#L361 assume !(1 == ~m_pc~0); 1074303#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1074353#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1074102#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1074103#L930 assume !(0 != activate_threads_~tmp~1#1); 1074498#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1074295#L380 assume !(1 == ~t1_pc~0); 1074296#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1074526#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1074527#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1074642#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1074022#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1073952#L399 assume !(1 == ~t2_pc~0); 1073953#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1074156#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1074542#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1074377#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1073860#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1073833#L418 assume !(1 == ~t3_pc~0); 1073794#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1073795#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1074326#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1074607#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1074679#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1074598#L437 assume !(1 == ~t4_pc~0); 1074461#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1074125#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1073954#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1073955#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1074430#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1074075#L456 assume !(1 == ~t5_pc~0); 1074076#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1074184#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1074569#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1073849#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1073850#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1073969#L475 assume !(1 == ~t6_pc~0); 1073970#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1074041#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1074042#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1073815#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1073816#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1074309#L494 assume !(1 == ~t7_pc~0); 1074311#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1074359#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1074564#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1074565#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1074695#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1074563#L837 assume !(1 == ~M_E~0); 1074380#L837-2 assume !(1 == ~T1_E~0); 1073937#L842-1 assume !(1 == ~T2_E~0); 1073938#L847-1 assume !(1 == ~T3_E~0); 1074453#L852-1 assume !(1 == ~T4_E~0); 1074557#L857-1 assume !(1 == ~T5_E~0); 1074392#L862-1 assume !(1 == ~T6_E~0); 1074393#L867-1 assume !(1 == ~T7_E~0); 1074406#L872-1 assume !(1 == ~E_1~0); 1074502#L877-1 assume !(1 == ~E_2~0); 1074402#L882-1 assume !(1 == ~E_3~0); 1074403#L887-1 assume !(1 == ~E_4~0); 1073990#L892-1 assume !(1 == ~E_5~0); 1073991#L897-1 assume !(1 == ~E_6~0); 1074427#L902-1 assume !(1 == ~E_7~0); 1074070#L907-1 assume { :end_inline_reset_delta_events } true; 1074071#L1148-2 [2021-12-19 19:17:51,380 INFO L793 eck$LassoCheckResult]: Loop: 1074071#L1148-2 assume !false; 1089524#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1089525#L729 assume !false; 1083629#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1083630#L569 assume !(0 == ~m_st~0); 1088852#L573 assume !(0 == ~t1_st~0); 1088853#L577 assume !(0 == ~t2_st~0); 1088843#L581 assume !(0 == ~t3_st~0); 1088845#L585 assume !(0 == ~t4_st~0); 1088854#L589 assume !(0 == ~t5_st~0); 1088855#L593 assume !(0 == ~t6_st~0); 1088848#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1088849#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1080427#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1080428#L626 assume !(0 != eval_~tmp~0#1); 1083612#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1083613#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1083608#L754-3 assume !(0 == ~M_E~0); 1083609#L754-5 assume !(0 == ~T1_E~0); 1083604#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1083605#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1083600#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1083601#L774-3 assume !(0 == ~T5_E~0); 1083596#L779-3 assume !(0 == ~T6_E~0); 1083597#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1083592#L789-3 assume !(0 == ~E_1~0); 1083593#L794-3 assume !(0 == ~E_2~0); 1083588#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1083589#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1083584#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1083585#L814-3 assume !(0 == ~E_6~0); 1083580#L819-3 assume !(0 == ~E_7~0); 1083581#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1083576#L361-24 assume !(1 == ~m_pc~0); 1083577#L361-26 is_master_triggered_~__retres1~0#1 := 0; 1083572#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1083573#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1083568#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1083569#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1083564#L380-24 assume !(1 == ~t1_pc~0); 1083565#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1083560#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1083561#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1083556#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 1083557#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1083552#L399-24 assume !(1 == ~t2_pc~0); 1083553#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1083548#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1083549#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1083544#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1083545#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1083539#L418-24 assume !(1 == ~t3_pc~0); 1083540#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1083534#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1083535#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1083530#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1083531#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1083526#L437-24 assume !(1 == ~t4_pc~0); 1083527#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1083522#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1083523#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1083518#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1083519#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1083513#L456-24 assume 1 == ~t5_pc~0; 1083514#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1083508#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1083509#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1083504#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1083505#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1083500#L475-24 assume !(1 == ~t6_pc~0); 1083501#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1083496#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1083497#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1083492#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1083493#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1083489#L494-24 assume !(1 == ~t7_pc~0); 1083488#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 1083483#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1083484#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1083479#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1083480#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1083476#L837-3 assume !(1 == ~M_E~0); 1083116#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1083472#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1083473#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1083468#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1083469#L857-3 assume !(1 == ~T5_E~0); 1083464#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1083465#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1083460#L872-3 assume !(1 == ~E_1~0); 1083461#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1083456#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1083457#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1083452#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1083453#L897-3 assume !(1 == ~E_6~0); 1083448#L902-3 assume !(1 == ~E_7~0); 1083449#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1083444#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1083438#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1083433#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1083434#L1167 assume !(0 == start_simulation_~tmp~3#1); 1083691#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1083692#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1096898#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1096897#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1096896#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1096895#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1096894#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1089538#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1074071#L1148-2 [2021-12-19 19:17:51,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:51,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2021-12-19 19:17:51,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:51,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396631062] [2021-12-19 19:17:51,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:51,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:51,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:51,389 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:51,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:51,417 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:51,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:51,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1977823074, now seen corresponding path program 1 times [2021-12-19 19:17:51,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:51,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578434822] [2021-12-19 19:17:51,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:51,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:51,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:51,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:51,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:51,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578434822] [2021-12-19 19:17:51,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578434822] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:51,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:51,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:51,478 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398442241] [2021-12-19 19:17:51,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:51,478 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:51,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:51,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:51,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:51,479 INFO L87 Difference]: Start difference. First operand 46383 states and 64214 transitions. cyclomatic complexity: 17847 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:51,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:51,785 INFO L93 Difference]: Finished difference Result 79063 states and 110153 transitions. [2021-12-19 19:17:51,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:51,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79063 states and 110153 transitions. [2021-12-19 19:17:52,423 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 78747 [2021-12-19 19:17:52,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79063 states to 79063 states and 110153 transitions. [2021-12-19 19:17:52,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79063 [2021-12-19 19:17:52,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79063 [2021-12-19 19:17:52,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79063 states and 110153 transitions. [2021-12-19 19:17:52,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:52,699 INFO L681 BuchiCegarLoop]: Abstraction has 79063 states and 110153 transitions. [2021-12-19 19:17:52,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79063 states and 110153 transitions. [2021-12-19 19:17:53,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79063 to 46893. [2021-12-19 19:17:53,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46893 states, 46893 states have (on average 1.3716546179600366) internal successors, (64321), 46892 states have internal predecessors, (64321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:53,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46893 states to 46893 states and 64321 transitions. [2021-12-19 19:17:53,218 INFO L704 BuchiCegarLoop]: Abstraction has 46893 states and 64321 transitions. [2021-12-19 19:17:53,218 INFO L587 BuchiCegarLoop]: Abstraction has 46893 states and 64321 transitions. [2021-12-19 19:17:53,218 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:17:53,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46893 states and 64321 transitions. [2021-12-19 19:17:53,341 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46633 [2021-12-19 19:17:53,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:53,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:53,343 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,343 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,343 INFO L791 eck$LassoCheckResult]: Stem: 1200238#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1200151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1200152#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1199442#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1199443#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1199948#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1199949#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1199899#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1199790#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1199791#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1199777#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1199778#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1199731#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1199732#L754 assume !(0 == ~M_E~0); 1200094#L754-2 assume !(0 == ~T1_E~0); 1199651#L759-1 assume !(0 == ~T2_E~0); 1199652#L764-1 assume !(0 == ~T3_E~0); 1200180#L769-1 assume !(0 == ~T4_E~0); 1200181#L774-1 assume !(0 == ~T5_E~0); 1199993#L779-1 assume !(0 == ~T6_E~0); 1199695#L784-1 assume !(0 == ~T7_E~0); 1199696#L789-1 assume !(0 == ~E_1~0); 1199361#L794-1 assume !(0 == ~E_2~0); 1199362#L799-1 assume !(0 == ~E_3~0); 1200187#L804-1 assume !(0 == ~E_4~0); 1200188#L809-1 assume !(0 == ~E_5~0); 1199794#L814-1 assume !(0 == ~E_6~0); 1199284#L819-1 assume !(0 == ~E_7~0); 1199285#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1199773#L361 assume !(1 == ~m_pc~0); 1199774#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1199821#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1199564#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1199565#L930 assume !(0 != activate_threads_~tmp~1#1); 1199987#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1199763#L380 assume !(1 == ~t1_pc~0); 1199764#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1200015#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1200016#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1200161#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1199482#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1199410#L399 assume !(1 == ~t2_pc~0); 1199411#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1199622#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1200033#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1199848#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1199318#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1199290#L418 assume !(1 == ~t3_pc~0); 1199253#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1199254#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1199796#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1200117#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1200214#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1200100#L437 assume !(1 == ~t4_pc~0); 1199952#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1199588#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1199412#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1199413#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1199914#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1199539#L456 assume !(1 == ~t5_pc~0); 1199540#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1199648#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1200061#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1199308#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1199309#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1199427#L475 assume !(1 == ~t6_pc~0); 1199428#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1199503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1199504#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1199274#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1199275#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1199783#L494 assume !(1 == ~t7_pc~0); 1199785#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1199829#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1200054#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1200055#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1200228#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200056#L837 assume !(1 == ~M_E~0); 1199852#L837-2 assume !(1 == ~T1_E~0); 1199395#L842-1 assume !(1 == ~T2_E~0); 1199396#L847-1 assume !(1 == ~T3_E~0); 1199941#L852-1 assume !(1 == ~T4_E~0); 1200044#L857-1 assume !(1 == ~T5_E~0); 1199868#L862-1 assume !(1 == ~T6_E~0); 1199869#L867-1 assume !(1 == ~T7_E~0); 1199885#L872-1 assume !(1 == ~E_1~0); 1199990#L877-1 assume !(1 == ~E_2~0); 1199880#L882-1 assume !(1 == ~E_3~0); 1199881#L887-1 assume !(1 == ~E_4~0); 1199449#L892-1 assume !(1 == ~E_5~0); 1199450#L897-1 assume !(1 == ~E_6~0); 1199908#L902-1 assume !(1 == ~E_7~0); 1199532#L907-1 assume { :end_inline_reset_delta_events } true; 1199533#L1148-2 [2021-12-19 19:17:53,343 INFO L793 eck$LassoCheckResult]: Loop: 1199533#L1148-2 assume !false; 1216146#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1216144#L729 assume !false; 1216142#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1216141#L569 assume !(0 == ~m_st~0); 1205295#L573 assume !(0 == ~t1_st~0); 1205296#L577 assume !(0 == ~t2_st~0); 1205290#L581 assume !(0 == ~t3_st~0); 1205291#L585 assume !(0 == ~t4_st~0); 1205294#L589 assume !(0 == ~t5_st~0); 1205287#L593 assume !(0 == ~t6_st~0); 1205289#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1205286#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1204920#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1204921#L626 assume !(0 != eval_~tmp~0#1); 1205284#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1205283#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1205282#L754-3 assume !(0 == ~M_E~0); 1205281#L754-5 assume !(0 == ~T1_E~0); 1205280#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1205279#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1205278#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1205277#L774-3 assume !(0 == ~T5_E~0); 1205276#L779-3 assume !(0 == ~T6_E~0); 1205275#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1205274#L789-3 assume !(0 == ~E_1~0); 1205273#L794-3 assume !(0 == ~E_2~0); 1205272#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1205271#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1205270#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1205269#L814-3 assume !(0 == ~E_6~0); 1205268#L819-3 assume !(0 == ~E_7~0); 1205267#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1205266#L361-24 assume !(1 == ~m_pc~0); 1205265#L361-26 is_master_triggered_~__retres1~0#1 := 0; 1205264#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1205263#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1205262#L930-24 assume !(0 != activate_threads_~tmp~1#1); 1205261#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1205260#L380-24 assume !(1 == ~t1_pc~0); 1205259#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1205258#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1205257#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1205256#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 1205255#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205254#L399-24 assume !(1 == ~t2_pc~0); 1205253#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1205252#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1205251#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1205250#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1205249#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1205248#L418-24 assume !(1 == ~t3_pc~0); 1205246#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1205245#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1205244#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1205243#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1205242#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1205241#L437-24 assume !(1 == ~t4_pc~0); 1205240#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1205239#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1205238#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1205237#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1205236#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1205235#L456-24 assume 1 == ~t5_pc~0; 1205234#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1205232#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1205231#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1205230#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1205229#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1205228#L475-24 assume !(1 == ~t6_pc~0); 1205227#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1205226#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1205225#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1205224#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1205223#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1205222#L494-24 assume !(1 == ~t7_pc~0); 1205220#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 1205219#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1205218#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1205217#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1205215#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1205213#L837-3 assume !(1 == ~M_E~0); 1205046#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1205210#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1205208#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1205206#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1205204#L857-3 assume !(1 == ~T5_E~0); 1205202#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1205200#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1205198#L872-3 assume !(1 == ~E_1~0); 1205196#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1205194#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1205192#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1205190#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1205188#L897-3 assume !(1 == ~E_6~0); 1205186#L902-3 assume !(1 == ~E_7~0); 1205184#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1205181#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1205173#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1205171#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1205168#L1167 assume !(0 == start_simulation_~tmp~3#1); 1205169#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1217165#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1217159#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1217157#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1217155#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1217154#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1216156#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1216154#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1199533#L1148-2 [2021-12-19 19:17:53,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,344 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2021-12-19 19:17:53,344 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467752617] [2021-12-19 19:17:53,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,363 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:53,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:53,379 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:53,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,408 INFO L85 PathProgramCache]: Analyzing trace with hash 2054723872, now seen corresponding path program 1 times [2021-12-19 19:17:53,408 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957914599] [2021-12-19 19:17:53,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,408 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:53,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:53,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:53,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957914599] [2021-12-19 19:17:53,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957914599] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:53,447 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:53,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:53,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080398701] [2021-12-19 19:17:53,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:53,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:53,448 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:53,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:53,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:53,448 INFO L87 Difference]: Start difference. First operand 46893 states and 64321 transitions. cyclomatic complexity: 17444 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:53,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:53,933 INFO L93 Difference]: Finished difference Result 72132 states and 97586 transitions. [2021-12-19 19:17:53,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:53,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72132 states and 97586 transitions. [2021-12-19 19:17:54,262 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 71882 [2021-12-19 19:17:54,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72132 states to 72132 states and 97586 transitions. [2021-12-19 19:17:54,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72132 [2021-12-19 19:17:54,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72132 [2021-12-19 19:17:54,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72132 states and 97586 transitions. [2021-12-19 19:17:54,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:54,582 INFO L681 BuchiCegarLoop]: Abstraction has 72132 states and 97586 transitions. [2021-12-19 19:17:54,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72132 states and 97586 transitions. [2021-12-19 19:17:55,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72132 to 70750. [2021-12-19 19:17:55,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70750 states, 70750 states have (on average 1.354713780918728) internal successors, (95846), 70749 states have internal predecessors, (95846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:55,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70750 states to 70750 states and 95846 transitions. [2021-12-19 19:17:55,695 INFO L704 BuchiCegarLoop]: Abstraction has 70750 states and 95846 transitions. [2021-12-19 19:17:55,696 INFO L587 BuchiCegarLoop]: Abstraction has 70750 states and 95846 transitions. [2021-12-19 19:17:55,696 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:17:55,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70750 states and 95846 transitions. [2021-12-19 19:17:55,896 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 70500 [2021-12-19 19:17:55,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:55,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:55,897 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:55,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:55,897 INFO L791 eck$LassoCheckResult]: Stem: 1319225#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1319157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1319158#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1318471#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1318472#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1318964#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1318965#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1318918#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1318816#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1318817#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1318803#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1318804#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1318761#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1318762#L754 assume !(0 == ~M_E~0); 1319114#L754-2 assume !(0 == ~T1_E~0); 1318679#L759-1 assume !(0 == ~T2_E~0); 1318680#L764-1 assume !(0 == ~T3_E~0); 1319180#L769-1 assume !(0 == ~T4_E~0); 1319181#L774-1 assume !(0 == ~T5_E~0); 1319015#L779-1 assume !(0 == ~T6_E~0); 1318725#L784-1 assume !(0 == ~T7_E~0); 1318726#L789-1 assume !(0 == ~E_1~0); 1318389#L794-1 assume !(0 == ~E_2~0); 1318390#L799-1 assume !(0 == ~E_3~0); 1319184#L804-1 assume !(0 == ~E_4~0); 1319185#L809-1 assume !(0 == ~E_5~0); 1318820#L814-1 assume !(0 == ~E_6~0); 1318313#L819-1 assume !(0 == ~E_7~0); 1318314#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1318800#L361 assume !(1 == ~m_pc~0); 1318801#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1318849#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1318590#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1318591#L930 assume !(0 != activate_threads_~tmp~1#1); 1319010#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1318792#L380 assume !(1 == ~t1_pc~0); 1318793#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1319037#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1319038#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1319168#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1318509#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1318439#L399 assume !(1 == ~t2_pc~0); 1318440#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1318647#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1319056#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1318873#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1318349#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318321#L418 assume !(1 == ~t3_pc~0); 1318284#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318285#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1318822#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1319131#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1319203#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1319117#L437 assume !(1 == ~t4_pc~0); 1318968#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1318612#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1318441#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1318442#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1318929#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1318560#L456 assume !(1 == ~t5_pc~0); 1318561#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1318676#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319090#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1318339#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1318340#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1318456#L475 assume !(1 == ~t6_pc~0); 1318457#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1318528#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1318529#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1318305#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1318306#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1318807#L494 assume !(1 == ~t7_pc~0); 1318809#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1318857#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1319083#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1319084#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1319216#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1319082#L837 assume !(1 == ~M_E~0); 1318876#L837-2 assume !(1 == ~T1_E~0); 1318424#L842-1 assume !(1 == ~T2_E~0); 1318425#L847-1 assume !(1 == ~T3_E~0); 1318957#L852-1 assume !(1 == ~T4_E~0); 1319074#L857-1 assume !(1 == ~T5_E~0); 1318890#L862-1 assume !(1 == ~T6_E~0); 1318891#L867-1 assume !(1 == ~T7_E~0); 1318903#L872-1 assume !(1 == ~E_1~0); 1319012#L877-1 assume !(1 == ~E_2~0); 1318899#L882-1 assume !(1 == ~E_3~0); 1318900#L887-1 assume !(1 == ~E_4~0); 1318477#L892-1 assume !(1 == ~E_5~0); 1318478#L897-1 assume !(1 == ~E_6~0); 1318924#L902-1 assume !(1 == ~E_7~0); 1318556#L907-1 assume { :end_inline_reset_delta_events } true; 1318557#L1148-2 assume !false; 1324818#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1324819#L729 [2021-12-19 19:17:55,898 INFO L793 eck$LassoCheckResult]: Loop: 1324819#L729 assume !false; 1344077#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1344074#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1344070#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1344067#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1344065#L626 assume 0 != eval_~tmp~0#1; 1344062#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1344057#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1344052#L631 assume !(0 == ~t1_st~0); 1324787#L645 assume !(0 == ~t2_st~0); 1324788#L659 assume !(0 == ~t3_st~0); 1325112#L673 assume !(0 == ~t4_st~0); 1324087#L687 assume !(0 == ~t5_st~0); 1344122#L701 assume !(0 == ~t6_st~0); 1344099#L715 assume !(0 == ~t7_st~0); 1324819#L729 [2021-12-19 19:17:55,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:55,898 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2021-12-19 19:17:55,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:55,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641304467] [2021-12-19 19:17:55,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:55,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:55,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:55,905 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:55,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:55,921 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:55,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:55,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 1 times [2021-12-19 19:17:55,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:55,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353302926] [2021-12-19 19:17:55,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:55,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:55,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:55,924 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:55,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:55,927 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:55,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:55,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1562289544, now seen corresponding path program 1 times [2021-12-19 19:17:55,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:55,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73068844] [2021-12-19 19:17:55,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:55,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:55,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:55,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:55,945 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:55,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73068844] [2021-12-19 19:17:55,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73068844] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:55,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:55,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:55,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535823143] [2021-12-19 19:17:55,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:56,036 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:56,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:56,037 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:56,037 INFO L87 Difference]: Start difference. First operand 70750 states and 95846 transitions. cyclomatic complexity: 25120 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:56,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:56,394 INFO L93 Difference]: Finished difference Result 123200 states and 164826 transitions. [2021-12-19 19:17:56,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:56,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123200 states and 164826 transitions. [2021-12-19 19:17:57,449 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 115410 [2021-12-19 19:17:57,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123200 states to 123200 states and 164826 transitions. [2021-12-19 19:17:57,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123200 [2021-12-19 19:17:57,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123200 [2021-12-19 19:17:57,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123200 states and 164826 transitions. [2021-12-19 19:17:57,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:57,952 INFO L681 BuchiCegarLoop]: Abstraction has 123200 states and 164826 transitions. [2021-12-19 19:17:58,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123200 states and 164826 transitions. [2021-12-19 19:17:59,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123200 to 123200. [2021-12-19 19:17:59,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123200 states, 123200 states have (on average 1.3378733766233766) internal successors, (164826), 123199 states have internal predecessors, (164826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:59,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123200 states to 123200 states and 164826 transitions. [2021-12-19 19:17:59,697 INFO L704 BuchiCegarLoop]: Abstraction has 123200 states and 164826 transitions. [2021-12-19 19:17:59,697 INFO L587 BuchiCegarLoop]: Abstraction has 123200 states and 164826 transitions. [2021-12-19 19:17:59,697 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:17:59,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123200 states and 164826 transitions. [2021-12-19 19:18:00,038 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 115410 [2021-12-19 19:18:00,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:00,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:00,040 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,040 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,040 INFO L791 eck$LassoCheckResult]: Stem: 1513156#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1513094#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1513095#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1512433#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1512434#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1512905#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1512906#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1512861#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1512766#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1512767#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1512757#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1512758#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1512717#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1512718#L754 assume !(0 == ~M_E~0); 1513044#L754-2 assume !(0 == ~T1_E~0); 1512639#L759-1 assume !(0 == ~T2_E~0); 1512640#L764-1 assume !(0 == ~T3_E~0); 1513114#L769-1 assume !(0 == ~T4_E~0); 1513115#L774-1 assume !(0 == ~T5_E~0); 1512951#L779-1 assume !(0 == ~T6_E~0); 1512682#L784-1 assume !(0 == ~T7_E~0); 1512683#L789-1 assume !(0 == ~E_1~0); 1512347#L794-1 assume !(0 == ~E_2~0); 1512348#L799-1 assume !(0 == ~E_3~0); 1513117#L804-1 assume !(0 == ~E_4~0); 1513118#L809-1 assume !(0 == ~E_5~0); 1548560#L814-1 assume !(0 == ~E_6~0); 1548558#L819-1 assume !(0 == ~E_7~0); 1512819#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1512754#L361 assume !(1 == ~m_pc~0); 1512755#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1512800#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1512554#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1512555#L930 assume !(0 != activate_threads_~tmp~1#1); 1512948#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1512746#L380 assume !(1 == ~t1_pc~0); 1512747#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1512974#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1512975#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1513103#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1512472#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1512401#L399 assume !(1 == ~t2_pc~0); 1512402#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1512609#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1512991#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1512825#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1512308#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1512309#L418 assume !(1 == ~t3_pc~0); 1548238#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1548236#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1548234#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1548232#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1548230#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1548228#L437 assume !(1 == ~t4_pc~0); 1548226#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1548224#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1548222#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1548220#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1512874#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1512875#L456 assume !(1 == ~t5_pc~0); 1548104#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1548103#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1548101#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1548099#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1548097#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1548095#L475 assume !(1 == ~t6_pc~0); 1548093#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1548091#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1548089#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1548088#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1548086#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1548084#L494 assume !(1 == ~t7_pc~0); 1548081#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1548079#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1548077#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1548074#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1548072#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1548070#L837 assume !(1 == ~M_E~0); 1548068#L837-2 assume !(1 == ~T1_E~0); 1548066#L842-1 assume !(1 == ~T2_E~0); 1548064#L847-1 assume !(1 == ~T3_E~0); 1548062#L852-1 assume !(1 == ~T4_E~0); 1548060#L857-1 assume !(1 == ~T5_E~0); 1548058#L862-1 assume !(1 == ~T6_E~0); 1548056#L867-1 assume !(1 == ~T7_E~0); 1548054#L872-1 assume !(1 == ~E_1~0); 1548052#L877-1 assume !(1 == ~E_2~0); 1548049#L882-1 assume !(1 == ~E_3~0); 1548047#L887-1 assume !(1 == ~E_4~0); 1548045#L892-1 assume !(1 == ~E_5~0); 1548043#L897-1 assume !(1 == ~E_6~0); 1548041#L902-1 assume !(1 == ~E_7~0); 1548039#L907-1 assume { :end_inline_reset_delta_events } true; 1548037#L1148-2 assume !false; 1546951#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1546949#L729 [2021-12-19 19:18:00,040 INFO L793 eck$LassoCheckResult]: Loop: 1546949#L729 assume !false; 1546947#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1546945#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1546943#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1546689#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1546688#L626 assume 0 != eval_~tmp~0#1; 1546686#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1546684#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1546685#L631 assume !(0 == ~t1_st~0); 1548999#L645 assume !(0 == ~t2_st~0); 1548151#L659 assume !(0 == ~t3_st~0); 1548147#L673 assume !(0 == ~t4_st~0); 1546965#L687 assume !(0 == ~t5_st~0); 1546957#L701 assume !(0 == ~t6_st~0); 1546955#L715 assume !(0 == ~t7_st~0); 1546949#L729 [2021-12-19 19:18:00,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,041 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2021-12-19 19:18:00,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830647888] [2021-12-19 19:18:00,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,042 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:00,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:00,055 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:00,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830647888] [2021-12-19 19:18:00,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830647888] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:00,056 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:00,056 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:00,056 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199707551] [2021-12-19 19:18:00,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:00,056 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:00,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 2 times [2021-12-19 19:18:00,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427240476] [2021-12-19 19:18:00,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,059 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:00,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:00,061 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:00,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:00,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:00,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:00,166 INFO L87 Difference]: Start difference. First operand 123200 states and 164826 transitions. cyclomatic complexity: 41692 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:00,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:00,315 INFO L93 Difference]: Finished difference Result 55381 states and 73790 transitions. [2021-12-19 19:18:00,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:00,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55381 states and 73790 transitions. [2021-12-19 19:18:00,538 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54073 [2021-12-19 19:18:00,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55381 states to 55381 states and 73790 transitions. [2021-12-19 19:18:00,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55381 [2021-12-19 19:18:00,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55381 [2021-12-19 19:18:00,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55381 states and 73790 transitions. [2021-12-19 19:18:00,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:00,753 INFO L681 BuchiCegarLoop]: Abstraction has 55381 states and 73790 transitions. [2021-12-19 19:18:00,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55381 states and 73790 transitions. [2021-12-19 19:18:01,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55381 to 55381. [2021-12-19 19:18:01,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55381 states, 55381 states have (on average 1.3324064209747024) internal successors, (73790), 55380 states have internal predecessors, (73790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:01,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55381 states to 55381 states and 73790 transitions. [2021-12-19 19:18:01,782 INFO L704 BuchiCegarLoop]: Abstraction has 55381 states and 73790 transitions. [2021-12-19 19:18:01,783 INFO L587 BuchiCegarLoop]: Abstraction has 55381 states and 73790 transitions. [2021-12-19 19:18:01,783 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:18:01,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55381 states and 73790 transitions. [2021-12-19 19:18:01,970 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54073 [2021-12-19 19:18:01,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:01,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:01,971 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,972 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,972 INFO L791 eck$LassoCheckResult]: Stem: 1691740#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1691671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1691672#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1691020#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1691021#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1691494#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1691495#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1691447#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1691356#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1691357#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1691348#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1691349#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1691305#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1691306#L754 assume !(0 == ~M_E~0); 1691632#L754-2 assume !(0 == ~T1_E~0); 1691225#L759-1 assume !(0 == ~T2_E~0); 1691226#L764-1 assume !(0 == ~T3_E~0); 1691691#L769-1 assume !(0 == ~T4_E~0); 1691692#L774-1 assume !(0 == ~T5_E~0); 1691538#L779-1 assume !(0 == ~T6_E~0); 1691270#L784-1 assume !(0 == ~T7_E~0); 1691271#L789-1 assume !(0 == ~E_1~0); 1690933#L794-1 assume !(0 == ~E_2~0); 1690934#L799-1 assume !(0 == ~E_3~0); 1691694#L804-1 assume !(0 == ~E_4~0); 1691695#L809-1 assume !(0 == ~E_5~0); 1691361#L814-1 assume !(0 == ~E_6~0); 1690858#L819-1 assume !(0 == ~E_7~0); 1690859#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1691345#L361 assume !(1 == ~m_pc~0); 1691346#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1691391#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1691142#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1691143#L930 assume !(0 != activate_threads_~tmp~1#1); 1691533#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1691337#L380 assume !(1 == ~t1_pc~0); 1691338#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1691559#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1691560#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1691678#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1691059#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1690988#L399 assume !(1 == ~t2_pc~0); 1690989#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1691196#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1691577#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1691414#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1690895#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1690866#L418 assume !(1 == ~t3_pc~0); 1690829#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1690830#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1691367#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1691646#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1691715#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1691634#L437 assume !(1 == ~t4_pc~0); 1691498#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1691166#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1690990#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1690991#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1691459#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1691111#L456 assume !(1 == ~t5_pc~0); 1691112#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1691222#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1691605#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1690884#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1690885#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1691003#L475 assume !(1 == ~t6_pc~0); 1691004#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1691080#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1691081#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1690850#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1690851#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1691351#L494 assume !(1 == ~t7_pc~0); 1691353#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1691398#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1691597#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1691598#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1691733#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1691599#L837 assume !(1 == ~M_E~0); 1691417#L837-2 assume !(1 == ~T1_E~0); 1690973#L842-1 assume !(1 == ~T2_E~0); 1690974#L847-1 assume !(1 == ~T3_E~0); 1691489#L852-1 assume !(1 == ~T4_E~0); 1691588#L857-1 assume !(1 == ~T5_E~0); 1691428#L862-1 assume !(1 == ~T6_E~0); 1691429#L867-1 assume !(1 == ~T7_E~0); 1691437#L872-1 assume !(1 == ~E_1~0); 1691537#L877-1 assume !(1 == ~E_2~0); 1691435#L882-1 assume !(1 == ~E_3~0); 1691436#L887-1 assume !(1 == ~E_4~0); 1691027#L892-1 assume !(1 == ~E_5~0); 1691028#L897-1 assume !(1 == ~E_6~0); 1691454#L902-1 assume !(1 == ~E_7~0); 1691108#L907-1 assume { :end_inline_reset_delta_events } true; 1691109#L1148-2 assume !false; 1710912#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1710909#L729 [2021-12-19 19:18:01,972 INFO L793 eck$LassoCheckResult]: Loop: 1710909#L729 assume !false; 1710907#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1710904#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1710902#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1710900#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1710898#L626 assume 0 != eval_~tmp~0#1; 1710896#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1710894#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1710893#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1710892#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1710891#L645 assume !(0 == ~t2_st~0); 1710889#L659 assume !(0 == ~t3_st~0); 1710929#L673 assume !(0 == ~t4_st~0); 1710925#L687 assume !(0 == ~t5_st~0); 1710918#L701 assume !(0 == ~t6_st~0); 1710916#L715 assume !(0 == ~t7_st~0); 1710909#L729 [2021-12-19 19:18:01,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:01,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2021-12-19 19:18:01,973 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:01,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805477700] [2021-12-19 19:18:01,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:01,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:01,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:01,985 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:01,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:02,003 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:02,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:02,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1848014684, now seen corresponding path program 1 times [2021-12-19 19:18:02,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:02,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853638573] [2021-12-19 19:18:02,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:02,004 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:02,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:02,010 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:02,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:02,013 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:02,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:02,014 INFO L85 PathProgramCache]: Analyzing trace with hash 621098027, now seen corresponding path program 1 times [2021-12-19 19:18:02,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:02,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19287981] [2021-12-19 19:18:02,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:02,014 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:02,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:02,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:02,033 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:02,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19287981] [2021-12-19 19:18:02,033 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19287981] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:02,033 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:02,033 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:02,033 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675587832] [2021-12-19 19:18:02,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:02,125 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:02,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:02,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:02,126 INFO L87 Difference]: Start difference. First operand 55381 states and 73790 transitions. cyclomatic complexity: 18433 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:02,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:02,398 INFO L93 Difference]: Finished difference Result 101217 states and 134468 transitions. [2021-12-19 19:18:02,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:02,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101217 states and 134468 transitions. [2021-12-19 19:18:03,338 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 99242 [2021-12-19 19:18:03,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101217 states to 101217 states and 134468 transitions. [2021-12-19 19:18:03,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101217 [2021-12-19 19:18:03,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101217 [2021-12-19 19:18:03,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101217 states and 134468 transitions. [2021-12-19 19:18:03,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:03,737 INFO L681 BuchiCegarLoop]: Abstraction has 101217 states and 134468 transitions. [2021-12-19 19:18:03,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101217 states and 134468 transitions. [2021-12-19 19:18:04,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101217 to 98528. [2021-12-19 19:18:04,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98528 states, 98528 states have (on average 1.3293277037999351) internal successors, (130976), 98527 states have internal predecessors, (130976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:05,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98528 states to 98528 states and 130976 transitions. [2021-12-19 19:18:05,201 INFO L704 BuchiCegarLoop]: Abstraction has 98528 states and 130976 transitions. [2021-12-19 19:18:05,201 INFO L587 BuchiCegarLoop]: Abstraction has 98528 states and 130976 transitions. [2021-12-19 19:18:05,201 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:18:05,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98528 states and 130976 transitions. [2021-12-19 19:18:05,490 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 96553 [2021-12-19 19:18:05,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:05,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:05,491 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:05,491 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:05,491 INFO L791 eck$LassoCheckResult]: Stem: 1848377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1848312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1848313#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1847624#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1847625#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1848113#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1848114#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1848069#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1847968#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1847969#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1847958#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1847959#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1847914#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1847915#L754 assume !(0 == ~M_E~0); 1848265#L754-2 assume !(0 == ~T1_E~0); 1847834#L759-1 assume !(0 == ~T2_E~0); 1847835#L764-1 assume !(0 == ~T3_E~0); 1848330#L769-1 assume !(0 == ~T4_E~0); 1848331#L774-1 assume !(0 == ~T5_E~0); 1848164#L779-1 assume !(0 == ~T6_E~0); 1847876#L784-1 assume !(0 == ~T7_E~0); 1847877#L789-1 assume !(0 == ~E_1~0); 1847543#L794-1 assume !(0 == ~E_2~0); 1847544#L799-1 assume !(0 == ~E_3~0); 1848333#L804-1 assume !(0 == ~E_4~0); 1848334#L809-1 assume !(0 == ~E_5~0); 1847973#L814-1 assume !(0 == ~E_6~0); 1847464#L819-1 assume !(0 == ~E_7~0); 1847465#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1847955#L361 assume !(1 == ~m_pc~0); 1847956#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1848001#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1847745#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1847746#L930 assume !(0 != activate_threads_~tmp~1#1); 1848157#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1847947#L380 assume !(1 == ~t1_pc~0); 1847948#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1848191#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1848192#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1848318#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1847662#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1847592#L399 assume !(1 == ~t2_pc~0); 1847593#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1847801#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1848210#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1848026#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1847501#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1847472#L418 assume !(1 == ~t3_pc~0); 1847435#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1847436#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1847975#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1848285#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1848355#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1848272#L437 assume !(1 == ~t4_pc~0); 1848117#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1847769#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1847594#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1847595#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1848082#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1847718#L456 assume !(1 == ~t5_pc~0); 1847719#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1847831#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1848236#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1847490#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1847491#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1847609#L475 assume !(1 == ~t6_pc~0); 1847610#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1847683#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1847684#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1847456#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1847457#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1847961#L494 assume !(1 == ~t7_pc~0); 1847963#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1848009#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1848232#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1848233#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1848373#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1848234#L837 assume !(1 == ~M_E~0); 1848029#L837-2 assume !(1 == ~T1_E~0); 1847577#L842-1 assume !(1 == ~T2_E~0); 1847578#L847-1 assume !(1 == ~T3_E~0); 1848107#L852-1 assume !(1 == ~T4_E~0); 1848221#L857-1 assume !(1 == ~T5_E~0); 1848043#L862-1 assume !(1 == ~T6_E~0); 1848044#L867-1 assume !(1 == ~T7_E~0); 1848057#L872-1 assume !(1 == ~E_1~0); 1848161#L877-1 assume !(1 == ~E_2~0); 1848054#L882-1 assume !(1 == ~E_3~0); 1848055#L887-1 assume !(1 == ~E_4~0); 1847630#L892-1 assume !(1 == ~E_5~0); 1847631#L897-1 assume !(1 == ~E_6~0); 1848076#L902-1 assume !(1 == ~E_7~0); 1847711#L907-1 assume { :end_inline_reset_delta_events } true; 1847712#L1148-2 assume !false; 1881954#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1881952#L729 [2021-12-19 19:18:05,491 INFO L793 eck$LassoCheckResult]: Loop: 1881952#L729 assume !false; 1881950#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1881948#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1881947#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1881946#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1881945#L626 assume 0 != eval_~tmp~0#1; 1881942#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1881939#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1881937#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1881935#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1881933#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1881931#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1881928#L659 assume !(0 == ~t3_st~0); 1881923#L673 assume !(0 == ~t4_st~0); 1881919#L687 assume !(0 == ~t5_st~0); 1881914#L701 assume !(0 == ~t6_st~0); 1881647#L715 assume !(0 == ~t7_st~0); 1881952#L729 [2021-12-19 19:18:05,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:05,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2021-12-19 19:18:05,492 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:05,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811558526] [2021-12-19 19:18:05,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:05,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:05,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:05,518 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:05,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:05,536 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:05,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:05,536 INFO L85 PathProgramCache]: Analyzing trace with hash -10094934, now seen corresponding path program 1 times [2021-12-19 19:18:05,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:05,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951363386] [2021-12-19 19:18:05,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:05,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:05,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:05,539 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:05,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:05,541 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:05,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:05,542 INFO L85 PathProgramCache]: Analyzing trace with hash -777012221, now seen corresponding path program 1 times [2021-12-19 19:18:05,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:05,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398433060] [2021-12-19 19:18:05,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:05,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:05,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:05,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:05,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:05,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398433060] [2021-12-19 19:18:05,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398433060] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:05,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:05,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:05,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589535296] [2021-12-19 19:18:05,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:05,679 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:05,680 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:05,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:05,681 INFO L87 Difference]: Start difference. First operand 98528 states and 130976 transitions. cyclomatic complexity: 32472 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:06,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:06,087 INFO L93 Difference]: Finished difference Result 184868 states and 245245 transitions. [2021-12-19 19:18:06,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:06,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184868 states and 245245 transitions. [2021-12-19 19:18:07,389 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 181016 [2021-12-19 19:18:07,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184868 states to 184868 states and 245245 transitions. [2021-12-19 19:18:07,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184868 [2021-12-19 19:18:07,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184868 [2021-12-19 19:18:07,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184868 states and 245245 transitions. [2021-12-19 19:18:07,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:07,835 INFO L681 BuchiCegarLoop]: Abstraction has 184868 states and 245245 transitions. [2021-12-19 19:18:07,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184868 states and 245245 transitions. [2021-12-19 19:18:09,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184868 to 175272. [2021-12-19 19:18:09,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175272 states, 175272 states have (on average 1.32977885800356) internal successors, (233073), 175271 states have internal predecessors, (233073), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:09,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175272 states to 175272 states and 233073 transitions. [2021-12-19 19:18:09,556 INFO L704 BuchiCegarLoop]: Abstraction has 175272 states and 233073 transitions. [2021-12-19 19:18:09,556 INFO L587 BuchiCegarLoop]: Abstraction has 175272 states and 233073 transitions. [2021-12-19 19:18:09,556 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:18:09,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 175272 states and 233073 transitions. [2021-12-19 19:18:10,560 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 171420 [2021-12-19 19:18:10,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:10,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:10,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:10,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:10,562 INFO L791 eck$LassoCheckResult]: Stem: 2131828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2131738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2131739#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2131029#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2131030#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2131526#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2131527#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2131478#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2131373#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2131374#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2131363#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2131364#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2131319#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2131320#L754 assume !(0 == ~M_E~0); 2131689#L754-2 assume !(0 == ~T1_E~0); 2131236#L759-1 assume !(0 == ~T2_E~0); 2131237#L764-1 assume !(0 == ~T3_E~0); 2131764#L769-1 assume !(0 == ~T4_E~0); 2131765#L774-1 assume !(0 == ~T5_E~0); 2131578#L779-1 assume !(0 == ~T6_E~0); 2131280#L784-1 assume !(0 == ~T7_E~0); 2131281#L789-1 assume !(0 == ~E_1~0); 2130947#L794-1 assume !(0 == ~E_2~0); 2130948#L799-1 assume !(0 == ~E_3~0); 2131771#L804-1 assume !(0 == ~E_4~0); 2131772#L809-1 assume !(0 == ~E_5~0); 2131378#L814-1 assume !(0 == ~E_6~0); 2130870#L819-1 assume !(0 == ~E_7~0); 2130871#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2131360#L361 assume !(1 == ~m_pc~0); 2131361#L361-2 is_master_triggered_~__retres1~0#1 := 0; 2131407#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2131148#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2131149#L930 assume !(0 != activate_threads_~tmp~1#1); 2131571#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2131352#L380 assume !(1 == ~t1_pc~0); 2131353#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2131603#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2131604#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2131747#L938 assume !(0 != activate_threads_~tmp___0~0#1); 2131067#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2130997#L399 assume !(1 == ~t2_pc~0); 2130998#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2131205#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2131620#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2131432#L946 assume !(0 != activate_threads_~tmp___1~0#1); 2130905#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2130876#L418 assume !(1 == ~t3_pc~0); 2130839#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2130840#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2131380#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2131706#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2131801#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2131694#L437 assume !(1 == ~t4_pc~0); 2131530#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2131172#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2130999#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2131000#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2131491#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2131122#L456 assume !(1 == ~t5_pc~0); 2131123#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2131233#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2131656#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2130894#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2130895#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2131014#L475 assume !(1 == ~t6_pc~0); 2131015#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2131088#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2131089#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2130860#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2130861#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2131366#L494 assume !(1 == ~t7_pc~0); 2131368#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2131413#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2131648#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2131649#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2131820#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2131647#L837 assume !(1 == ~M_E~0); 2131437#L837-2 assume !(1 == ~T1_E~0); 2130982#L842-1 assume !(1 == ~T2_E~0); 2130983#L847-1 assume !(1 == ~T3_E~0); 2131520#L852-1 assume !(1 == ~T4_E~0); 2131636#L857-1 assume !(1 == ~T5_E~0); 2131451#L862-1 assume !(1 == ~T6_E~0); 2131452#L867-1 assume !(1 == ~T7_E~0); 2131465#L872-1 assume !(1 == ~E_1~0); 2131575#L877-1 assume !(1 == ~E_2~0); 2131462#L882-1 assume !(1 == ~E_3~0); 2131463#L887-1 assume !(1 == ~E_4~0); 2131035#L892-1 assume !(1 == ~E_5~0); 2131036#L897-1 assume !(1 == ~E_6~0); 2131486#L902-1 assume !(1 == ~E_7~0); 2131115#L907-1 assume { :end_inline_reset_delta_events } true; 2131116#L1148-2 assume !false; 2184861#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2184859#L729 [2021-12-19 19:18:10,562 INFO L793 eck$LassoCheckResult]: Loop: 2184859#L729 assume !false; 2184857#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2184854#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2184852#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2184851#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2184849#L626 assume 0 != eval_~tmp~0#1; 2184657#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2184653#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 2184651#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2184648#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 2184647#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2164822#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 2164823#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2176807#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 2184878#L673 assume !(0 == ~t4_st~0); 2184875#L687 assume !(0 == ~t5_st~0); 2184867#L701 assume !(0 == ~t6_st~0); 2184865#L715 assume !(0 == ~t7_st~0); 2184859#L729 [2021-12-19 19:18:10,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:10,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2021-12-19 19:18:10,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:10,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022003044] [2021-12-19 19:18:10,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:10,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:10,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,568 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:10,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:10,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:10,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1673301209, now seen corresponding path program 1 times [2021-12-19 19:18:10,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:10,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3780955] [2021-12-19 19:18:10,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:10,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:10,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,581 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:10,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,583 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:10,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:10,583 INFO L85 PathProgramCache]: Analyzing trace with hash -626298208, now seen corresponding path program 1 times [2021-12-19 19:18:10,583 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:10,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447260954] [2021-12-19 19:18:10,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:10,584 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:10,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:10,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:10,598 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:10,599 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447260954] [2021-12-19 19:18:10,599 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447260954] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:10,599 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:10,599 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:10,599 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620765604] [2021-12-19 19:18:10,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:10,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:10,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:10,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:10,741 INFO L87 Difference]: Start difference. First operand 175272 states and 233073 transitions. cyclomatic complexity: 57825 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:11,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:11,413 INFO L93 Difference]: Finished difference Result 320977 states and 426182 transitions. [2021-12-19 19:18:11,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:11,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 320977 states and 426182 transitions.